42743 lines
2.8 MiB
42743 lines
2.8 MiB
; --------------------------------------------------------------------------------
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; @Title: netX4000app On-Chip Peripherals
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; @Props: Released
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; @Author: KOL, KRZ
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; @Changelog: 2019-12-30 KOL
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; 2022-02-03 KRZ
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; @Manufacturer: HILSCHER - Hilscher GmbH
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; @Doc: SVD Generated, based on: regdef_netx4000_arm_app.svd (ver 1.0)
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; @Core: Cortex-A9
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; @Chip: NETX4000-APP
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; @Copyright: (C) 1989-2021 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pernetx4000app.per 14235 2022-02-03 12:33:34Z kwisniewski $
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config 16. 8.
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tree "Core Registers (Cortex-A9MPCore)"
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup.long c15:0x0++0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x100++0x0
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
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bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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textline " "
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup.long c15:0x200++0x0
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line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register"
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rgroup.long c15:0x300++0x0
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line.long 0x0 "TLBTR,TLB Type Register"
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hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
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hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
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bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128"
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textline " "
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bitfld.long 0x0 0. " nU ,Unified or Separate TLBs" "Unified,Separate"
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rgroup.long c15:0x500++0x0
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
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bitfld.long 0x00 8.--11. " ClusterID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "0,1,2,3"
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rgroup.long c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " ISB ,Innermost shareability bits" "Non-cacheable,Hardware coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored"
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " ARS ,Auxiliary Registers Support" "Not supported,Control only,Fault status and Control,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,IMPLEMENTATION DEFINED,?..."
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bitfld.long 0x00 12.--15. " SLS ,Shareability levels Support" "One level,Two levels,?..."
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bitfld.long 0x00 8.--11. " OSS ,Outermost shareability Support" "Non-cacheable,Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored"
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,IMPLEMENTATION DEFINED,PMSAv6,PMSAv7,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Not supported,IMPLEMENTATION DEFINED,VMSAv6,VMSAv7,?..."
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rgroup.long c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Disabled,Required,Required,Required,Not required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
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rgroup.long c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,Supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Not supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not supported"
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bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
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bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Not supported,Supported,?..."
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Not supported,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Not supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Not supported,Supported,?..."
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bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Not supported,Supported,Supported,?..."
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rgroup.long c15:0x0010++0x00
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line.long 0x00 "PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Not supported,Supported,?..."
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bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Not supported,Supported,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0110++0x00
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line.long 0x00 "PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0210++0x00
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line.long 0x00 "DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,Supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Not supported,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,Reserved,Reserved,v6.1,v7,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,Reserved,v6,v6.1,v7,?..."
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group.long c15:0x1++0x0
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line.long 0x0 "SCTLR,Control Register"
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bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
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bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disabled,Enabled"
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bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
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bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin"
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textline " "
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bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
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bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
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bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
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bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
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bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
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group.long c15:0x101++0x0
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line.long 0x0 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " PARON ,Parity On" "Disabled,Enabled"
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bitfld.long 0x00 8. " ALIOW ,Enable allocation in one cache way only" "Disabled,Enabled"
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bitfld.long 0x00 7. " EXCL ,Exclusive cache Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 6. " SMP ,Signals if the Cortex-A9 processor is taking part in coherency or not" "0,1"
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bitfld.long 0x00 3. " FOZ ,Full Of Zero mode Enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " DP1 ,L1 Dside prefetch Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 1. " PH2 ,L2 prefetch hint Enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " FW ,Cache and TLB maintenance broadcast" "Disabled,Enabled"
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group.long c15:0x201++0x0
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line.long 0x0 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
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bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes"
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bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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group.long c15:0x11++0x0
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line.long 0x0 "SCR,Secure Configuration Register"
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bitfld.long 0x00 6. " nET ,Not early termination" "Not early,Early"
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bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
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bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
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textline " "
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bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
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bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
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bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
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textline " "
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bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
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group.long c15:0x111++0x0
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line.long 0x0 "SDER,Secure Debug Enable Register"
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bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
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bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
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group.long c15:0x0211++0x00
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line.long 0x00 "NSACR,Non-Secure Access Control Register"
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bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writable in Non-secure state" "Disabled,Enabled"
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bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted"
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bitfld.long 0x00 16. " PLE ,NS accesses to the Preload Engine resources control" "Secure,Non-secure"
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textline " "
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bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
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bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register" "No,Yes"
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bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted"
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textline " "
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bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted"
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group.long c15:0x0311++0x00
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line.long 0x00 "VCR,Virtualization Control Register"
|
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bitfld.long 0x00 8. " AMO ,Abort Mask Override" "0,1"
|
|
bitfld.long 0x00 7. " IMO ,IRQ Mask Override" "0,1"
|
|
bitfld.long 0x00 6. " IFO ,FIQ Mask Override" "0,1"
|
|
group.long c15:0xf++0x0
|
|
line.long 0x00 "PCR,Power Control Register"
|
|
bitfld.long 0x00 8.--10. " MCL ,Max Clock Latency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EDCG ,Enable Dynamic Clock Gating" "Disabled,Enabled"
|
|
textline " "
|
|
group.long c15:0x000c++0x00
|
|
line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address"
|
|
group.long c15:0x10c++0x00
|
|
line.long 0x0 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address"
|
|
rgroup.long c15:0x1C++0x0
|
|
line.long 0x0 "ISR,Interrupt status Register"
|
|
bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending"
|
|
bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending"
|
|
bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending"
|
|
group.long c15:0x11c++0x0
|
|
line.long 0x00 "VIR,Virtualization Interrupt Register"
|
|
bitfld.long 0x00 8. " VA ,Virtual Abort" "0,1"
|
|
bitfld.long 0x00 7. " VI ,Virtual IRQ" "0,1"
|
|
bitfld.long 0x00 6. " VF ,Virtual FIQ" "0,1"
|
|
tree.end
|
|
width 0x0d
|
|
tree "Memory Management Unit"
|
|
group.long c15:0x1++0x0
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin"
|
|
textline " "
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
|
|
textline " "
|
|
group.long c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address"
|
|
bitfld.long 0x00 0. 6. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
bitfld.long 0x00 5. " NOS ,Not Outer Shareable" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
bitfld.long 0x00 2. " IMP ,Implementation Defined" "0,1"
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C ,Cacheable" "Non-cacheable,Cacheable"
|
|
group.long c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address"
|
|
bitfld.long 0x00 0. 6. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
bitfld.long 0x00 5. " NOS ,Not Outer Shareable" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
bitfld.long 0x00 2. " IMP ,Implementation Defined" "0,1"
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C ,Cacheable" "Non-cacheable,Cacheable"
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable"
|
|
bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable"
|
|
bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000"
|
|
textline " "
|
|
group.long c15:0x3--0x3
|
|
line.long 0x0 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFA ,Data Fault Address"
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " SD ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " IFA ,Instruction Fault Address"
|
|
group.long c15:0x0015++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
hexmask.long 0x00 0.--31. 1. " DAFS ,Data Auxiliary Fault Status"
|
|
group.long c15:0x0115++0x00
|
|
line.long 0x00 "AIFSR,AuxiliaryInstruction Fault Status Register"
|
|
hexmask.long 0x00 0.--31. 1. " IAFS ,Instruction Auxiliary Fault Status"
|
|
textline " "
|
|
group.long c15:0xa++0x0
|
|
line.long 0x0 "TLBLR,TLB Lockdown Register"
|
|
bitfld.long 0x0 28.--29. " VICTIM ,Victim Value Increments after Each Tabel Walk" "0,1,2,3"
|
|
bitfld.long 0x0 0. " P ,Lockdown by Victim or Set Associative Region of TLB" "Associative,Lockdown"
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,PA Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " PA ,Physical Adress"
|
|
bitfld.long 0x00 10. " NOS ,Not Outer Shareable attribute" "Outer shareable,Not outer shareable"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NS ,Non-secure" "Not secured,Secured"
|
|
bitfld.long 0x00 7. " SH ,Shareable attribute" "Non-shareable,Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " Inner ,Signals region inner attributes" "Noncacheable,Strongly-ordered,Reserved,Device,Reserved,Write-back allocate,Write-through,Write-back"
|
|
bitfld.long 0x00 2.--3. " Outer ,Signals region outer attributes for normal memory type" "Noncacheable,Write-back allocate,Write-through,Write-back"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SS ,Supersection Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " F ,Translation Successful" "Successful,No successful"
|
|
textline " "
|
|
group.long c15:0x002A++0x0
|
|
line.long 0x00 "PRRR,Primary Region Remap Register"
|
|
bitfld.long 0x00 31. " NOS7 ,Outer Shareable property mapping for memory attribute 7" "Outer,Inner"
|
|
bitfld.long 0x00 30. " NOS6 ,Outer Shareable property mapping for memory attribute 6" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 29. " NOS5 ,Outer Shareable property mapping for memory attribute 5" "Outer,Inner"
|
|
bitfld.long 0x00 28. " NOS4 ,Outer Shareable property mapping for memory attribute 4" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NOS3 ,Outer Shareable property mapping for memory attribute 3" "Outer,Inner"
|
|
bitfld.long 0x00 26. " NOS2 ,Outer Shareable property mapping for memory attribute 2" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 25. " NOS1 ,Outer Shareable property mapping for memory attribute 1" "Outer,Inner"
|
|
bitfld.long 0x00 24. " NOS0 ,Outer Shareable property mapping for memory attribute 0" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,?..."
|
|
group.long c15:0x012A++0x0
|
|
line.long 0x00 "NMRR,Normal Memory Remap Register"
|
|
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
group.long c15:0x400f++0x0
|
|
line.long 0x00 "CBAR,Configuration Base Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " CBA ,Configuration Base Address"
|
|
textline " "
|
|
rgroup.long c15:0x000d++0x00
|
|
line.long 0x00 "FCSEIDR,FCSE PID Register"
|
|
hexmask.long.byte 0x00 25.--31. 0x02 " PID ,Process for Fast Context Switch Identification and Specification"
|
|
group.long c15:0x10d++0x0
|
|
line.long 0x0 "CONTEXTIDR,Context ID Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID"
|
|
hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID"
|
|
group.long c15:0x020d++0x00
|
|
line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " TPIDRURW ,User Read/Write Thread ID"
|
|
group.long c15:0x030d++0x00
|
|
line.long 0x00 "TPIDRURO,User Read-only Thread ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " TPIDRURO ,User Read-only Thread ID"
|
|
group.long c15:0x040d++0x00
|
|
line.long 0x00 "TPIDRPRW,Privileged Only Thread ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " TPIDRPRW ,Privileged Only Thread ID"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100++0x0
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 18.--20. " CType7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CType6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 12.--14. " CType5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CType4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 6.--8. " CType3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CType2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CType1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
rgroup.long c15:0x1000++0x0
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words"
|
|
group.long c15:0x2000++0x0
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data,Instruction"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group.long c15:0xC9++0x0
|
|
line.long 0x0 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
|
|
group.long c15:0x1C9++0x0
|
|
line.long 0x0 "PMCNTENSET,Count Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled"
|
|
group.long c15:0x2C9++0x0
|
|
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
|
|
bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled"
|
|
group.long c15:0x3C9++0x0
|
|
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 4. " P4 ,PMN5 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow"
|
|
group.long c15:0x4C9++0x0
|
|
line.long 0x0 "PMSWINC,Software Increment Register"
|
|
eventfld.long 0x00 5. " P5 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 4. " P4 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
textline " "
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group.long c15:0x5C9++0x0
|
|
line.long 0x0 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,CNT4,CNT5,?..."
|
|
group.long c15:0xD9++0x0
|
|
line.long 0x00 "PMCCNTR,Cycle Count Register"
|
|
hexmask.long 0x00 0.--31. 1. " CCNT ,Cycle Count"
|
|
group.long c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Type Select Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVCNT ,Event to count"
|
|
group.long c15:0x02d9++0x00
|
|
line.long 0x00 "PMXEVCNTR,Event Count Register"
|
|
hexmask.long 0x00 0.--31. 1. " PMNX ,Event Count"
|
|
group.long c15:0xE9++0x0
|
|
line.long 0x0 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
|
|
group.long c15:0x1E9++0x0
|
|
line.long 0x0 "PMINTENSET,Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.long c15:0x2E9++0x0
|
|
line.long 0x0 "PMINTENCLR,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 8.
|
|
tree "Preload Engine"
|
|
rgroup.long c15:0x000b++0x00
|
|
line.long 0x00 "PLEIDR,PLE ID Register"
|
|
bitfld.long 0x00 16.--20. " FIFOS ,PLE FIFO size" "Not present,Reserved,Reserved,Reserved,4,Reserved,Reserved,Reserved,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,?..."
|
|
bitfld.long 0x00 0. " PEP ,Preload Engine presence" "Not present,Present"
|
|
rgroup.long c15:0x020b++0x00
|
|
line.long 0x00 "PLEASR,PLE Activity Status Register"
|
|
bitfld.long 0x00 0. " R ,PLE Channel running" "Not running,Running"
|
|
rgroup.long c15:0x040b++0x00
|
|
line.long 0x00 "PLEFSR,PLE FIFO Status Register"
|
|
bitfld.long 0x00 0.--4. " AE ,Number of available entries in the PLE FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long c15:0x001b++0x00
|
|
line.long 0x00 "PLEUAR,Preload Engine User Accessibility Register"
|
|
bitfld.long 0x00 0. " U ,User accessibility" "Not permited,Permited"
|
|
group.long c15:0x011b++0x00
|
|
line.long 0x00 "PLEPCR,Preload Engine Parameters Control Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " BSM ,Block size mask"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BNM ,Block number mask"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WS ,PLE wait states"
|
|
tree.end
|
|
tree "NEON"
|
|
rgroup.long c15:0x000f++0x00
|
|
line.long 0x00 "NEON,NEON busy Register"
|
|
bitfld.long 0x00 0. " Busy ,NEON busy" "Not busy,Busy"
|
|
tree.end
|
|
width 0xb
|
|
width 9.
|
|
tree "Debug Registers"
|
|
tree "Jazelle Register"
|
|
group.long c14:0x7000++0x0
|
|
line.long 0x00 "JIDR,Jazelle ID Register"
|
|
bitfld.long 0x00 28.--31. " ARCH ,Architecture code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 20.--27. 1. " DESIGN ,Implementor code of the designer of the subarchitecture"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--19. 1. " SAMAJ ,The subarchitecture code"
|
|
bitfld.long 0x00 8.--11. " SAMIN ,The subarchitecture minor code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRTBFR ,Format of the Jazelle Configurable Opcode Translation Table Register" "0,1"
|
|
bitfld.long 0x00 0.--5. " TRTBSZ ,Size of the Jazelle Configurable Opcode Translation Table Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long c14:0x7001++0x0
|
|
line.long 0x00 "JOSCR,Jazelle OS Control Register"
|
|
bitfld.long 0x00 1. " CV ,Configuration Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " CD ,Configuration Disabled" "No,Yes"
|
|
group.long c14:0x7002++0x0
|
|
line.long 0x00 "JMCR,Jazelle Main Configuration Register"
|
|
bitfld.long 0x00 31. " nAR ,Not Array Operations" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " FP ,Floating-point opcodes handler" "VM implementation,VFP instructions"
|
|
bitfld.long 0x00 29. " AP ,Array Pointer" "Handler,Pointer"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OP ,Object Pointer" "Handler,Pointer"
|
|
bitfld.long 0x00 27. " IS ,Index Size" "8 bits,16 bits"
|
|
bitfld.long 0x00 26. " SP ,Static Pointer" "Handler,Pointer"
|
|
textline " "
|
|
bitfld.long 0x00 0. " JE ,Jazelle Enable" "Disabled,Enabled"
|
|
group.long c14:0x7003++0x0
|
|
line.long 0x00 "JPR,Jazelle Parameters Register"
|
|
bitfld.long 0x00 17.--21. " BSH ,Bounds SHift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--16. " sADO ,Signed Array Descriptor Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--11. " ARO ,Array Reference Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STO ,STatic Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " ODO ,Object Descriptor Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long c14:0x7004++0x0
|
|
line.long 0x00 "JCOTTRR,Jazelle Configurable Opcode Translation Table Register"
|
|
bitfld.long 0x00 10.--15. " OPCODE ,Bottom bits of the configurable opcode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. " OPERATION ,Code for the operation" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
tree.end
|
|
width 11.
|
|
tree "Processor Identifier Registers"
|
|
rgroup c14:0x340--0x340
|
|
line.long 0x00 "CPUID,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup c14:0x341--0x341
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
|
|
bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DMinLine ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " L1_Ipolicy ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " IMinLine ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup c14:0x343--0x343
|
|
line.long 0x00 "TLBTYPE,TLB Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 0x1 " ILsize ,Specifies the number of instruction TLB lockable entries"
|
|
hexmask.long.byte 0x0 8.--15. 0x1 " DLsize ,Specifies the number of unified or data TLB lockable entries"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128"
|
|
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
|
|
rgroup c14:0x348--0x348
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Not supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Not supported,Supported,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x349--0x349
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Not supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x34a--0x34a
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Not supported,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,Reserved,Reserved,v6.1,v7,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,Reserved,v6,v6.1,v7,?..."
|
|
rgroup c14:0x34c--0x34c
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " ISB ,Innermost shareability bits" "Non-cacheable,Hardware coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored"
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ARS ,Auxiliary Registers Support" "Not supported,Control only,Fault status and Control,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,IMPLEMENTATION DEFINED,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SLS ,Shareability levels Support" "One level,Two levels,?..."
|
|
bitfld.long 0x00 8.--11. " OSS ,Outermost shareability Support" "Non-cacheable,Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,IMPLEMENTATION DEFINED,PMSAv6,PMSAv7,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Not supported,IMPLEMENTATION DEFINED,VMSAv6,VMSAv7,?..."
|
|
rgroup c14:0x34d--0x34d
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Disabled,Required,Required,Required,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
|
|
rgroup c14:0x34e--0x34e
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Not supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x34f--0x34f
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
|
|
bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x350--0x350
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x351--0x351
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Not supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Not supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x352--0x352
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Not supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Not supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Not supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x353--0x353
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x354--0x354
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Not supported,Supported,Supported,?..."
|
|
tree.end
|
|
tree "Coresight Management Registers"
|
|
width 0xC
|
|
textline " "
|
|
group c14:0x3c0--0x3c0
|
|
line.long 0x0 "ITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group c14:0x3e8--0x3e8
|
|
line.long 0x0 "CLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
|
|
group c14:0x3e9--0x3e9
|
|
line.long 0x0 "CLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
|
|
wgroup c14:0x3ec--0x3ec
|
|
line.long 0x0 "LAR,Lock Access Register"
|
|
hexmask.long.long 0x0 0.--31. 1. " LACK ,Lock Access Control Key"
|
|
rgroup c14:0x3ed--0x3ed
|
|
line.long 0x0 "LSR,Lock Status Register"
|
|
bitfld.long 0x0 2. " 32ACND ,32-bit Access Needed" "Needed,Not needed"
|
|
bitfld.long 0x0 1. " WLCK ,Writes Lock" "Permitted,Ignored"
|
|
textline " "
|
|
bitfld.long 0x0 0. " LI ,Lock Implementation" "Lock ignored,Unlock required"
|
|
width 0xc
|
|
rgroup c14:0x3ee--0x3ee
|
|
line.long 0x0 "AUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x0 7. " SNIDFI ,Secure Non-invasive Debug Features Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 6. " SNIDE ,Secure Non-invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SIDFI ,Secure Invasive Debug Feauter Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 4. " SIDE ,Secure Invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " NSNIDFI ,Non-secure Non-invasive Debug Feature Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 2. " NSNIDE ,Non-secure Non-invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " NSIDFI ,Non-secure Invasive Debug Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 0. " NSIDE ,Non-secure Invasive Debug Enable" "Disabled,Enabled"
|
|
width 0xc
|
|
rgroup c14:0x3f2--0x3f2
|
|
line.long 0x0 "DEVID,Device Identifier"
|
|
bitfld.long 0x00 0.--3. " PCSAMPLE ,Level of Program Counter sampling support (DBGPCSR and DBGCIDSR)" "Not implemented,DBGPCSR,Both,?..."
|
|
rgroup c14:0x3f3--0x3f3
|
|
line.long 0x0 "DEVTYPE,Device Type"
|
|
hexmask.long.byte 0x0 4.--7. 1. " STPC ,Sub Type: Processor Core"
|
|
hexmask.long.byte 0x0 0.--3. 1. " MCDL ,Main Class: Debug Logic"
|
|
rgroup c14:0x3f8--0x3f8
|
|
line.long 0x0 "PID0,Peripherial ID0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PN ,Part Number [7:0]"
|
|
rgroup c14:0x3f9--0x3f9
|
|
line.long 0x0 "PID1,Peripherial ID1"
|
|
hexmask.long.byte 0x0 4.--7. 1. " JEP106 ,JEP106 Identity Code [3:0]"
|
|
hexmask.long.byte 0x0 0.--3. 1. " PN ,Part Number [11:8]"
|
|
rgroup c14:0x3fa--0x3fa
|
|
line.long 0x0 "PID2,Peripherial ID2"
|
|
hexmask.long.byte 0x0 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x00 3. " JEPCD ,JEP 106 ID code" "Not used,Used"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--2. 1. " JEP106 ,JEP106 Identity Code [6:4]"
|
|
rgroup c14:0x3fb--0x3fb
|
|
line.long 0x0 "PID3,Peripherial ID3"
|
|
hexmask.long.byte 0x0 4.--7. 1. " REVA ,RevAnd"
|
|
hexmask.long.byte 0x0 0.--3. 1. " CMOD ,Customer Modified"
|
|
rgroup c14:0x3f4--0x3f4
|
|
line.long 0x0 "PID4,Peripherial ID4"
|
|
bitfld.long 0x0 4.--7. " 4KBC ,Number of 4KB Blocks Occupied" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x0 0.--3. " JEP106 ,JEP106 Continuation Code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
rgroup c14:0x3fc--0x3fc
|
|
line.long 0x0 "COMPONENTID0,Component ID0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3fd--0x3fd
|
|
line.long 0x0 "COMPONENTID1,Component ID1"
|
|
hexmask.long.byte 0x0 4.--7. 1. " CCLASS ,Component Class (CoreSight Component)"
|
|
hexmask.long.byte 0x0 0.--3. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3fe--0x3fe
|
|
line.long 0x0 "COMPONENTID2,Component ID2"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3ff--0x3ff
|
|
line.long 0x0 "COMPONENTID3,Component ID3"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
tree.end
|
|
textline " "
|
|
width 0x7
|
|
rgroup c14:0x000--0x000
|
|
line.long 0x0 "DIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " Version ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,ARMv7 no ext.,?..."
|
|
textline " "
|
|
bitfld.long 0x0 15. " DEVID_IMP ,Debug Device ID Register DBGDEVID implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 14. " NSUHD_IMP ,Secure User halting debug implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSR_IMP ,Program Counter Sampling Register implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 12. " SE_IMP ,Security Extensions implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " Variant ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " Revision ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x7
|
|
group c14:0x22--0x22
|
|
line.long 0x0 "DSCR,Debug Status and Control Register"
|
|
bitfld.long 0x0 30. " DTRRXfull ,The DTRRX Full Flag" "Empty,Full"
|
|
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DTRRXfull_l ,The DTRRX Full Flag 1" "Empty,Full"
|
|
bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x0 25. " PIPEADV ,Sticky Pipeline Advance" "No effect,Instruction retired"
|
|
bitfld.long 0x0 24. " INSTRCOMPL_L ,Latched Instruction Complete" "Executing,Not executing"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " EXTDCCMODE ,External DCC access mode" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x0 19. " ADADISCARD ,Asynchronous Data Aborts Discarded" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
|
|
bitfld.long 0x0 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 16. " SPIDDIS ,Secure Privileged Invasive Debug Disabled" "No,Yes"
|
|
bitfld.long 0x0 15. " MDBGEN ,Monitor Debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " UDCCDIS ,User mode access to Comms Channel disable" "No,Yes"
|
|
bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DbgAck ,Force Debug Acknowledge" "Not forced,Forced"
|
|
bitfld.long 0x0 8. " UND_l ,Sticky Undefined Instruction" "No exception,Exception"
|
|
textline " "
|
|
bitfld.long 0x0 7. " ADABORT_l ,Sticky Asynchronous Data Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x0 6. " SDABORT_l ,Sticky Synchronous Data Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Halt request,Breakpoint,Asynchronous Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
|
|
width 0x7
|
|
if (((data.long(c14:0x00))&0x01000)==0x00000)
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "VCR,Vector Catch Register"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
else
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "VCR,Vector Catch Register"
|
|
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
endif
|
|
;rgroup c14:0x1++0x1
|
|
; line.long 0x0 "DRAR,Debug ROM Address Register"
|
|
; hexmask.long 0x0 12.--31. 0x1000 " DBROMPA ,Debug bus ROM physical address"
|
|
; bitfld.long 0x0 0.--1. " VB ,Valid bits" "Not valid,Reserved,Reserved,Valid"
|
|
; line.long 0x4 "DSAR,Debug Self Address Offset Register"
|
|
; hexmask.long 0x4 12.--31. 0x1000 " DBSAOV ,Debug bus self-address offset value"
|
|
; bitfld.long 0x4 0.--1. " VB ,Valid bits" "Not valid,Reserved,Reserved,Valid"
|
|
;hgroup c14:0x50++0x0
|
|
; hide.long 0x0 "DTR,Data Transfer Register"
|
|
; in
|
|
width 0x7
|
|
hgroup c14:0x020--0x020
|
|
hide.long 0x0 "DTRRX,Target -> Host Data Transfer Register"
|
|
in
|
|
group c14:0x023--0x023
|
|
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data"
|
|
wgroup c14:0x21++0x00
|
|
line.long 0x00 "ITR,Instruction Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " Data ,ARM Instruction for the Processor in Debug State Execute"
|
|
wgroup c14:0x24++0x00
|
|
line.long 0x00 "DRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 4. " CBIUR , Cancel Bus Interface Unit Requests" "Not canceled,Canceled"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
|
|
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
|
|
rgroup c14:0xc4++0x00
|
|
line.long 0x00 "PRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HNDLR ,Hold non-debug logic reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " WRR ,Warm reset request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high"
|
|
hgroup c14:0xc5++0x00
|
|
hide.long 0x00 "PRSR,Device Power-Down and Reset Status Register"
|
|
in
|
|
tree.end
|
|
width 6.
|
|
tree "Breakpoint Registers"
|
|
group c14:0x40++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
|
|
group c14:0x50++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x41++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
|
|
group c14:0x51++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x42++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
|
|
group c14:0x52++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x43++0x00
|
|
line.long 0x00 "BVR3,Breakpoint Value Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
|
|
group c14:0x53++0x00
|
|
line.long 0x00 "BCR3,Breakpoint Control Register 3"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x44++0x00
|
|
line.long 0x00 "BVR4,Breakpoint Value Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
|
|
group c14:0x54++0x00
|
|
line.long 0x00 "BCR4,Breakpoint Control Register 4"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x45++0x00
|
|
line.long 0x00 "BVR5,Breakpoint Value Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
|
|
group c14:0x55++0x00
|
|
line.long 0x00 "BCR5,Breakpoint Control Register 5"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 6.
|
|
tree "Watchpoint Control Registers"
|
|
group c14:0x60++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group c14:0x70--0x70
|
|
line.long 0x0 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x61++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
|
|
group c14:0x71--0x71
|
|
line.long 0x0 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x62++0x00
|
|
line.long 0x00 "WVR2,Watchpoint Value Register 2"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA2 ,Watchpoint Address 2"
|
|
group c14:0x72--0x72
|
|
line.long 0x0 "WCR2,Watchpoint Control Register 2"
|
|
bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x63++0x00
|
|
line.long 0x00 "WVR3,Watchpoint Value Register 3"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA3 ,Watchpoint Address 3"
|
|
group c14:0x73--0x73
|
|
line.long 0x0 "WCR3,Watchpoint Control Register 3"
|
|
bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x006--0x006
|
|
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
|
|
hexmask.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
width 0xb
|
|
width 9.
|
|
base ad:(d.l(c15:0x400f))
|
|
tree "Snoop Control Unit (SCU)"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCUCR,SCU Control Register"
|
|
bitfld.long 0x00 6. " ICSE ,IC standby enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCUSE ,SCU standby enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FADTP0E ,Force all Device to port0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCUSLE ,SCU Speculative linefills enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCURPE ,SCU RAMs Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AFE ,Address filtering enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCUE ,SCU enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SCUCON,SCU Configuration Register"
|
|
bitfld.long 0x00 14.--15. " RAM3 ,Cortex-A9 CPU3 Tag RAM Size" "16KB,32KB,64KB,?..."
|
|
bitfld.long 0x00 12.--13. " RAM2 ,Cortex-A9 CPU2 Tag RAM Size" "16KB,32KB,64KB,?..."
|
|
bitfld.long 0x00 10.--11. " RAM1 ,Cortex-A9 CPU1 Tag RAM Size" "16KB,32KB,64KB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RAM0 ,Cortex-A9 CPU0 Tag RAM Size" "16KB,32KB,64KB,?..."
|
|
bitfld.long 0x00 7. " MOD3 ,CPU3 Mode" "AMP,SMP"
|
|
bitfld.long 0x00 6. " MOD2 ,CPU2 Mode" "AMP,SMP"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MOD1 ,CPU1 Mode" "AMP,SMP"
|
|
bitfld.long 0x00 4. " MOD0 ,CPU0 Mode" "AMP,SMP"
|
|
bitfld.long 0x00 0.--1. " NUM ,CPU Number" "CPU0,CPU0-CPU1,CPU0-CPU2,CPU0-CPU3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SCUSTAT,SCU CPU Power Status Register"
|
|
bitfld.long 0x00 24.--25. " STAT3 ,CPU3 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
bitfld.long 0x00 16.--17. " STAT2 ,CPU2 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " STAT1 ,CPU1 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
bitfld.long 0x00 0.--1. " STAT0 ,CPU0 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "INV,SCU Invalidate All Register"
|
|
bitfld.long 0x00 12.--15. " WAY3 ,Cortex-A9 CPU3 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " WAY2 ,Cortex-A9 CPU2 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " WAY1 ,Cortex-A9 CPU1 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " WAY0 ,Cortex-A9 CPU0 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FSAR,Filtering Start Address Register"
|
|
hexmask.long.word 0x00 20.--31. 0x10 " FSA ,Filtering start address"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FEAR,Filtering End Address Register"
|
|
hexmask.long.word 0x00 20.--31. 0x10 " FEA ,Filtering end address"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SAC,SCU Access Control Register"
|
|
bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SSAC,SCU Secure Access Control Register"
|
|
bitfld.long 0x00 11. " GCPU3 ,Global timer for CPU3" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 10. " GCPU2 ,Global timer for CPU2" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 9. " GCPU1 ,Global timer for CPU1" "Secure only,Secure/Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GCPU0 ,Global timer for CPU0" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 7. " TCPU3 ,Private timer for CPU3 Access" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 6. " TCPU2 ,Private timer for CPU2 Access" "Secure only,Secure/Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TCPU1 ,Private timer for CPU1 Access" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 4. " TCPU0 ,Private timer for CPU0 Access" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access"
|
|
tree.end
|
|
width 0xb
|
|
width 8.
|
|
tree "Timer and Watchdog Blocks"
|
|
base ad:(d.l(c15:0x400f))+0x600
|
|
group.long 0x00++0xb "Timer"
|
|
line.long 0x00 "TLR,Timer Load Register"
|
|
line.long 0x04 "TCR,Timer Counter Register"
|
|
line.long 0x08 "TCONR,Timer Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler"
|
|
bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " AREL ,Auto reload" "Single shot,Auto-reload"
|
|
bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled"
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TISR,Timer Interrupt Status Register"
|
|
eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1"
|
|
group.long 0x20++0x13 "Watchdog"
|
|
line.long 0x00 "WLR,Watchdog Load Register"
|
|
line.long 0x04 "WCR,Watchdog Counter Register"
|
|
line.long 0x08 "WCONR,Watchdog Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler"
|
|
bitfld.long 0x08 3. " WDM ,WD Mode" "Timer,Watchdog"
|
|
bitfld.long 0x08 2. " ITEN ,IT Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " AREL ,Auto-Reload" "Single shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x08 0. " WEN ,Watchdog Enable" "Disabled,Enabled"
|
|
line.long 0x0c "WISR,Watchdog Interrupt Status Register"
|
|
eventfld.long 0x0C 0. " EFLAG ,Event Flag" "0,1"
|
|
line.long 0x10 "WRSR,Watchdog Reset Sent Register"
|
|
eventfld.long 0x10 0. " RFLAG ,Reset Flag" "No effect,Reset"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "WDR,Watchdog Disable Register"
|
|
base ad:(d.l(c15:0x400f))+0x200
|
|
group.long 0x00++0xb "Global Timer"
|
|
line.long 0x00 "GTLCR,Lower 32-bit Timer Counter Register"
|
|
line.long 0x04 "GTUCR,Upper 32-bit Timer Counter Register"
|
|
line.long 0x08 "GTCONR,Timer Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler"
|
|
bitfld.long 0x08 3. " AINC ,Auto Increment" "Single shot,Auto increment"
|
|
bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " COMPEN ,Comp Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled"
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "GTSR,Timer Status Register"
|
|
eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1"
|
|
group.long 0x10++0xb
|
|
line.long 0x00 "GTLCOMR,Lower 32-bit Comparator Register"
|
|
line.long 0x04 "GTUCOMR,Upper 32-bit Comparator Register"
|
|
line.long 0x08 "GTINCR,Auto-increment Register for Comparator"
|
|
tree.end
|
|
width 11.
|
|
tree.open "Interrupt Controller (GIC-400)"
|
|
width 17.
|
|
base AD:(per.long(c15:0x400F)&0xffff8000)+0x1000
|
|
tree "Distributor Interface"
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400)
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)"
|
|
bitfld.long 0x00 1. " ENABLEGRP1 ,Global Interrupt Enable Group 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLEGRP0 ,Global Interrupt Enable Group 1" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICD_CTLR,Distributor Control Register"
|
|
bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400)
|
|
rgroup.long 0x0004++0x03
|
|
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..."
|
|
bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020"
|
|
else
|
|
rgroup.long 0x0004++0x03
|
|
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..."
|
|
bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020"
|
|
endif
|
|
rgroup.long 0x0008++0x03
|
|
line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register"
|
|
bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "PL390,PL390,GIC400,GIC400,?..."
|
|
bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer"
|
|
sif CPU.FEATURE(hypervisor)||CPU.FEATURE(secure)
|
|
width 17.
|
|
tree "Group/Security Registers"
|
|
group.long 0x0080++0x03
|
|
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1"
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x0084++0x03
|
|
line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0084++0x03
|
|
hide.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x0088++0x03
|
|
line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0088++0x03
|
|
hide.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x008C++0x03
|
|
line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x008C++0x03
|
|
hide.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x0090++0x03
|
|
line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0090++0x03
|
|
hide.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x0094++0x03
|
|
line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0094++0x03
|
|
hide.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x0098++0x03
|
|
line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0098++0x03
|
|
hide.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x009C++0x03
|
|
line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x009C++0x03
|
|
hide.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x00A0++0x03
|
|
line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00A0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x00A4++0x03
|
|
line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00A4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x00A8++0x03
|
|
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00A8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x00AC++0x03
|
|
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00AC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x00B0++0x03
|
|
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00B0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x00B4++0x03
|
|
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00B4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x00B8++0x03
|
|
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00B8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x00BC++0x03
|
|
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00BC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10)
|
|
group.long 0x00C0++0x03
|
|
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00C0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11)
|
|
group.long 0x00C4++0x03
|
|
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00C4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12)
|
|
group.long 0x00C8++0x03
|
|
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00C8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13)
|
|
group.long 0x00CC++0x03
|
|
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00CC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14)
|
|
group.long 0x00D0++0x03
|
|
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00D0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15)
|
|
group.long 0x00D4++0x03
|
|
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00D4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16)
|
|
group.long 0x00D8++0x03
|
|
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00D8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17)
|
|
group.long 0x00DC++0x03
|
|
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00DC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18)
|
|
group.long 0x00E0++0x03
|
|
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0E0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19)
|
|
group.long 0x00E4++0x03
|
|
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00E4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0x00E8++0x03
|
|
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00E8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0x00EC++0x03
|
|
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Non-Secure access)"
|
|
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00EC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0x00F0++0x03
|
|
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0F0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0x00F4++0x03
|
|
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00F4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0x00F8++0x03
|
|
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00F8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)==0x1F)
|
|
group.long 0x00FC++0x03
|
|
line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Non-secure access)"
|
|
bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00FC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
endif
|
|
width 24.
|
|
tree "Set/Clear Enable Registers"
|
|
group.long 0x0100++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled"
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x0104++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0104++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x0108++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0108++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x010C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x010C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x0110++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0110++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x0114++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0114++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x0118++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0118++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x011C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x011C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x0120++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0120++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x0124++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0124++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x0128++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0128++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x012C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x012C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x0130++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0130++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x0134++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0134++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x0138++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0138++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x013C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x013C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10)
|
|
group.long 0x0140++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0140++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11)
|
|
group.long 0x0144++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0144++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12)
|
|
group.long 0x0148++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0148++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13)
|
|
group.long 0x014C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x014C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14)
|
|
group.long 0x0150++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0150++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15)
|
|
group.long 0x0154++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0154++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16)
|
|
group.long 0x0158++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0158++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17)
|
|
group.long 0x015C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x015C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18)
|
|
group.long 0x0160++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0160++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19)
|
|
group.long 0x0164++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0164++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0x0168++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0168++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0x016C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x016C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0x0170++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0170++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0x0174++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0174++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0x0178++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0178++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)==0x1F)
|
|
group.long 0x017C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB1019 ,Set/Clear Enable Bit 1019" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB1018 ,Set/Clear Enable Bit 1018" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB1017 ,Set/Clear Enable Bit 1017" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB1016 ,Set/Clear Enable Bit 1016" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB1015 ,Set/Clear Enable Bit 1015" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB1014 ,Set/Clear Enable Bit 1014" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB1013 ,Set/Clear Enable Bit 1013" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB1012 ,Set/Clear Enable Bit 1012" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB1011 ,Set/Clear Enable Bit 1011" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB1010 ,Set/Clear Enable Bit 1010" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB1009 ,Set/Clear Enable Bit 1009" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB1008 ,Set/Clear Enable Bit 1008" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB1007 ,Set/Clear Enable Bit 1007" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB1006 ,Set/Clear Enable Bit 1006" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB1005 ,Set/Clear Enable Bit 1005" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB1004 ,Set/Clear Enable Bit 1004" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB1003 ,Set/Clear Enable Bit 1003" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB1002 ,Set/Clear Enable Bit 1002" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB1001 ,Set/Clear Enable Bit 1001" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB1000 ,Set/Clear Enable Bit 1000" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB999 ,Set/Clear Enable Bit 999" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB998 ,Set/Clear Enable Bit 998" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB997 ,Set/Clear Enable Bit 997" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB996 ,Set/Clear Enable Bit 996" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB995 ,Set/Clear Enable Bit 995" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB994 ,Set/Clear Enable Bit 994" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB993 ,Set/Clear Enable Bit 993" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB992 ,Set/Clear Enable Bit 992" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x017C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 22.
|
|
tree "Set/Clear Pending Registers"
|
|
group.long 0x0200++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Disabled,Enabled"
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x0204++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0204++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x0208++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0208++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x020C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x020C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x0210++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0210++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x0214++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0214++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x0218++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0218++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x021C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x021C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x0220++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0220++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x0224++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0224++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x0228++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0228++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x022C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x022C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x0230++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0230++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x0234++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0234++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x0238++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0238++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x023C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x023C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10)
|
|
group.long 0x0240++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0240++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11)
|
|
group.long 0x0244++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0244++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12)
|
|
group.long 0x0248++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0248++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13)
|
|
group.long 0x024C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x024C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14)
|
|
group.long 0x0250++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0250++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15)
|
|
group.long 0x0254++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0254++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16)
|
|
group.long 0x0258++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0258++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17)
|
|
group.long 0x025C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x025C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18)
|
|
group.long 0x0260++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0260++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19)
|
|
group.long 0x0264++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0264++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0x0268++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0268++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0x026C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x026C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0x0270++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0270++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0x0274++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0274++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0x0278++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0278++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)==0x1F)
|
|
group.long 0x027C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND1019 ,Set/Clear Pending Bit 1019" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND1018 ,Set/Clear Pending Bit 1018" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND1017 ,Set/Clear Pending Bit 1017" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND1016 ,Set/Clear Pending Bit 1016" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND1015 ,Set/Clear Pending Bit 1015" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND1014 ,Set/Clear Pending Bit 1014" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND1013 ,Set/Clear Pending Bit 1013" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND1012 ,Set/Clear Pending Bit 1012" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND1011 ,Set/Clear Pending Bit 1011" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND1010 ,Set/Clear Pending Bit 1010" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND1009 ,Set/Clear Pending Bit 1009" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND1008 ,Set/Clear Pending Bit 1008" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND1007 ,Set/Clear Pending Bit 1007" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND1006 ,Set/Clear Pending Bit 1006" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND1005 ,Set/Clear Pending Bit 1005" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND1004 ,Set/Clear Pending Bit 1004" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND1003 ,Set/Clear Pending Bit 1003" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND1002 ,Set/Clear Pending Bit 1002" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND1001 ,Set/Clear Pending Bit 1001" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND1000 ,Set/Clear Pending Bit 1000" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND999 ,Set/Clear Pending Bit 999" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND998 ,Set/Clear Pending Bit 998" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND997 ,Set/Clear Pending Bit 997" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND996 ,Set/Clear Pending Bit 996" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND995 ,Set/Clear Pending Bit 995" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND994 ,Set/Clear Pending Bit 994" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND993 ,Set/Clear Pending Bit 993" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND992 ,Set/Clear Pending Bit 992" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x027C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 24.
|
|
tree "Set/Clear Active Registers"
|
|
group.long 0x0300++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active"
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x0304++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0304++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x0308++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0308++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x030C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active"
|
|
else
|
|
hgroup.long 0x030C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x0310++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0310++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x0314++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0314++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x0318++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0318++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x031C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active"
|
|
else
|
|
hgroup.long 0x031C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x0320++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0320++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x0324++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0324++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x0328++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0328++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x032C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active"
|
|
else
|
|
hgroup.long 0x032C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x0330++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0330++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x0334++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0334++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x0338++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0338++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x033C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active"
|
|
else
|
|
hgroup.long 0x033C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
hgroup.long 0x0340++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x0344++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x0348++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x034C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x0350++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x0354++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x0358++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x035C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x0360++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x0364++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x0368++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x036C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x0370++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x0374++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x0378++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.long 0x037C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER31,Interrupt Set/Clear Active Register 31"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
tree.end
|
|
width 20.
|
|
tree "Priority Registers"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 "
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 "
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 "
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 "
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 "
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 "
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 "
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 "
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 "
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 "
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 "
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 "
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 "
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 "
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 "
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 "
|
|
else
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
|
|
hgroup.long 0x424++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
|
|
hgroup.long 0x428++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
|
|
hgroup.long 0x42C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
|
|
hgroup.long 0x430++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
|
|
hgroup.long 0x434++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
|
|
hgroup.long 0x438++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
|
|
hgroup.long 0x43C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 "
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 "
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 "
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 "
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 "
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 "
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 "
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 "
|
|
else
|
|
hgroup.long 0x440++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
|
|
hgroup.long 0x444++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
|
|
hgroup.long 0x448++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
|
|
hgroup.long 0x44C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
|
|
hgroup.long 0x450++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
|
|
hgroup.long 0x454++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
|
|
hgroup.long 0x458++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
|
|
hgroup.long 0x45C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 "
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 "
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 "
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 "
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 "
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 "
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 "
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 "
|
|
else
|
|
hgroup.long 0x460++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
|
|
hgroup.long 0x464++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
|
|
hgroup.long 0x468++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
|
|
hgroup.long 0x46C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
|
|
hgroup.long 0x470++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
|
|
hgroup.long 0x474++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
|
|
hgroup.long 0x478++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
|
|
hgroup.long 0x47C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 "
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 "
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 "
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 "
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 "
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 "
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 "
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 "
|
|
else
|
|
hgroup.long 0x480++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
|
|
hgroup.long 0x484++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
|
|
hgroup.long 0x488++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
|
|
hgroup.long 0x48C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
|
|
hgroup.long 0x490++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
|
|
hgroup.long 0x494++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
|
|
hgroup.long 0x498++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
|
|
hgroup.long 0x49C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 "
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 "
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 "
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 "
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 "
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 "
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 "
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 "
|
|
else
|
|
hgroup.long 0x4A0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
|
|
hgroup.long 0x4A4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
|
|
hgroup.long 0x4A8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
|
|
hgroup.long 0x4AC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
|
|
hgroup.long 0x4B0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
|
|
hgroup.long 0x4B4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
|
|
hgroup.long 0x4B8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
|
|
hgroup.long 0x4BC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 "
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 "
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 "
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 "
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 "
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 "
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 "
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 "
|
|
else
|
|
hgroup.long 0x4C0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
|
|
hgroup.long 0x4C4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
|
|
hgroup.long 0x4C8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
|
|
hgroup.long 0x4CC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
|
|
hgroup.long 0x4D0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
|
|
hgroup.long 0x4D4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
|
|
hgroup.long 0x4D8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
|
|
hgroup.long 0x4DC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 "
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 "
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 "
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 "
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 "
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 "
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 "
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 "
|
|
else
|
|
hgroup.long 0x4E0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
|
|
hgroup.long 0x4E4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
|
|
hgroup.long 0x4E8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
|
|
hgroup.long 0x4EC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
|
|
hgroup.long 0x4F0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
|
|
hgroup.long 0x4F4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
|
|
hgroup.long 0x4F8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
|
|
hgroup.long 0x4FC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 "
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 "
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 "
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 "
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 "
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 "
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 "
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 "
|
|
else
|
|
hgroup.long 0x500++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
|
|
hgroup.long 0x504++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
|
|
hgroup.long 0x508++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
|
|
hgroup.long 0x50C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
|
|
hgroup.long 0x510++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
|
|
hgroup.long 0x514++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
|
|
hgroup.long 0x518++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
|
|
hgroup.long 0x51C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 "
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 "
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 "
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 "
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 "
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 "
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 "
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 "
|
|
else
|
|
hgroup.long 0x520++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
|
|
hgroup.long 0x524++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
|
|
hgroup.long 0x528++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
|
|
hgroup.long 0x52C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
|
|
hgroup.long 0x530++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
|
|
hgroup.long 0x534++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
|
|
hgroup.long 0x538++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
|
|
hgroup.long 0x53C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 "
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 "
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 "
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 "
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 "
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 "
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 "
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 "
|
|
else
|
|
hgroup.long 0x540++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
|
|
hgroup.long 0x544++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
|
|
hgroup.long 0x548++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
|
|
hgroup.long 0x54C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
|
|
hgroup.long 0x550++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
|
|
hgroup.long 0x554++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
|
|
hgroup.long 0x558++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
|
|
hgroup.long 0x55C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 "
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 "
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 "
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 "
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 "
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 "
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 "
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 "
|
|
else
|
|
hgroup.long 0x560++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
|
|
hgroup.long 0x564++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
|
|
hgroup.long 0x568++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
|
|
hgroup.long 0x56C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
|
|
hgroup.long 0x570++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
|
|
hgroup.long 0x574++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
|
|
hgroup.long 0x578++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
|
|
hgroup.long 0x57C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 "
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 "
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 "
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 "
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 "
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 "
|
|
group.long 0x598++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 "
|
|
group.long 0x59C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 "
|
|
else
|
|
hgroup.long 0x580++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
|
|
hgroup.long 0x584++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
|
|
hgroup.long 0x588++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
|
|
hgroup.long 0x58C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
|
|
hgroup.long 0x590++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
|
|
hgroup.long 0x594++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
|
|
hgroup.long 0x598++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
|
|
hgroup.long 0x59C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 "
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 "
|
|
group.long 0x5A8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 "
|
|
group.long 0x5AC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 "
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 "
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 "
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 "
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 "
|
|
else
|
|
hgroup.long 0x5A0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
|
|
hgroup.long 0x5A4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
|
|
hgroup.long 0x5A8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
|
|
hgroup.long 0x5AC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
|
|
hgroup.long 0x5B0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
|
|
hgroup.long 0x5B4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
|
|
hgroup.long 0x5B8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
|
|
hgroup.long 0x5BC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 "
|
|
group.long 0x5C4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 "
|
|
group.long 0x5C8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 "
|
|
group.long 0x5CC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 "
|
|
group.long 0x5D0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 "
|
|
group.long 0x5D4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 "
|
|
group.long 0x5D8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 "
|
|
group.long 0x5DC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 "
|
|
else
|
|
hgroup.long 0x5C0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
|
|
hgroup.long 0x5C4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
|
|
hgroup.long 0x5C8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
|
|
hgroup.long 0x5CC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
|
|
hgroup.long 0x5D0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
|
|
hgroup.long 0x5D4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
|
|
hgroup.long 0x5D8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
|
|
hgroup.long 0x5DC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 "
|
|
group.long 0x5E4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 "
|
|
group.long 0x5E8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 "
|
|
group.long 0x5EC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 "
|
|
group.long 0x5F0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 "
|
|
group.long 0x5F4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 "
|
|
group.long 0x5F8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 "
|
|
group.long 0x5FC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 "
|
|
else
|
|
hgroup.long 0x5E0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
|
|
hgroup.long 0x5E4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
|
|
hgroup.long 0x5E8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
|
|
hgroup.long 0x5EC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
|
|
hgroup.long 0x5F0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
|
|
hgroup.long 0x5F4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
|
|
hgroup.long 0x5F8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
|
|
hgroup.long 0x5FC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10)
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 "
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 "
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 "
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 "
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 "
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 "
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 "
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 "
|
|
else
|
|
hgroup.long 0x600++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
|
|
hgroup.long 0x604++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
|
|
hgroup.long 0x608++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
|
|
hgroup.long 0x60C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
|
|
hgroup.long 0x610++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
|
|
hgroup.long 0x614++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
|
|
hgroup.long 0x618++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
|
|
hgroup.long 0x61C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11)
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 "
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 "
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 "
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 "
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 "
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 "
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 "
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 "
|
|
else
|
|
hgroup.long 0x620++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
|
|
hgroup.long 0x624++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
|
|
hgroup.long 0x628++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
|
|
hgroup.long 0x62C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
|
|
hgroup.long 0x630++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
|
|
hgroup.long 0x634++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
|
|
hgroup.long 0x638++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
|
|
hgroup.long 0x63C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12)
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 "
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 "
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 "
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 "
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 "
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 "
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 "
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 "
|
|
else
|
|
hgroup.long 0x640++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
|
|
hgroup.long 0x644++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
|
|
hgroup.long 0x648++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
|
|
hgroup.long 0x64C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
|
|
hgroup.long 0x650++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
|
|
hgroup.long 0x654++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
|
|
hgroup.long 0x658++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
|
|
hgroup.long 0x65C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13)
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 "
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 "
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 "
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 "
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 "
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 "
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 "
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 "
|
|
else
|
|
hgroup.long 0x660++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
|
|
hgroup.long 0x664++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
|
|
hgroup.long 0x668++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
|
|
hgroup.long 0x66C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
|
|
hgroup.long 0x670++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
|
|
hgroup.long 0x674++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
|
|
hgroup.long 0x678++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
|
|
hgroup.long 0x67C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14)
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 "
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 "
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 "
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 "
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 "
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 "
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 "
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 "
|
|
else
|
|
hgroup.long 0x680++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
|
|
hgroup.long 0x684++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
|
|
hgroup.long 0x688++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
|
|
hgroup.long 0x68C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
|
|
hgroup.long 0x690++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
|
|
hgroup.long 0x694++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
|
|
hgroup.long 0x698++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
|
|
hgroup.long 0x69C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15)
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 "
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 "
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 "
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 "
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 "
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 "
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 "
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 "
|
|
else
|
|
hgroup.long 0x6A0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
|
|
hgroup.long 0x6A4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
|
|
hgroup.long 0x6A8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
|
|
hgroup.long 0x6AC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
|
|
hgroup.long 0x6B0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
|
|
hgroup.long 0x6B4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
|
|
hgroup.long 0x6B8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
|
|
hgroup.long 0x6BC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16)
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 "
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 "
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 "
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 "
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 "
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 "
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 "
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 "
|
|
else
|
|
hgroup.long 0x6C0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
|
|
hgroup.long 0x6C4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
|
|
hgroup.long 0x6C8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
|
|
hgroup.long 0x6CC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
|
|
hgroup.long 0x6D0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
|
|
hgroup.long 0x6D4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
|
|
hgroup.long 0x6D8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
|
|
hgroup.long 0x6DC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17)
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 "
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 "
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 "
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 "
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 "
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 "
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 "
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 "
|
|
else
|
|
hgroup.long 0x6E0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
|
|
hgroup.long 0x6E4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
|
|
hgroup.long 0x6E8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
|
|
hgroup.long 0x6EC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
|
|
hgroup.long 0x6F0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
|
|
hgroup.long 0x6F4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
|
|
hgroup.long 0x6F8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
|
|
hgroup.long 0x6FC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18)
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 "
|
|
group.long 0x704++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 "
|
|
group.long 0x708++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 "
|
|
group.long 0x70C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 "
|
|
group.long 0x710++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 "
|
|
group.long 0x714++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 "
|
|
group.long 0x718++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 "
|
|
group.long 0x71C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 "
|
|
else
|
|
hgroup.long 0x700++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
|
|
hgroup.long 0x704++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
|
|
hgroup.long 0x708++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
|
|
hgroup.long 0x70C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
|
|
hgroup.long 0x710++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
|
|
hgroup.long 0x714++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
|
|
hgroup.long 0x718++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
|
|
hgroup.long 0x71C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19)
|
|
group.long 0x720++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 "
|
|
group.long 0x724++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 "
|
|
group.long 0x728++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 "
|
|
group.long 0x72C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 "
|
|
group.long 0x730++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 "
|
|
group.long 0x734++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 "
|
|
group.long 0x738++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 "
|
|
group.long 0x73C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 "
|
|
else
|
|
hgroup.long 0x720++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
|
|
hgroup.long 0x724++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
|
|
hgroup.long 0x728++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
|
|
hgroup.long 0x72C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
|
|
hgroup.long 0x730++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
|
|
hgroup.long 0x734++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
|
|
hgroup.long 0x738++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
|
|
hgroup.long 0x73C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0x740++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 "
|
|
group.long 0x744++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 "
|
|
group.long 0x748++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 "
|
|
group.long 0x74C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 "
|
|
group.long 0x750++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 "
|
|
group.long 0x754++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 "
|
|
group.long 0x758++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 "
|
|
group.long 0x75C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 "
|
|
else
|
|
hgroup.long 0x740++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
|
|
hgroup.long 0x744++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
|
|
hgroup.long 0x748++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
|
|
hgroup.long 0x74C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
|
|
hgroup.long 0x750++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
|
|
hgroup.long 0x754++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
|
|
hgroup.long 0x758++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
|
|
hgroup.long 0x75C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0x760++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 "
|
|
group.long 0x764++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 "
|
|
group.long 0x768++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 "
|
|
group.long 0x76C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 "
|
|
group.long 0x770++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 "
|
|
group.long 0x774++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 "
|
|
group.long 0x778++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 "
|
|
group.long 0x77C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 "
|
|
else
|
|
hgroup.long 0x760++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
|
|
hgroup.long 0x764++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
|
|
hgroup.long 0x768++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
|
|
hgroup.long 0x76C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
|
|
hgroup.long 0x770++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
|
|
hgroup.long 0x774++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
|
|
hgroup.long 0x778++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
|
|
hgroup.long 0x77C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0x780++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 "
|
|
group.long 0x784++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 "
|
|
group.long 0x788++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 "
|
|
group.long 0x78C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 "
|
|
group.long 0x790++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 "
|
|
group.long 0x794++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 "
|
|
group.long 0x798++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 "
|
|
group.long 0x79C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 "
|
|
else
|
|
hgroup.long 0x780++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
|
|
hgroup.long 0x784++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
|
|
hgroup.long 0x788++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
|
|
hgroup.long 0x78C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
|
|
hgroup.long 0x790++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
|
|
hgroup.long 0x794++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
|
|
hgroup.long 0x798++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
|
|
hgroup.long 0x79C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0x7A0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 "
|
|
group.long 0x7A4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 "
|
|
group.long 0x7A8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 "
|
|
group.long 0x7AC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 "
|
|
group.long 0x7B0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 "
|
|
group.long 0x7B4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 "
|
|
group.long 0x7B8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 "
|
|
group.long 0x7BC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 "
|
|
else
|
|
hgroup.long 0x7A0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
|
|
hgroup.long 0x7A4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
|
|
hgroup.long 0x7A8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
|
|
hgroup.long 0x7AC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
|
|
hgroup.long 0x7B0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
|
|
hgroup.long 0x7B4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
|
|
hgroup.long 0x7B8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
|
|
hgroup.long 0x7BC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0x7C0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 "
|
|
group.long 0x7C4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 "
|
|
group.long 0x7C8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 "
|
|
group.long 0x7CC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 "
|
|
group.long 0x7D0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 "
|
|
group.long 0x7D4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 "
|
|
group.long 0x7D8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 "
|
|
group.long 0x7DC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 "
|
|
else
|
|
hgroup.long 0x7C0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
|
|
hgroup.long 0x7C4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
|
|
hgroup.long 0x7C8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
|
|
hgroup.long 0x7CC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
|
|
hgroup.long 0x7D0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
|
|
hgroup.long 0x7D4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
|
|
hgroup.long 0x7D8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
|
|
hgroup.long 0x7DC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1F)
|
|
group.long 0x7E0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID995 ,Interrupt ID995 Priority/Priority Byte Offset 995 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID994 ,Interrupt ID994 Priority/Priority Byte Offset 994 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID993 ,Interrupt ID993 Priority/Priority Byte Offset 993 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID992 ,Interrupt ID992 Priority/Priority Byte Offset 992 "
|
|
group.long 0x7E4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID999 ,Interrupt ID999 Priority/Priority Byte Offset 999 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID998 ,Interrupt ID998 Priority/Priority Byte Offset 998 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID997 ,Interrupt ID997 Priority/Priority Byte Offset 997 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID996 ,Interrupt ID996 Priority/Priority Byte Offset 996 "
|
|
group.long 0x7E8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID1003 ,Interrupt ID1003 Priority/Priority Byte Offset 1003"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID1002 ,Interrupt ID1002 Priority/Priority Byte Offset 1002"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1001 ,Interrupt ID1001 Priority/Priority Byte Offset 1001"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID1000 ,Interrupt ID1000 Priority/Priority Byte Offset 1000"
|
|
group.long 0x7EC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID1007 ,Interrupt ID1007 Priority/Priority Byte Offset 1007"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID1006 ,Interrupt ID1006 Priority/Priority Byte Offset 1006"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1005 ,Interrupt ID1005 Priority/Priority Byte Offset 1005"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID1004 ,Interrupt ID1004 Priority/Priority Byte Offset 1004"
|
|
group.long 0x7F0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID1011 ,Interrupt ID1011 Priority/Priority Byte Offset 1011"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID1010 ,Interrupt ID1010 Priority/Priority Byte Offset 1010"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1009 ,Interrupt ID1009 Priority/Priority Byte Offset 1009"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID1008 ,Interrupt ID1008 Priority/Priority Byte Offset 1008"
|
|
group.long 0x7F4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID1015 ,Interrupt ID1015 Priority/Priority Byte Offset 1015"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID1014 ,Interrupt ID1014 Priority/Priority Byte Offset 1014"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1013 ,Interrupt ID1013 Priority/Priority Byte Offset 1013"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID1012 ,Interrupt ID1012 Priority/Priority Byte Offset 1012"
|
|
group.long 0x7F8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID1019 ,Interrupt ID1019 Priority/Priority Byte Offset 1019"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID1018 ,Interrupt ID1018 Priority/Priority Byte Offset 1018"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1017 ,Interrupt ID1017 Priority/Priority Byte Offset 1017"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID1016 ,Interrupt ID1016 Priority/Priority Byte Offset 1016"
|
|
else
|
|
hgroup.long 0x7E0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248"
|
|
hgroup.long 0x7E4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249"
|
|
hgroup.long 0x7E8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250"
|
|
hgroup.long 0x7EC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251"
|
|
hgroup.long 0x7F0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252"
|
|
hgroup.long 0x7F4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253"
|
|
hgroup.long 0x7F8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254"
|
|
endif
|
|
tree.end
|
|
width 19.
|
|
tree "Processor Targets Registers"
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x000000E0)>0x1)
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0 "
|
|
rgroup.long 0x804++0x03
|
|
line.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO7 ,CPU Targets Byte Offset 7 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO6 ,CPU Targets Byte Offset 6 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO5 ,CPU Targets Byte Offset 5 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO4 ,CPU Targets Byte Offset 4 "
|
|
rgroup.long 0x808++0x03
|
|
line.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO11 ,CPU Targets Byte Offset 11 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO10 ,CPU Targets Byte Offset 10 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO9 ,CPU Targets Byte Offset 9 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO8 ,CPU Targets Byte Offset 8 "
|
|
rgroup.long 0x80C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO15 ,CPU Targets Byte Offset 15 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO14 ,CPU Targets Byte Offset 14 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO13 ,CPU Targets Byte Offset 13 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO12 ,CPU Targets Byte Offset 12 "
|
|
rgroup.long 0x810++0x03
|
|
line.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO19 ,CPU Targets Byte Offset 19 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO18 ,CPU Targets Byte Offset 18 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO17 ,CPU Targets Byte Offset 17 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO16 ,CPU Targets Byte Offset 16 "
|
|
rgroup.long 0x814++0x03
|
|
line.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO23 ,CPU Targets Byte Offset 23 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO22 ,CPU Targets Byte Offset 22 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO21 ,CPU Targets Byte Offset 21 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO20 ,CPU Targets Byte Offset 20 "
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO27 ,CPU Targets Byte Offset 27 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO26 ,CPU Targets Byte Offset 26 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO25 ,CPU Targets Byte Offset 25 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO24 ,CPU Targets Byte Offset 24 "
|
|
rgroup.long 0x81C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO31 ,CPU Targets Byte Offset 31 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO30 ,CPU Targets Byte Offset 30 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO29 ,CPU Targets Byte Offset 29 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO28 ,CPU Targets Byte Offset 28 "
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 "
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 "
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 "
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 "
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 "
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 "
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 "
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 "
|
|
else
|
|
hgroup.long 0x820++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
|
|
hgroup.long 0x824++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
|
|
hgroup.long 0x828++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
|
|
hgroup.long 0x82C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
|
|
hgroup.long 0x830++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
|
|
hgroup.long 0x834++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
|
|
hgroup.long 0x838++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
|
|
hgroup.long 0x83C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 "
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 "
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 "
|
|
group.long 0x84C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 "
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 "
|
|
group.long 0x854++0x03
|
|
line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 "
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 "
|
|
group.long 0x85C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 "
|
|
else
|
|
hgroup.long 0x840++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
|
|
hgroup.long 0x844++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
|
|
hgroup.long 0x848++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
|
|
hgroup.long 0x84C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
|
|
hgroup.long 0x850++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
|
|
hgroup.long 0x854++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
|
|
hgroup.long 0x858++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
|
|
hgroup.long 0x85C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 "
|
|
group.long 0x864++0x03
|
|
line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 "
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 "
|
|
group.long 0x86C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 "
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 "
|
|
group.long 0x874++0x03
|
|
line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 "
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 "
|
|
group.long 0x87C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 "
|
|
else
|
|
hgroup.long 0x860++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
|
|
hgroup.long 0x864++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
|
|
hgroup.long 0x868++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
|
|
hgroup.long 0x86C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
|
|
hgroup.long 0x870++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
|
|
hgroup.long 0x874++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
|
|
hgroup.long 0x878++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
|
|
hgroup.long 0x87C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 "
|
|
group.long 0x884++0x03
|
|
line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 "
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 "
|
|
group.long 0x88C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 "
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 "
|
|
group.long 0x894++0x03
|
|
line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 "
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 "
|
|
group.long 0x89C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 "
|
|
else
|
|
hgroup.long 0x880++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
|
|
hgroup.long 0x884++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
|
|
hgroup.long 0x888++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
|
|
hgroup.long 0x88C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
|
|
hgroup.long 0x890++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
|
|
hgroup.long 0x894++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
|
|
hgroup.long 0x898++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
|
|
hgroup.long 0x89C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 "
|
|
group.long 0x8A4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 "
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 "
|
|
group.long 0x8AC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 "
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 "
|
|
group.long 0x8B4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 "
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 "
|
|
group.long 0x8BC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 "
|
|
else
|
|
hgroup.long 0x8A0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
|
|
hgroup.long 0x8A4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
|
|
hgroup.long 0x8A8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
|
|
hgroup.long 0x8AC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
|
|
hgroup.long 0x8B0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
|
|
hgroup.long 0x8B4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
|
|
hgroup.long 0x8B8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
|
|
hgroup.long 0x8BC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 "
|
|
group.long 0x8C4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 "
|
|
group.long 0x8C8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 "
|
|
group.long 0x8CC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 "
|
|
group.long 0x8D0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 "
|
|
group.long 0x8D4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 "
|
|
group.long 0x8D8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 "
|
|
group.long 0x8DC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 "
|
|
else
|
|
hgroup.long 0x8C0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
|
|
hgroup.long 0x8C4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
|
|
hgroup.long 0x8C8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
|
|
hgroup.long 0x8CC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
|
|
hgroup.long 0x8D0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
|
|
hgroup.long 0x8D4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
|
|
hgroup.long 0x8D8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
|
|
hgroup.long 0x8DC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x8E0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 "
|
|
group.long 0x8E4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 "
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 "
|
|
group.long 0x8EC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 "
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 "
|
|
group.long 0x8F4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 "
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 "
|
|
group.long 0x8FC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 "
|
|
else
|
|
hgroup.long 0x8E0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
|
|
hgroup.long 0x8E4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
|
|
hgroup.long 0x8E8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
|
|
hgroup.long 0x8EC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
|
|
hgroup.long 0x8F0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
|
|
hgroup.long 0x8F4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
|
|
hgroup.long 0x8F8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
|
|
hgroup.long 0x8FC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 "
|
|
group.long 0x904++0x03
|
|
line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 "
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 "
|
|
group.long 0x90C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 "
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 "
|
|
group.long 0x914++0x03
|
|
line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 "
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 "
|
|
group.long 0x91C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 "
|
|
else
|
|
hgroup.long 0x900++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
|
|
hgroup.long 0x904++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
|
|
hgroup.long 0x908++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
|
|
hgroup.long 0x90C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
|
|
hgroup.long 0x910++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
|
|
hgroup.long 0x914++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
|
|
hgroup.long 0x918++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
|
|
hgroup.long 0x91C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 "
|
|
group.long 0x924++0x03
|
|
line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 "
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 "
|
|
group.long 0x92C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 "
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 "
|
|
group.long 0x934++0x03
|
|
line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 "
|
|
group.long 0x938++0x03
|
|
line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 "
|
|
group.long 0x93C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 "
|
|
else
|
|
hgroup.long 0x920++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
|
|
hgroup.long 0x924++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
|
|
hgroup.long 0x928++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
|
|
hgroup.long 0x92C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
|
|
hgroup.long 0x930++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
|
|
hgroup.long 0x934++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
|
|
hgroup.long 0x938++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
|
|
hgroup.long 0x93C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 "
|
|
group.long 0x944++0x03
|
|
line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 "
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 "
|
|
group.long 0x94C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 "
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 "
|
|
group.long 0x954++0x03
|
|
line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 "
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 "
|
|
group.long 0x95C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 "
|
|
else
|
|
hgroup.long 0x940++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
|
|
hgroup.long 0x944++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
|
|
hgroup.long 0x948++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
|
|
hgroup.long 0x94C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
|
|
hgroup.long 0x950++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
|
|
hgroup.long 0x954++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
|
|
hgroup.long 0x958++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
|
|
hgroup.long 0x95C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 "
|
|
group.long 0x964++0x03
|
|
line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 "
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 "
|
|
group.long 0x96C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 "
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 "
|
|
group.long 0x974++0x03
|
|
line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 "
|
|
group.long 0x978++0x03
|
|
line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 "
|
|
group.long 0x97C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 "
|
|
else
|
|
hgroup.long 0x960++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
|
|
hgroup.long 0x964++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
|
|
hgroup.long 0x968++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
|
|
hgroup.long 0x96C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
|
|
hgroup.long 0x970++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
|
|
hgroup.long 0x974++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
|
|
hgroup.long 0x978++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
|
|
hgroup.long 0x97C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 "
|
|
group.long 0x984++0x03
|
|
line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 "
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 "
|
|
group.long 0x98C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 "
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 "
|
|
group.long 0x994++0x03
|
|
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 "
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 "
|
|
group.long 0x99C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 "
|
|
else
|
|
hgroup.long 0x980++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
|
|
hgroup.long 0x984++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
|
|
hgroup.long 0x988++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
|
|
hgroup.long 0x98C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
|
|
hgroup.long 0x990++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
|
|
hgroup.long 0x994++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
|
|
hgroup.long 0x998++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
|
|
hgroup.long 0x99C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 "
|
|
group.long 0x9A4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 "
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 "
|
|
group.long 0x9AC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 "
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 "
|
|
group.long 0x9B4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 "
|
|
group.long 0x9B8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 "
|
|
group.long 0x9BC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 "
|
|
else
|
|
hgroup.long 0x9A0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
|
|
hgroup.long 0x9A4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
|
|
hgroup.long 0x9A8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
|
|
hgroup.long 0x9AC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
|
|
hgroup.long 0x9B0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
|
|
hgroup.long 0x9B4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
|
|
hgroup.long 0x9B8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
|
|
hgroup.long 0x9BC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 "
|
|
group.long 0x9C4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 "
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 "
|
|
group.long 0x9CC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 "
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 "
|
|
group.long 0x9D4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 "
|
|
group.long 0x9D8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 "
|
|
group.long 0x9DC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 "
|
|
else
|
|
hgroup.long 0x9C0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
|
|
hgroup.long 0x9C4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
|
|
hgroup.long 0x9C8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
|
|
hgroup.long 0x9CC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
|
|
hgroup.long 0x9D0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
|
|
hgroup.long 0x9D4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
|
|
hgroup.long 0x9D8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
|
|
hgroup.long 0x9DC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 "
|
|
group.long 0x9E4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 "
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 "
|
|
group.long 0x9EC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 "
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 "
|
|
group.long 0x9F4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 "
|
|
group.long 0x9F8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 "
|
|
group.long 0x9FC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 "
|
|
else
|
|
hgroup.long 0x9E0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
|
|
hgroup.long 0x9E4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
|
|
hgroup.long 0x9E8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
|
|
hgroup.long 0x9EC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
|
|
hgroup.long 0x9F0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
|
|
hgroup.long 0x9F4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
|
|
hgroup.long 0x9F8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
|
|
hgroup.long 0x9FC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10)
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 "
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 "
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 "
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 "
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 "
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 "
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 "
|
|
group.long 0xA1C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 "
|
|
else
|
|
hgroup.long 0xA00++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
|
|
hgroup.long 0xA04++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
|
|
hgroup.long 0xA08++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
|
|
hgroup.long 0xA0C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
|
|
hgroup.long 0xA10++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
|
|
hgroup.long 0xA14++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
|
|
hgroup.long 0xA18++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
|
|
hgroup.long 0xA1C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11)
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 "
|
|
group.long 0xA24++0x03
|
|
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 "
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 "
|
|
group.long 0xA2C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 "
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 "
|
|
group.long 0xA34++0x03
|
|
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 "
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 "
|
|
group.long 0xA3C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 "
|
|
else
|
|
hgroup.long 0xA20++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
|
|
hgroup.long 0xA24++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
|
|
hgroup.long 0xA28++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
|
|
hgroup.long 0xA2C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
|
|
hgroup.long 0xA30++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
|
|
hgroup.long 0xA34++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
|
|
hgroup.long 0xA38++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
|
|
hgroup.long 0xA3C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12)
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 "
|
|
group.long 0xA44++0x03
|
|
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 "
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 "
|
|
group.long 0xA4C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 "
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 "
|
|
group.long 0xA54++0x03
|
|
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 "
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 "
|
|
group.long 0xA5C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 "
|
|
else
|
|
hgroup.long 0xA40++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
|
|
hgroup.long 0xA44++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
|
|
hgroup.long 0xA48++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
|
|
hgroup.long 0xA4C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
|
|
hgroup.long 0xA50++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
|
|
hgroup.long 0xA54++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
|
|
hgroup.long 0xA58++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
|
|
hgroup.long 0xA5C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13)
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 "
|
|
group.long 0xA64++0x03
|
|
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 "
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 "
|
|
group.long 0xA6C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 "
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 "
|
|
group.long 0xA74++0x03
|
|
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 "
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 "
|
|
group.long 0xA7C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 "
|
|
else
|
|
hgroup.long 0xA60++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
|
|
hgroup.long 0xA64++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
|
|
hgroup.long 0xA68++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
|
|
hgroup.long 0xA6C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
|
|
hgroup.long 0xA70++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
|
|
hgroup.long 0xA74++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
|
|
hgroup.long 0xA78++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
|
|
hgroup.long 0xA7C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14)
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 "
|
|
group.long 0xA84++0x03
|
|
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 "
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 "
|
|
group.long 0xA8C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 "
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 "
|
|
group.long 0xA94++0x03
|
|
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 "
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 "
|
|
group.long 0xA9C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 "
|
|
else
|
|
hgroup.long 0xA80++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
|
|
hgroup.long 0xA84++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
|
|
hgroup.long 0xA88++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
|
|
hgroup.long 0xA8C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
|
|
hgroup.long 0xA90++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
|
|
hgroup.long 0xA94++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
|
|
hgroup.long 0xA98++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
|
|
hgroup.long 0xA9C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15)
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 "
|
|
group.long 0xAA4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 "
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 "
|
|
group.long 0xAAC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 "
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 "
|
|
group.long 0xAB4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 "
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 "
|
|
group.long 0xABC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 "
|
|
else
|
|
hgroup.long 0xAA0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
|
|
hgroup.long 0xAA4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
|
|
hgroup.long 0xAA8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
|
|
hgroup.long 0xAAC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
|
|
hgroup.long 0xAB0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
|
|
hgroup.long 0xAB4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
|
|
hgroup.long 0xAB8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
|
|
hgroup.long 0xABC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16)
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 "
|
|
group.long 0xAC4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 "
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 "
|
|
group.long 0xACC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 "
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 "
|
|
group.long 0xAD4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 "
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 "
|
|
group.long 0xADC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 "
|
|
else
|
|
hgroup.long 0xAC0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
|
|
hgroup.long 0xAC4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
|
|
hgroup.long 0xAC8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
|
|
hgroup.long 0xACC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
|
|
hgroup.long 0xAD0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
|
|
hgroup.long 0xAD4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
|
|
hgroup.long 0xAD8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
|
|
hgroup.long 0xADC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17)
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 "
|
|
group.long 0xAE4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 "
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 "
|
|
group.long 0xAEC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 "
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 "
|
|
group.long 0xAF4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 "
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 "
|
|
group.long 0xAFC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 "
|
|
else
|
|
hgroup.long 0xAE0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
|
|
hgroup.long 0xAE4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
|
|
hgroup.long 0xAE8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
|
|
hgroup.long 0xAEC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
|
|
hgroup.long 0xAF0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
|
|
hgroup.long 0xAF4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
|
|
hgroup.long 0xAF8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
|
|
hgroup.long 0xAFC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18)
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 "
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 "
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 "
|
|
group.long 0xB0C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 "
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 "
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 "
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 "
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 "
|
|
else
|
|
hgroup.long 0xB00++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
|
|
hgroup.long 0xB04++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
|
|
hgroup.long 0xB08++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
|
|
hgroup.long 0xB0C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
|
|
hgroup.long 0xB10++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
|
|
hgroup.long 0xB14++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
|
|
hgroup.long 0xB18++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
|
|
hgroup.long 0xB1C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 "
|
|
group.long 0xB24++0x03
|
|
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 "
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 "
|
|
group.long 0xB2C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 "
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 "
|
|
group.long 0xB34++0x03
|
|
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 "
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 "
|
|
group.long 0xB3C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 "
|
|
else
|
|
hgroup.long 0xB20++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
|
|
hgroup.long 0xB24++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
|
|
hgroup.long 0xB28++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
|
|
hgroup.long 0xB2C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
|
|
hgroup.long 0xB30++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
|
|
hgroup.long 0xB34++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
|
|
hgroup.long 0xB38++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
|
|
hgroup.long 0xB3C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 "
|
|
group.long 0xB44++0x03
|
|
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 "
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 "
|
|
group.long 0xB4C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 "
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 "
|
|
group.long 0xB54++0x03
|
|
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 "
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 "
|
|
group.long 0xB5C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 "
|
|
else
|
|
hgroup.long 0xB40++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
|
|
hgroup.long 0xB44++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
|
|
hgroup.long 0xB48++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
|
|
hgroup.long 0xB4C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
|
|
hgroup.long 0xB50++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
|
|
hgroup.long 0xB54++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
|
|
hgroup.long 0xB58++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
|
|
hgroup.long 0xB5C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 "
|
|
group.long 0xB64++0x03
|
|
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 "
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 "
|
|
group.long 0xB6C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 "
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 "
|
|
group.long 0xB74++0x03
|
|
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 "
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 "
|
|
group.long 0xB7C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 "
|
|
else
|
|
hgroup.long 0xB60++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
|
|
hgroup.long 0xB64++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
|
|
hgroup.long 0xB68++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
|
|
hgroup.long 0xB6C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
|
|
hgroup.long 0xB70++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
|
|
hgroup.long 0xB74++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
|
|
hgroup.long 0xB78++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
|
|
hgroup.long 0xB7C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 "
|
|
group.long 0xB84++0x03
|
|
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 "
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 "
|
|
group.long 0xB8C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 "
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 "
|
|
group.long 0xB94++0x03
|
|
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 "
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 "
|
|
group.long 0xB9C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 "
|
|
else
|
|
hgroup.long 0xB80++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
|
|
hgroup.long 0xB84++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
|
|
hgroup.long 0xB88++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
|
|
hgroup.long 0xB8C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
|
|
hgroup.long 0xB90++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
|
|
hgroup.long 0xB94++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
|
|
hgroup.long 0xB98++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
|
|
hgroup.long 0xB9C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 "
|
|
group.long 0xBA4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 "
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 "
|
|
group.long 0xBAC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 "
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 "
|
|
group.long 0xBB4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 "
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 "
|
|
group.long 0xBBC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 "
|
|
else
|
|
hgroup.long 0xBA0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
|
|
hgroup.long 0xBA4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
|
|
hgroup.long 0xBA8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
|
|
hgroup.long 0xBAC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
|
|
hgroup.long 0xBB0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
|
|
hgroup.long 0xBB4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
|
|
hgroup.long 0xBB8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
|
|
hgroup.long 0xBBC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 "
|
|
group.long 0xBC4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 "
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 "
|
|
group.long 0xBCC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 "
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 "
|
|
group.long 0xBD4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 "
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 "
|
|
group.long 0xBDC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 "
|
|
else
|
|
hgroup.long 0xBC0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
|
|
hgroup.long 0xBC4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
|
|
hgroup.long 0xBC8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
|
|
hgroup.long 0xBCC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
|
|
hgroup.long 0xBD0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
|
|
hgroup.long 0xBD4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
|
|
hgroup.long 0xBD8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
|
|
hgroup.long 0xBDC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1F)
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO995 ,CPU Targets Byte Offset 995 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO994 ,CPU Targets Byte Offset 994 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO993 ,CPU Targets Byte Offset 993 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO992 ,CPU Targets Byte Offset 992 "
|
|
group.long 0xBE4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO999 ,CPU Targets Byte Offset 999 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO998 ,CPU Targets Byte Offset 998 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO997 ,CPU Targets Byte Offset 997 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO996 ,CPU Targets Byte Offset 996 "
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1003 ,CPU Targets Byte Offset 1003"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1002 ,CPU Targets Byte Offset 1002"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1001 ,CPU Targets Byte Offset 1001"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1000 ,CPU Targets Byte Offset 1000"
|
|
group.long 0xBEC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1007 ,CPU Targets Byte Offset 1007"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1006 ,CPU Targets Byte Offset 1006"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1005 ,CPU Targets Byte Offset 1005"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1004 ,CPU Targets Byte Offset 1004"
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1011 ,CPU Targets Byte Offset 1011"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1010 ,CPU Targets Byte Offset 1010"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1009 ,CPU Targets Byte Offset 1009"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1008 ,CPU Targets Byte Offset 1008"
|
|
group.long 0xBF4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1015 ,CPU Targets Byte Offset 1015"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1014 ,CPU Targets Byte Offset 1014"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1013 ,CPU Targets Byte Offset 1013"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1012 ,CPU Targets Byte Offset 1012"
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1019 ,CPU Targets Byte Offset 1019"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1018 ,CPU Targets Byte Offset 1018"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1017 ,CPU Targets Byte Offset 1017"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1016 ,CPU Targets Byte Offset 1016"
|
|
else
|
|
hgroup.long 0xBE0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248"
|
|
hgroup.long 0xBE4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249"
|
|
hgroup.long 0xBE8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250"
|
|
hgroup.long 0xBEC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251"
|
|
hgroup.long 0xBF0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252"
|
|
hgroup.long 0xBF4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253"
|
|
hgroup.long 0xBF8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254"
|
|
endif
|
|
else
|
|
hgroup.long 0x800++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 "
|
|
hgroup.long 0x804++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 "
|
|
hgroup.long 0x808++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 "
|
|
hgroup.long 0x80C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 "
|
|
hgroup.long 0x810++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 "
|
|
hgroup.long 0x814++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 "
|
|
hgroup.long 0x818++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 "
|
|
hgroup.long 0x81C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 "
|
|
hgroup.long 0x820++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 "
|
|
hgroup.long 0x824++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 "
|
|
hgroup.long 0x828++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 "
|
|
hgroup.long 0x82C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 "
|
|
hgroup.long 0x830++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 "
|
|
hgroup.long 0x834++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 "
|
|
hgroup.long 0x838++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 "
|
|
hgroup.long 0x83C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 "
|
|
hgroup.long 0x840++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 "
|
|
hgroup.long 0x844++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 "
|
|
hgroup.long 0x848++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 "
|
|
hgroup.long 0x84C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 "
|
|
hgroup.long 0x850++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 "
|
|
hgroup.long 0x854++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 "
|
|
hgroup.long 0x858++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 "
|
|
hgroup.long 0x85C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 "
|
|
hgroup.long 0x860++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 "
|
|
hgroup.long 0x864++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 "
|
|
hgroup.long 0x868++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 "
|
|
hgroup.long 0x86C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 "
|
|
hgroup.long 0x870++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 "
|
|
hgroup.long 0x874++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 "
|
|
hgroup.long 0x878++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 "
|
|
hgroup.long 0x87C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 "
|
|
hgroup.long 0x880++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 "
|
|
hgroup.long 0x884++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 "
|
|
hgroup.long 0x888++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 "
|
|
hgroup.long 0x88C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 "
|
|
hgroup.long 0x890++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 "
|
|
hgroup.long 0x894++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 "
|
|
hgroup.long 0x898++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 "
|
|
hgroup.long 0x89C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 "
|
|
hgroup.long 0x8A0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 "
|
|
hgroup.long 0x8A4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 "
|
|
hgroup.long 0x8A8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 "
|
|
hgroup.long 0x8AC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 "
|
|
hgroup.long 0x8B0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 "
|
|
hgroup.long 0x8B4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 "
|
|
hgroup.long 0x8B8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 "
|
|
hgroup.long 0x8BC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 "
|
|
hgroup.long 0x8C0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 "
|
|
hgroup.long 0x8C4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 "
|
|
hgroup.long 0x8C8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 "
|
|
hgroup.long 0x8CC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 "
|
|
hgroup.long 0x8D0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 "
|
|
hgroup.long 0x8D4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 "
|
|
hgroup.long 0x8D8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 "
|
|
hgroup.long 0x8DC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 "
|
|
hgroup.long 0x8E0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 "
|
|
hgroup.long 0x8E4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 "
|
|
hgroup.long 0x8E8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 "
|
|
hgroup.long 0x8EC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 "
|
|
hgroup.long 0x8F0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 "
|
|
hgroup.long 0x8F4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 "
|
|
hgroup.long 0x8F8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 "
|
|
hgroup.long 0x8FC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 "
|
|
hgroup.long 0x900++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 "
|
|
hgroup.long 0x904++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 "
|
|
hgroup.long 0x908++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 "
|
|
hgroup.long 0x90C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 "
|
|
hgroup.long 0x910++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 "
|
|
hgroup.long 0x914++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 "
|
|
hgroup.long 0x918++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 "
|
|
hgroup.long 0x91C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 "
|
|
hgroup.long 0x920++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 "
|
|
hgroup.long 0x924++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 "
|
|
hgroup.long 0x928++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 "
|
|
hgroup.long 0x92C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 "
|
|
hgroup.long 0x930++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 "
|
|
hgroup.long 0x934++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 "
|
|
hgroup.long 0x938++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 "
|
|
hgroup.long 0x93C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 "
|
|
hgroup.long 0x940++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 "
|
|
hgroup.long 0x944++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 "
|
|
hgroup.long 0x948++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 "
|
|
hgroup.long 0x94C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 "
|
|
hgroup.long 0x950++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 "
|
|
hgroup.long 0x954++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 "
|
|
hgroup.long 0x958++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 "
|
|
hgroup.long 0x95C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 "
|
|
hgroup.long 0x960++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 "
|
|
hgroup.long 0x964++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 "
|
|
hgroup.long 0x968++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 "
|
|
hgroup.long 0x96C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 "
|
|
hgroup.long 0x970++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 "
|
|
hgroup.long 0x974++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 "
|
|
hgroup.long 0x978++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 "
|
|
hgroup.long 0x97C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 "
|
|
hgroup.long 0x980++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 "
|
|
hgroup.long 0x984++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 "
|
|
hgroup.long 0x988++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 "
|
|
hgroup.long 0x98C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 "
|
|
hgroup.long 0x990++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
|
|
hgroup.long 0x994++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
|
|
hgroup.long 0x998++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
|
|
hgroup.long 0x99C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
|
|
hgroup.long 0x9A0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
|
|
hgroup.long 0x9A4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
|
|
hgroup.long 0x9A8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
|
|
hgroup.long 0x9AC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
|
|
hgroup.long 0x9B0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
|
|
hgroup.long 0x9B4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
|
|
hgroup.long 0x9B8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
|
|
hgroup.long 0x9BC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
|
|
hgroup.long 0x9C0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
|
|
hgroup.long 0x9C4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
|
|
hgroup.long 0x9C8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
|
|
hgroup.long 0x9CC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
|
|
hgroup.long 0x9D0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
|
|
hgroup.long 0x9D4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
|
|
hgroup.long 0x9D8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
|
|
hgroup.long 0x9DC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
|
|
hgroup.long 0x9E0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
|
|
hgroup.long 0x9E4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
|
|
hgroup.long 0x9E8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
|
|
hgroup.long 0x9EC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
|
|
hgroup.long 0x9F0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
|
|
hgroup.long 0x9F4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
|
|
hgroup.long 0x9F8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
|
|
hgroup.long 0x9FC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
|
|
hgroup.long 0xA00++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
|
|
hgroup.long 0xA04++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
|
|
hgroup.long 0xA08++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
|
|
hgroup.long 0xA0C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
|
|
hgroup.long 0xA10++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
|
|
hgroup.long 0xA14++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
|
|
hgroup.long 0xA18++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
|
|
hgroup.long 0xA1C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
|
|
hgroup.long 0xA20++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
|
|
hgroup.long 0xA24++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
|
|
hgroup.long 0xA28++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
|
|
hgroup.long 0xA2C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
|
|
hgroup.long 0xA30++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
|
|
hgroup.long 0xA34++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
|
|
hgroup.long 0xA38++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
|
|
hgroup.long 0xA3C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
|
|
hgroup.long 0xA40++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
|
|
hgroup.long 0xA44++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
|
|
hgroup.long 0xA48++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
|
|
hgroup.long 0xA4C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
|
|
hgroup.long 0xA50++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
|
|
hgroup.long 0xA54++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
|
|
hgroup.long 0xA58++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
|
|
hgroup.long 0xA5C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
|
|
hgroup.long 0xA60++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
|
|
hgroup.long 0xA64++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
|
|
hgroup.long 0xA68++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
|
|
hgroup.long 0xA6C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
|
|
hgroup.long 0xA70++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
|
|
hgroup.long 0xA74++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
|
|
hgroup.long 0xA78++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
|
|
hgroup.long 0xA7C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
|
|
hgroup.long 0xA80++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
|
|
hgroup.long 0xA84++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
|
|
hgroup.long 0xA88++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
|
|
hgroup.long 0xA8C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
|
|
hgroup.long 0xA90++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
|
|
hgroup.long 0xA94++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
|
|
hgroup.long 0xA98++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
|
|
hgroup.long 0xA9C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
|
|
hgroup.long 0xAA0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
|
|
hgroup.long 0xAA4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
|
|
hgroup.long 0xAA8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
|
|
hgroup.long 0xAAC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
|
|
hgroup.long 0xAB0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
|
|
hgroup.long 0xAB4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
|
|
hgroup.long 0xAB8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
|
|
hgroup.long 0xABC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
|
|
hgroup.long 0xAC0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
|
|
hgroup.long 0xAC4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
|
|
hgroup.long 0xAC8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
|
|
hgroup.long 0xACC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
|
|
hgroup.long 0xAD0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
|
|
hgroup.long 0xAD4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
|
|
hgroup.long 0xAD8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
|
|
hgroup.long 0xADC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
|
|
hgroup.long 0xAE0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
|
|
hgroup.long 0xAE4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
|
|
hgroup.long 0xAE8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
|
|
hgroup.long 0xAEC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
|
|
hgroup.long 0xAF0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
|
|
hgroup.long 0xAF4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
|
|
hgroup.long 0xAF8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
|
|
hgroup.long 0xAFC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
|
|
hgroup.long 0xB00++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
|
|
hgroup.long 0xB04++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
|
|
hgroup.long 0xB08++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
|
|
hgroup.long 0xB0C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
|
|
hgroup.long 0xB10++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
|
|
hgroup.long 0xB14++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
|
|
hgroup.long 0xB18++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
|
|
hgroup.long 0xB1C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
|
|
hgroup.long 0xB20++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
|
|
hgroup.long 0xB24++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
|
|
hgroup.long 0xB28++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
|
|
hgroup.long 0xB2C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
|
|
hgroup.long 0xB30++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
|
|
hgroup.long 0xB34++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
|
|
hgroup.long 0xB38++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
|
|
hgroup.long 0xB3C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
|
|
hgroup.long 0xB40++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
|
|
hgroup.long 0xB44++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
|
|
hgroup.long 0xB48++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
|
|
hgroup.long 0xB4C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
|
|
hgroup.long 0xB50++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
|
|
hgroup.long 0xB54++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
|
|
hgroup.long 0xB58++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
|
|
hgroup.long 0xB5C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
|
|
hgroup.long 0xB60++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
|
|
hgroup.long 0xB64++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
|
|
hgroup.long 0xB68++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
|
|
hgroup.long 0xB6C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
|
|
hgroup.long 0xB70++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
|
|
hgroup.long 0xB74++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
|
|
hgroup.long 0xB78++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
|
|
hgroup.long 0xB7C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
|
|
hgroup.long 0xB80++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
|
|
hgroup.long 0xB84++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
|
|
hgroup.long 0xB88++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
|
|
hgroup.long 0xB8C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
|
|
hgroup.long 0xB90++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
|
|
hgroup.long 0xB94++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
|
|
hgroup.long 0xB98++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
|
|
hgroup.long 0xB9C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
|
|
hgroup.long 0xBA0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
|
|
hgroup.long 0xBA4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
|
|
hgroup.long 0xBA8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
|
|
hgroup.long 0xBAC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
|
|
hgroup.long 0xBB0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
|
|
hgroup.long 0xBB4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
|
|
hgroup.long 0xBB8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
|
|
hgroup.long 0xBBC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
|
|
hgroup.long 0xBC0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
|
|
hgroup.long 0xBC4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
|
|
hgroup.long 0xBC8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
|
|
hgroup.long 0xBCC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
|
|
hgroup.long 0xBD0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
|
|
hgroup.long 0xBD4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
|
|
hgroup.long 0xBD8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
|
|
hgroup.long 0xBDC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
|
|
hgroup.long 0xBE0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248"
|
|
hgroup.long 0xBE4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249"
|
|
hgroup.long 0xBE8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250"
|
|
hgroup.long 0xBEC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251"
|
|
hgroup.long 0xBF0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252"
|
|
hgroup.long 0xBF4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253"
|
|
hgroup.long 0xBF8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254"
|
|
endif
|
|
tree.end
|
|
width 14.
|
|
tree "Configuration Registers"
|
|
hgroup.long 0xC00++0x03
|
|
hide.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register"
|
|
textline " "
|
|
rgroup.long 0xC04++0x03
|
|
line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1)
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC08++0x03
|
|
hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
|
|
hgroup.long 0xC0C++0x03
|
|
hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x2)
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC14++0x03
|
|
line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC10++0x03
|
|
hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
|
|
hgroup.long 0xC14++0x03
|
|
hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x3)
|
|
group.long 0xC18++0x03
|
|
line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC1C++0x03
|
|
line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC18++0x03
|
|
hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
|
|
hgroup.long 0xC1C++0x03
|
|
hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x4)
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC24++0x03
|
|
line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC20++0x03
|
|
hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
|
|
hgroup.long 0xC24++0x03
|
|
hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x5)
|
|
group.long 0xC28++0x03
|
|
line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC2C++0x03
|
|
line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC28++0x03
|
|
hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
|
|
hgroup.long 0xC2C++0x03
|
|
hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x6)
|
|
group.long 0xC30++0x03
|
|
line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC34++0x03
|
|
line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC30++0x03
|
|
hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
|
|
hgroup.long 0xC34++0x03
|
|
hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x7)
|
|
group.long 0xC38++0x03
|
|
line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC3C++0x03
|
|
line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC38++0x03
|
|
hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
|
|
hgroup.long 0xC3C++0x03
|
|
hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x8)
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC44++0x03
|
|
line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC40++0x03
|
|
hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
|
|
hgroup.long 0xC44++0x03
|
|
hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x9)
|
|
group.long 0xC48++0x03
|
|
line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC4C++0x03
|
|
line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC48++0x03
|
|
hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
|
|
hgroup.long 0xC4C++0x03
|
|
hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0xA)
|
|
group.long 0xC50++0x03
|
|
line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC54++0x03
|
|
line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC50++0x03
|
|
hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
|
|
hgroup.long 0xC54++0x03
|
|
hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0xB)
|
|
group.long 0xC58++0x03
|
|
line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC5C++0x03
|
|
line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC58++0x03
|
|
hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
|
|
hgroup.long 0xC5C++0x03
|
|
hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0xC)
|
|
group.long 0xC60++0x03
|
|
line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC64++0x03
|
|
line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC60++0x03
|
|
hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
|
|
hgroup.long 0xC64++0x03
|
|
hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0xD)
|
|
group.long 0xC68++0x03
|
|
line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC6C++0x03
|
|
line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC68++0x03
|
|
hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
|
|
hgroup.long 0xC6C++0x03
|
|
hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0xE)
|
|
group.long 0xC70++0x03
|
|
line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC74++0x03
|
|
line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC70++0x03
|
|
hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
|
|
hgroup.long 0xC74++0x03
|
|
hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0xF)
|
|
group.long 0xC78++0x03
|
|
line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC7C++0x03
|
|
line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC78++0x03
|
|
hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
|
|
hgroup.long 0xC7C++0x03
|
|
hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10)
|
|
group.long 0xC80++0x03
|
|
line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC84++0x03
|
|
line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC80++0x03
|
|
hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
|
|
hgroup.long 0xC84++0x03
|
|
hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11)
|
|
group.long 0xC88++0x03
|
|
line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC8C++0x03
|
|
line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC88++0x03
|
|
hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
|
|
hgroup.long 0xC8C++0x03
|
|
hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12)
|
|
group.long 0xC90++0x03
|
|
line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC94++0x03
|
|
line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC90++0x03
|
|
hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
|
|
hgroup.long 0xC94++0x03
|
|
hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13)
|
|
group.long 0xC98++0x03
|
|
line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC9C++0x03
|
|
line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC98++0x03
|
|
hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
|
|
hgroup.long 0xC9C++0x03
|
|
hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14)
|
|
group.long 0xCA0++0x03
|
|
line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCA4++0x03
|
|
line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCA0++0x03
|
|
hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
|
|
hgroup.long 0xCA4++0x03
|
|
hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15)
|
|
group.long 0xCA8++0x03
|
|
line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCAC++0x03
|
|
line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCA8++0x03
|
|
hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
|
|
hgroup.long 0xCAC++0x03
|
|
hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16)
|
|
group.long 0xCB0++0x03
|
|
line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCB4++0x03
|
|
line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCB0++0x03
|
|
hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
|
|
hgroup.long 0xCB4++0x03
|
|
hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17)
|
|
group.long 0xCB8++0x03
|
|
line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCBC++0x03
|
|
line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCB8++0x03
|
|
hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
|
|
hgroup.long 0xCBC++0x03
|
|
hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18)
|
|
group.long 0xCC0++0x03
|
|
line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCC4++0x03
|
|
line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCC0++0x03
|
|
hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
|
|
hgroup.long 0xCC4++0x03
|
|
hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19)
|
|
group.long 0xCC8++0x03
|
|
line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCCC++0x03
|
|
line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCC8++0x03
|
|
hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
|
|
hgroup.long 0xCCC++0x03
|
|
hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0xCD0++0x03
|
|
line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCD4++0x03
|
|
line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCD0++0x03
|
|
hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
|
|
hgroup.long 0xCD4++0x03
|
|
hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0xCD8++0x03
|
|
line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCDC++0x03
|
|
line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCD8++0x03
|
|
hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
|
|
hgroup.long 0xCDC++0x03
|
|
hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0xCE0++0x03
|
|
line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCE4++0x03
|
|
line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCE0++0x03
|
|
hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
|
|
hgroup.long 0xCE4++0x03
|
|
hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0xCE8++0x03
|
|
line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCEC++0x03
|
|
line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCE8++0x03
|
|
hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
|
|
hgroup.long 0xCEC++0x03
|
|
hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0xCF0++0x03
|
|
line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCF4++0x03
|
|
line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCF0++0x03
|
|
hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
|
|
hgroup.long 0xCF4++0x03
|
|
hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1F)
|
|
group.long 0xCF8++0x03
|
|
line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCFC++0x03
|
|
line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCF8++0x03
|
|
hide.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62"
|
|
hgroup.long 0xCFC++0x03
|
|
hide.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "Peripheral Interrupt Status Registers"
|
|
rgroup.long 0x0D00++0x03
|
|
line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 15. " PPI3S ,nIRQ pin status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " PPI2S ,Non-secure Physical Timer event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PPI1S ,Secure Physical Timer event status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " PPI0S ,nFIQ pin status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PPI4S ,Virtual Timer event status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " PPI5S ,Hypervisor Timer event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PPI6S ,Virtual Maintenance Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
width 22.
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01)
|
|
rgroup.long 0x0D04++0x03
|
|
line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
|
|
bitfld.long 0x00 31. " IRQS31 ,IRQS Status Bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS30 ,IRQS Status Bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS29 ,IRQS Status Bit 29" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS28 ,IRQS Status Bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS27 ,IRQS Status Bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS26 ,IRQS Status Bit 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS25 ,IRQS Status Bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS24 ,IRQS Status Bit 24" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS23 ,IRQS Status Bit 23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS22 ,IRQS Status Bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS21 ,IRQS Status Bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS20 ,IRQS Status Bit 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS19 ,IRQS Status Bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS18 ,IRQS Status Bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS17 ,IRQS Status Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS16 ,IRQS Status Bit 16" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS15 ,IRQS Status Bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS14 ,IRQS Status Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS13 ,IRQS Status Bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS12 ,IRQS Status Bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS11 ,IRQS Status Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS10 ,IRQS Status Bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS9 ,IRQS Status Bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS8 ,IRQS Status Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS7 ,IRQS Status Bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS6 ,IRQS Status Bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS5 ,IRQS Status Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS4 ,IRQS Status Bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS3 ,IRQS Status Bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS2 ,IRQS Status Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS1 ,IRQS Status Bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS0 ,IRQS Status Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x0D04++0x03
|
|
hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 1"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02)
|
|
rgroup.long 0x0D08++0x03
|
|
line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
|
|
bitfld.long 0x00 31. " IRQS63 ,IRQS Status Bit 63" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS62 ,IRQS Status Bit 62" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS61 ,IRQS Status Bit 61" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS60 ,IRQS Status Bit 60" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS59 ,IRQS Status Bit 59" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS58 ,IRQS Status Bit 58" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS57 ,IRQS Status Bit 57" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS56 ,IRQS Status Bit 56" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS55 ,IRQS Status Bit 55" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS54 ,IRQS Status Bit 54" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS53 ,IRQS Status Bit 53" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS52 ,IRQS Status Bit 52" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS51 ,IRQS Status Bit 51" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS50 ,IRQS Status Bit 50" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS49 ,IRQS Status Bit 49" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS48 ,IRQS Status Bit 48" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS47 ,IRQS Status Bit 47" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS46 ,IRQS Status Bit 46" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS45 ,IRQS Status Bit 45" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS44 ,IRQS Status Bit 44" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS43 ,IRQS Status Bit 43" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS42 ,IRQS Status Bit 42" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS41 ,IRQS Status Bit 41" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS40 ,IRQS Status Bit 40" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS39 ,IRQS Status Bit 39" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS38 ,IRQS Status Bit 38" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS37 ,IRQS Status Bit 37" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS36 ,IRQS Status Bit 36" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS35 ,IRQS Status Bit 35" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS34 ,IRQS Status Bit 34" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS33 ,IRQS Status Bit 33" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS32 ,IRQS Status Bit 32" "Low,High"
|
|
else
|
|
hgroup.long 0x0D08++0x03
|
|
hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03)
|
|
rgroup.long 0x0D0C++0x03
|
|
line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
|
|
bitfld.long 0x00 31. " IRQS95 ,IRQS Status Bit 95" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS94 ,IRQS Status Bit 94" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS93 ,IRQS Status Bit 93" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS92 ,IRQS Status Bit 92" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS91 ,IRQS Status Bit 91" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS90 ,IRQS Status Bit 90" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS89 ,IRQS Status Bit 89" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS88 ,IRQS Status Bit 88" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS87 ,IRQS Status Bit 87" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS86 ,IRQS Status Bit 86" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS85 ,IRQS Status Bit 85" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS84 ,IRQS Status Bit 84" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS83 ,IRQS Status Bit 83" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS82 ,IRQS Status Bit 82" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS81 ,IRQS Status Bit 81" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS80 ,IRQS Status Bit 80" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS79 ,IRQS Status Bit 79" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS78 ,IRQS Status Bit 78" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS77 ,IRQS Status Bit 77" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS76 ,IRQS Status Bit 76" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS75 ,IRQS Status Bit 75" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS74 ,IRQS Status Bit 74" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS73 ,IRQS Status Bit 73" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS72 ,IRQS Status Bit 72" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS71 ,IRQS Status Bit 71" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS70 ,IRQS Status Bit 70" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS69 ,IRQS Status Bit 69" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS68 ,IRQS Status Bit 68" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS67 ,IRQS Status Bit 67" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS66 ,IRQS Status Bit 66" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS65 ,IRQS Status Bit 65" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS64 ,IRQS Status Bit 64" "Low,High"
|
|
else
|
|
hgroup.long 0x0D0C++0x03
|
|
hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04)
|
|
rgroup.long 0x0D10++0x03
|
|
line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
|
|
bitfld.long 0x00 31. " IRQS127 ,IRQS Status Bit 127" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS126 ,IRQS Status Bit 126" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS125 ,IRQS Status Bit 125" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS124 ,IRQS Status Bit 124" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS123 ,IRQS Status Bit 123" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS122 ,IRQS Status Bit 122" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS121 ,IRQS Status Bit 121" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS120 ,IRQS Status Bit 120" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS119 ,IRQS Status Bit 119" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS118 ,IRQS Status Bit 118" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS117 ,IRQS Status Bit 117" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS116 ,IRQS Status Bit 116" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS115 ,IRQS Status Bit 115" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS114 ,IRQS Status Bit 114" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS113 ,IRQS Status Bit 113" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS112 ,IRQS Status Bit 112" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS111 ,IRQS Status Bit 111" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS110 ,IRQS Status Bit 110" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS109 ,IRQS Status Bit 109" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS108 ,IRQS Status Bit 108" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS107 ,IRQS Status Bit 107" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS106 ,IRQS Status Bit 106" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS105 ,IRQS Status Bit 105" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS104 ,IRQS Status Bit 104" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS103 ,IRQS Status Bit 103" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS102 ,IRQS Status Bit 102" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS101 ,IRQS Status Bit 101" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS100 ,IRQS Status Bit 100" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS99 ,IRQS Status Bit 99" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS98 ,IRQS Status Bit 98" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS97 ,IRQS Status Bit 97" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS96 ,IRQS Status Bit 96" "Low,High"
|
|
else
|
|
hgroup.long 0x0D10++0x03
|
|
hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05)
|
|
rgroup.long 0x0D14++0x03
|
|
line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
|
|
bitfld.long 0x00 31. " IRQS159 ,IRQS Status Bit 159" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS158 ,IRQS Status Bit 158" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS157 ,IRQS Status Bit 157" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS156 ,IRQS Status Bit 156" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS155 ,IRQS Status Bit 155" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS154 ,IRQS Status Bit 154" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS153 ,IRQS Status Bit 153" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS152 ,IRQS Status Bit 152" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS151 ,IRQS Status Bit 151" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS150 ,IRQS Status Bit 150" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS149 ,IRQS Status Bit 149" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS148 ,IRQS Status Bit 148" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS147 ,IRQS Status Bit 147" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS146 ,IRQS Status Bit 146" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS145 ,IRQS Status Bit 145" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS144 ,IRQS Status Bit 144" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS143 ,IRQS Status Bit 143" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS142 ,IRQS Status Bit 142" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS141 ,IRQS Status Bit 141" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS140 ,IRQS Status Bit 140" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS139 ,IRQS Status Bit 139" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS138 ,IRQS Status Bit 138" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS137 ,IRQS Status Bit 137" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS136 ,IRQS Status Bit 136" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS135 ,IRQS Status Bit 135" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS134 ,IRQS Status Bit 134" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS133 ,IRQS Status Bit 133" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS132 ,IRQS Status Bit 132" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS131 ,IRQS Status Bit 131" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS130 ,IRQS Status Bit 130" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS129 ,IRQS Status Bit 129" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS128 ,IRQS Status Bit 128" "Low,High"
|
|
else
|
|
hgroup.long 0x0D14++0x03
|
|
hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06)
|
|
rgroup.long 0x0D18++0x03
|
|
line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
|
|
bitfld.long 0x00 31. " IRQS191 ,IRQS Status Bit 191" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS190 ,IRQS Status Bit 190" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS189 ,IRQS Status Bit 189" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS188 ,IRQS Status Bit 188" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS187 ,IRQS Status Bit 187" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS186 ,IRQS Status Bit 186" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS185 ,IRQS Status Bit 185" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS184 ,IRQS Status Bit 184" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS183 ,IRQS Status Bit 183" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS182 ,IRQS Status Bit 182" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS181 ,IRQS Status Bit 181" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS180 ,IRQS Status Bit 180" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS179 ,IRQS Status Bit 179" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS178 ,IRQS Status Bit 178" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS177 ,IRQS Status Bit 177" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS176 ,IRQS Status Bit 176" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS175 ,IRQS Status Bit 175" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS174 ,IRQS Status Bit 174" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS173 ,IRQS Status Bit 173" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS172 ,IRQS Status Bit 172" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS171 ,IRQS Status Bit 171" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS170 ,IRQS Status Bit 170" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS169 ,IRQS Status Bit 169" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS168 ,IRQS Status Bit 168" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS167 ,IRQS Status Bit 167" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS166 ,IRQS Status Bit 166" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS165 ,IRQS Status Bit 165" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS164 ,IRQS Status Bit 164" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS163 ,IRQS Status Bit 163" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS162 ,IRQS Status Bit 162" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS161 ,IRQS Status Bit 161" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS160 ,IRQS Status Bit 160" "Low,High"
|
|
else
|
|
hgroup.long 0x0D18++0x03
|
|
hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07)
|
|
rgroup.long 0x0D1C++0x03
|
|
line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
|
|
bitfld.long 0x00 31. " IRQS223 ,IRQS Status Bit 223" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS222 ,IRQS Status Bit 222" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS221 ,IRQS Status Bit 221" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS220 ,IRQS Status Bit 220" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS219 ,IRQS Status Bit 219" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS218 ,IRQS Status Bit 218" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS217 ,IRQS Status Bit 217" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS216 ,IRQS Status Bit 216" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS215 ,IRQS Status Bit 215" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS214 ,IRQS Status Bit 214" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS213 ,IRQS Status Bit 213" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS212 ,IRQS Status Bit 212" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS211 ,IRQS Status Bit 211" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS210 ,IRQS Status Bit 210" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS209 ,IRQS Status Bit 209" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS208 ,IRQS Status Bit 208" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS207 ,IRQS Status Bit 207" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS206 ,IRQS Status Bit 206" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS205 ,IRQS Status Bit 205" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS204 ,IRQS Status Bit 204" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS203 ,IRQS Status Bit 203" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS202 ,IRQS Status Bit 202" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS201 ,IRQS Status Bit 201" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS200 ,IRQS Status Bit 200" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS199 ,IRQS Status Bit 199" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS198 ,IRQS Status Bit 198" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS197 ,IRQS Status Bit 197" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS196 ,IRQS Status Bit 196" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS195 ,IRQS Status Bit 195" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS194 ,IRQS Status Bit 194" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS193 ,IRQS Status Bit 193" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS192 ,IRQS Status Bit 192" "Low,High"
|
|
else
|
|
hgroup.long 0x0D1C++0x03
|
|
hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08)
|
|
rgroup.long 0x0D20++0x03
|
|
line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
|
|
bitfld.long 0x00 31. " IRQS255 ,IRQS Status Bit 255" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS254 ,IRQS Status Bit 254" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS253 ,IRQS Status Bit 253" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS252 ,IRQS Status Bit 252" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS251 ,IRQS Status Bit 251" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS250 ,IRQS Status Bit 250" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS249 ,IRQS Status Bit 249" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS248 ,IRQS Status Bit 248" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS247 ,IRQS Status Bit 247" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS246 ,IRQS Status Bit 246" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS245 ,IRQS Status Bit 245" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS244 ,IRQS Status Bit 244" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS243 ,IRQS Status Bit 243" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS242 ,IRQS Status Bit 242" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS241 ,IRQS Status Bit 241" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS240 ,IRQS Status Bit 240" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS239 ,IRQS Status Bit 239" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS238 ,IRQS Status Bit 238" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS237 ,IRQS Status Bit 237" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS236 ,IRQS Status Bit 236" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS235 ,IRQS Status Bit 235" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS234 ,IRQS Status Bit 234" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS233 ,IRQS Status Bit 233" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS232 ,IRQS Status Bit 232" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS231 ,IRQS Status Bit 231" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS230 ,IRQS Status Bit 230" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS229 ,IRQS Status Bit 229" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS228 ,IRQS Status Bit 228" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS227 ,IRQS Status Bit 227" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS226 ,IRQS Status Bit 226" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS225 ,IRQS Status Bit 225" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS224 ,IRQS Status Bit 224" "Low,High"
|
|
else
|
|
hgroup.long 0x0D20++0x03
|
|
hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09)
|
|
rgroup.long 0x0D24++0x03
|
|
line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
|
|
bitfld.long 0x00 31. " IRQS287 ,IRQS Status Bit 287" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS286 ,IRQS Status Bit 286" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS285 ,IRQS Status Bit 285" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS284 ,IRQS Status Bit 284" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS283 ,IRQS Status Bit 283" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS282 ,IRQS Status Bit 282" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS281 ,IRQS Status Bit 281" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS280 ,IRQS Status Bit 280" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS279 ,IRQS Status Bit 279" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS278 ,IRQS Status Bit 278" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS277 ,IRQS Status Bit 277" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS276 ,IRQS Status Bit 276" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS275 ,IRQS Status Bit 275" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS274 ,IRQS Status Bit 274" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS273 ,IRQS Status Bit 273" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS272 ,IRQS Status Bit 272" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS271 ,IRQS Status Bit 271" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS270 ,IRQS Status Bit 270" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS269 ,IRQS Status Bit 269" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS268 ,IRQS Status Bit 268" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS267 ,IRQS Status Bit 267" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS266 ,IRQS Status Bit 266" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS265 ,IRQS Status Bit 265" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS264 ,IRQS Status Bit 264" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS263 ,IRQS Status Bit 263" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS262 ,IRQS Status Bit 262" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS261 ,IRQS Status Bit 261" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS260 ,IRQS Status Bit 260" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS259 ,IRQS Status Bit 259" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS258 ,IRQS Status Bit 258" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS257 ,IRQS Status Bit 257" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS256 ,IRQS Status Bit 256" "Low,High"
|
|
else
|
|
hgroup.long 0x0D24++0x03
|
|
hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A)
|
|
rgroup.long 0x0D28++0x03
|
|
line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
|
|
bitfld.long 0x00 31. " IRQS319 ,IRQS Status Bit 319" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS318 ,IRQS Status Bit 318" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS317 ,IRQS Status Bit 317" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS316 ,IRQS Status Bit 316" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS315 ,IRQS Status Bit 315" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS314 ,IRQS Status Bit 314" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS313 ,IRQS Status Bit 313" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS312 ,IRQS Status Bit 312" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS311 ,IRQS Status Bit 311" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS310 ,IRQS Status Bit 310" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS309 ,IRQS Status Bit 309" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS308 ,IRQS Status Bit 308" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS307 ,IRQS Status Bit 307" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS306 ,IRQS Status Bit 306" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS305 ,IRQS Status Bit 305" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS304 ,IRQS Status Bit 304" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS303 ,IRQS Status Bit 303" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS302 ,IRQS Status Bit 302" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS301 ,IRQS Status Bit 301" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS300 ,IRQS Status Bit 300" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS299 ,IRQS Status Bit 299" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS298 ,IRQS Status Bit 298" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS297 ,IRQS Status Bit 297" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS296 ,IRQS Status Bit 296" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS295 ,IRQS Status Bit 295" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS294 ,IRQS Status Bit 294" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS293 ,IRQS Status Bit 293" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS292 ,IRQS Status Bit 292" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS291 ,IRQS Status Bit 291" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS290 ,IRQS Status Bit 290" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS289 ,IRQS Status Bit 289" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS288 ,IRQS Status Bit 288" "Low,High"
|
|
else
|
|
hgroup.long 0x0D28++0x03
|
|
hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B)
|
|
rgroup.long 0x0D2C++0x03
|
|
line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
|
|
bitfld.long 0x00 31. " IRQS351 ,IRQS Status Bit 351" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS350 ,IRQS Status Bit 350" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS349 ,IRQS Status Bit 349" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS348 ,IRQS Status Bit 348" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS347 ,IRQS Status Bit 347" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS346 ,IRQS Status Bit 346" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS345 ,IRQS Status Bit 345" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS344 ,IRQS Status Bit 344" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS343 ,IRQS Status Bit 343" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS342 ,IRQS Status Bit 342" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS341 ,IRQS Status Bit 341" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS340 ,IRQS Status Bit 340" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS339 ,IRQS Status Bit 339" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS338 ,IRQS Status Bit 338" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS337 ,IRQS Status Bit 337" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS336 ,IRQS Status Bit 336" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS335 ,IRQS Status Bit 335" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS334 ,IRQS Status Bit 334" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS333 ,IRQS Status Bit 333" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS332 ,IRQS Status Bit 332" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS331 ,IRQS Status Bit 331" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS330 ,IRQS Status Bit 330" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS329 ,IRQS Status Bit 329" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS328 ,IRQS Status Bit 328" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS327 ,IRQS Status Bit 327" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS326 ,IRQS Status Bit 326" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS325 ,IRQS Status Bit 325" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS324 ,IRQS Status Bit 324" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS323 ,IRQS Status Bit 323" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS322 ,IRQS Status Bit 322" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS321 ,IRQS Status Bit 321" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS320 ,IRQS Status Bit 320" "Low,High"
|
|
else
|
|
hgroup.long 0x0D2C++0x03
|
|
hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C)
|
|
rgroup.long 0x0D30++0x03
|
|
line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
|
|
bitfld.long 0x00 31. " IRQS383 ,IRQS Status Bit 383" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS382 ,IRQS Status Bit 382" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS381 ,IRQS Status Bit 381" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS380 ,IRQS Status Bit 380" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS379 ,IRQS Status Bit 379" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS378 ,IRQS Status Bit 378" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS377 ,IRQS Status Bit 377" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS376 ,IRQS Status Bit 376" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS375 ,IRQS Status Bit 375" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS374 ,IRQS Status Bit 374" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS373 ,IRQS Status Bit 373" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS372 ,IRQS Status Bit 372" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS371 ,IRQS Status Bit 371" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS370 ,IRQS Status Bit 370" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS369 ,IRQS Status Bit 369" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS368 ,IRQS Status Bit 368" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS367 ,IRQS Status Bit 367" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS366 ,IRQS Status Bit 366" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS365 ,IRQS Status Bit 365" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS364 ,IRQS Status Bit 364" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS363 ,IRQS Status Bit 363" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS362 ,IRQS Status Bit 362" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS361 ,IRQS Status Bit 361" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS360 ,IRQS Status Bit 360" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS359 ,IRQS Status Bit 359" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS358 ,IRQS Status Bit 358" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS357 ,IRQS Status Bit 357" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS356 ,IRQS Status Bit 356" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS355 ,IRQS Status Bit 355" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS354 ,IRQS Status Bit 354" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS353 ,IRQS Status Bit 353" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS352 ,IRQS Status Bit 352" "Low,High"
|
|
else
|
|
hgroup.long 0x0D30++0x03
|
|
hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D)
|
|
rgroup.long 0x0D34++0x03
|
|
line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
|
|
bitfld.long 0x00 31. " IRQS415 ,IRQS Status Bit 415" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS414 ,IRQS Status Bit 414" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS413 ,IRQS Status Bit 413" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS412 ,IRQS Status Bit 412" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS411 ,IRQS Status Bit 411" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS410 ,IRQS Status Bit 410" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS409 ,IRQS Status Bit 409" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS408 ,IRQS Status Bit 408" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS407 ,IRQS Status Bit 407" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS406 ,IRQS Status Bit 406" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS405 ,IRQS Status Bit 405" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS404 ,IRQS Status Bit 404" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS403 ,IRQS Status Bit 403" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS402 ,IRQS Status Bit 402" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS401 ,IRQS Status Bit 401" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS400 ,IRQS Status Bit 400" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS399 ,IRQS Status Bit 399" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS398 ,IRQS Status Bit 398" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS397 ,IRQS Status Bit 397" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS396 ,IRQS Status Bit 396" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS395 ,IRQS Status Bit 395" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS394 ,IRQS Status Bit 394" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS393 ,IRQS Status Bit 393" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS392 ,IRQS Status Bit 392" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS391 ,IRQS Status Bit 391" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS390 ,IRQS Status Bit 390" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS389 ,IRQS Status Bit 389" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS388 ,IRQS Status Bit 388" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS387 ,IRQS Status Bit 387" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS386 ,IRQS Status Bit 386" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS385 ,IRQS Status Bit 385" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS384 ,IRQS Status Bit 384" "Low,High"
|
|
else
|
|
hgroup.long 0x0D34++0x03
|
|
hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E)
|
|
rgroup.long 0x0D38++0x03
|
|
line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
|
|
bitfld.long 0x00 31. " IRQS447 ,IRQS Status Bit 447" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS446 ,IRQS Status Bit 446" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS445 ,IRQS Status Bit 445" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS444 ,IRQS Status Bit 444" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS443 ,IRQS Status Bit 443" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS442 ,IRQS Status Bit 442" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS441 ,IRQS Status Bit 441" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS440 ,IRQS Status Bit 440" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS439 ,IRQS Status Bit 439" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS438 ,IRQS Status Bit 438" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS437 ,IRQS Status Bit 437" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS436 ,IRQS Status Bit 436" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS435 ,IRQS Status Bit 435" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS434 ,IRQS Status Bit 434" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS433 ,IRQS Status Bit 433" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS432 ,IRQS Status Bit 432" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS431 ,IRQS Status Bit 431" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS430 ,IRQS Status Bit 430" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS429 ,IRQS Status Bit 429" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS428 ,IRQS Status Bit 428" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS427 ,IRQS Status Bit 427" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS426 ,IRQS Status Bit 426" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS425 ,IRQS Status Bit 425" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS424 ,IRQS Status Bit 424" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS423 ,IRQS Status Bit 423" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS422 ,IRQS Status Bit 422" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS421 ,IRQS Status Bit 421" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS420 ,IRQS Status Bit 420" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS419 ,IRQS Status Bit 419" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS418 ,IRQS Status Bit 418" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS417 ,IRQS Status Bit 417" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS416 ,IRQS Status Bit 416" "Low,High"
|
|
else
|
|
hgroup.long 0x0D38++0x03
|
|
hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F)
|
|
rgroup.long 0x0D3C++0x03
|
|
line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
|
|
bitfld.long 0x00 31. " IRQS479 ,IRQS Status Bit 479" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS478 ,IRQS Status Bit 478" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS477 ,IRQS Status Bit 477" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS476 ,IRQS Status Bit 476" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS475 ,IRQS Status Bit 475" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS474 ,IRQS Status Bit 474" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS473 ,IRQS Status Bit 473" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS472 ,IRQS Status Bit 472" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS471 ,IRQS Status Bit 471" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS470 ,IRQS Status Bit 470" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS469 ,IRQS Status Bit 469" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS468 ,IRQS Status Bit 468" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS467 ,IRQS Status Bit 467" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS466 ,IRQS Status Bit 466" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS465 ,IRQS Status Bit 465" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS464 ,IRQS Status Bit 464" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS463 ,IRQS Status Bit 463" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS462 ,IRQS Status Bit 462" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS461 ,IRQS Status Bit 461" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS460 ,IRQS Status Bit 460" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS459 ,IRQS Status Bit 459" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS458 ,IRQS Status Bit 458" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS457 ,IRQS Status Bit 457" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS456 ,IRQS Status Bit 456" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS455 ,IRQS Status Bit 455" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS454 ,IRQS Status Bit 454" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS453 ,IRQS Status Bit 453" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS452 ,IRQS Status Bit 452" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS451 ,IRQS Status Bit 451" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS450 ,IRQS Status Bit 450" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS449 ,IRQS Status Bit 449" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS448 ,IRQS Status Bit 448" "Low,High"
|
|
else
|
|
hgroup.long 0x0D3C++0x03
|
|
hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10)
|
|
rgroup.long 0x0D40++0x03
|
|
line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
|
|
bitfld.long 0x00 31. " IRQS511 ,IRQS Status Bit 511" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS510 ,IRQS Status Bit 510" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS509 ,IRQS Status Bit 509" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS508 ,IRQS Status Bit 508" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS507 ,IRQS Status Bit 507" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS506 ,IRQS Status Bit 506" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS505 ,IRQS Status Bit 505" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS504 ,IRQS Status Bit 504" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS503 ,IRQS Status Bit 503" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS502 ,IRQS Status Bit 502" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS501 ,IRQS Status Bit 501" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS500 ,IRQS Status Bit 500" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS499 ,IRQS Status Bit 499" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS498 ,IRQS Status Bit 498" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS497 ,IRQS Status Bit 497" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS496 ,IRQS Status Bit 496" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS495 ,IRQS Status Bit 495" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS494 ,IRQS Status Bit 494" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS493 ,IRQS Status Bit 493" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS492 ,IRQS Status Bit 492" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS491 ,IRQS Status Bit 491" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS490 ,IRQS Status Bit 490" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS489 ,IRQS Status Bit 489" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS488 ,IRQS Status Bit 488" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS487 ,IRQS Status Bit 487" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS486 ,IRQS Status Bit 486" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS485 ,IRQS Status Bit 485" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS484 ,IRQS Status Bit 484" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS483 ,IRQS Status Bit 483" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS482 ,IRQS Status Bit 482" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS481 ,IRQS Status Bit 481" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS480 ,IRQS Status Bit 480" "Low,High"
|
|
else
|
|
hgroup.long 0x0D40++0x03
|
|
hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11)
|
|
rgroup.long 0x0D44++0x03
|
|
line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
|
|
bitfld.long 0x00 31. " IRQS543 ,IRQS Status Bit 543" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS542 ,IRQS Status Bit 542" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS541 ,IRQS Status Bit 541" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS540 ,IRQS Status Bit 540" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS539 ,IRQS Status Bit 539" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS538 ,IRQS Status Bit 538" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS537 ,IRQS Status Bit 537" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS536 ,IRQS Status Bit 536" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS535 ,IRQS Status Bit 535" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS534 ,IRQS Status Bit 534" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS533 ,IRQS Status Bit 533" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS532 ,IRQS Status Bit 532" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS531 ,IRQS Status Bit 531" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS530 ,IRQS Status Bit 530" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS529 ,IRQS Status Bit 529" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS528 ,IRQS Status Bit 528" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS527 ,IRQS Status Bit 527" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS526 ,IRQS Status Bit 526" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS525 ,IRQS Status Bit 525" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS524 ,IRQS Status Bit 524" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS523 ,IRQS Status Bit 523" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS522 ,IRQS Status Bit 522" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS521 ,IRQS Status Bit 521" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS520 ,IRQS Status Bit 520" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS519 ,IRQS Status Bit 519" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS518 ,IRQS Status Bit 518" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS517 ,IRQS Status Bit 517" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS516 ,IRQS Status Bit 516" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS515 ,IRQS Status Bit 515" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS514 ,IRQS Status Bit 514" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS513 ,IRQS Status Bit 513" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS512 ,IRQS Status Bit 512" "Low,High"
|
|
else
|
|
hgroup.long 0x0D44++0x03
|
|
hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12)
|
|
rgroup.long 0x0D48++0x03
|
|
line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
|
|
bitfld.long 0x00 31. " IRQS575 ,IRQS Status Bit 575" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS574 ,IRQS Status Bit 574" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS573 ,IRQS Status Bit 573" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS572 ,IRQS Status Bit 572" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS571 ,IRQS Status Bit 571" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS570 ,IRQS Status Bit 570" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS569 ,IRQS Status Bit 569" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS568 ,IRQS Status Bit 568" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS567 ,IRQS Status Bit 567" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS566 ,IRQS Status Bit 566" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS565 ,IRQS Status Bit 565" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS564 ,IRQS Status Bit 564" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS563 ,IRQS Status Bit 563" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS562 ,IRQS Status Bit 562" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS561 ,IRQS Status Bit 561" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS560 ,IRQS Status Bit 560" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS559 ,IRQS Status Bit 559" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS558 ,IRQS Status Bit 558" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS557 ,IRQS Status Bit 557" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS556 ,IRQS Status Bit 556" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS555 ,IRQS Status Bit 555" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS554 ,IRQS Status Bit 554" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS553 ,IRQS Status Bit 553" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS552 ,IRQS Status Bit 552" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS551 ,IRQS Status Bit 551" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS550 ,IRQS Status Bit 550" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS549 ,IRQS Status Bit 549" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS548 ,IRQS Status Bit 548" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS547 ,IRQS Status Bit 547" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS546 ,IRQS Status Bit 546" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS545 ,IRQS Status Bit 545" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS544 ,IRQS Status Bit 544" "Low,High"
|
|
else
|
|
hgroup.long 0x0D48++0x03
|
|
hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13)
|
|
rgroup.long 0x0D4C++0x03
|
|
line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
|
|
bitfld.long 0x00 31. " IRQS607 ,IRQS Status Bit 607" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS606 ,IRQS Status Bit 606" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS605 ,IRQS Status Bit 605" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS604 ,IRQS Status Bit 604" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS603 ,IRQS Status Bit 603" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS602 ,IRQS Status Bit 602" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS601 ,IRQS Status Bit 601" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS600 ,IRQS Status Bit 600" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS599 ,IRQS Status Bit 599" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS598 ,IRQS Status Bit 598" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS597 ,IRQS Status Bit 597" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS596 ,IRQS Status Bit 596" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS595 ,IRQS Status Bit 595" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS594 ,IRQS Status Bit 594" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS593 ,IRQS Status Bit 593" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS592 ,IRQS Status Bit 592" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS591 ,IRQS Status Bit 591" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS590 ,IRQS Status Bit 590" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS589 ,IRQS Status Bit 589" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS588 ,IRQS Status Bit 588" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS587 ,IRQS Status Bit 587" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS586 ,IRQS Status Bit 586" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS585 ,IRQS Status Bit 585" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS584 ,IRQS Status Bit 584" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS583 ,IRQS Status Bit 583" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS582 ,IRQS Status Bit 582" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS581 ,IRQS Status Bit 581" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS580 ,IRQS Status Bit 580" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS579 ,IRQS Status Bit 579" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS578 ,IRQS Status Bit 578" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS577 ,IRQS Status Bit 577" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS576 ,IRQS Status Bit 576" "Low,High"
|
|
else
|
|
hgroup.long 0x0D4C++0x03
|
|
hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14)
|
|
rgroup.long 0x0D50++0x03
|
|
line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
|
|
bitfld.long 0x00 31. " IRQS639 ,IRQS Status Bit 639" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS638 ,IRQS Status Bit 638" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS637 ,IRQS Status Bit 637" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS636 ,IRQS Status Bit 636" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS635 ,IRQS Status Bit 635" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS634 ,IRQS Status Bit 634" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS633 ,IRQS Status Bit 633" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS632 ,IRQS Status Bit 632" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS631 ,IRQS Status Bit 631" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS630 ,IRQS Status Bit 630" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS629 ,IRQS Status Bit 629" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS628 ,IRQS Status Bit 628" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS627 ,IRQS Status Bit 627" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS626 ,IRQS Status Bit 626" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS625 ,IRQS Status Bit 625" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS624 ,IRQS Status Bit 624" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS623 ,IRQS Status Bit 623" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS622 ,IRQS Status Bit 622" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS621 ,IRQS Status Bit 621" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS620 ,IRQS Status Bit 620" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS619 ,IRQS Status Bit 619" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS618 ,IRQS Status Bit 618" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS617 ,IRQS Status Bit 617" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS616 ,IRQS Status Bit 616" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS615 ,IRQS Status Bit 615" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS614 ,IRQS Status Bit 614" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS613 ,IRQS Status Bit 613" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS612 ,IRQS Status Bit 612" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS611 ,IRQS Status Bit 611" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS610 ,IRQS Status Bit 610" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS609 ,IRQS Status Bit 609" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS608 ,IRQS Status Bit 608" "Low,High"
|
|
else
|
|
hgroup.long 0x0D50++0x03
|
|
hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15)
|
|
rgroup.long 0x0D54++0x03
|
|
line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
|
|
bitfld.long 0x00 31. " IRQS671 ,IRQS Status Bit 671" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS670 ,IRQS Status Bit 670" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS669 ,IRQS Status Bit 669" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS668 ,IRQS Status Bit 668" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS667 ,IRQS Status Bit 667" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS666 ,IRQS Status Bit 666" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS665 ,IRQS Status Bit 665" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS664 ,IRQS Status Bit 664" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS663 ,IRQS Status Bit 663" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS662 ,IRQS Status Bit 662" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS661 ,IRQS Status Bit 661" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS660 ,IRQS Status Bit 660" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS659 ,IRQS Status Bit 659" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS658 ,IRQS Status Bit 658" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS657 ,IRQS Status Bit 657" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS656 ,IRQS Status Bit 656" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS655 ,IRQS Status Bit 655" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS654 ,IRQS Status Bit 654" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS653 ,IRQS Status Bit 653" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS652 ,IRQS Status Bit 652" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS651 ,IRQS Status Bit 651" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS650 ,IRQS Status Bit 650" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS649 ,IRQS Status Bit 649" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS648 ,IRQS Status Bit 648" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS647 ,IRQS Status Bit 647" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS646 ,IRQS Status Bit 646" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS645 ,IRQS Status Bit 645" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS644 ,IRQS Status Bit 644" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS643 ,IRQS Status Bit 643" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS642 ,IRQS Status Bit 642" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS641 ,IRQS Status Bit 641" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS640 ,IRQS Status Bit 640" "Low,High"
|
|
else
|
|
hgroup.long 0x0D54++0x03
|
|
hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16)
|
|
rgroup.long 0x0D58++0x03
|
|
line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
|
|
bitfld.long 0x00 31. " IRQS703 ,IRQS Status Bit 703" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS702 ,IRQS Status Bit 702" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS701 ,IRQS Status Bit 701" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS700 ,IRQS Status Bit 700" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS699 ,IRQS Status Bit 699" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS698 ,IRQS Status Bit 698" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS697 ,IRQS Status Bit 697" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS696 ,IRQS Status Bit 696" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS695 ,IRQS Status Bit 695" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS694 ,IRQS Status Bit 694" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS693 ,IRQS Status Bit 693" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS692 ,IRQS Status Bit 692" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS691 ,IRQS Status Bit 691" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS690 ,IRQS Status Bit 690" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS689 ,IRQS Status Bit 689" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS688 ,IRQS Status Bit 688" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS687 ,IRQS Status Bit 687" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS686 ,IRQS Status Bit 686" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS685 ,IRQS Status Bit 685" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS684 ,IRQS Status Bit 684" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS683 ,IRQS Status Bit 683" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS682 ,IRQS Status Bit 682" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS681 ,IRQS Status Bit 681" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS680 ,IRQS Status Bit 680" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS679 ,IRQS Status Bit 679" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS678 ,IRQS Status Bit 678" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS677 ,IRQS Status Bit 677" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS676 ,IRQS Status Bit 676" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS675 ,IRQS Status Bit 675" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS674 ,IRQS Status Bit 674" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS673 ,IRQS Status Bit 673" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS672 ,IRQS Status Bit 672" "Low,High"
|
|
else
|
|
hgroup.long 0x0D58++0x03
|
|
hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17)
|
|
rgroup.long 0x0D5C++0x03
|
|
line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
|
|
bitfld.long 0x00 31. " IRQS735 ,IRQS Status Bit 735" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS734 ,IRQS Status Bit 734" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS733 ,IRQS Status Bit 733" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS732 ,IRQS Status Bit 732" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS731 ,IRQS Status Bit 731" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS730 ,IRQS Status Bit 730" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS729 ,IRQS Status Bit 729" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS728 ,IRQS Status Bit 728" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS727 ,IRQS Status Bit 727" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS726 ,IRQS Status Bit 726" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS725 ,IRQS Status Bit 725" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS724 ,IRQS Status Bit 724" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS723 ,IRQS Status Bit 723" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS722 ,IRQS Status Bit 722" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS721 ,IRQS Status Bit 721" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS720 ,IRQS Status Bit 720" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS719 ,IRQS Status Bit 719" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS718 ,IRQS Status Bit 718" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS717 ,IRQS Status Bit 717" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS716 ,IRQS Status Bit 716" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS715 ,IRQS Status Bit 715" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS714 ,IRQS Status Bit 714" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS713 ,IRQS Status Bit 713" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS712 ,IRQS Status Bit 712" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS711 ,IRQS Status Bit 711" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS710 ,IRQS Status Bit 710" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS709 ,IRQS Status Bit 709" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS708 ,IRQS Status Bit 708" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS707 ,IRQS Status Bit 707" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS706 ,IRQS Status Bit 706" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS705 ,IRQS Status Bit 705" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS704 ,IRQS Status Bit 704" "Low,High"
|
|
else
|
|
hgroup.long 0x0D5C++0x03
|
|
hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18)
|
|
rgroup.long 0x060++0x03
|
|
line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
|
|
bitfld.long 0x00 31. " IRQS767 ,IRQS Status Bit 767" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS766 ,IRQS Status Bit 766" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS765 ,IRQS Status Bit 765" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS764 ,IRQS Status Bit 764" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS763 ,IRQS Status Bit 763" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS762 ,IRQS Status Bit 762" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS761 ,IRQS Status Bit 761" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS760 ,IRQS Status Bit 760" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS759 ,IRQS Status Bit 759" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS758 ,IRQS Status Bit 758" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS757 ,IRQS Status Bit 757" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS756 ,IRQS Status Bit 756" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS755 ,IRQS Status Bit 755" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS754 ,IRQS Status Bit 754" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS753 ,IRQS Status Bit 753" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS752 ,IRQS Status Bit 752" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS751 ,IRQS Status Bit 751" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS750 ,IRQS Status Bit 750" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS749 ,IRQS Status Bit 749" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS748 ,IRQS Status Bit 748" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS747 ,IRQS Status Bit 747" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS746 ,IRQS Status Bit 746" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS745 ,IRQS Status Bit 745" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS744 ,IRQS Status Bit 744" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS743 ,IRQS Status Bit 743" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS742 ,IRQS Status Bit 742" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS741 ,IRQS Status Bit 741" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS740 ,IRQS Status Bit 740" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS739 ,IRQS Status Bit 739" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS738 ,IRQS Status Bit 738" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS737 ,IRQS Status Bit 737" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS736 ,IRQS Status Bit 736" "Low,High"
|
|
else
|
|
hgroup.long 0x0D60++0x03
|
|
hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19)
|
|
rgroup.long 0x0D64++0x03
|
|
line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
|
|
bitfld.long 0x00 31. " IRQS799 ,IRQS Status Bit 799" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS798 ,IRQS Status Bit 798" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS797 ,IRQS Status Bit 797" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS796 ,IRQS Status Bit 796" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS795 ,IRQS Status Bit 795" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS794 ,IRQS Status Bit 794" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS793 ,IRQS Status Bit 793" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS792 ,IRQS Status Bit 792" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS791 ,IRQS Status Bit 791" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS790 ,IRQS Status Bit 790" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS789 ,IRQS Status Bit 789" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS788 ,IRQS Status Bit 788" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS787 ,IRQS Status Bit 787" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS786 ,IRQS Status Bit 786" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS785 ,IRQS Status Bit 785" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS784 ,IRQS Status Bit 784" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS783 ,IRQS Status Bit 783" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS782 ,IRQS Status Bit 782" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS781 ,IRQS Status Bit 781" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS780 ,IRQS Status Bit 780" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS779 ,IRQS Status Bit 779" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS778 ,IRQS Status Bit 778" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS777 ,IRQS Status Bit 777" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS776 ,IRQS Status Bit 776" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS775 ,IRQS Status Bit 775" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS774 ,IRQS Status Bit 774" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS773 ,IRQS Status Bit 773" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS772 ,IRQS Status Bit 772" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS771 ,IRQS Status Bit 771" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS770 ,IRQS Status Bit 770" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS769 ,IRQS Status Bit 769" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS768 ,IRQS Status Bit 768" "Low,High"
|
|
else
|
|
hgroup.long 0x0D64++0x03
|
|
hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A)
|
|
rgroup.long 0x0D68++0x03
|
|
line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
|
|
bitfld.long 0x00 31. " IRQS831 ,IRQS Status Bit 831" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS830 ,IRQS Status Bit 830" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS829 ,IRQS Status Bit 829" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS828 ,IRQS Status Bit 828" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS827 ,IRQS Status Bit 827" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS826 ,IRQS Status Bit 826" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS825 ,IRQS Status Bit 825" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS824 ,IRQS Status Bit 824" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS823 ,IRQS Status Bit 823" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS822 ,IRQS Status Bit 822" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS821 ,IRQS Status Bit 821" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS820 ,IRQS Status Bit 820" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS819 ,IRQS Status Bit 819" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS818 ,IRQS Status Bit 818" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS817 ,IRQS Status Bit 817" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS816 ,IRQS Status Bit 816" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS815 ,IRQS Status Bit 815" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS814 ,IRQS Status Bit 814" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS813 ,IRQS Status Bit 813" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS812 ,IRQS Status Bit 812" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS811 ,IRQS Status Bit 811" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS810 ,IRQS Status Bit 810" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS809 ,IRQS Status Bit 809" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS808 ,IRQS Status Bit 808" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS807 ,IRQS Status Bit 807" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS806 ,IRQS Status Bit 806" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS805 ,IRQS Status Bit 805" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS804 ,IRQS Status Bit 804" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS803 ,IRQS Status Bit 803" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS802 ,IRQS Status Bit 802" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS801 ,IRQS Status Bit 801" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS800 ,IRQS Status Bit 800" "Low,High"
|
|
else
|
|
hgroup.long 0x0D68++0x03
|
|
hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B)
|
|
rgroup.long 0x0D6C++0x03
|
|
line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
|
|
bitfld.long 0x00 31. " IRQS863 ,IRQS Status Bit 863" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS862 ,IRQS Status Bit 862" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS861 ,IRQS Status Bit 861" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS860 ,IRQS Status Bit 860" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS859 ,IRQS Status Bit 859" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS858 ,IRQS Status Bit 858" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS857 ,IRQS Status Bit 857" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS856 ,IRQS Status Bit 856" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS855 ,IRQS Status Bit 855" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS854 ,IRQS Status Bit 854" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS853 ,IRQS Status Bit 853" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS852 ,IRQS Status Bit 852" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS851 ,IRQS Status Bit 851" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS850 ,IRQS Status Bit 850" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS849 ,IRQS Status Bit 849" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS848 ,IRQS Status Bit 848" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS847 ,IRQS Status Bit 847" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS846 ,IRQS Status Bit 846" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS845 ,IRQS Status Bit 845" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS844 ,IRQS Status Bit 844" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS843 ,IRQS Status Bit 843" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS842 ,IRQS Status Bit 842" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS841 ,IRQS Status Bit 841" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS840 ,IRQS Status Bit 840" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS839 ,IRQS Status Bit 839" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS838 ,IRQS Status Bit 838" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS837 ,IRQS Status Bit 837" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS836 ,IRQS Status Bit 836" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS835 ,IRQS Status Bit 835" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS834 ,IRQS Status Bit 834" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS833 ,IRQS Status Bit 833" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS832 ,IRQS Status Bit 832" "Low,High"
|
|
else
|
|
hgroup.long 0x0D6C++0x03
|
|
hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C)
|
|
rgroup.long 0x0D70++0x03
|
|
line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
|
|
bitfld.long 0x00 31. " IRQS895 ,IRQS Status Bit 895" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS894 ,IRQS Status Bit 894" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS893 ,IRQS Status Bit 893" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS892 ,IRQS Status Bit 892" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS891 ,IRQS Status Bit 891" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS890 ,IRQS Status Bit 890" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS889 ,IRQS Status Bit 889" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS888 ,IRQS Status Bit 888" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS887 ,IRQS Status Bit 887" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS886 ,IRQS Status Bit 886" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS885 ,IRQS Status Bit 885" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS884 ,IRQS Status Bit 884" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS883 ,IRQS Status Bit 883" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS882 ,IRQS Status Bit 882" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS881 ,IRQS Status Bit 881" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS880 ,IRQS Status Bit 880" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS879 ,IRQS Status Bit 879" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS878 ,IRQS Status Bit 878" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS877 ,IRQS Status Bit 877" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS876 ,IRQS Status Bit 876" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS875 ,IRQS Status Bit 875" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS874 ,IRQS Status Bit 874" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS873 ,IRQS Status Bit 873" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS872 ,IRQS Status Bit 872" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS871 ,IRQS Status Bit 871" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS870 ,IRQS Status Bit 870" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS869 ,IRQS Status Bit 869" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS868 ,IRQS Status Bit 868" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS867 ,IRQS Status Bit 867" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS866 ,IRQS Status Bit 866" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS865 ,IRQS Status Bit 865" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS864 ,IRQS Status Bit 864" "Low,High"
|
|
else
|
|
hgroup.long 0x0D70++0x03
|
|
hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D)
|
|
rgroup.long 0x0D74++0x03
|
|
line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
|
|
bitfld.long 0x00 31. " IRQS927 ,IRQS Status Bit 927" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS926 ,IRQS Status Bit 926" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS925 ,IRQS Status Bit 925" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS924 ,IRQS Status Bit 924" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS923 ,IRQS Status Bit 923" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS922 ,IRQS Status Bit 922" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS921 ,IRQS Status Bit 921" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS920 ,IRQS Status Bit 920" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS919 ,IRQS Status Bit 919" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS918 ,IRQS Status Bit 918" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS917 ,IRQS Status Bit 917" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS916 ,IRQS Status Bit 916" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS915 ,IRQS Status Bit 915" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS914 ,IRQS Status Bit 914" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS913 ,IRQS Status Bit 913" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS912 ,IRQS Status Bit 912" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS911 ,IRQS Status Bit 911" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS910 ,IRQS Status Bit 910" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS909 ,IRQS Status Bit 909" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS908 ,IRQS Status Bit 908" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS907 ,IRQS Status Bit 907" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS906 ,IRQS Status Bit 906" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS905 ,IRQS Status Bit 905" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS904 ,IRQS Status Bit 904" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS903 ,IRQS Status Bit 903" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS902 ,IRQS Status Bit 902" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS901 ,IRQS Status Bit 901" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS900 ,IRQS Status Bit 900" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS899 ,IRQS Status Bit 899" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS898 ,IRQS Status Bit 898" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS897 ,IRQS Status Bit 897" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS896 ,IRQS Status Bit 896" "Low,High"
|
|
else
|
|
hgroup.long 0x0D74++0x03
|
|
hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E)
|
|
rgroup.long 0x0D78++0x03
|
|
line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
|
|
bitfld.long 0x00 31. " IRQS959 ,IRQS Status Bit 959" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS958 ,IRQS Status Bit 958" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS957 ,IRQS Status Bit 957" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS956 ,IRQS Status Bit 956" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS955 ,IRQS Status Bit 955" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS954 ,IRQS Status Bit 954" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS953 ,IRQS Status Bit 953" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS952 ,IRQS Status Bit 952" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS951 ,IRQS Status Bit 951" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS950 ,IRQS Status Bit 950" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS949 ,IRQS Status Bit 949" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS948 ,IRQS Status Bit 948" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS947 ,IRQS Status Bit 947" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS946 ,IRQS Status Bit 946" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS945 ,IRQS Status Bit 945" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS944 ,IRQS Status Bit 944" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS943 ,IRQS Status Bit 943" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS942 ,IRQS Status Bit 942" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS941 ,IRQS Status Bit 941" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS940 ,IRQS Status Bit 940" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS939 ,IRQS Status Bit 939" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS938 ,IRQS Status Bit 938" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS937 ,IRQS Status Bit 937" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS936 ,IRQS Status Bit 936" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS935 ,IRQS Status Bit 935" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS934 ,IRQS Status Bit 934" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS933 ,IRQS Status Bit 933" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS932 ,IRQS Status Bit 932" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS931 ,IRQS Status Bit 931" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS930 ,IRQS Status Bit 930" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS929 ,IRQS Status Bit 929" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS928 ,IRQS Status Bit 928" "Low,High"
|
|
else
|
|
hgroup.long 0x0D78++0x03
|
|
hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1F)
|
|
rgroup.long 0x0D7C++0x03
|
|
line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30"
|
|
bitfld.long 0x00 27. " IRQS987 ,IRQS Status Bit 987" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS986 ,IRQS Status Bit 986" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS985 ,IRQS Status Bit 985" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS984 ,IRQS Status Bit 984" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS983 ,IRQS Status Bit 983" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS982 ,IRQS Status Bit 982" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS981 ,IRQS Status Bit 981" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS980 ,IRQS Status Bit 980" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS979 ,IRQS Status Bit 979" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS978 ,IRQS Status Bit 978" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS977 ,IRQS Status Bit 977" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS976 ,IRQS Status Bit 976" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS975 ,IRQS Status Bit 975" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS974 ,IRQS Status Bit 974" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS973 ,IRQS Status Bit 973" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS972 ,IRQS Status Bit 972" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS971 ,IRQS Status Bit 971" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS970 ,IRQS Status Bit 970" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS969 ,IRQS Status Bit 969" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS968 ,IRQS Status Bit 968" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS967 ,IRQS Status Bit 967" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS966 ,IRQS Status Bit 966" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS965 ,IRQS Status Bit 965" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS964 ,IRQS Status Bit 964" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS963 ,IRQS Status Bit 963" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS962 ,IRQS Status Bit 962" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS961 ,IRQS Status Bit 961" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS960 ,IRQS Status Bit 960" "Low,High"
|
|
else
|
|
hgroup.long 0x0D7C++0x03
|
|
hide.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 25.
|
|
tree "Software Generated Interrupt"
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400)
|
|
wgroup.long 0x0F00++0x03
|
|
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
|
|
bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NSATT ,NSATT" "Secure,Non-secure"
|
|
bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
wgroup.long 0x0F00++0x03
|
|
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
|
|
bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x0F20++0x03
|
|
line.long 0x00 "GICD_SET/CLR_PENDSGIR0,SGI Set/Clear Pending Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
group.long 0x0F24++0x03
|
|
line.long 0x00 "GICD_SET/CLR_PENDSGIR1,SGI Set/Clear Pending Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
group.long 0x0F28++0x03
|
|
line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
group.long 0x0F2C++0x03
|
|
line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
|
|
tree.end
|
|
width 12.
|
|
tree "Peripheral/Component ID Registers"
|
|
rgroup.byte 0x0FE0++0x00
|
|
line.byte 0x00 "GICD_PIDR0,Peripheral ID0 Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DEVID ,DevID field"
|
|
rgroup.byte 0x0FE4++0x00
|
|
line.byte 0x00 "GICD_PIDR1,Peripheral ID1 Register"
|
|
bitfld.byte 0x00 4.--7. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " DEVID ,DevID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0x0FE8++0x00
|
|
line.byte 0x00 "GICD_PIDR2,Peripheral ID2 Register"
|
|
bitfld.byte 0x00 4.--7. " ARCHREV ,ArchRev field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 3. " UJEPCODE ,UsesJEPcode field" "Low,High"
|
|
bitfld.byte 0x00 0.--2. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7"
|
|
rgroup.byte 0x0FEC++0x00
|
|
line.byte 0x00 "GICD_PIDR3,Peripheral ID3 Register"
|
|
bitfld.byte 0x00 4.--7. " REVID ,Revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0x0FD0++0x00
|
|
line.byte 0x00 "GICD_PIDR4,Peripheral ID4 Register"
|
|
bitfld.byte 0x00 0.--3. " CC ,ContinuationCode field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.byte 0xFD4++0x00
|
|
hide.byte 0x00 "GICD_PIDR5,Peripheral ID5 Register"
|
|
hgroup.byte 0xFD8++0x00
|
|
hide.byte 0x00 "GICD_PIDR6,Peripheral ID6 Register"
|
|
hgroup.byte 0xFDC++0x00
|
|
hide.byte 0x00 "GICD_PIDR7,Peripheral ID7 Register"
|
|
textline " "
|
|
rgroup.byte 0xFF0++0x00
|
|
line.byte 0x00 "GICD_CIDR0,Component ID0 Register"
|
|
hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.byte 0xFF4++0x00
|
|
line.byte 0x00 "GICD_CIDR1,Component ID1 Register"
|
|
hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.byte 0xFF8++0x00
|
|
line.byte 0x00 "GICD_CIDR2,Component ID2 Register"
|
|
hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.byte 0xFFC++0x00
|
|
line.byte 0x00 "GICD_CIDR3,Component ID3 Register"
|
|
hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
textline " "
|
|
tree.end
|
|
tree.end
|
|
base AD:(per.long(c15:0x400F)&0xffff8000)+0x100
|
|
width 17.
|
|
tree "CPU Interface"
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x0)
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
|
|
bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop"
|
|
bitfld.long 0x00 6. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled"
|
|
bitfld.long 0x00 5. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
else
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Non-secure access)"
|
|
bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop"
|
|
bitfld.long 0x00 6. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled"
|
|
bitfld.long 0x00 5. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
group.long 0x0004++0x03
|
|
line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface"
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400)
|
|
group.long 0x0008++0x03
|
|
line.long 0x00 "GICC_BPR,Binary Point Register (Non-secure access)"
|
|
bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
else
|
|
group.long 0x0008++0x03
|
|
line.long 0x00 "GICC_BPR,Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
endif
|
|
hgroup.long 0x000C++0x03
|
|
hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register"
|
|
in
|
|
wgroup.long 0x0010++0x03
|
|
line.long 0x00 "GICC_EOIR,End Of Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access"
|
|
rgroup.long 0x0014++0x03
|
|
line.long 0x00 "GICC_RPR,Running Priority Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the CPU interface"
|
|
rgroup.long 0x0018++0x03
|
|
line.long 0x00 "GICC_HPIR,Highest Priority Pending Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt"
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400)
|
|
group.long 0x001C++0x03
|
|
line.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
else
|
|
hgroup.long 0x001C++0x03
|
|
hide.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
|
|
endif
|
|
hgroup.long 0x0020++0x003
|
|
hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register"
|
|
in
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400)
|
|
wgroup.long 0x0024++0x03
|
|
line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access"
|
|
rgroup.long 0x0028++0x03
|
|
line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt"
|
|
else
|
|
hgroup.long 0x0024++0x03
|
|
hide.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register"
|
|
hgroup.long 0x0028++0x03
|
|
hide.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
|
|
endif
|
|
group.long 0x00D0++0x03
|
|
line.long 0x00 "GICC_APR0,Active Priorities Register"
|
|
if (((per.l(AD:(per.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400)
|
|
group.long 0x00E0++0x03
|
|
line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register"
|
|
else
|
|
hgroup.long 0x00E0++0x03
|
|
hide.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register"
|
|
endif
|
|
rgroup.long 0x00FC++0x03
|
|
line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID"
|
|
bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv1,GICv2,GICv2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer"
|
|
wgroup.long 0x1000++0x03
|
|
line.long 0x00 "GICC_DIR,Deactivate Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " INTID ,The interrupt ID"
|
|
tree.end
|
|
sif CPU.FEATURE(hypervisor)
|
|
base AD:0x0
|
|
width 12.
|
|
tree "Virtual CPU Control Interface"
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICH_HCR,Hypervisor Control Register"
|
|
bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " VGRP1DIE ,VM Disable Group 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VGRP1EIE ,VM Enable Group 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VGRP0DIE ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VGRP0EIE ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
rgroup.long 0x0004++0x03
|
|
line.long 0x00 "GICH_VTR,VGIC Type Register"
|
|
bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRI levels,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRE levels,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " LISTREGS ,List regs number" "Reserved,Reserved,Reserved,4 lists,?..."
|
|
group.long 0x008++0x03
|
|
line.long 0x00 "GICH_VMCR,Virtual Machine Control Register"
|
|
bitfld.long 0x00 27.--31. " VMPRIMASK ,Alias of GICV_PMR.Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " VMBP ,Alias of GICV_BPR.Binary point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. " VMABP ,Alias of GICV_ABPR.Binary point" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VEM ,Alias of GICV_CTLR.EOImode" "0,1"
|
|
bitfld.long 0x00 4. " VMCBPR ,Alias of GICV_CTLR.CBPR" "0,1"
|
|
bitfld.long 0x00 3. " VMFIQEN ,Alias of GICV_CTLR.FIQEn" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VMACKCTL ,Alias of GICV_CTLR.AckCtl" "0,1"
|
|
bitfld.long 0x00 1. " VMGRP1EN ,Alias of GICV_CTLR.EnableGrp1" "0,1"
|
|
bitfld.long 0x00 0. " VMGRP0EN ,Alias of GICV_CTLR.EnableGrp0" "0,1"
|
|
rgroup.long 0x0010++0x03
|
|
line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register"
|
|
bitfld.long 0x00 7. " VGRP1D ,Disabled Group 1 maintenance interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " VGRP1E ,Enabled Group 1 maintenance interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " VGRP0D ,Disabled Group 0 maintenance interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VGRP0E ,Enabled Group 0 maintenance interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " U ,Underflow maintenance interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " EOI ,EOI maintenance interrupt" "No interrupt,Interrupt"
|
|
rgroup.long 0x020++0x03
|
|
line.long 0x00 "GICH_EISR0,End of Interrupt Status Register"
|
|
bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt"
|
|
rgroup.long 0x0030++0x03
|
|
line.long 0x00 "GICH_ELSR0,Empty List register Status Register"
|
|
bitfld.long 0x00 3. " STATUS3 ,Emptiness status bit for List register 3" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " STATUS2 ,Emptiness status bit for List register 2" "Not empty,Empty"
|
|
bitfld.long 0x00 1. " STATUS1 ,Emptiness status bit for List register 1" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STATUS0 ,Emptiness status bit for List register 0" "Not empty,Empty"
|
|
group.long 0x00F0++0x03
|
|
line.long 0x00 "GICH_APR0,Active Priorities Register"
|
|
bitfld.long 0x00 31. " APB31 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 30. " APB30 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 29. " APB29 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " APB28 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 27. " APB27 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 26. " APB26 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " APB25 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 24. " APB24 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 23. " APB23 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " APB22 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 21. " APB21 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 20. " APB20 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " APB19 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 18. " APB18 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 17. " APB17 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " APB16 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 15. " APB15 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 14. " APB14 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " APB13 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 12. " APB12 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 11. " APB11 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " APB10 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 9. " APB9 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 8. " APB8 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " APB7 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 6. " APB6 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 5. " APB5 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " APB4 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 3. " APB3 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 2. " APB2 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " APB1 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 0. " APB0 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
if (((per.l(AD:0x0+0x100))&0x80000000)==0x80000000)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GICH_LR0,List Register 0"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor"
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GICH_LR0,List Register 0"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted"
|
|
bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
|
|
endif
|
|
if (((per.l(AD:0x0+0x104))&0x80000000)==0x80000000)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "GICH_LR1,List Register 1"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor"
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "GICH_LR1,List Register 1"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted"
|
|
bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
|
|
endif
|
|
if (((per.l(AD:0x0+0x108))&0x80000000)==0x80000000)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "GICH_LR2,List Register 2"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor"
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
|
|
else
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "GICH_LR2,List Register 2"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted"
|
|
bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
|
|
endif
|
|
if (((per.l(AD:0x0+0x10C))&0x80000000)==0x80000000)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "GICH_LR3,List Register 3"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor"
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "GICH_LR3,List Register 3"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted"
|
|
bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
|
|
endif
|
|
tree.end
|
|
base AD:0x0
|
|
width 12.
|
|
tree "Virtual CPU Interface"
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICV_CTLR,Virtual Machine Control Register"
|
|
bitfld.long 0x00 9. " EOIMODE ,Controls the behavior associated with the GICV_EOIR GICV_AEOIR and GICV_DIR registers" "Priority drop/Deactivate,Priority drop"
|
|
bitfld.long 0x00 4. " CBPR ,Controls whether the GICV_BPR controls both Group 0 and Group 1 virtual interrupts" "BPR/ABPR split,BPR common"
|
|
bitfld.long 0x00 3. " FIQEN ,Controls whether interrupts marked as Group 0 are presented as virtual FIQs" "IRQs,FIQs"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACKCTL ,Acknowledge Control" "ID 1022 interrupt,Corresponding interrupt"
|
|
bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled"
|
|
group.long 0x0004++0x03
|
|
line.long 0x00 "GICV_PMR,VM Priority Mask Register"
|
|
bitfld.long 0x00 3.--7. " PRIORITY ,Priority mask level for CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x0008++0x03
|
|
line.long 0x00 "GICV_BPR,VM Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
hgroup.long 0x000C++0x03
|
|
hide.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register"
|
|
in
|
|
wgroup.long 0x0010++0x03
|
|
line.long 0x00 "GICV_EOIR,VM End of Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access"
|
|
rgroup.long 0x0014++0x03
|
|
line.long 0x00 "GICV_RPR,VM Running Priority Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the Virtual CPU interface"
|
|
rgroup.long 0x0018++0x03
|
|
line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt"
|
|
group.long 0x001C++0x03
|
|
line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
hgroup.long 0x0020++0x03
|
|
hide.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register"
|
|
in
|
|
wgroup.long 0x0024++0x03
|
|
line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access"
|
|
rgroup.long 0x0028++0x03
|
|
line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt"
|
|
group.long 0x00D0++0x03
|
|
line.long 0x00 "GICV_APR0,VM Active Priority Register"
|
|
bitfld.long 0x00 31. " APB31 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 30. " APB30 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 29. " APB29 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " APB28 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 27. " APB27 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 26. " APB26 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " APB25 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 24. " APB24 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 23. " APB23 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " APB22 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 21. " APB21 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 20. " APB20 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " APB19 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 18. " APB18 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 17. " APB17 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " APB16 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 15. " APB15 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 14. " APB14 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " APB13 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 12. " APB12 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 11. " APB11 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " APB10 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 9. " APB9 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 8. " APB8 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " APB7 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 6. " APB6 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 5. " APB5 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " APB4 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 3. " APB3 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 2. " APB2 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " APB1 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
bitfld.long 0x00 0. " APB0 ,Determines whether the corresponding preemption level is active" "Not active,Active"
|
|
rgroup.long 0x00FC++0x03
|
|
line.long 0x00 "GICV_IIDR,VM CPU Interface Identification Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID"
|
|
bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer"
|
|
wgroup.long 0x1000++0x03
|
|
line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " INTID ,The interrupt ID"
|
|
tree.end
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
autoindent.on center tree
|
|
tree "ASIC_CTRL"
|
|
base ad:0xF4080100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "io_config,IO Config Register: Selects of output pin multiplexing"
|
|
bitfld.long 0x00 31. "sel_lcd_col_b,select outputs for Couloured LCD Display position b (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "sel_lcd_col_a,select outputs for Couloured LCD Display position a (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "sel_lcd_bw,select outputs for Black and White LCD Display (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "sel_pwm7,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "sel_pwm6,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "sel_pwm5,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 25. "sel_pwm4,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "sel_pwm3,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "sel_pwm2,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "sel_pwm1,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 21. "sel_pwm0,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "sel_lvds2mii1,select interface for LVDS2MII1" "0: none (connect neither to ETH nor to XC),1: connect to XC1 (disables connection of XC1 to,2: connect to XC3 (disables connection of XC3 to,3: connect to ETH (disables connection of ETH to"
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|
newline
|
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bitfld.long 0x00 17.--18. "sel_lvds2mii0,select interface for LVDS2MII0" "0: none (connect neither to ETH nor to XC),1: connect to XC0 (disables connection of XC0 to,2: connect to XC2 (disables connection of XC2 to,3: connect to ETH (disables connection of ETH to"
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|
newline
|
|
bitfld.long 0x00 16. "usb2jtag_en,global enable of USB2JTAG debug feature: Note: Addionally USB2JTAG debugging requires an enable from USB_DEV module which is only active if USB_DEV module is running and connection is established (s. usb_dev_cfg-usb_to_jtag_enable)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "sel_fb11clk,select pad for fieldbus-clk11 (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "sel_xm11_eclk,select pad for xMAC11 eclk (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 13. "sel_xm11_txoe,select pad for xMAC11 tx-bitstream direct output enable (s. pinning table)" "0,1"
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|
newline
|
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bitfld.long 0x00 12. "sel_xm11_tx,select pad for xMAC11 tx-bitstream direct output (s. pinning table)" "0,1"
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newline
|
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bitfld.long 0x00 11. "sel_fb10clk,select pad for fieldbus-clk10 (s. pinning table)" "0,1"
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newline
|
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bitfld.long 0x00 10. "sel_xm10_eclk,select pad for xMAC10 eclk (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "sel_xm10_txoe,select pad for xMAC10 tx-bitstream direct output enable (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "sel_xm10_tx,select pad for xMAC10 tx-bitstream direct output (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "sel_fb01clk,select pad for fieldbus-clk01 (s. pinning table)" "0,1"
|
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newline
|
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bitfld.long 0x00 6. "sel_xm01_eclk,select pad for xMAC01 eclk (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "sel_xm01_txoe,select pad for xMAC01 tx-bitstream direct output enable (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "sel_xm01_tx,select pad for xMAC01 tx-bitstream direct output (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "sel_fb00clk,select pad for fieldbus-clk00 (s. pinning table)" "0,1"
|
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newline
|
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bitfld.long 0x00 2. "sel_xm00_eclk,select pad for xMAC00 eclk (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "sel_xm00_txoe,select pad for xMAC00 tx-bitstream direct output enable (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "sel_xm00_tx,select pad for xMAC00 tx-bitstream direct output (s. pinning table)" "0,1"
|
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group.long 0x04++0x03
|
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line.long 0x00 "io_config_mask,IO Config Mask Register: This register might be used to lock special IO configurations for restricted netX devices"
|
|
bitfld.long 0x00 31. "sel_lcd_col_b,select outputs for Couloured LCD Display position b (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "sel_lcd_col_a,select outputs for Couloured LCD Display position a (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "sel_lcd_bw,select outputs for Black and White LCD Display (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "sel_pwm7,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 27. "sel_pwm6,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 26. "sel_pwm5,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 25. "sel_pwm4,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 24. "sel_pwm3,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 23. "sel_pwm2,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 22. "sel_pwm1,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
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bitfld.long 0x00 21. "sel_pwm0,select pad for PWM output (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "sel_lvds2mii1,select interface for LVDS2MII1" "0: none (connect neither to ETH nor to XC),1: connect to XC1 (disables connection of XC1 to,2: connect to XC3 (disables connection of XC3 to,3: connect to ETH (disables connection of ETH to"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "sel_lvds2mii0,select interface for LVDS2MII0" "0: none (connect neither to ETH nor to XC),1: connect to XC0 (disables connection of XC0 to,2: connect to XC2 (disables connection of XC2 to,3: connect to ETH (disables connection of ETH to"
|
|
newline
|
|
bitfld.long 0x00 16. "usb2jtag_en,global enable of USB2JTAG debug feature: Note: Addionally USB2JTAG debugging requires an enable from USB_DEV module which is only active if USB_DEV module is running and connection is established (s. usb_dev_cfg-usb_to_jtag_enable)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "sel_fb11clk,select pad for fieldbus-clk11 (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "sel_xm11_eclk,select pad for xMAC11 eclk (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "sel_xm11_txoe,select pad for xMAC11 tx-bitstream direct output enable (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "sel_xm11_tx,select pad for xMAC11 tx-bitstream direct output (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "sel_fb10clk,select pad for fieldbus-clk10 (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "sel_xm10_eclk,select pad for xMAC10 eclk (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "sel_xm10_txoe,select pad for xMAC10 tx-bitstream direct output enable (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "sel_xm10_tx,select pad for xMAC10 tx-bitstream direct output (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "sel_fb01clk,select pad for fieldbus-clk01 (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "sel_xm01_eclk,select pad for xMAC01 eclk (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "sel_xm01_txoe,select pad for xMAC01 tx-bitstream direct output enable (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "sel_xm01_tx,select pad for xMAC01 tx-bitstream direct output (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "sel_fb00clk,select pad for fieldbus-clk00 (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "sel_xm00_eclk,select pad for xMAC00 eclk (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "sel_xm00_txoe,select pad for xMAC00 tx-bitstream direct output enable (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "sel_xm00_tx,select pad for xMAC00 tx-bitstream direct output (s. pinning table)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "io_config2,IO Config2 Register: Selects of output pin multiplexing"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 19. "mdio_bidi,PxMDIO bidirectional" "0: use pads PHYx_MDIOIN PHYx_MDIOOUT and,1: use pad PHYx_MDIOIN for connection to external"
|
|
newline
|
|
bitfld.long 0x00 18. "sel_usb2jtag_devel,select USB2JTAG development outputs (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "sel_phy_devel,select PHY development outputs (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--16. "sel_eth_mii,description too long please enter short description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "sel_xm11_mii,select pads for xMAC11 external MII pins (s. pinning table)" "0: no select,1: select pins for RMII (rxd[1:0] rxdv rxer txclk,2: select pins for RX only mode (rxclk rxd[3:0],3: select pins for minimum data transfer in phy,4: select also rxclk pin for mac mode (rxclk),5: select also RX error signal (rxer),6: select also collision and carrier sense (col..,7: select also TX error signal (txer)"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "sel_xm10_mii,select pads for xMAC10 external MII pins (s. pinning table)" "0: no select,1: select pins for RMII (rxd[1:0] rxdv rxer txclk,2: select pins for RX only mode (rxclk rxd[3:0],3: select pins for minimum data transfer in phy,4: select also rxclk pin for mac mode (rxclk),5: select also RX error signal (rxer),6: select also collision and carrier sense (col..,7: select also TX error signal (txer)"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "sel_xm01_mii,select pads for xMAC01 external MII pins (s. pinning table)" "0: no select (use internal PHY),1: select pins for RMII (rxd[1:0] rxdv rxer txclk,2: select pins for RX only mode (rxclk rxd[3:0],3: select pins for minimum data transfer in phy,4: select also rxclk pin for mac mode (rxclk),5: select also RX error signal (rxer),6: select also collision and carrier sense (col..,7: select also TX error signal (txer)"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "sel_xm00_mii,select pads for xMAC00 external MII pins (s. pinning table)" "0: no select (use internal PHY),1: select pins for RMII (rxd[1:0] rxdv rxer txclk,2: select pins for RX only mode (rxclk rxd[3:0],3: select pins for minimum data transfer in phy,4: select also rxclk pin for mac mode (rxclk),5: select also RX error signal (rxer),6: select also collision and carrier sense (col..,7: select also TX error signal (txer)"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "io_config2_mask,IO Config2 Mask Register: This register might be used to lock special IO configurations for restricted netX devices"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 19. "mdio_bidi,PxMDIO bidirectional: This high active bit mask allows to restrict changes of mdio_bidi mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "sel_usb2jtag_devel,select USB2JTAG development outputs (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "sel_phy_devel,select PHY development outputs (s. pinning table)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--16. "sel_eth_mii,select pads for ETH external MII pins: This high active bit mask allows to restrict some combinations of where ETH signals might be mapped to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "sel_xm11_mii,select pads for xMAC11 external MII pins (s. pinning table): This high active bit mask allows to restrict some combinations of where xMAC11 signals might be mapped to" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "sel_xm10_mii,select pads for xMAC10 external MII pins (s. pinning table): This high active bit mask allows to restrict some combinations of where xMAC10 signals might be mapped to" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "sel_xm01_mii,select pads for xMAC01 external MII pins (s. pinning table): This high active bit mask allows to restrict some combinations of where xMAC01 signals might be mapped to" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "sel_xm00_mii,select pads for xMAC00 external MII pins (s. pinning table): This high active bit mask allows to restrict some combinations of where xMAC00 signals might be mapped to" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "reset_ctrl,Reset Control Register: This register controls the NETX isolation for a reset of the NETX part and the reset out pin (RST_OUT_N)"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "isolate_netx,Purpose: Reset of the NETX part" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2. "rst_out_n_in_ro,Status of reset pin (RST_OUT_N)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "rst_out_n_oe,Output enable of external reset pin (RST_OUT_N)" "0: RST_OUT_N is not driven (High-Z),1: Drive RST_OUT_N high or low depending on"
|
|
newline
|
|
bitfld.long 0x00 0. "rst_out_n_out,Output of external reset pin (RST_OUT_N)" "0: Drive RST_OUT_N low if rst_out_n_oe=1,1: Drive RST_OUT_N high if rst_out_n_oe=1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ahbl_master_ready,all ahbl master ready signals read ahbl ready = 1'b1 status for start stop reset clockenable masters like XC or XPIC"
|
|
bitfld.long 0x00 27.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long 0x00 0.--26. 1. "val,netx ahbl_master readys (0-26) M_DPM 0 M_XC01_d 1 M_XC23_d 2 M_XC01_s 3 M_XC23_s 4 M_SYSDEBUG 5 M_LCD 6 M_OSAC 7 M_XPIC0_d 8 M_XPIC0_i 9 M_XPIC1_d 10 M_XPIC1_i 11 M_XPIC2_d 12 M_XPIC2_i 13 M_XPIC3_d 14 M_XPIC3_i 15 M_RAP2NX_RAM0 16 M_RAP2NX_RAM1 17.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "usb12clk_rate_mul_add,Rate Multiplier Add Value of 12MHz USB clock"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "usb12clk_rate_mul_add,This value is added each clk400 cycle to usb12clk_rate_mul to generate usb12clk"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "adcclk_div,Divisor of clock divider for 20MHz ADC clock"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "val,Divisor for generating 20MHz MHz adcclk out of clk400: Change value according to formula: adcclk_div = (200 / [freq in MHz]) - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "systime_ctrl,select systime for feth gpio gmac"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "gmac,systime for gmac (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..reserved)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "gpio,systime for gpio (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "feth,systime for feth (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap)" "0,1,2,3"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "clock_enable,Global Clock Enable Register: Use this registers to disable modules completely for power saving purposes"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "lcd,enables clock for LCD controller" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "dpm,enables clock for DPM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "dma,enables clock for DMA controller" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "xpic3,enables clock for XPIC3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "xpic2,enables clock for XPIC2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "xpic1,enables clock for XPIC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "xpic0,enables clock for XPIC0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "xc_misc,enables clock for global XC logic (expect rpec/tpec/xmac cores)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "fb11,enables clock for fieldbus11" "0: use external xm11_eclk to resample xMAC outputs,1: use internally generated fb11clk to resample"
|
|
newline
|
|
bitfld.long 0x00 14. "fb10,enables clock for fieldbus10" "0: use external xm10_eclk to resample xMAC outputs,1: use internally generated fb10clk to resample"
|
|
newline
|
|
bitfld.long 0x00 13. "fb01,enables clock for fieldbus01" "0: use external xm01_eclk to resample xMAC outputs,1: use internally generated fb01clk to resample"
|
|
newline
|
|
bitfld.long 0x00 12. "fb00,enables clock for fieldbus00" "0: use external xm00_eclk to resample xMAC outputs,1: use internally generated fb00clk to resample"
|
|
newline
|
|
bitfld.long 0x00 11. "xmac11,enables clock for xMAC11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "xmac10,enables clock for xMAC10" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "xmac01,enables clock for xMAC01" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "xmac00,enables clock for xMAC00" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "tpec11,enables clock for tPEC11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "tpec10,enables clock for tPEC10" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "tpec01,enables clock for tPEC01" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "tpec00,enables clock for tPEC00" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "rpec11,enables clock for rPEC11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "rpec10,enables clock for rPEC10" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "rpec01,enables clock for rPEC01" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "rpec00,enables clock for rPEC00" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "clock_enable_mask,Global Clock Enable Mask Register: allows to disable modules for different netX-versions This register is lockable by netX locking algorithm"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "lcd,enables clock for LCD controller" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "dpm,enables clock for DPM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "dma,enables clock for DMA controller" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "xpic3,enables clock for XPIC3" "0,1"
|
|
newline
|
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bitfld.long 0x00 19. "xpic2,enables clock for XPIC2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "xpic1,enables clock for XPIC1" "0,1"
|
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newline
|
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bitfld.long 0x00 17. "xpic0,enables clock for XPIC0" "0,1"
|
|
newline
|
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bitfld.long 0x00 16. "xc_misc,enables clock for global XC logic (expect rpec/tpec/xmac cores)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "fb11,enables clock for fieldbus11" "0: use external xm11_eclk to resample xMAC outputs,1: use internally generated fb11clk to resample"
|
|
newline
|
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bitfld.long 0x00 14. "fb10,enables clock for fieldbus10" "0: use external xm10_eclk to resample xMAC outputs,1: use internally generated fb10clk to resample"
|
|
newline
|
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bitfld.long 0x00 13. "fb01,enables clock for fieldbus01" "0: use external xm01_eclk to resample xMAC outputs,1: use internally generated fb01clk to resample"
|
|
newline
|
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bitfld.long 0x00 12. "fb00,enables clock for fieldbus00" "0: use external xm00_eclk to resample xMAC outputs,1: use internally generated fb00clk to resample"
|
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newline
|
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bitfld.long 0x00 11. "xmac11,enables clock for xMAC11" "0,1"
|
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newline
|
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bitfld.long 0x00 10. "xmac10,enables clock for xMAC10" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "xmac01,enables clock for xMAC01" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "xmac00,enables clock for xMAC00" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "tpec11,enables clock for tPEC11" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "tpec10,enables clock for tPEC10" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "tpec01,enables clock for tPEC01" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "tpec00,enables clock for tPEC00" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "rpec11,enables clock for rPEC11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "rpec10,enables clock for rPEC10" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "rpec01,enables clock for rPEC01" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "rpec00,enables clock for rPEC00" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "misc_asic_ctrl,Miscellaneous ASIC Control Register: This register is lockable by netX locking algorithm"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 11. "lic_err_delay_en,Random Delay between a detected license error and abort-generation/change to tainted mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "lic_err_irq_en,In case of a detected license error ARM-IRQ will be generated" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "lic_err_abort_en,In case of a detected license error ARM-Abort will be generated on the next data write (no data loss caused)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "lic_err_taint_en,In case of a detected license error xPECs and xMACs will be stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "sysdebug_ir,JTAG Instruction for SYSDEBUG usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "quick_count,Testmode 'quick_count': -> diverse internal counters count faster (SDRAM init procedure us and ms system ticks)" "0,1"
|
|
group.long 0x48++0x03
|
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line.long 0x00 "netx_version,netX Revision Register: This register contains information about netX hardware and bootloader revision"
|
|
abitfld.long 0x00 0.--31. "netx_version,netX4000 revision number: Hardware reset values of netX version register is" "0x00000001=1: netx50,0x00000002=2: netx5_mpw,0x00000005=5: netx51/52,0x00000006=6: reserved,0x00000007=7: netx6,0x00000008=8: netx4000_relaxed,0x00000009=9: reserved,0x0000000A=10: netx4000 This register,0x00000041=65: netx5,0x00000042=66: netx51/52,0x00000050=80: netx10"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "rom_wdg,netX ROM watchdog: Write the ROM watchdog trigger sequence to this register to reset the watchdog"
|
|
hexmask.long 0x00 0.--31. 1. "rst_wdg,Write trigger sequence here to reset ROM watchdog"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "netx_status,netX System Status Configuration Register"
|
|
bitfld.long 0x00 26.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
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bitfld.long 0x00 25. "RUN_DRV,Driver enable for RUN LED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RDY_DRV,Driver enable for RDY LED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19. "RUN_POL,Output polarity RUN LED outsig = RUN exor RUN_POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "RDY_POL,Output polarity RDY LED outsig = RDY exor RDY_POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "RUN_IN,Physical input signal level at RUN pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "RDY_IN,Physical input signal level at RDY pin" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "NETX_STA_CODE,netX Status Code"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "HOST_STATE_ro,Host Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "NETX_STATE,User defined status bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "RUN,Signal Level of the RUN LED output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RDY,Signal level of the RDY LED output" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "rdy_run_cfg,netX RDY/RUN IO System Status Configuration Register"
|
|
bitfld.long 0x00 26.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 25. "RUN_DRV,Driver enable for RUN LED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RDY_DRV,Driver enable for RDY LED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19. "RUN_POL,Output polarity RUN LED outsig = RUN exor RUN_POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "RDY_POL,Output polarity RDY LED outsig = RDY exor RDY_POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "RUN_IN,Physical input signal level at RUN pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "RDY_IN,Physical input signal level at RDY pin" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 1. "RUN,Signal Level of the RUN LED output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RDY,Signal level of the RDY LED output" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "system_status,netX System Status Register"
|
|
bitfld.long 0x00 30.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 29. "firewall_irq_status_netx_reg,Firewall IRQ status of NETX-NoC AHB channel NETX_REG Note: This bit must be cleared by writing a '1' to the related firewall_cfg.irq_stat bit (ASIC_CTRL area)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "firewall_irq_status_netx_xc_config,Firewall IRQ status of NETX-NoC AHB channel NETX_XC_CONFIG Note: This bit must be cleared by writing a '1' to the related firewall_cfg.irq_stat bit (ASIC_CTRL area)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "firewall_irq_status_netx_hifmem,Firewall IRQ status of NETX-NoC AHB channel NETX_HIFMEM Note: This bit must be cleared by writing a '1' to the related firewall_cfg.irq_stat bit (ASIC_CTRL area)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "firewall_irq_status_netx_extmem,Firewall IRQ status of NETX-NoC AHB channel NETX_EXTMEM Note: This bit must be cleared by writing a '1' to the related firewall_cfg.irq_stat bit (ASIC_CTRL area)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "firewall_irq_status_netx_rameth,Firewall IRQ status of NETX-NoC AHB channel NETX_RAMETH Note: This bit must be cleared by writing a '1' to the related firewall_cfg.irq_stat bit (ASIC_CTRL area)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "firewall_irq_status_netx_ramhs1,Firewall IRQ status of NETX-NoC AHB channel NETX_RAMHS1 Note: This bit must be cleared by writing a '1' to the related firewall_cfg.irq_stat bit (ASIC_CTRL area)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "firewall_irq_status_netx_ramhs0,Firewall IRQ status of NETX-NoC AHB channel NETX_RAMHS0 Note: This bit must be cleared by writing a '1' to the related firewall_cfg.irq_stat bit (ASIC_CTRL area)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "firewall_irq_status_netx_ram2,Firewall IRQ status of NETX-NoC AHB channel NETX_RAM2 Note: This bit must be cleared by writing a '1' to the related firewall_cfg.irq_stat bit (ASIC_CTRL area)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "firewall_irq_status_netx_ram1,Firewall IRQ status of NETX-NoC AHB channel NETX_RAM1 Note: This bit must be cleared by writing a '1' to the related firewall_cfg.irq_stat bit (ASIC_CTRL area)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "firewall_irq_status_netx_ram0,Firewall IRQ status of NETX-NoC AHB channel NETX_RAM0 Note: This bit must be cleared by writing a '1' to the related firewall_cfg.irq_stat bit (ASIC_CTRL area)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "lic_err_abort_status,Current status of netX licence abort" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 7.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "netx_master_error_irq_status,Current status of 'netx_master_error_irq' IRQ Note: This IRQ is controlled/cleared by 'netx_master_stat0' register (area ASIC_CTRL)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ecc_dbe,Current status of ECC_CTRL Double Bit Error IRQ Note: This IRQ is controlled/cleared by ecc_ctrl_status_dbe register (area ECC_CTRL)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ecc_sbe,Current status of ECC_CTRL Single Bit Error IRQ Note: This IRQ is controlled/cleared by ecc_ctrl_status_sbe register (area ECC_CTRL)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "mem_to_irq_status,Current status of MEM-Bus Ready Timeout IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "extbus_to_irq_status,Current status of HIF-Extension Bus Ready Timeout IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "dpm_irq_status,Current status of DPM_IRQ_ARM (e.g dpm_err IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "lic_err_irq_status,Current status of netX licence error IRQ" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "netx_lic_id,netX License ID Register: This register contains license information read from security memory during boot phase This register is lockable by netX locking algorithm"
|
|
hexmask.long 0x00 0.--31. 1. "id,License ID from security memory"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "netx_lic_flags0,netX License Flags 0 Register: This register is part of netX licence error detection mechanism"
|
|
hexmask.long 0x00 0.--31. 1. "flags,License flag bits from security memory"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "netx_lic_flags1,netX License Flags 1 Register: This register is part of netX licence error detection mechanism"
|
|
hexmask.long 0x00 0.--31. 1. "flags,License flag bits from security memory"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "netx_lic_errors0,netX License Errors 0 Status Register: This register is part of netX licence error detection mechanism"
|
|
hexmask.long 0x00 0.--31. 1. "err_ro,License error bits set in case of license mismatch according to netx_lic_flags0 (OR of all occured errors)"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "netx_lic_errors1,netX License Errors 1 Status Register: This register is part of netX licence error detection mechanism"
|
|
hexmask.long 0x00 0.--31. 1. "err_ro,License error bits set in case of license mismatch according to netx_lic_flags1 (OR of all occured errors)"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "asic_ctrl_access_key,ASIC Control Locking access-key Register: Writing to any register in the asic_ctrl or mmio_ctrl address area is only possible after setting the correct key here to avoid unmeant changes e.g"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "access_key,Locking access-key for next write access"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "debug_ctrl_status,Debug control status register This register represents the current status of the debug control signals to the CoreSight and netX debug logic"
|
|
bitfld.long 0x00 28.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "hw_sigs_dbg,Used for debugging-purposes only: represents the state of the signals connected to the debug logic"
|
|
newline
|
|
bitfld.long 0x00 15. "sysdebug_global_dbg_en,State of netX SYSDEBUG global debug enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 14. "ca9_global_dbg_en,State of Cortex A9 global debug enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "cr7_global_dbg_en,State of Cortex R7 global debug enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "sysdebug_en,State of netX SYSDEBUG debugging mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "ca9_pl310_spnid_en,State of Cortex A9 secure non-invasive debugging mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "ca9_spid_en,State of Cortex A9 secure invasive debugging mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "ca9_nid_en,State of Cortex A9 non-invasive debugging mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "ca9_dbg_en,State of Cortex A9 debugging mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "cr7_nid_en,State of Cortex R7 non-invasive debugging mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "cr7_dbg_en,State of Cortex R7 debugging mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "cs_spnid_en,State of CoreSight secure non-invasive debugging mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "cs_spid_en,State of CoreSight secure invasive debugging mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "cs_nid_en,State of CoreSight non-invasive debugging mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "cs_dbg_en,State of CoreSight AHB-AP master" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "cs_device_en,State of CoreSight internal APB-AP master" "0: disabled,1: enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "debug_ctrl_set,Debug control set register This register can be used to set one or more debug feature enable bits"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 15. "sysdebug_global_dbg_en,Enable netX SYSDEBUG global debug" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "ca9_global_dbg_en,Enable Cortex A9 global debug" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "cr7_global_dbg_en,Enable Cortex R7 global debug" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "sysdebug_en,Enable netX SYSDEBUG debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "ca9_pl310_spnid_en,Enable Cortex A9 secure non-invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ca9_spid_en,Enable Cortex A9 secure invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ca9_nid_en,Enable Cortex A9 non-invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ca9_dbg_en,Enable Cortex A9 debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "cr7_nid_en,Enable Cortex R7 non-invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "cr7_dbg_en,Enable Cortex R7 debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "cs_spnid_en,Enable CoreSight secure non-invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "cs_spid_en,Enable CoreSight secure invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "cs_nid_en,Enable CoreSight non-invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "cs_dbg_en,Enable CoreSight AHB-AP master" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "cs_device_en,Enable CoreSight internal APB-AP master" "0,1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "debug_ctrl_reset,Debug control reset register This register can be used to clear one or more debug feature enable bits"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 15. "sysdebug_global_dbg_en,Disable netX SYSDEBUG global debug" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "ca9_global_dbg_en,Disable Cortex A9 global debug" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "cr7_global_dbg_en,Disable Cortex R7 global debug" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "sysdebug_en,Disable netX SYSDEBUG debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "ca9_pl310_spnid_en,Disable Cortex A9 secure non-invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ca9_spid_en,Disable Cortex A9 secure invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ca9_nid_en,Disable Cortex A9 non-invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ca9_dbg_en,Disable Cortex A9 debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "cr7_nid_en,Disable Cortex R7 non-invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "cr7_dbg_en,Disable Cortex R7 debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "cs_spnid_en,Disable CoreSight secure non-invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "cs_spid_en,Disable CoreSight secure invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "cs_nid_en,Disable CoreSight non-invasive debugging mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "cs_dbg_en,Disable CoreSight AHB-AP master" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "cs_device_en,Disable CoreSight internal APB-AP master" "0,1"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "netx_master_stat0,NETX_MASTER AHB channel status register 0"
|
|
bitfld.long 0x00 31. "netx_master_error,HRESP status (write '1' to clear)" "0: OKAY was responded,1: An ERROR-responses was returned"
|
|
newline
|
|
bitfld.long 0x00 30. "netx_master_error_irq_en,IRQ enable for the 'netx_master_error' bit" "0: ERROR resonse doesn't generate a SYSTEM IRQ,1: When the 'netx_master_error' bit is set a.."
|
|
newline
|
|
hexmask.long.byte 0x00 23.--29. 1. "bf_align4,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "hburst_netx_master,HBURST (bit-field is a read only status)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "hsize_netx_master,HSIZE (bit-field is a read only status)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "htrans_netx_master,HTRANS (bit-field is a read only status)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "hwrite_netx_master,HWRITE (writable but can also be changed by hardware)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "hsel_ms_netx_master,Access master from netX side (bit-field is a read only status)" "?,1: XC01_d,2: XC23_d,?,?,5: LCD,6: OSAC,7: XPIC0_d,8: XPIC0_i,9: XPIC1_d,10: XPIC1_i,11: XPIC2_d,12: XPIC2_i,13: XPIC3_d,14: XPIC3_i,?,?,?,?,?,?,?,?,?,?,25: SYSDEBUG,?,27: DMAC others,?..."
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "netx_master_stat1,NETX_MASTER AHB channel status register 0"
|
|
hexmask.long 0x00 0.--31. 1. "haddr_netx_master,HADDR (bit-field is a read only status)"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "firewall_cfg_netx_ram0,Firewall configuration register for the NETX_RAM0 NETX AHB channel"
|
|
hexmask.long.word 0x00 21.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 20. "irq_stat_ro,current IRQ status of the NETX_RAM0 firewall" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "stat_rest,status for rest" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "stat_coresight,status for CORESIGHT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "stat_ca9,status for CA9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "stat_cr7,status for CR7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "irq_en_rest,irq enable for denied access of rest of outside-NETX-system (e.g. PCIe RAP-DMAC like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "irq_en_coresight,irq enable for denied access of CORESIGHT (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "irq_en_ca9,irq enable for denied access of CA9 (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "irq_en_cr7,irq enable for denied access of CR7" "0: no IRQ for denied accesss of CR7,1: rise IRQ on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 11. "abort_en_rest,abort enable for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "abort_en_coresight,abort enable for CORESIGHT (like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "abort_en_ca9,abort enable for CA9 (like abort_en_cr7 for response to CA9 for access from CA9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "abort_en_cr7,abort enable for CR7 for denied accesss of CR7" "0: no ERROR response to CR7,1: ERROR response to CR7 on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 7. "rp_rest,read permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "rp_coresight,read permission for CORESIGHT (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "rp_ca9,read permission for CA9 (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "rp_cr7,read permission for CR7" "0: deny read access for CR7,1: permit read access for CR7"
|
|
newline
|
|
bitfld.long 0x00 3. "wp_rest,write permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "wp_coresight,write permission for CORESIGHT (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_ca9,write permission for CA9 (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wp_cr7,write permission for CR7" "0: deny write access for CR7,1: permit write access for CR7"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "firewall_cfg_netx_ram1,Firewall configuration register for the NETX_RAM1 NETX AHB channel"
|
|
hexmask.long.word 0x00 21.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 20. "irq_stat_ro,current IRQ status of the NETX_RAM1 firewall" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "stat_rest,status for rest" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "stat_coresight,status for CORESIGHT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "stat_ca9,status for CA9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "stat_cr7,status for CR7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "irq_en_rest,irq enable for denied access of rest of outside-NETX-system (e.g. PCIe RAP-DMAC like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "irq_en_coresight,irq enable for denied access of CORESIGHT (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "irq_en_ca9,irq enable for denied access of CA9 (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "irq_en_cr7,irq enable for denied access of CR7" "0: no IRQ for denied accesss of CR7,1: rise IRQ on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 11. "abort_en_rest,abort enable for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "abort_en_coresight,abort enable for CORESIGHT (like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "abort_en_ca9,abort enable for CA9 (like abort_en_cr7 for response to CA9 for access from CA9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "abort_en_cr7,abort enable for CR7 for denied accesss of CR7" "0: no ERROR response to CR7,1: ERROR response to CR7 on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 7. "rp_rest,read permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "rp_coresight,read permission for CORESIGHT (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "rp_ca9,read permission for CA9 (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "rp_cr7,read permission for CR7" "0: deny read access for CR7,1: permit read access for CR7"
|
|
newline
|
|
bitfld.long 0x00 3. "wp_rest,write permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "wp_coresight,write permission for CORESIGHT (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_ca9,write permission for CA9 (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wp_cr7,write permission for CR7" "0: deny write access for CR7,1: permit write access for CR7"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "firewall_cfg_netx_ram2,Firewall configuration register for the NETX_RAM2 NETX AHB channel"
|
|
hexmask.long.word 0x00 21.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 20. "irq_stat_ro,current IRQ status of the NETX_RAM2 firewall" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "stat_rest,status for rest" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "stat_coresight,status for CORESIGHT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "stat_ca9,status for CA9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "stat_cr7,status for CR7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "irq_en_rest,irq enable for denied access of rest of outside-NETX-system (e.g. PCIe RAP-DMAC like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "irq_en_coresight,irq enable for denied access of CORESIGHT (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "irq_en_ca9,irq enable for denied access of CA9 (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "irq_en_cr7,irq enable for denied access of CR7" "0: no IRQ for denied accesss of CR7,1: rise IRQ on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 11. "abort_en_rest,abort enable for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "abort_en_coresight,abort enable for CORESIGHT (like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "abort_en_ca9,abort enable for CA9 (like abort_en_cr7 for response to CA9 for access from CA9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "abort_en_cr7,abort enable for CR7 for denied accesss of CR7" "0: no ERROR response to CR7,1: ERROR response to CR7 on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 7. "rp_rest,read permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "rp_coresight,read permission for CORESIGHT (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "rp_ca9,read permission for CA9 (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "rp_cr7,read permission for CR7" "0: deny read access for CR7,1: permit read access for CR7"
|
|
newline
|
|
bitfld.long 0x00 3. "wp_rest,write permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "wp_coresight,write permission for CORESIGHT (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_ca9,write permission for CA9 (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wp_cr7,write permission for CR7" "0: deny write access for CR7,1: permit write access for CR7"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "firewall_cfg_netx_ramhs0,Firewall configuration register for the NETX_RAMHS0 NETX AHB channel"
|
|
hexmask.long.word 0x00 21.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 20. "irq_stat_ro,current IRQ status of the NETX_RAMHS0 firewall" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "stat_rest,status for rest" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "stat_coresight,status for CORESIGHT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "stat_ca9,status for CA9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "stat_cr7,status for CR7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "irq_en_rest,irq enable for denied access of rest of outside-NETX-system (e.g. PCIe RAP-DMAC like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "irq_en_coresight,irq enable for denied access of CORESIGHT (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "irq_en_ca9,irq enable for denied access of CA9 (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "irq_en_cr7,irq enable for denied access of CR7" "0: no IRQ for denied accesss of CR7,1: rise IRQ on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 11. "abort_en_rest,abort enable for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "abort_en_coresight,abort enable for CORESIGHT (like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "abort_en_ca9,abort enable for CA9 (like abort_en_cr7 for response to CA9 for access from CA9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "abort_en_cr7,abort enable for CR7 for denied accesss of CR7" "0: no ERROR response to CR7,1: ERROR response to CR7 on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 7. "rp_rest,read permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "rp_coresight,read permission for CORESIGHT (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "rp_ca9,read permission for CA9 (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "rp_cr7,read permission for CR7" "0: deny read access for CR7,1: permit read access for CR7"
|
|
newline
|
|
bitfld.long 0x00 3. "wp_rest,write permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "wp_coresight,write permission for CORESIGHT (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_ca9,write permission for CA9 (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wp_cr7,write permission for CR7" "0: deny write access for CR7,1: permit write access for CR7"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "firewall_cfg_netx_ramhs1,Firewall configuration register for the NETX_RAMHS1 NETX AHB channel"
|
|
hexmask.long.word 0x00 21.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 20. "irq_stat_ro,current IRQ status of the NETX_RAMHS1 firewall" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "stat_rest,status for rest" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "stat_coresight,status for CORESIGHT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "stat_ca9,status for CA9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "stat_cr7,status for CR7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "irq_en_rest,irq enable for denied access of rest of outside-NETX-system (e.g. PCIe RAP-DMAC like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "irq_en_coresight,irq enable for denied access of CORESIGHT (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "irq_en_ca9,irq enable for denied access of CA9 (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "irq_en_cr7,irq enable for denied access of CR7" "0: no IRQ for denied accesss of CR7,1: rise IRQ on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 11. "abort_en_rest,abort enable for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "abort_en_coresight,abort enable for CORESIGHT (like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "abort_en_ca9,abort enable for CA9 (like abort_en_cr7 for response to CA9 for access from CA9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "abort_en_cr7,abort enable for CR7 for denied accesss of CR7" "0: no ERROR response to CR7,1: ERROR response to CR7 on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 7. "rp_rest,read permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "rp_coresight,read permission for CORESIGHT (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "rp_ca9,read permission for CA9 (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "rp_cr7,read permission for CR7" "0: deny read access for CR7,1: permit read access for CR7"
|
|
newline
|
|
bitfld.long 0x00 3. "wp_rest,write permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "wp_coresight,write permission for CORESIGHT (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_ca9,write permission for CA9 (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wp_cr7,write permission for CR7" "0: deny write access for CR7,1: permit write access for CR7"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "firewall_cfg_netx_rameth,Firewall configuration register for the NETX_RAMETH NETX AHB channel"
|
|
hexmask.long.word 0x00 21.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 20. "irq_stat_ro,current IRQ status of the NETX_RAMETH firewall" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "stat_rest,status for rest" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "stat_coresight,status for CORESIGHT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "stat_ca9,status for CA9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "stat_cr7,status for CR7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "irq_en_rest,irq enable for denied access of rest of outside-NETX-system (e.g. PCIe RAP-DMAC like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "irq_en_coresight,irq enable for denied access of CORESIGHT (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "irq_en_ca9,irq enable for denied access of CA9 (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "irq_en_cr7,irq enable for denied access of CR7" "0: no IRQ for denied accesss of CR7,1: rise IRQ on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 11. "abort_en_rest,abort enable for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "abort_en_coresight,abort enable for CORESIGHT (like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "abort_en_ca9,abort enable for CA9 (like abort_en_cr7 for response to CA9 for access from CA9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "abort_en_cr7,abort enable for CR7 for denied accesss of CR7" "0: no ERROR response to CR7,1: ERROR response to CR7 on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 7. "rp_rest,read permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "rp_coresight,read permission for CORESIGHT (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "rp_ca9,read permission for CA9 (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "rp_cr7,read permission for CR7" "0: deny read access for CR7,1: permit read access for CR7"
|
|
newline
|
|
bitfld.long 0x00 3. "wp_rest,write permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "wp_coresight,write permission for CORESIGHT (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_ca9,write permission for CA9 (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wp_cr7,write permission for CR7" "0: deny write access for CR7,1: permit write access for CR7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "firewall_cfg_netx_extmem,Firewall configuration register for the NETX_EXTMEM NETX AHB channel"
|
|
hexmask.long.word 0x00 21.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 20. "irq_stat_ro,current IRQ status of the NETX_EXTMEM firewall" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "stat_rest,status for rest" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "stat_coresight,status for CORESIGHT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "stat_ca9,status for CA9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "stat_cr7,status for CR7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "irq_en_rest,irq enable for denied access of rest of outside-NETX-system (e.g. PCIe RAP-DMAC like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "irq_en_coresight,irq enable for denied access of CORESIGHT (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "irq_en_ca9,irq enable for denied access of CA9 (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "irq_en_cr7,irq enable for denied access of CR7" "0: no IRQ for denied accesss of CR7,1: rise IRQ on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 11. "abort_en_rest,abort enable for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "abort_en_coresight,abort enable for CORESIGHT (like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "abort_en_ca9,abort enable for CA9 (like abort_en_cr7 for response to CA9 for access from CA9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "abort_en_cr7,abort enable for CR7 for denied accesss of CR7" "0: no ERROR response to CR7,1: ERROR response to CR7 on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 7. "rp_rest,read permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "rp_coresight,read permission for CORESIGHT (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "rp_ca9,read permission for CA9 (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "rp_cr7,read permission for CR7" "0: deny read access for CR7,1: permit read access for CR7"
|
|
newline
|
|
bitfld.long 0x00 3. "wp_rest,write permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "wp_coresight,write permission for CORESIGHT (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_ca9,write permission for CA9 (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wp_cr7,write permission for CR7" "0: deny write access for CR7,1: permit write access for CR7"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "firewall_cfg_netx_hifmem,Firewall configuration register for the NETX_HIFMEM NETX AHB channel"
|
|
hexmask.long.word 0x00 21.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 20. "irq_stat_ro,current IRQ status of the NETX_HIFMEM firewall" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "stat_rest,status for rest" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "stat_coresight,status for CORESIGHT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "stat_ca9,status for CA9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "stat_cr7,status for CR7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "irq_en_rest,irq enable for denied access of rest of outside-NETX-system (e.g. PCIe RAP-DMAC like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "irq_en_coresight,irq enable for denied access of CORESIGHT (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "irq_en_ca9,irq enable for denied access of CA9 (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "irq_en_cr7,irq enable for denied access of CR7" "0: no IRQ for denied accesss of CR7,1: rise IRQ on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 11. "abort_en_rest,abort enable for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "abort_en_coresight,abort enable for CORESIGHT (like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "abort_en_ca9,abort enable for CA9 (like abort_en_cr7 for response to CA9 for access from CA9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "abort_en_cr7,abort enable for CR7 for denied accesss of CR7" "0: no ERROR response to CR7,1: ERROR response to CR7 on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 7. "rp_rest,read permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "rp_coresight,read permission for CORESIGHT (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "rp_ca9,read permission for CA9 (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "rp_cr7,read permission for CR7" "0: deny read access for CR7,1: permit read access for CR7"
|
|
newline
|
|
bitfld.long 0x00 3. "wp_rest,write permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "wp_coresight,write permission for CORESIGHT (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_ca9,write permission for CA9 (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wp_cr7,write permission for CR7" "0: deny write access for CR7,1: permit write access for CR7"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "firewall_cfg_netx_xc_config,Firewall configuration register for the NETX_XC_CONFIG NETX AHB channel"
|
|
hexmask.long.word 0x00 21.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 20. "irq_stat_ro,current IRQ status of the NETX_XC_CONFIG firewall" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "stat_rest,status for rest" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "stat_coresight,status for CORESIGHT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "stat_ca9,status for CA9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "stat_cr7,status for CR7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "irq_en_rest,irq enable for denied access of rest of outside-NETX-system (e.g. PCIe RAP-DMAC like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "irq_en_coresight,irq enable for denied access of CORESIGHT (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "irq_en_ca9,irq enable for denied access of CA9 (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "irq_en_cr7,irq enable for denied access of CR7" "0: no IRQ for denied accesss of CR7,1: rise IRQ on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 11. "abort_en_rest,abort enable for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "abort_en_coresight,abort enable for CORESIGHT (like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "abort_en_ca9,abort enable for CA9 (like abort_en_cr7 for response to CA9 for access from CA9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "abort_en_cr7,abort enable for CR7 for denied accesss of CR7" "0: no ERROR response to CR7,1: ERROR response to CR7 on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 7. "rp_rest,read permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "rp_coresight,read permission for CORESIGHT (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "rp_ca9,read permission for CA9 (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "rp_cr7,read permission for CR7" "0: deny read access for CR7,1: permit read access for CR7"
|
|
newline
|
|
bitfld.long 0x00 3. "wp_rest,write permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "wp_coresight,write permission for CORESIGHT (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_ca9,write permission for CA9 (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wp_cr7,write permission for CR7" "0: deny write access for CR7,1: permit write access for CR7"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "firewall_cfg_netx_reg,Firewall configuration register for the NETX_REG NETX AHB channel"
|
|
hexmask.long.word 0x00 21.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 20. "irq_stat_ro,current IRQ status of the NETX_REG firewall" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "stat_rest,status for rest" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "stat_coresight,status for CORESIGHT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "stat_ca9,status for CA9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "stat_cr7,status for CR7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "irq_en_rest,irq enable for denied access of rest of outside-NETX-system (e.g. PCIe RAP-DMAC like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "irq_en_coresight,irq enable for denied access of CORESIGHT (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "irq_en_ca9,irq enable for denied access of CA9 (like irq_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "irq_en_cr7,irq enable for denied access of CR7" "0: no IRQ for denied accesss of CR7,1: rise IRQ on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 11. "abort_en_rest,abort enable for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "abort_en_coresight,abort enable for CORESIGHT (like abort_en_cr7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "abort_en_ca9,abort enable for CA9 (like abort_en_cr7 for response to CA9 for access from CA9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "abort_en_cr7,abort enable for CR7 for denied accesss of CR7" "0: no ERROR response to CR7,1: ERROR response to CR7 on denied access of CR7"
|
|
newline
|
|
bitfld.long 0x00 7. "rp_rest,read permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "rp_coresight,read permission for CORESIGHT (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "rp_ca9,read permission for CA9 (like rp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "rp_cr7,read permission for CR7" "0: deny read access for CR7,1: permit read access for CR7"
|
|
newline
|
|
bitfld.long 0x00 3. "wp_rest,write permission for rest of outside-NETX-system (e.g. PCIe RAP-DMAC like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "wp_coresight,write permission for CORESIGHT (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_ca9,write permission for CA9 (like wp_cr7 but disabled by default)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wp_cr7,write permission for CR7" "0: deny write access for CR7,1: permit write access for CR7"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "asr_id0,ASIC Secure Register ID Area - register 0 This register is lockable by netX locking algorithm"
|
|
hexmask.long 0x00 0.--31. 1. "val,ASIC Secure Register ID Area - value of register 0"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "asr_id1,ASIC Secure Register ID Area - register 1 This register is lockable by netX locking algorithm"
|
|
hexmask.long 0x00 0.--31. 1. "val,ASIC Secure Register ID Area - value of register 1"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "asr_id2,ASIC Secure Register ID Area - register 2 This register is lockable by netX locking algorithm"
|
|
hexmask.long 0x00 0.--31. 1. "val,ASIC Secure Register ID Area - value of register 2"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "asr_id3,ASIC Secure Register ID Area - register 3 This register is lockable by netX locking algorithm"
|
|
hexmask.long 0x00 0.--31. 1. "val,ASIC Secure Register ID Area - value of register 3"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "asr_id4,ASIC Secure Register ID Area - register 4 This register is lockable by netX locking algorithm"
|
|
hexmask.long 0x00 0.--31. 1. "val,ASIC Secure Register ID Area - value of register 4"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "asr_id5,ASIC Secure Register ID Area - register 5 This register is lockable by netX locking algorithm"
|
|
hexmask.long 0x00 0.--31. 1. "val,ASIC Secure Register ID Area - value of register 5"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "asr_id6,ASIC Secure Register ID Area - register 6 This register is lockable by netX locking algorithm"
|
|
hexmask.long 0x00 0.--31. 1. "val,ASIC Secure Register ID Area - value of register 6"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "asr_id7,ASIC Secure Register ID Area - register 7 This register is lockable by netX locking algorithm"
|
|
hexmask.long 0x00 0.--31. 1. "val,ASIC Secure Register ID Area - value of register 7"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "asr_id8,ASIC Secure Register ID Area - register 8 This register is lockable by netX locking algorithm"
|
|
hexmask.long 0x00 0.--31. 1. "val,ASIC Secure Register ID Area - value of register 8"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "asr_id9,ASIC Secure Register ID Area - register 9 This register is lockable by netX locking algorithm"
|
|
hexmask.long 0x00 0.--31. 1. "val,ASIC Secure Register ID Area - value of register 9"
|
|
tree.end
|
|
tree "ECC_CTRL"
|
|
base ad:0xF4080800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_rpec0_pram_ctrl,XC0_RPEC0_PRAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_rpec1_pram_ctrl,XC0_RPEC1_PRAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_rpec0_pram_ctrl,XC1_RPEC0_PRAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_rpec1_pram_ctrl,XC1_RPEC1_PRAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_tpec0_pram_ctrl,XC0_TPEC0_PRAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_tpec1_pram_ctrl,XC0_TPEC1_PRAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_tpec0_pram_ctrl,XC1_TPEC0_PRAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_tpec1_pram_ctrl,XC1_TPEC1_PRAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_dpram0_ctrl,XC0_DPRAM0 syndrome manipulation register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_dpram1_ctrl,XC0_DPRAM1 syndrome manipulation register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_dpram0_ctrl,XC1_DPRAM0 syndrome manipulation register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_dpram1_ctrl,XC1_DPRAM1 syndrome manipulation register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_rpu0_ram_ctrl,XC0_RPU0_RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_rpu1_ram_ctrl,XC0_RPU1_RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_rpu0_ram_ctrl,XC1_RPU0_RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_rpu1_ram_ctrl,XC1_RPU1_RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_tpu0_ram_ctrl,XC0_TPU0_RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_tpu1_ram_ctrl,XC0_TPU1_RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_tpu0_ram_ctrl,XC1_TPU0_RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_tpu1_ram_ctrl,XC1_TPU1_RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_pfifo_ctrl,XC0_PFIFO syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_pfifo_ctrl,XC1_PFIFO syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic0_pram_ctrl,XPIC0_PRAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic1_pram_ctrl,XPIC1_PRAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic2_pram_ctrl,XPIC2_PRAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic3_pram_ctrl,XPIC3_PRAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic0_dram_ctrl,XPIC0_DRAM syndrome manipulation register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic1_dram_ctrl,XPIC1_DRAM syndrome manipulation register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic2_dram_ctrl,XPIC2_DRAM syndrome manipulation register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic3_dram_ctrl,XPIC3_DRAM syndrome manipulation register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "ecc_ctrl_intrameth_ctrl,INTRAMETH syndrome manipulation register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_rpec0_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_rpec1_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_rpec0_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_rpec1_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_tpec0_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_tpec1_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_tpec0_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_tpec1_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_rpu0_ram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_rpu1_ram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_rpu0_ram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_rpu1_ram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_tpu0_ram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_tpu1_ram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_tpu0_ram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_tpu1_ram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic0_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic1_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic2_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic3_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic0_dram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic1_dram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic2_dram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic3_dram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "ecc_ctrl_intrameth_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
|
|
hexmask.long.word 0x00 18.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 13.--17. "add_addr,Number of master that started errorneous RAM access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "address,Address of last ECC single bit error"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_rpec0_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_rpec1_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_rpec0_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_rpec1_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_tpec0_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_tpec1_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_tpec0_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_tpec1_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_rpu0_ram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_rpu1_ram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_rpu0_ram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_rpu1_ram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_tpu0_ram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "ecc_ctrl_xc0_tpu1_ram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_tpu0_ram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "ecc_ctrl_xc1_tpu1_ram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic0_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic1_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic2_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic3_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic0_dram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic1_dram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic2_dram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "ecc_ctrl_xpic3_dram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "ecc_ctrl_intrameth_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
|
|
hexmask.long.word 0x00 18.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 13.--17. "add_addr,Number of master that started errorneous RAM access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "address,Address of last ECC double bit error"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "ecc_ctrl_status_sbe,ECC status SBE: This register collects single bit error (SBE) status information"
|
|
bitfld.long 0x00 31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 30. "intrameth,INTRAMETH Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "xpic3_dram,XPIC3_DRAM Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 28. "xpic2_dram,XPIC2_DRAM Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "xpic1_dram,XPIC1_DRAM Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 26. "xpic0_dram,XPIC0_DRAM Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "xpic3_pram,XPIC3_PRAM Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 24. "xpic2_pram,XPIC2_PRAM Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "xpic1_pram,XPIC1_PRAM Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 22. "xpic0_pram,XPIC0_PRAM Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "xc1_pfifo,XC1_PFIFO Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 20. "xc0_pfifo,XC0_PFIFO Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "xc1_tpu1_ram,XC1_TPU1_RAM Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 18. "xc1_tpu0_ram,XC1_TPU0_RAM Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "xc0_tpu1_ram,XC0_TPU1_RAM Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 16. "xc0_tpu0_ram,XC0_TPU0_RAM Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "xc1_rpu1_ram,XC1_RPU1_RAM Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 14. "xc1_rpu0_ram,XC1_RPU0_RAM Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "xc0_rpu1_ram,XC0_RPU1_RAM Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 12. "xc0_rpu0_ram,XC0_RPU0_RAM Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "xc1_dpram1,XC1_DPRAM1 Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 10. "xc1_dpram0,XC1_DPRAM0 Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "xc0_dpram1,XC0_DPRAM1 Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 8. "xc0_dpram0,XC0_DPRAM0 Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "xc1_tpec1_pram,XC1_TPEC1_PRAM Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 6. "xc1_tpec0_pram,XC1_TPEC0_PRAM Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "xc0_tpec1_pram,XC0_TPEC1_PRAM Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 4. "xc0_tpec0_pram,XC0_TPEC0_PRAM Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "xc1_rpec1_pram,XC1_RPEC1_PRAM Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 2. "xc1_rpec0_pram,XC1_RPEC0_PRAM Single Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "xc0_rpec1_pram,XC0_RPEC1_PRAM Single Bit Error occured" "0,1"
|
|
bitfld.long 0x00 0. "xc0_rpec0_pram,XC0_RPEC0_PRAM Single Bit Error occured" "0,1"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "ecc_ctrl_status_dbe,ECC status DBE: This register collects double bit error (DBE) status information"
|
|
bitfld.long 0x00 31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 30. "intrameth,INTRAMETH Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "xpic3_dram,XPIC3_DRAM Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 28. "xpic2_dram,XPIC2_DRAM Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "xpic1_dram,XPIC1_DRAM Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 26. "xpic0_dram,XPIC0_DRAM Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "xpic3_pram,XPIC3_PRAM Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 24. "xpic2_pram,XPIC2_PRAM Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "xpic1_pram,XPIC1_PRAM Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 22. "xpic0_pram,XPIC0_PRAM Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "xc1_pfifo,XC1_PFIFO Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 20. "xc0_pfifo,XC0_PFIFO Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "xc1_tpu1_ram,XC1_TPU1_RAM Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 18. "xc1_tpu0_ram,XC1_TPU0_RAM Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "xc0_tpu1_ram,XC0_TPU1_RAM Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 16. "xc0_tpu0_ram,XC0_TPU0_RAM Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "xc1_rpu1_ram,XC1_RPU1_RAM Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 14. "xc1_rpu0_ram,XC1_RPU0_RAM Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "xc0_rpu1_ram,XC0_RPU1_RAM Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 12. "xc0_rpu0_ram,XC0_RPU0_RAM Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "xc1_dpram1,XC1_DPRAM1 Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 10. "xc1_dpram0,XC1_DPRAM0 Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "xc0_dpram1,XC0_DPRAM1 Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 8. "xc0_dpram0,XC0_DPRAM0 Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "xc1_tpec1_pram,XC1_TPEC1_PRAM Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 6. "xc1_tpec0_pram,XC1_TPEC0_PRAM Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "xc0_tpec1_pram,XC0_TPEC1_PRAM Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 4. "xc0_tpec0_pram,XC0_TPEC0_PRAM Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "xc1_rpec1_pram,XC1_RPEC1_PRAM Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 2. "xc1_rpec0_pram,XC1_RPEC0_PRAM Double Bit Error occured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "xc0_rpec1_pram,XC0_RPEC1_PRAM Double Bit Error occured" "0,1"
|
|
bitfld.long 0x00 0. "xc0_rpec0_pram,XC0_RPEC0_PRAM Double Bit Error occured" "0,1"
|
|
tree.end
|
|
tree "DPM"
|
|
base ad:0xF4081000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "dpm_cfg0x0,DPM IO Control Register 0"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "endian,Endianess of 32 bit (DWord) address alignment (B0: least significant byte B3: most significant byte): { | | | | | coding Address A+3 A+2 A+1 A+0 00 little endian B3 B2 B1 B0 01 16 bit big endian B2 B3 B0 B1 10 32 bit big endian B0 B1 B2 B3 11.." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "mode,description too long please enter short description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "dpm_if_cfg,description too long please enter short description"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 24. "isa_bhe3_is_memcs16n,ISA usage of BHE3 signal" "0: BHE3 is used as byte-enable or PIO and input by,1: BHE3 is used as ISA memcs16n signal and driven"
|
|
newline
|
|
bitfld.long 0x00 19.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "cs_ctrl,chip-select controlling" "0: Use 1 low active chip-select signal (DPM_CSN),1: Use 2 low active chip-select signals (DPM_CSN..,2: Use high active chip-select signal (DPM_CSN),3: Use 2 high active chip-select signals (DPM_CSN,4: No chip-select signal,?,?,7: Chip access is disabled"
|
|
newline
|
|
bitfld.long 0x00 15. "addr_sh,Address is Byte address or shifted according to selected data size" "0,1"
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|
newline
|
|
bitfld.long 0x00 14. "aen_pol,Address-Enable active level polarity" "0: Address is latched while ALE-signal is low (i.e,1: Address is latched while ALE-signal is high"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "aen_sel,Address-Enable (AEN-modes) or Address-Latch-Enable (multiplexed modes) Control" "0: No additional Address controlling function,1: netx50 compatibe Address controlling signal,2: Not netx50 compatibe Address controlling signal,3: reserved"
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|
newline
|
|
bitfld.long 0x00 8.--11. "be_pol,DPM access byte-enable active level polarity" "0: BE signals are low active byte-enables,1: BE signals are high active byte-enables (e.g. 8,?..."
|
|
newline
|
|
bitfld.long 0x00 7. "be_wr_dis,DPM write access byte-enable configuration" "0: byte-enables will be used on write access only,1: byte-enables will be ignored on write access.."
|
|
newline
|
|
bitfld.long 0x00 6. "be_rd_dis,DPM read access byte-enable configuration" "0: byte-enables will be used on read access only,1: byte-enables will be ignored on read access all"
|
|
newline
|
|
bitfld.long 0x00 5. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "be_sel,DPM access byte-enable signal selection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "dir_ctrl,DPM access direction control" "0: dedicated low active read- and write control,1: RDn is direction signal nRW (signal high: write,2: RDn is direction signal nWR (signal low: write,?..."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "dpm_pio_cfg0,DPM PIO Configuration Register0"
|
|
hexmask.long 0x00 0.--31. 1. "sel_d_pio,Use related DPM_D-pin as PIO pin"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "dpm_pio_cfg1,DPM PIO Configuration Register1"
|
|
bitfld.long 0x00 31. "sel_sirq_pio,Use DPM_SIRQ-pin as PIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "sel_dirq_pio,Use DPM_DIRQ-pin as PIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "sel_rdy_pio,Use DPM_RDY-pin as PIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "sel_wrn_pio,Use DPM_WRN-pin as PIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "sel_rdn_pio,Use DPM_RDN-pin as PIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "sel_csn_pio,Use DPM_CSN-pin as PIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "sel_bhe3_pio,Use DPM_BHE3-pin as PIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "sel_bhe1_pio,Use DPM_BHE1-pin as PIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "sel_a_pio,Use related DPM_A-pin as PIO pin"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "dpm_addr_cfg,DPM External Address Configuration Register"
|
|
bitfld.long 0x00 30.--31. "addr_cmp_a19,Address comparator controlling for DPM_A19" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "addr_cmp_a18,Address comparator controlling for DPM_A18" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "addr_cmp_a17,Address comparator controlling for DPM_A17" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "addr_cmp_a16,Address comparator controlling for DPM_A16" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "addr_cmp_a15,Address comparator controlling for DPM_A15" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "addr_cmp_a14,Address comparator controlling for DPM_A14" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "addr_cmp_a13,Address comparator controlling for DPM_A13" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "addr_cmp_a12,Address comparator controlling for DPM_A12" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "addr_cmp_a11,Address comparator controlling for DPM_A11" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 6.--13. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "cfg_win_addr_cfg,Location of the DPM Configuration Window (Window 0)" "0: Low Configuration Window,1: High Configuration Window,2: reserved,3: Configuration Window is disabled for external"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "addr_range,DPM external address range" "0: Address bits A7..0 are sampled from DPM_D7..0,1: Address bits A16..1 are sampled from DPM_D15..0,2: 16 bit data multiplexed mode 1024KB address,?..."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "dpm_timing_cfg,DPM timing and access configuration register"
|
|
bitfld.long 0x00 31. "sdpm_miso_early,Serial DPM early MISO (read-data) generation" "0: Change MISO on the clock edge following the,1: Change MISO on the sampling edge"
|
|
newline
|
|
bitfld.long 0x00 30. "en_dpm_serial_sqi,When DPM is in serial mode ('dpm_status.sel_dpm_serial' active) serial DPM can be switched to SQI-compatible 4-bit mode" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 8.--29. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 7. "rd_burst_en,Read burst enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "t_rds,Read data setup time (in steps of 10ns)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "filter,Filter DPM Control Signals" "0: no spike suppression,1: Spikes < 10ns are suppressed read data access"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "t_osa,Address Setup Time (t_osa * 10ns)" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "dpm_rdy_cfg,DPM Ready (DPM_RDY) Signal Configuration Register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "rdy_to_cfg,Ready Timeout Configuration" "0: Ready Timeout after 2048 netX system clock,1: Ready Timeout after 256 netX system clock..,2: reserved,3: Ready Timeout disabled"
|
|
newline
|
|
bitfld.long 0x00 3. "rdy_sig_mode,Ready signal mode" "0: DPM_RDY is generated as wait/busy state signal,1: DPM_RDY is generated as ready/acknowledge pulse"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "rdy_drv_mode,Ready generation mode" "0: ready signal generation is disabled,1: ready is driven when active and inactive,2: ready is driven when active and for a short..,3: ready is only driven when cycle active"
|
|
newline
|
|
bitfld.long 0x00 0. "rdy_pol,Ready signal ready-state polarity" "0: DPM is busy when external RDY-signal is high,1: DPM is ready when external RDY-signal is high"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "dpm_status,description too long please enter short description"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 7. "sel_dpm_serial,Serial mode configuration state" "0: DPM is in parallel mode,1: DPM is in serial mode"
|
|
newline
|
|
bitfld.long 0x00 6. "bus_conflict_rd_addr_err,Parallel DPM read access address change bus error detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "bus_conflict_rd_err,Parallel DPM read access bus error detected" "0: Write-control (nWR) signal becomes active (low,1: Direction line (nRD) signal changes to write"
|
|
newline
|
|
bitfld.long 0x00 4. "bus_conflict_wr_err,Parallel DPM write access bus error detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "rdy_to_err,DPM_RDY Timeout Error Status Flag" "0: Access was finished successfully by DPM_RDY,1: Last access went to netX busy address and was"
|
|
newline
|
|
bitfld.long 0x00 2. "wr_err,DPM Write Error Status Flag" "0: Write access terminated without error,1: The external DPM write access was too fast to"
|
|
newline
|
|
bitfld.long 0x00 1. "rd_err,DPM Read Error Status Flag" "0: Read data OK,1: The external DPM read access was too fast"
|
|
newline
|
|
bitfld.long 0x00 0. "unlocked,DPM is locked during netX power up and boot phase" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "dpm_status_err_reset,DPM Error Status Reset Register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "bus_conflict_rd_addr_err_rst,Parallel DPM read access address change bus error detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "bus_conflict_rd_err_rst,Parallel DPM read access bus error detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "bus_conflict_wr_err_rst,Parallel DPM write access bus error detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "rdy_to_err_rst,DPM_RDY timeout error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "wr_err_rst,DPM write error detection bit with auto reset function" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "rd_err_rst,DPM read error detection bit with auto reset function" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "dpm_status_err_addr,DPM Error Address Status Register"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "err_addr,Access error address"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "dpm_misc_cfg,DPM Configuration Register for some Special Functions"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 2. "dis_bus_conflict_err_detect,This bit controls bus-error-detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "dis_access_err_halt,Disable halt after access-errors where detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "enable_flag_reset_on_rd,Enable Status Flag Reset by reading the 'dpm_status_err_reset' register" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "dpm_io_cfg_misc,DPM IO Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 7. "fiq_oec,FIQ/SIRQ output enable controlled" "0: FIQ/SIRQ signal is always driven,1: FIQ/SIRQ signal is only driven when active"
|
|
newline
|
|
bitfld.long 0x00 6. "fiq_pol,FIQ/SIRQ signal polarity" "0: FIQ/SIRQ is active low,1: FIQ/SIRQ is active high"
|
|
newline
|
|
bitfld.long 0x00 5. "irq_oec,IRQ output enable controlled" "0: IRQ/DIRQ signal is always driven,1: IRQ/DIRQ signal is only driven when active"
|
|
newline
|
|
bitfld.long 0x00 4. "irq_pol,IRQ/DIRQ signal polarity" "0: IRQ/DIRQ is active low,1: IRQ/DIRQ is active high"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "dpm_tunnel_cfg,description too long please enter short description"
|
|
bitfld.long 0x00 31. "wp_cfg_win,Write-protect tunnel configuration inside the configuration window 0" "0: The two tunnel configuration registers,1: The tunnel configuration registers"
|
|
newline
|
|
hexmask.long.word 0x00 20.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 6.--19. 1. "base,DPM Access Tunnel (DATunnel) Base Address divided by 64 on external visible address space"
|
|
newline
|
|
bitfld.long 0x00 5. "dis_rd_latch,Disabled read data latch for Tunnel" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "byte_area,Tunnel is byte area or not" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "tunnel_all,Enable/disable external access to Internal Target Base Address (ITBAddr) Configuration Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "enable,Enable/disable Access Tunnel function" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_itbaddr,ITBAddr is write-protected from host" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wp_data,Access Tunnel function is write-protected from data access (DWords 0 to 14 of DATunnel)" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "dpm_itbaddr,DPM Access Tunnel (DATunnel) netX Internal Target Base Address (ITBAddr) Configuration Register"
|
|
hexmask.long 0x00 6.--31. 1. "base,Internal netX Tunnel Target Base Address (ITBAddr) divided by 64"
|
|
newline
|
|
bitfld.long 0x00 2.--5. "map,Mapping part of ITBAddr" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_itbaddr_ro,ITBAddr is write-protected from host" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wp_data_ro,Access Tunnel function is write-protected from data access (DWords 0 to 14 of DATunnel)" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "dpm_win1_end,DPM Window 1 End Address Configuration Register"
|
|
hexmask.long.word 0x00 21.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 7.--20. 1. "win_end,Window 1 End Address divided by 128"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "dpm_win1_map,DPM Window 1 Address Map Configuration Register"
|
|
hexmask.long.word 0x00 20.--31. 1. "win_page,Window 1 address page"
|
|
newline
|
|
hexmask.long.word 0x00 7.--19. 1. "win_map,Window 1 Address Mapping"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "wp_cfg_win,Write-protect window configuration inside the configuration window 0" "0: All 8 window configuration registers,1: All 8 window configuration registers"
|
|
newline
|
|
bitfld.long 0x00 4. "dis_rd_latch,Window 1 read data latch disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "win_map_alt,Window 1 Alternative Address Mapping Configuration" "0: Alternative Address Mapping disabled,1: Alternative Address Mapping enabled,2: Alternative Address Mapping enabled,3: reserved If Alternative Address Mapping is"
|
|
newline
|
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bitfld.long 0x00 1. "read_ahead,Read ahead" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "byte_area,Window is byte-write area" "0: Target area of this window is 32 bit accessible,1: Target area of this window is byte accessible"
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group.long 0x48++0x03
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line.long 0x00 "dpm_win2_end,DPM Window 2 End Address Configuration Register"
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|
hexmask.long.word 0x00 21.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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newline
|
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hexmask.long.word 0x00 7.--20. 1. "win_end,Window 2 End Address divided by 128"
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newline
|
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hexmask.long.byte 0x00 0.--6. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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group.long 0x4C++0x03
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line.long 0x00 "dpm_win2_map,DPM Window 2 Address Map Configuration Register"
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hexmask.long.word 0x00 20.--31. 1. "win_page,Window address page"
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newline
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hexmask.long.word 0x00 7.--19. 1. "win_map,Window address mapping"
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newline
|
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bitfld.long 0x00 5.--6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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newline
|
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bitfld.long 0x00 4. "dis_rd_latch,Window read data latch disable" "0,1"
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newline
|
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bitfld.long 0x00 2.--3. "win_map_alt,Window Alternative Address Mapping Configuration" "0,1,2,3"
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|
newline
|
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bitfld.long 0x00 1. "read_ahead,Read ahead" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "byte_area,Window is byte area" "0,1"
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group.long 0x50++0x03
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line.long 0x00 "dpm_win3_end,DPM Window 3 End Address Configuration Register"
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hexmask.long.word 0x00 21.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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newline
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hexmask.long.word 0x00 7.--20. 1. "win_end,Window 3 End Address divided by 128"
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newline
|
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hexmask.long.byte 0x00 0.--6. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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group.long 0x54++0x03
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line.long 0x00 "dpm_win3_map,DPM Window 3 Address Map Configuration Register"
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hexmask.long.word 0x00 20.--31. 1. "win_page,Window address page"
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newline
|
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hexmask.long.word 0x00 7.--19. 1. "win_map,Window map address"
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newline
|
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bitfld.long 0x00 5.--6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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newline
|
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bitfld.long 0x00 4. "dis_rd_latch,Window read data latch disable" "0,1"
|
|
newline
|
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bitfld.long 0x00 2.--3. "win_map_alt,Window Alternative Address Mapping Configuration" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x00 1. "read_ahead,Read ahead" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "byte_area,Window is byte area" "0,1"
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group.long 0x58++0x03
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line.long 0x00 "dpm_win4_end,DPM Window 4 End Address Configuration Register"
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hexmask.long.word 0x00 21.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 7.--20. 1. "win_end,Window 4 End Address divided by 128"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
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group.long 0x5C++0x03
|
|
line.long 0x00 "dpm_win4_map,DPM Window 4 Address Map Configuration Register"
|
|
hexmask.long.word 0x00 20.--31. 1. "win_page,Window address page"
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|
newline
|
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hexmask.long.word 0x00 7.--19. 1. "win_map,Window map address"
|
|
newline
|
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bitfld.long 0x00 5.--6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x00 4. "dis_rd_latch,Window read data latch disable" "0,1"
|
|
newline
|
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bitfld.long 0x00 2.--3. "win_map_alt,Window Alternative Address Mapping Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "read_ahead,Read ahead" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "byte_area,Window is byte area" "0,1"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "dpm_irq_raw,DPM Raw (before masking) IRQ Status Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
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bitfld.long 0x00 9. "crypt,raw CRYPT unit interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,raw Trigger-Latch of xC23 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,raw Trigger-Latch of xC01 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,raw combined GPIO 0-15 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,raw combined Watchdog from WDG_SYS and XPIC_WDG module interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,raw ARM_TIMER (arm_timer_systime_s) interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,raw ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,raw combined handshake-cell and SYS_STA firmware interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "dpm_err,raw DPM access error interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "dpm_sw,raw software IRQ for netX IRQ targets (e.g. ARM xPIC) interrupt" "0,1"
|
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group.long 0x84++0x03
|
|
line.long 0x00 "dpm_irq_arm_mask_set,DPM Interrupt Mask Register for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
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bitfld.long 0x00 9. "crypt,set CRYPT unit interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,set Trigger-Latch of xC23 interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,set Trigger-Latch of xC01 interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "gpio,set combined GPIO 0-15 interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,set combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,set ARM_TIMER (arm_timer_systime_s) interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,set ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,set combined handshake-cell and SYS_STA firmware interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "dpm_err,set DPM access error interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,set software IRQ for netX IRQ targets (e.g. ARM xPIC) interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "dpm_irq_arm_mask_reset,DPM Interrupt Mask Reset Register for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,reset CRYPT unit interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,reset Trigger-Latch of xC23 interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,reset Trigger-Latch of xC01 interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,reset combined GPIO 0-15 interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,reset combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,reset ARM_TIMER (arm_timer_systime_s) interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,reset ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,reset combined handshake-cell and SYS_STA firmware interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "dpm_err,reset DPM access error interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,reset software IRQ for netX IRQ targets (e.g. ARM xPIC) interrupt mask for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "dpm_irq_arm_masked,DPM Masked Interrupt Status Register for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,masked CRYPT unit interrupt state for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,masked Trigger-Latch of xC23 interrupt state for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,masked Trigger-Latch of xC01 interrupt state for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,masked combined GPIO 0-15 interrupt state for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,masked combined Watchdog from WDG_SYS and XPIC_WDG module interrupt state for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,masked ARM_TIMER (arm_timer_systime_s) interrupt state for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,masked ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt state for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,masked combined handshake-cell and SYS_STA firmware interrupt state for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "dpm_err,masked DPM access error interrupt state for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,masked software IRQ for netX IRQ targets (e.g. ARM xPIC) interrupt state for netX internal ARM-CPU (part of SYSTEM IRQ for ARM CPU(s))" "0,1"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "dpm_irq_xpic_mask_set,DPM Interrupt Mask Register for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,set CRYPT unit interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,set Trigger-Latch of xC23 interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,set Trigger-Latch of xC01 interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,set combined GPIO 0-15 interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,set combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,set ARM_TIMER (arm_timer_systime_s) interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,set ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,set combined handshake-cell and SYS_STA firmware interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "dpm_err,set DPM access error interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,set software IRQ for netX IRQ targets (e.g. ARM xPIC) interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "dpm_irq_xpic_mask_reset,DPM Interrupt Mask Reset Register for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,reset CRYPT unit interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,reset Trigger-Latch of xC23 interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,reset Trigger-Latch of xC01 interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,reset combined GPIO 0-15 interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,reset combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,reset ARM_TIMER (arm_timer_systime_s) interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,reset ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,reset combined handshake-cell and SYS_STA firmware interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "dpm_err,reset DPM access error interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,reset software IRQ for netX IRQ targets (e.g. ARM xPIC) interrupt mask for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "dpm_irq_xpic_masked,DPM Masked Interrupt Status Register for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,masked CRYPT unit interrupt state for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,masked Trigger-Latch of xC23 interrupt state for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,masked Trigger-Latch of xC01 interrupt state for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,masked combined GPIO 0-15 interrupt state for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,masked combined Watchdog from WDG_SYS and XPIC_WDG module interrupt state for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,masked ARM_TIMER (arm_timer_systime_s) interrupt state for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,masked ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt state for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,masked combined handshake-cell and SYS_STA firmware interrupt state for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "dpm_err,masked DPM access error interrupt state for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,masked software IRQ for netX IRQ targets (e.g. ARM xPIC) interrupt state for netX internal xPIC-CPU (part of XSYSTEM xPIC-IRQ)" "0,1"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "dpm_irq_fiq_mask_set,DPM Interrupt Mask Register for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,set CRYPT unit interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,set Trigger-Latch of xC23 interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,set Trigger-Latch of xC01 interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,set combined GPIO 0-15 interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,set combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,set ARM_TIMER (arm_timer_systime_s) interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,set ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,set combined handshake-cell and SYS_STA firmware interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "dpm_err,set DPM access error interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,set software IRQ for netX IRQ targets (e.g. ARM xPIC) interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "dpm_irq_fiq_mask_reset,DPM Interrupt Mask Reset Register for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,reset CRYPT unit interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,reset Trigger-Latch of xC23 interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "trigger_lt0,reset Trigger-Latch of xC01 interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "gpio,reset combined GPIO 0-15 interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,reset combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "systime_s,reset ARM_TIMER (arm_timer_systime_s) interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "systime_ns,reset ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
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|
newline
|
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bitfld.long 0x00 2. "firmware,reset combined handshake-cell and SYS_STA firmware interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
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newline
|
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bitfld.long 0x00 1. "dpm_err,reset DPM access error interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
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newline
|
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bitfld.long 0x00 0. "dpm_sw,reset software IRQ for netX IRQ targets (e.g. ARM xPIC) interrupt mask for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
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rgroup.long 0xA4++0x03
|
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line.long 0x00 "dpm_irq_fiq_masked,DPM Masked Interrupt Status Register for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
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bitfld.long 0x00 9. "crypt,masked CRYPT unit interrupt state for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "trigger_lt1,masked Trigger-Latch of xC23 interrupt state for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "trigger_lt0,masked Trigger-Latch of xC01 interrupt state for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "gpio,masked combined GPIO 0-15 interrupt state for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "watchdog,masked combined Watchdog from WDG_SYS and XPIC_WDG module interrupt state for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "systime_s,masked ARM_TIMER (arm_timer_systime_s) interrupt state for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "systime_ns,masked ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt state for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
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newline
|
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bitfld.long 0x00 2. "firmware,masked combined handshake-cell and SYS_STA firmware interrupt state for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "dpm_err,masked DPM access error interrupt state for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
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newline
|
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bitfld.long 0x00 0. "dpm_sw,masked software IRQ for netX IRQ targets (e.g. ARM xPIC) interrupt state for fast netX interrupt output signal (DPM_FIQ/HIF_SIRQ)" "0,1"
|
|
group.long 0xA8++0x03
|
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line.long 0x00 "dpm_irq_irq_mask_set,DPM Interrupt Mask Register for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)"
|
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hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
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bitfld.long 0x00 9. "crypt,set CRYPT unit interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
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newline
|
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bitfld.long 0x00 8. "trigger_lt1,set Trigger-Latch of xC23 interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
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newline
|
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bitfld.long 0x00 7. "trigger_lt0,set Trigger-Latch of xC01 interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
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newline
|
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bitfld.long 0x00 6. "gpio,set combined GPIO 0-15 interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
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newline
|
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bitfld.long 0x00 5. "watchdog,set combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "systime_s,set ARM_TIMER (arm_timer_systime_s) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "systime_ns,set ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
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newline
|
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bitfld.long 0x00 2. "firmware,set combined handshake-cell and SYS_STA firmware interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
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newline
|
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bitfld.long 0x00 1. "dpm_err,set DPM access error interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "dpm_sw,set software IRQ for netX IRQ targets (e.g. ARM xPIC) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
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|
group.long 0xAC++0x03
|
|
line.long 0x00 "dpm_irq_irq_mask_reset,DPM Interrupt Mask Reset Register for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)"
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hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
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bitfld.long 0x00 9. "crypt,reset CRYPT unit interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "trigger_lt1,reset Trigger-Latch of xC23 interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "trigger_lt0,reset Trigger-Latch of xC01 interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,reset combined GPIO 0-15 interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,reset combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,reset ARM_TIMER (arm_timer_systime_s) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "systime_ns,reset ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "firmware,reset combined handshake-cell and SYS_STA firmware interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "dpm_err,reset DPM access error interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "dpm_sw,reset software IRQ for netX IRQ targets (e.g. ARM xPIC) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
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|
rgroup.long 0xB0++0x03
|
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line.long 0x00 "dpm_irq_irq_masked,DPM Masked Interrupt Status Register for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)"
|
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hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
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bitfld.long 0x00 9. "crypt,masked CRYPT unit interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "trigger_lt1,masked Trigger-Latch of xC23 interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "trigger_lt0,masked Trigger-Latch of xC01 interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "gpio,masked combined GPIO 0-15 interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "watchdog,masked combined Watchdog from WDG_SYS and XPIC_WDG module interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "systime_s,masked ARM_TIMER (arm_timer_systime_s) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "systime_ns,masked ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "firmware,masked combined handshake-cell and SYS_STA firmware interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "dpm_err,masked DPM access error interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "dpm_sw,masked software IRQ for netX IRQ targets (e.g. ARM xPIC) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)" "0,1"
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group.long 0xB8++0x03
|
|
line.long 0x00 "dpm_sw_irq,DPM Register for Software Interrupt Generation to Host and netX Interrupt Targets"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
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bitfld.long 0x00 11. "reset_irq,Reset 'dpm_sw' IRQ for IRQ-signal (always 0 when read)" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "reset_fiq,Reset 'dpm_sw' IRQ for FIQ-signal (always 0 when read)" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "reset_xpic,Reset 'dpm_sw' IRQ for xPIC (always 0 when read)" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "reset_arm,Reset 'dpm_sw' IRQ for ARM (always 0 when read)" "0,1"
|
|
newline
|
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bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x00 3. "set_irq,Set 'dpm_sw' IRQ for IRQ-signal (current 'dpm_sw' status for IRQ when read)" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "set_fiq,Set 'dpm_sw' IRQ for FIQ-signal (current 'dpm_sw' status for FIQ when read)" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "set_xpic,Set 'dpm_sw' IRQ for xPIC (current 'dpm_sw' status for xPIC when read)" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "set_arm,Set 'dpm_sw' IRQ for ARM (current 'dpm_sw' status for ARM when read)" "0,1"
|
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group.long 0xBC++0x03
|
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line.long 0x00 "dpm_crc,DPM CRC for access to NETX data (window1-4)"
|
|
hexmask.long.word 0x00 16.--31. 1. "crc_wdata,Provides the current CRC of data written to DPM windows 1-4 since last write-CRC clear"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "crc_rdata,Provides the current CRC of data read from DPM windows 1-4 since last read-CRC clear"
|
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rgroup.long 0xC0++0x03
|
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line.long 0x00 "dpm_reserved_netx50_wgd_host_timeout,Address reserved for netx50 DPM_HOST_WDG_HOST_TIMEOUT"
|
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hexmask.long 0x00 0.--31. 1. "zero_ro,reserved for netx50 DPM_HOST_WDG_HOST_TIMEOUT"
|
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rgroup.long 0xC4++0x03
|
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line.long 0x00 "dpm_reserved_netx50_wgd_host_trigger,Address reserved for netx50 DPM_HOST_WDG_HOST_TRIG"
|
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hexmask.long 0x00 0.--31. 1. "zero_ro,reserved for netx50 DPM_HOST_WDG_HOST_TRIG"
|
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rgroup.long 0xC8++0x03
|
|
line.long 0x00 "dpm_reserved_netx50_wgd_netx_timeout,Address reserved for netx50 DPM_HOST_WDG_ARM_TIMEOUT"
|
|
hexmask.long 0x00 0.--31. 1. "zero_ro,reserved for netx50 DPM_HOST_WDG_ARM_TIMEOUT"
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "dpm_sys_sta_bigend16,DPM System Status Information Register in big endianess 16 data mapping"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HOST_STATE_swap_ro,Bit field for Hilscher firmware compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "NETX_STATE_swap_ro,Bit field for Hilscher firmware compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "RUN_ro,Output state of netX RUN LED IO" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "RDY_ro,Output state of netX RDY LED IO" "0,1"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "NETX_STA_CODE_swap_ro,Bit field for Hilscher firmware compatibility"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "dpm_reserved_netx50_timer_ctrl,Address reserved for netx50 DPM_HOST_TMR_CTRL"
|
|
hexmask.long 0x00 0.--31. 1. "zero_ro,reserved for netx50 DPM_HOST_TMR_CTRL"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "dpm_reserved_netx50_timer_start_val,Address reserved for netx50 DPM_HOST_TMR_START_VAL"
|
|
hexmask.long 0x00 0.--31. 1. "zero_ro,reserved for netx50 DPM_HOST_TMR_START_VAL"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "dpm_sys_sta,DPM System Status Information Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "NETX_STA_CODE_ro,Bit field for Hilscher firmware compatibility (read only)"
|
|
newline
|
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bitfld.long 0x00 4.--7. "HOST_STATE,Bit field for Hilscher firmware compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x00 2.--3. "NETX_STATE_ro,Bit field for Hilscher firmware compatibility" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x00 1. "RUN_ro,Output state of netX RUN LED IO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RDY_ro,Output state of netX RDY LED IO" "0,1"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "dpm_reset_request,DPM Reset Request Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "reset_key,Reset key sequence register"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "dpm_firmware_irq_raw,1st netx50 compatible DPM Interrupt Status Register (related to 'dpm_firmware_irq_mask'-register)"
|
|
bitfld.long 0x00 31. "INT_REQ,Interrupt Request for IRQs handled in this register" "0: No Interrupts to host requested by IRQ sources,1: IRQ sources handled in this register request a"
|
|
newline
|
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bitfld.long 0x00 30. "res_MEM_LCK_ro,reserved for Memory Lock IRQ flag (not available in this netX version)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "res_WDG_NETX_ro,reserved for netX supervision Watchdog Timeout IRQ flag (not available in this netX version)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "RDY_TIMEOUT,DPM_RDY timeout error was detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "SYS_STA,System Status Change IRQ flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "res_TMR_ro,reserved for Timer IRQ flag (not available in this netX version)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "IRQ_VECTOR,Interrupt Vector according to status flags generated by enabled IRQ sources"
|
|
newline
|
|
bitfld.long 0x00 15. "HS_EVENT15,Handshake Event 15 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "HS_EVENT14,Handshake Event 14 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "HS_EVENT13,Handshake Event 13 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "HS_EVENT12,Handshake Event 12 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "HS_EVENT11,Handshake Event 11 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "HS_EVENT10,Handshake Event 10 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "HS_EVENT9,Handshake Event 9 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "HS_EVENT8,Handshake Event 8 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "HS_EVENT7,Handshake Event 7 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "HS_EVENT6,Handshake Event 6 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "HS_EVENT5,Handshake Event 5 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "HS_EVENT4,Handshake Event 4 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "HS_EVENT3,Handshake Event 3 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "HS_EVENT2,Handshake Event 2 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "HS_EVENT1,Handshake Event 1 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "HS_EVENT0,Handshake Event 0 IRQ status flag" "0,1"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "dpm_firmware_irq_mask,DPM Handshake Interrupt Enable Register"
|
|
bitfld.long 0x00 31. "INT_EN,Interrupt Enable for IRQs handled in this register" "0: No Interrupts to host ARM or xPIC are generated,1: Enabled IRQ sources handled in this register"
|
|
newline
|
|
bitfld.long 0x00 30. "res_MEM_LCK_ro,reserved for Memory Lock IRQ (not available in this netX version)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "res_WDG_NETX_ro,reserved for netX supervision Watchdog Timeout IRQ (not available in this netX version)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "RDY_TIMEOUT,Enable for 'dpm_firmware_irq_raw.RDY_TIMEOUT' bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "SYS_STA,System Status Change IRQ Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "res_TMR_ro,reserved for Timer IRQ (not available in this netX version)" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 16.--24. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 15. "HS_EVENT15,Handshake Event 15 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "HS_EVENT14,Handshake Event 14 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "HS_EVENT13,Handshake Event 13 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "HS_EVENT12,Handshake Event 12 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "HS_EVENT11,Handshake Event 11 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "HS_EVENT10,Handshake Event 10 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "HS_EVENT9,Handshake Event 9 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "HS_EVENT8,Handshake Event 8 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "HS_EVENT7,Handshake Event 7 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "HS_EVENT6,Handshake Event 6 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "HS_EVENT5,Handshake Event 5 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "HS_EVENT4,Handshake Event 4 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "HS_EVENT3,Handshake Event 3 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "HS_EVENT2,Handshake Event 2 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "HS_EVENT1,Handshake Event 1 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "HS_EVENT0,Handshake Event 0 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "dpm_netx_version_bigend16,DPM netX Version Register in big endianess 16 data mapping"
|
|
hexmask.long.byte 0x00 24.--31. 1. "netx_version_byte2_swap,netX version bits 24 to 16"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "netx_version_byte3_swap,netX version bits 31 to 24"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "netx_version_byte0_swap,netX version bits 8 to 0"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "netx_version_byte1_swap,netX version bits 16 to 8"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "dpm_netx_version,DPM netX Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "netx_version_byte3,netX version bits 31 to 24"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "netx_version_byte2,netX version bits 24 to 16"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "netx_version_byte1,netX version bits 16 to 8"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "netx_version_byte0,netX version bits 8 to 0"
|
|
tree.end
|
|
tree "IDPM"
|
|
repeat 2. (list 0. 1.) (list ad:0xF4081200 ad:0xF4081300)
|
|
tree "IDPM$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "idpm_cfg0x0,DPM IO Control Register 0"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "endian,Endianess of 32 bit (DWord) address alignment (B0: least significant byte B3: most significant byte): { | | | | | coding Address A+3 A+2 A+1 A+0 00 little endian B3 B2 B1 B0 01 16 bit big endian B2 B3 B0 B1 10 32 bit big endian B0 B1 B2 B3 11.." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,Global IDPM enable bit" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "idpm_addr_cfg,DPM External Address Configuration Register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "cfg_win_addr_cfg,Location of the DPM Configuration Window (Window 0)" "0: Low Configuration Window,1: High Configuration Window,2: reserved,3: Configuration Window is disabled for external"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "idpm_status,DPM Status Register"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "unlocked,DPM is locked during netX power up and boot phase" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "idpm_tunnel_cfg,description too long please enter short description"
|
|
bitfld.long 0x00 31. "wp_cfg_win,Write-protect tunnel configuration inside the configuration window 0" "0: The two tunnel configuration registers,1: The tunnel configuration registers"
|
|
newline
|
|
hexmask.long.word 0x00 16.--30. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 6.--15. 1. "base,DPM Access Tunnel (DATunnel) Base Address divided by 64 on external visible address space"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3. "tunnel_all,Enable/disable the ITBAddr configuration register at tunnel offset 0x3C" "0: Only 15 DWords are tunneled to the internal,1: All 16 DWords are tunneled to the internal"
|
|
newline
|
|
bitfld.long 0x00 2. "enable,Enable/disable Access Tunnel function" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_itbaddr,ITBAddr is write-protected from host" "0: The ITBAddr is mirrored to offset 0x3C of the,1: ITBAddr (Internal netX 32 bit Tunnel Target.."
|
|
newline
|
|
bitfld.long 0x00 0. "wp_data,Access Tunnel function is write-protected for data access (DWords 0 to 14 (15 for 'tunnel_all') of DATunnel)" "0: Write access is forwarded through the tunnel,1: Write access to DWords 0 to 14 (15 for"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "idpm_itbaddr,DPM Access Tunnel (DATunnel) netX Internal Target Base Address (ITBAddr) Configuration Register"
|
|
hexmask.long 0x00 6.--31. 1. "base,Internal netX Tunnel Target Base Address (ITBAddr) divided by 64"
|
|
newline
|
|
bitfld.long 0x00 2.--5. "map,Mapping part of ITBAddr" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1. "wp_itbaddr_ro,ITBAddr is write-protected from host" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wp_data_ro,Access Tunnel function is write-protected from data access (DWords 0 to 14 of DATunnel)" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "idpm_win1_end,DPM Window 1 End Address Configuration Register"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 7.--16. 1. "win_end,Window 1 End Address divided by 128"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "idpm_win1_map,DPM Window 1 Address Map Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 7.--15. 1. "win_map,Window 1 Address Mapping"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "wp_cfg_win,Write-protect window configuration inside the configuration window 0" "0: All 8 window configuration registers,1: All 8 window configuration registers"
|
|
newline
|
|
bitfld.long 0x00 4. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "win_map_alt,Window 1 Alternative Address Mapping Configuration" "0: Alternative Address Mapping disabled,1: Alternative Address Mapping enabled,2: Alternative Address Mapping enabled,3: reserved If Alternative Address Mapping is"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "idpm_win2_end,DPM Window 2 End Address Configuration Register"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 7.--16. 1. "win_end,Window 2 End Address divided by 128"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "idpm_win2_map,DPM Window 2 Address Map Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 7.--15. 1. "win_map,Window address mapping"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "win_map_alt,Window Alternative Address Mapping Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "idpm_win3_end,DPM Window 3 End Address Configuration Register"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 7.--16. 1. "win_end,Window 3 End Address divided by 128"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "idpm_win3_map,DPM Window 3 Address Map Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 7.--15. 1. "win_map,Window map address"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "win_map_alt,Window Alternative Address Mapping Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "idpm_win4_end,DPM Window 4 End Address Configuration Register"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 7.--16. 1. "win_end,Window 4 End Address divided by 128"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "idpm_win4_map,DPM Window 4 Address Map Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 7.--15. 1. "win_map,Window map address"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "win_map_alt,Window Alternative Address Mapping Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "idpm_irq_raw,DPM Raw (before masking) IRQ Status Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,raw CRYPT unit interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,raw Trigger-Latch of xC23 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,raw Trigger-Latch of xC01 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,raw combined GPIO 0-15 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,raw combined Watchdog from WDG_SYS and XPIC_WDG module interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,raw ARM_TIMER (arm_timer_systime_s) interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,raw ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,raw combined handshake-cell and SYS_STA firmware interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,raw software IRQ for IRQ targets interrupt" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "idpm_irq_arm_mask_set,DPM Interrupt Mask Register for IDPM host interrupt to ARM"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,set CRYPT unit interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,set Trigger-Latch of xC23 interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,set Trigger-Latch of xC01 interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,set combined GPIO 0-15 interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,set combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,set ARM_TIMER (arm_timer_systime_s) interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,set ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,set combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,set software IRQ for IRQ targets interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "idpm_irq_arm_mask_reset,DPM Interrupt Mask Reset Register for IDPM host interrupt to ARM"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,reset CRYPT unit interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,reset Trigger-Latch of xC23 interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,reset Trigger-Latch of xC01 interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,reset combined GPIO 0-15 interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,reset combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,reset ARM_TIMER (arm_timer_systime_s) interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,reset ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,reset combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,reset software IRQ for IRQ targets interrupt mask for IDPM host interrupt to ARM" "0,1"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "idpm_irq_arm_masked,DPM Masked Interrupt Status Register for IDPM host interrupt to ARM"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,masked CRYPT unit interrupt state for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,masked Trigger-Latch of xC23 interrupt state for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,masked Trigger-Latch of xC01 interrupt state for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,masked combined GPIO 0-15 interrupt state for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,masked combined Watchdog from WDG_SYS and XPIC_WDG module interrupt state for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,masked ARM_TIMER (arm_timer_systime_s) interrupt state for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,masked ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt state for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,masked combined handshake-cell and SYS_STA firmware interrupt state for IDPM host interrupt to ARM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,masked software IRQ for IRQ targets interrupt state for IDPM host interrupt to ARM" "0,1"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "idpm_irq_pci_inta_mask_set,DPM Interrupt Mask Register for IDPM host interrupt to PCIe root complex legacy INTA"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,set CRYPT unit interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,set Trigger-Latch of xC23 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,set Trigger-Latch of xC01 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,set combined GPIO 0-15 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,set combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,set ARM_TIMER (arm_timer_systime_s) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,set ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,set combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,set software IRQ for IRQ targets interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "idpm_irq_pci_inta_mask_reset,DPM Interrupt Mask Reset Register for IDPM host interrupt to PCIe root complex legacy INTA"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,reset CRYPT unit interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,reset Trigger-Latch of xC23 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "trigger_lt0,reset Trigger-Latch of xC01 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,reset combined GPIO 0-15 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,reset combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,reset ARM_TIMER (arm_timer_systime_s) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "systime_ns,reset ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "firmware,reset combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
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|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "dpm_sw,reset software IRQ for IRQ targets interrupt mask for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
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rgroup.long 0x98++0x03
|
|
line.long 0x00 "idpm_irq_pci_inta_masked,DPM Masked Interrupt Status Register for IDPM host interrupt to PCIe root complex legacy INTA"
|
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hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
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bitfld.long 0x00 9. "crypt,masked CRYPT unit interrupt state for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "trigger_lt1,masked Trigger-Latch of xC23 interrupt state for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,masked Trigger-Latch of xC01 interrupt state for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,masked combined GPIO 0-15 interrupt state for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,masked combined Watchdog from WDG_SYS and XPIC_WDG module interrupt state for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "systime_s,masked ARM_TIMER (arm_timer_systime_s) interrupt state for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "systime_ns,masked ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt state for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "firmware,masked combined handshake-cell and SYS_STA firmware interrupt state for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "dpm_sw,masked software IRQ for IRQ targets interrupt state for IDPM host interrupt to PCIe root complex legacy INTA" "0,1"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "idpm_irq_pci_intb_mask_set,DPM Interrupt Mask Register for IDPM host interrupt to PCIe root complex legacy INTB"
|
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hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,set CRYPT unit interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,set Trigger-Latch of xC23 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,set Trigger-Latch of xC01 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,set combined GPIO 0-15 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,set combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,set ARM_TIMER (arm_timer_systime_s) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,set ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "firmware,set combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,set software IRQ for IRQ targets interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "idpm_irq_pci_intb_mask_reset,DPM Interrupt Mask Reset Register for IDPM host interrupt to PCIe root complex legacy INTB"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,reset CRYPT unit interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,reset Trigger-Latch of xC23 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,reset Trigger-Latch of xC01 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,reset combined GPIO 0-15 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,reset combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,reset ARM_TIMER (arm_timer_systime_s) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,reset ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,reset combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,reset software IRQ for IRQ targets interrupt mask for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "idpm_irq_pci_intb_masked,DPM Masked Interrupt Status Register for IDPM host interrupt to PCIe root complex legacy INTB"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,masked CRYPT unit interrupt state for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,masked Trigger-Latch of xC23 interrupt state for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,masked Trigger-Latch of xC01 interrupt state for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,masked combined GPIO 0-15 interrupt state for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,masked combined Watchdog from WDG_SYS and XPIC_WDG module interrupt state for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,masked ARM_TIMER (arm_timer_systime_s) interrupt state for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,masked ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt state for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,masked combined handshake-cell and SYS_STA firmware interrupt state for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,masked software IRQ for IRQ targets interrupt state for IDPM host interrupt to PCIe root complex legacy INTB" "0,1"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "idpm_irq_pci_intc_mask_set,DPM Interrupt Mask Register for IDPM host interrupt to PCIe root complex legacy INTC"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,set CRYPT unit interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,set Trigger-Latch of xC23 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,set Trigger-Latch of xC01 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,set combined GPIO 0-15 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,set combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,set ARM_TIMER (arm_timer_systime_s) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,set ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,set combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,set software IRQ for IRQ targets interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "idpm_irq_pci_intc_mask_reset,DPM Interrupt Mask Reset Register for IDPM host interrupt to PCIe root complex legacy INTC"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,reset CRYPT unit interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,reset Trigger-Latch of xC23 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,reset Trigger-Latch of xC01 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,reset combined GPIO 0-15 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,reset combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,reset ARM_TIMER (arm_timer_systime_s) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,reset ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,reset combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,reset software IRQ for IRQ targets interrupt mask for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "idpm_irq_pci_intc_masked,DPM Masked Interrupt Status Register for IDPM host interrupt to PCIe root complex legacy INTC"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,masked CRYPT unit interrupt state for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,masked Trigger-Latch of xC23 interrupt state for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,masked Trigger-Latch of xC01 interrupt state for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,masked combined GPIO 0-15 interrupt state for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,masked combined Watchdog from WDG_SYS and XPIC_WDG module interrupt state for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,masked ARM_TIMER (arm_timer_systime_s) interrupt state for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,masked ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt state for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,masked combined handshake-cell and SYS_STA firmware interrupt state for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,masked software IRQ for IRQ targets interrupt state for IDPM host interrupt to PCIe root complex legacy INTC" "0,1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "idpm_irq_pci_intd_mask_set,DPM Interrupt Mask Register for IDPM host interrupt to PCIe root complex legacy INTD"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,set CRYPT unit interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,set Trigger-Latch of xC23 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,set Trigger-Latch of xC01 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,set combined GPIO 0-15 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,set combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,set ARM_TIMER (arm_timer_systime_s) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,set ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,set combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,set software IRQ for IRQ targets interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "idpm_irq_pci_intd_mask_reset,DPM Interrupt Mask Reset Register for IDPM host interrupt to PCIe root complex legacy INTD"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,reset CRYPT unit interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,reset Trigger-Latch of xC23 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,reset Trigger-Latch of xC01 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,reset combined GPIO 0-15 interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,reset combined Watchdog from WDG_SYS and XPIC_WDG module interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,reset ARM_TIMER (arm_timer_systime_s) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,reset ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,reset combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,reset software IRQ for IRQ targets interrupt mask for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "idpm_irq_pci_intd_masked,DPM Masked Interrupt Status Register for IDPM host interrupt to PCIe root complex legacy INTD"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9. "crypt,masked CRYPT unit interrupt state for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "trigger_lt1,masked Trigger-Latch of xC23 interrupt state for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trigger_lt0,masked Trigger-Latch of xC01 interrupt state for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpio,masked combined GPIO 0-15 interrupt state for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "watchdog,masked combined Watchdog from WDG_SYS and XPIC_WDG module interrupt state for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_s,masked ARM_TIMER (arm_timer_systime_s) interrupt state for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "systime_ns,masked ARM_TIMER (arm_timer0 arm_timer1 arm_timer2) interrupt state for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "firmware,masked combined handshake-cell and SYS_STA firmware interrupt state for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dpm_sw,masked software IRQ for IRQ targets interrupt state for IDPM host interrupt to PCIe root complex legacy INTD" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "idpm_sw_irq,DPM Register for Software Interrupt Generation to Host and netX Interrupt Targets"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12. "reset_pci_d,Reset 'dpm_sw' IRQ for PCIe legacy IRQ D (current 'dpm_sw' status for pcie_d when read)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "reset_pci_c,Reset 'dpm_sw' IRQ for PCIe legacy IRQ C (current 'dpm_sw' status for pcie_c when read)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "reset_pci_b,Reset 'dpm_sw' IRQ for PCIe legacy IRQ B (current 'dpm_sw' status for pcie_b when read)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "reset_pci_a,Reset 'dpm_sw' IRQ for PCIe legacy IRQ A (current 'dpm_sw' status for pcie_a when read)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "reset_arm,Reset 'dpm_sw' IRQ for host (always 0 when read)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4. "set_pci_d,Set 'dpm_sw' IRQ for PCIe legacy IRQ D (current 'dpm_sw' status for pcie_d when read)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "set_pci_c,Set 'dpm_sw' IRQ for PCIe legacy IRQ C (current 'dpm_sw' status for pcie_c when read)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "set_pci_b,Set 'dpm_sw' IRQ for PCIe legacy IRQ B (current 'dpm_sw' status for pcie_b when read)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "set_pci_a,Set 'dpm_sw' IRQ for PCIe legacy IRQ A (current 'dpm_sw' status for pcie_a when read)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "set_arm,Set 'dpm_sw' IRQ for host (current 'dpm_sw' status for host when read)" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "idpm_sys_sta,DPM System Status Information Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "NETX_STA_CODE_ro,Bit field for Hilscher firmware compatibility (read only)"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "HOST_STATE,Bit field for Hilscher firmware" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "NETX_STATE_ro,Bit field for Hilscher firmware compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "RUN_ro,Output state of netX RUN LED IO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RDY_ro,Output state of netX RDY LED IO" "0,1"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "idpm_reset_request,DPM Reset Request Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "reset_key,Reset key sequence register"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "idpm_firmware_irq_raw,1st netx50 compatible DPM Interrupt Status Register (related to 'dpm_firmware_irq_mask'-register)"
|
|
bitfld.long 0x00 31. "INT_REQ,Interrupt Request for IRQs handled in this register" "0: No Interrupts to host requested by IRQ sources,1: IRQ sources handled in this register request a"
|
|
newline
|
|
bitfld.long 0x00 30. "res_MEM_LCK_ro,reserved for Memory Lock IRQ flag (not available in this netX version)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "res_WDG_NETX_ro,reserved for netX supervision Watchdog Timeout IRQ flag (not available in this netX version)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "res_RDY_TIMEOUT_ro,reserved DPM_RDY timeout error does not exist for IDPM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "SYS_STA,System Status Change IRQ flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "res_TMR_ro,reserved for Timer IRQ flag (not available in this netX version)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "IRQ_VECTOR,Interrupt Vector according to status flags generated by enabled IRQ sources"
|
|
newline
|
|
bitfld.long 0x00 15. "HS_EVENT15,Handshake Event 15 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "HS_EVENT14,Handshake Event 14 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "HS_EVENT13,Handshake Event 13 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "HS_EVENT12,Handshake Event 12 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "HS_EVENT11,Handshake Event 11 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "HS_EVENT10,Handshake Event 10 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "HS_EVENT9,Handshake Event 9 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "HS_EVENT8,Handshake Event 8 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "HS_EVENT7,Handshake Event 7 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "HS_EVENT6,Handshake Event 6 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "HS_EVENT5,Handshake Event 5 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "HS_EVENT4,Handshake Event 4 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "HS_EVENT3,Handshake Event 3 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "HS_EVENT2,Handshake Event 2 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "HS_EVENT1,Handshake Event 1 IRQ status flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "HS_EVENT0,Handshake Event 0 IRQ status flag" "0,1"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "idpm_firmware_irq_mask,DPM Handshake Interrupt Enable Register"
|
|
bitfld.long 0x00 31. "INT_EN,Interrupt Enable for IRQs handled in this register" "0: No Interrupts to host ARM or xPIC are generated,1: Enabled IRQ sources handled in this register"
|
|
newline
|
|
bitfld.long 0x00 30. "res_MEM_LCK_ro,reserved for Memory Lock IRQ (not available in this netX version)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "res_WDG_NETX_ro,reserved for netX supervision Watchdog Timeout IRQ (not available in this netX version)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "res_RDY_TIMEOUT_ro,reserved DPM_RDY timeout error does not exist for IDPM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "SYS_STA,System Status Change IRQ Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "res_TMR_ro,reserved for Timer IRQ (not available in this netX version)" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 16.--24. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 15. "HS_EVENT15,Handshake Event 15 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "HS_EVENT14,Handshake Event 14 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "HS_EVENT13,Handshake Event 13 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "HS_EVENT12,Handshake Event 12 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "HS_EVENT11,Handshake Event 11 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "HS_EVENT10,Handshake Event 10 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "HS_EVENT9,Handshake Event 9 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "HS_EVENT8,Handshake Event 8 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "HS_EVENT7,Handshake Event 7 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "HS_EVENT6,Handshake Event 6 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "HS_EVENT5,Handshake Event 5 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "HS_EVENT4,Handshake Event 4 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "HS_EVENT3,Handshake Event 3 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "HS_EVENT2,Handshake Event 2 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "HS_EVENT1,Handshake Event 1 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "HS_EVENT0,Handshake Event 0 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "idpm_netx_version,DPM netX Version Register"
|
|
hexmask.long 0x00 0.--31. 1. "netx_version,netX version from version register"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "HANDSHAKE_CTRL"
|
|
repeat 2. (list 0. 1.) (list ad:0xF4081400 ad:0xF4081500)
|
|
tree "HANDSHAKE_CTRL$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "handshake_base_addr,Handshake Cell address base configuration register"
|
|
bitfld.long 0x00 31. "enable,Global Handshake Cell address compare logic enable" "0: All Handshake Cell features like IRQ generation,1: Handshake Cell features are enabled for"
|
|
newline
|
|
bitfld.long 0x00 30. "netx50_comp,Netx50 compatibility for Handshake Cell IRQ generation" "0: Handshake Cell IRQ generation is netx10 (not,1: Handshake Cell IRQ generation is netx50"
|
|
newline
|
|
hexmask.long.word 0x00 16.--29. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "base256,Address base configuration in 256 byte steps inside 64kB INTRAMHS blocks"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "zero_ro,Low address bits not configurable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "handshake_cfg,Global handshake configuration register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "sel_dpm,Select DPM for this handshake unit" "0: DPM is internal IDPM (host connected via NoC,1: DPM is classic HIF-DPM (external host on HIF"
|
|
newline
|
|
bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "dis_irq_rst_rd_dpm,Disables the reset-IRQ-on-read behaviour of the handshake cells for DPM" "0: A handshake cell IRQ for the DPM is cleared..,1: A handshake cell IRQ for the DPM is not cleared"
|
|
newline
|
|
bitfld.long 0x00 1. "dis_irq_rst_rd_arm,Disables the reset-IRQ-on-read behaviour of the handshake cells for ARM" "0: A handshake cell IRQ for the ARM-CPU is cleared,1: A handshake cell IRQ for the ARM-CPU is not"
|
|
newline
|
|
bitfld.long 0x00 0. "dis_irq_rst_rd_xpic,Disables the reset-IRQ-on-read behaviour of the handshake cells for xPIC" "0: A handshake cell IRQ for the xPIC-CPU is..,1: A handshake cell IRQ for the xPIC-CPU is not"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "handshake_dpm_irq_raw_clear,Handshake Cell Raw Interrupt for DPM register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "hsc15,Handshake Cell 15 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "hsc14,Handshake Cell 14 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "hsc13,Handshake Cell 13 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "hsc12,Handshake Cell 12 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "hsc11,Handshake Cell 11 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "hsc10,Handshake Cell 10 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "hsc9,Handshake Cell 9 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "hsc8,Handshake Cell 8 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "hsc7,Handshake Cell 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "hsc6,Handshake Cell 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "hsc5,Handshake Cell 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "hsc4,Handshake Cell 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "hsc3,Handshake Cell 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "hsc2,Handshake Cell 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "hsc1,Handshake Cell 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "hsc0,Handshake Cell 0 IRQ" "0,1"
|
|
newline
|
|
abitfld.long 0x00 0.--7. "vector,Interrupt Vector generated by masked DPM IRQ flags" "0x00=0: No IRQ,0x10=16: Handshake Cell 0 IRQ,0x11=17: Handshake Cell 1 IRQ,0x12=18: Handshake Cell 2 IRQ,0x13=19: Handshake Cell 3 IRQ,0x14=20: Handshake Cell 4 IRQ,0x15=21: Handshake Cell 5 IRQ,0x16=22: Handshake Cell 6 IRQ,0x17=23: Handshake Cell 7 IRQ,0x18=24: Handshake Cell 8 IRQ,0x19=25: Handshake Cell 9 IRQ,0x1A=26: Handshake Cell 10 IRQ,0x1B=27: Handshake Cell 11 IRQ,0x1C=28: Handshake Cell 12 IRQ,0x1D=29: Handshake Cell 13 IRQ,0x1E=30: Handshake Cell 14 IRQ,0x1F=31: Handshake Cell 15 IRQ"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "handshake_dpm_irq_masked,Handshake Cell Masked Interrupt for DPM register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "hsc15,Handshake Cell 15 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "hsc14,Handshake Cell 14 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "hsc13,Handshake Cell 13 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "hsc12,Handshake Cell 12 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "hsc11,Handshake Cell 11 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "hsc10,Handshake Cell 10 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "hsc9,Handshake Cell 9 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "hsc8,Handshake Cell 8 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "hsc7,Handshake Cell 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "hsc6,Handshake Cell 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "hsc5,Handshake Cell 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "hsc4,Handshake Cell 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "hsc3,Handshake Cell 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "hsc2,Handshake Cell 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "hsc1,Handshake Cell 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "hsc0,Handshake Cell 0 IRQ" "0,1"
|
|
newline
|
|
abitfld.long 0x00 0.--7. "vector,Interrupt Vector generated by masked DPM IRQ flags" "0x00=0: No IRQ,0x10=16: Handshake Cell 0 IRQ,0x11=17: Handshake Cell 1 IRQ,0x12=18: Handshake Cell 2 IRQ,0x13=19: Handshake Cell 3 IRQ,0x14=20: Handshake Cell 4 IRQ,0x15=21: Handshake Cell 5 IRQ,0x16=22: Handshake Cell 6 IRQ,0x17=23: Handshake Cell 7 IRQ,0x18=24: Handshake Cell 8 IRQ,0x19=25: Handshake Cell 9 IRQ,0x1A=26: Handshake Cell 10 IRQ,0x1B=27: Handshake Cell 11 IRQ,0x1C=28: Handshake Cell 12 IRQ,0x1D=29: Handshake Cell 13 IRQ,0x1E=30: Handshake Cell 14 IRQ,0x1F=31: Handshake Cell 15 IRQ"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "handshake_dpm_irq_msk_set,Handshake Cell Interrupt Mask Enable for DPM register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "hsc15,Handshake Cell 15 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "hsc14,Handshake Cell 14 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "hsc13,Handshake Cell 13 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "hsc12,Handshake Cell 12 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "hsc11,Handshake Cell 11 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "hsc10,Handshake Cell 10 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "hsc9,Handshake Cell 9 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "hsc8,Handshake Cell 8 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "hsc7,Handshake Cell 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "hsc6,Handshake Cell 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "hsc5,Handshake Cell 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "hsc4,Handshake Cell 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "hsc3,Handshake Cell 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "hsc2,Handshake Cell 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "hsc1,Handshake Cell 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "hsc0,Handshake Cell 0 IRQ" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "handshake_dpm_irq_msk_reset,Handshake Cell Interrupt Mask Disable for DPM register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "hsc15,Handshake Cell 15 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "hsc14,Handshake Cell 14 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "hsc13,Handshake Cell 13 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "hsc12,Handshake Cell 12 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "hsc11,Handshake Cell 11 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "hsc10,Handshake Cell 10 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "hsc9,Handshake Cell 9 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "hsc8,Handshake Cell 8 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "hsc7,Handshake Cell 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "hsc6,Handshake Cell 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "hsc5,Handshake Cell 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "hsc4,Handshake Cell 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "hsc3,Handshake Cell 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "hsc2,Handshake Cell 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "hsc1,Handshake Cell 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "hsc0,Handshake Cell 0 IRQ" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "handshake_arm_irq_raw_clear,Handshake Cell Raw Interrupt for ARM register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "hsc15,Handshake Cell 15 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "hsc14,Handshake Cell 14 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "hsc13,Handshake Cell 13 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "hsc12,Handshake Cell 12 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "hsc11,Handshake Cell 11 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "hsc10,Handshake Cell 10 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "hsc9,Handshake Cell 9 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "hsc8,Handshake Cell 8 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "hsc7,Handshake Cell 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "hsc6,Handshake Cell 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "hsc5,Handshake Cell 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "hsc4,Handshake Cell 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "hsc3,Handshake Cell 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "hsc2,Handshake Cell 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "hsc1,Handshake Cell 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "hsc0,Handshake Cell 0 IRQ" "0,1"
|
|
newline
|
|
abitfld.long 0x00 0.--7. "vector,Interrupt Vector generated by masked ARM IRQ flags" "0x00=0: No IRQ,0x10=16: Handshake Cell 0 IRQ,0x11=17: Handshake Cell 1 IRQ,0x12=18: Handshake Cell 2 IRQ,0x13=19: Handshake Cell 3 IRQ,0x14=20: Handshake Cell 4 IRQ,0x15=21: Handshake Cell 5 IRQ,0x16=22: Handshake Cell 6 IRQ,0x17=23: Handshake Cell 7 IRQ,0x18=24: Handshake Cell 8 IRQ,0x19=25: Handshake Cell 9 IRQ,0x1A=26: Handshake Cell 10 IRQ,0x1B=27: Handshake Cell 11 IRQ,0x1C=28: Handshake Cell 12 IRQ,0x1D=29: Handshake Cell 13 IRQ,0x1E=30: Handshake Cell 14 IRQ,0x1F=31: Handshake Cell 15 IRQ"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "handshake_arm_irq_masked,Handshake Cell Masked Interrupt for ARM register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "hsc15,Handshake Cell 15 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "hsc14,Handshake Cell 14 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "hsc13,Handshake Cell 13 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "hsc12,Handshake Cell 12 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "hsc11,Handshake Cell 11 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "hsc10,Handshake Cell 10 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "hsc9,Handshake Cell 9 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "hsc8,Handshake Cell 8 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "hsc7,Handshake Cell 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "hsc6,Handshake Cell 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "hsc5,Handshake Cell 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "hsc4,Handshake Cell 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "hsc3,Handshake Cell 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "hsc2,Handshake Cell 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "hsc1,Handshake Cell 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "hsc0,Handshake Cell 0 IRQ" "0,1"
|
|
newline
|
|
abitfld.long 0x00 0.--7. "vector,Interrupt Vector generated by masked ARM IRQ flags" "0x00=0: No IRQ,0x10=16: Handshake Cell 0 IRQ,0x11=17: Handshake Cell 1 IRQ,0x12=18: Handshake Cell 2 IRQ,0x13=19: Handshake Cell 3 IRQ,0x14=20: Handshake Cell 4 IRQ,0x15=21: Handshake Cell 5 IRQ,0x16=22: Handshake Cell 6 IRQ,0x17=23: Handshake Cell 7 IRQ,0x18=24: Handshake Cell 8 IRQ,0x19=25: Handshake Cell 9 IRQ,0x1A=26: Handshake Cell 10 IRQ,0x1B=27: Handshake Cell 11 IRQ,0x1C=28: Handshake Cell 12 IRQ,0x1D=29: Handshake Cell 13 IRQ,0x1E=30: Handshake Cell 14 IRQ,0x1F=31: Handshake Cell 15 IRQ"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "handshake_arm_irq_msk_set,Handshake Cell Interrupt Mask Enable for ARM register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "hsc15,Handshake Cell 15 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "hsc14,Handshake Cell 14 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "hsc13,Handshake Cell 13 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "hsc12,Handshake Cell 12 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "hsc11,Handshake Cell 11 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "hsc10,Handshake Cell 10 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "hsc9,Handshake Cell 9 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "hsc8,Handshake Cell 8 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "hsc7,Handshake Cell 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "hsc6,Handshake Cell 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "hsc5,Handshake Cell 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "hsc4,Handshake Cell 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "hsc3,Handshake Cell 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "hsc2,Handshake Cell 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "hsc1,Handshake Cell 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "hsc0,Handshake Cell 0 IRQ" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "handshake_arm_irq_msk_reset,Handshake Cell Interrupt Mask Disable for ARM register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "hsc15,Handshake Cell 15 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "hsc14,Handshake Cell 14 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "hsc13,Handshake Cell 13 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "hsc12,Handshake Cell 12 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "hsc11,Handshake Cell 11 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "hsc10,Handshake Cell 10 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "hsc9,Handshake Cell 9 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "hsc8,Handshake Cell 8 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "hsc7,Handshake Cell 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "hsc6,Handshake Cell 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "hsc5,Handshake Cell 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "hsc4,Handshake Cell 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "hsc3,Handshake Cell 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "hsc2,Handshake Cell 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "hsc1,Handshake Cell 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "hsc0,Handshake Cell 0 IRQ" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "handshake_xpic_irq_raw_clear,Handshake Cell Raw Interrupt for xPIC register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "hsc15,Handshake Cell 15 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "hsc14,Handshake Cell 14 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "hsc13,Handshake Cell 13 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "hsc12,Handshake Cell 12 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "hsc11,Handshake Cell 11 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "hsc10,Handshake Cell 10 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "hsc9,Handshake Cell 9 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "hsc8,Handshake Cell 8 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "hsc7,Handshake Cell 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "hsc6,Handshake Cell 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "hsc5,Handshake Cell 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "hsc4,Handshake Cell 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "hsc3,Handshake Cell 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "hsc2,Handshake Cell 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "hsc1,Handshake Cell 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "hsc0,Handshake Cell 0 IRQ" "0,1"
|
|
newline
|
|
abitfld.long 0x00 0.--7. "vector,Interrupt Vector generated by masked xPIC IRQ flags" "0x00=0: No IRQ,0x10=16: Handshake Cell 0 IRQ,0x11=17: Handshake Cell 1 IRQ,0x12=18: Handshake Cell 2 IRQ,0x13=19: Handshake Cell 3 IRQ,0x14=20: Handshake Cell 4 IRQ,0x15=21: Handshake Cell 5 IRQ,0x16=22: Handshake Cell 6 IRQ,0x17=23: Handshake Cell 7 IRQ,0x18=24: Handshake Cell 8 IRQ,0x19=25: Handshake Cell 9 IRQ,0x1A=26: Handshake Cell 10 IRQ,0x1B=27: Handshake Cell 11 IRQ,0x1C=28: Handshake Cell 12 IRQ,0x1D=29: Handshake Cell 13 IRQ,0x1E=30: Handshake Cell 14 IRQ,0x1F=31: Handshake Cell 15 IRQ"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "handshake_xpic_irq_masked,Handshake Cell Masked Interrupt for xPIC register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "hsc15,Handshake Cell 15 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "hsc14,Handshake Cell 14 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "hsc13,Handshake Cell 13 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "hsc12,Handshake Cell 12 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "hsc11,Handshake Cell 11 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "hsc10,Handshake Cell 10 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "hsc9,Handshake Cell 9 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "hsc8,Handshake Cell 8 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "hsc7,Handshake Cell 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "hsc6,Handshake Cell 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "hsc5,Handshake Cell 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "hsc4,Handshake Cell 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "hsc3,Handshake Cell 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "hsc2,Handshake Cell 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "hsc1,Handshake Cell 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "hsc0,Handshake Cell 0 IRQ" "0,1"
|
|
newline
|
|
abitfld.long 0x00 0.--7. "vector,Interrupt Vector generated by masked xPIC IRQ flags" "0x00=0: No IRQ,0x10=16: Handshake Cell 0 IRQ,0x11=17: Handshake Cell 1 IRQ,0x12=18: Handshake Cell 2 IRQ,0x13=19: Handshake Cell 3 IRQ,0x14=20: Handshake Cell 4 IRQ,0x15=21: Handshake Cell 5 IRQ,0x16=22: Handshake Cell 6 IRQ,0x17=23: Handshake Cell 7 IRQ,0x18=24: Handshake Cell 8 IRQ,0x19=25: Handshake Cell 9 IRQ,0x1A=26: Handshake Cell 10 IRQ,0x1B=27: Handshake Cell 11 IRQ,0x1C=28: Handshake Cell 12 IRQ,0x1D=29: Handshake Cell 13 IRQ,0x1E=30: Handshake Cell 14 IRQ,0x1F=31: Handshake Cell 15 IRQ"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "handshake_xpic_irq_msk_set,Handshake Cell Interrupt Mask Enable for xPIC register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "hsc15,Handshake Cell 15 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "hsc14,Handshake Cell 14 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "hsc13,Handshake Cell 13 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "hsc12,Handshake Cell 12 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "hsc11,Handshake Cell 11 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "hsc10,Handshake Cell 10 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "hsc9,Handshake Cell 9 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "hsc8,Handshake Cell 8 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "hsc7,Handshake Cell 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "hsc6,Handshake Cell 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "hsc5,Handshake Cell 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "hsc4,Handshake Cell 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "hsc3,Handshake Cell 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "hsc2,Handshake Cell 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "hsc1,Handshake Cell 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "hsc0,Handshake Cell 0 IRQ" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "handshake_xpic_irq_msk_reset,Handshake Cell Interrupt Mask Disable for xPIC register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "hsc15,Handshake Cell 15 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "hsc14,Handshake Cell 14 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "hsc13,Handshake Cell 13 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "hsc12,Handshake Cell 12 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "hsc11,Handshake Cell 11 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "hsc10,Handshake Cell 10 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "hsc9,Handshake Cell 9 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "hsc8,Handshake Cell 8 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "hsc7,Handshake Cell 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "hsc6,Handshake Cell 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "hsc5,Handshake Cell 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "hsc4,Handshake Cell 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "hsc3,Handshake Cell 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "hsc2,Handshake Cell 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "hsc1,Handshake Cell 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "hsc0,Handshake Cell 0 IRQ" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "handshake_hsc0_ctrl,Handshake Cell 0 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 0 Width" "0: 8 bit handshake width,1: 16 bit handshake width"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 0 Mode" "0: Handshake Cell 0 is disabled Related memory..,1: Use Handshake Cell 0 for handshaking between..,2: Use Handshake Cell 0 for handshaking between..,3: Use Handshake Cell 0 for handshaking between.."
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "handshake_hsc1_ctrl,Handshake Cell 1 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 1 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 1 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "handshake_hsc2_ctrl,Handshake Cell 2 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 2 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 2 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "handshake_hsc3_ctrl,Handshake Cell 3 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 3 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 3 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "handshake_hsc4_ctrl,Handshake Cell 4 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 4 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 4 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "handshake_hsc5_ctrl,Handshake Cell 5 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 5 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 5 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "handshake_hsc6_ctrl,Handshake Cell 6 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 6 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 6 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "handshake_hsc7_ctrl,Handshake Cell 7 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 7 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 7 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "handshake_hsc8_ctrl,Handshake Cell 8 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 8 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 8 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "handshake_hsc9_ctrl,Handshake Cell 9 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 9 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 9 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "handshake_hsc10_ctrl,Handshake Cell 10 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 10 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 10 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "handshake_hsc11_ctrl,Handshake Cell 11 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 11 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 11 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "handshake_hsc12_ctrl,Handshake Cell 12 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 12 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 12 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "handshake_hsc13_ctrl,Handshake Cell 13 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 13 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 13 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "handshake_hsc14_ctrl,Handshake Cell 14 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 14 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 14 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "handshake_hsc15_ctrl,Handshake Cell 15 Control Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "width,Handshake Cell 15 Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Handshake Cell 15 Mode (view handshake_hsc0_ctrl documentation)" "0,1,2,3"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "handshake_buf_man0_ctrl,Handshake Triple Buffer Manager 0 Control register"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "buf_dam_cfg,Handshake Triple Buffer Manager 0 DPM Address Mapping Configuration" "0: Use mapping value programmed in DPM,1: Use alternative mapping 1 value programmed in,2: Use alternative mapping 2 value programmed in,3: Generate window mapping by current buffer state"
|
|
newline
|
|
bitfld.long 0x00 1. "reset,Handshake Triple Buffer Manager 0 FSM Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "hsc2_auto_PD_OUT,Handshake Cell 2 Handshake Triple Buffer Manager 0 action enable for HCF_PD_OUT_CMD/NCF_PD_OUT_ACK" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "handshake_buf_man0_status_ctrl_netx,Handshake Triple Buffer Manager 0 netX Status and Control Register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "cmd,Handshake Triple Buffer Manager 0 Command for netX buffer" "0: nop/idle,1: request new read buffer,2: request new write buffer,3: release current buffer"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "buf_ro,Handshake Triple Buffer Manager 0 valid netX Buffer" "0: Buffer 0 valid,1: Buffer 1 valid,2: Buffer 2 valid,3: No buffer is valid"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "handshake_buf_man0_status_ctrl_host,Handshake Triple Buffer Manager 0 Host Status register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "cmd,Handshake Triple Buffer Manager 1 Command for host buffer" "0: nop/idle,1: request new read buffer,2: request new write buffer,3: release current buffer"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "buf_ro,Handshake Triple Buffer Manager 0 valid Host Buffer" "0: Buffer 0 valid (mapping value programmed inside,1: Buffer 1 valid (mapping value programmed from,2: Buffer 2 valid (mapping value programmed from,3: No buffer is valid (mapping value programmed"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "handshake_buf_man0_win_map,DPM Window Address Map Alternative Configuration Register for Handshake Triple Buffer Manager 0"
|
|
bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 16.--28. 1. "win_map_buf2,Buffer 2 of Handshake Triple Buffer Manager 0 Alternative DPM Window Address Map"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "win_map_buf1,Buffer 1 of Handshake Triple Buffer Manager 0 Alternative DPM Window Address Map"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "handshake_buf_man1_ctrl,Handshake Triple Buffer Manager 1 Control register"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "buf_dam_cfg,Handshake Triple Buffer Manager 1 DPM Address Mapping Configuration" "0: Use mapping value programmed in DPM,1: Use alternative mapping 1 value programmed in,2: Use alternative mapping 2 value programmed in,3: Generate window mapping by current buffer state"
|
|
newline
|
|
bitfld.long 0x00 1. "reset,Handshake Triple Buffer Manager 1 FSM Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "hsc2_auto_PD_IN,Handshake Cell 2 Handshake Triple Buffer Manager 1 action enable for HCF_PD_IN_CMD/NCF_PD_IN_ACK" "0,1"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "handshake_buf_man1_status_ctrl_netx,Handshake Triple Buffer Manager 1 netX Status and Control Register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "cmd,Handshake Triple Buffer Manager 1 Command for netX buffer" "0: nop/idle,1: request new read buffer,2: request new write buffer,3: release current buffer"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "buf_ro,Handshake Triple Buffer Manager 1 valid netX Buffer" "0: Buffer 0 valid,1: Buffer 1 valid,2: Buffer 2 valid,3: No buffer is valid"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "handshake_buf_man1_status_ctrl_host,Handshake Triple Buffer Manager 1 Host Status register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "cmd,Handshake Triple Buffer Manager 1 Command for host buffer" "0: nop/idle,1: request new read buffer,2: request new write buffer,3: release current buffer"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "buf_ro,Handshake Triple Buffer Manager 1 valid Host Buffer" "0: Buffer 0 valid (mapping value programmed inside,1: Buffer 1 valid (mapping value programmed from,2: Buffer 2 valid (mapping value programmed from,3: No buffer is valid (mapping value programmed"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "handshake_buf_man1_win_map,DPM Window Address Map Alternative Configuration Register for Handshake Triple Buffer Manager 1"
|
|
bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 16.--28. 1. "win_map_buf2,Buffer 2 of Handshake Triple Buffer Manager 1 Alternative DPM Window Address Map"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "win_map_buf1,Buffer 1 of Handshake Triple Buffer Manager 1 Alternative DPM Window Address Map"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "CA9_MULTI_CPU_PING_IRQ"
|
|
repeat 2. (list 0. 1.) (list ad:0xF409B860 ad:0xF409B880)
|
|
tree "CA9_MULTI_CPU_PING_IRQ$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "hs_irq_set_raw,read: hs_iq_reg value write: hs_iq_reg set bit(s)"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_set_bits,IRQs for Inter-CPU-Communication"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "hs_irq_reset_raw,read: hs_iq_reg value write: hs_iq_reg reset bit(s)"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_bits,IRQs for Inter-CPU-Communication"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "hs_irq_set_mask,read: mask value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_set_mask,IRQs for Inter-CPU-Communication"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "hs_irq_reset_mask,read: mask value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_mask,reset IRQs for Inter-CPU-Communication"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "hs_irq_masked,read: hs_iq_reg masked value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_masked,mask IRQs for Inter-CPU-Communication"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SYSTIME_RAP"
|
|
base ad:0xF409C1D0
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "systime_rap_s,Upper SYSTIME register: To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime high Sample systime_ns at read access to systime_s"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "systime_rap_ns,Lower SYSTIME register: To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
|
|
hexmask.long 0x00 0.--31. 1. "val,Systime low: Sample systime_ns at read access to systime_s"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "systime_rap_border,SYSTIME RAP border register / only for internal netX - XC read no influence on RAP systime"
|
|
hexmask.long 0x00 0.--31. 1. "val,Systime border for rap systime"
|
|
tree.end
|
|
tree "ADC_CTRL"
|
|
repeat 2. (list 0. 1.) (list ad:0xF409CA00 ad:0xF409CB00)
|
|
tree "ADC_CTRL$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "adc_ctrl_config,ADC general config register: This register is for static config values of ADC"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "systime_shift,shift of sampletime written to FIFO" "0: systime_ns[15:0],1: systime_ns[16:1],?,?,?,?,?,7: systime_ns[22:7]"
|
|
newline
|
|
bitfld.long 0x00 5. "exact_start,Guarantee exact start of AD conversion for highest prior sequencer" "0: Always finish running AD conversion before,1: AD conversions of lower prior sequencers can be"
|
|
newline
|
|
bitfld.long 0x00 4. "shenb8,Sample/hold enable of analog input AIN8" "0: Use analog inputs directly (sample/hold,1: Use sample/hold"
|
|
newline
|
|
bitfld.long 0x00 3. "shenb7,Sample/hold enable of analog input AIN7" "0: Use analog inputs directly (sample/hold,1: Use sample/hold"
|
|
newline
|
|
bitfld.long 0x00 2. "shenb6,Sample/hold enable of analog input AIN6" "0: Use analog inputs directly (sample/hold,1: Use sample/hold"
|
|
newline
|
|
bitfld.long 0x00 1. "power,Power-down mode of ADC" "0: Power-down,1: Power up"
|
|
newline
|
|
bitfld.long 0x00 0. "reset,Soft reset ADC and state machine: There are no constraints on reset length" "0: Reset is inactive,1: Reset is active"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "adc_ctrl_task0,ADC control register for task0: This register contains all information about one AD task different AD tasks can be combined to a sequence using the nxt_task pointer"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable: Generate an IRQ when this ADC task is finished" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select: 0..7: Number of comparator unit to which ADC value is send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0: Send data to output FIFO,1: Dont send data to output FIFO (to only compare"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp: Add sample timestamp (lower 16 bits of systime_ns) to FIFO (before ADC data)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling: Multiple sequential samples can be averaged" "0: no hardware oversampling,1: 2x hardware oversampling,2: 4x hardware oversampling,3: 8x hardware oversampling,4: 16x hardware oversampling,5: 32x hardware oversampling,6: 64x hardware oversampling,?..."
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0: Do not resample AIN8 hold previously sampled..,1: Sample AIN8 at start of AD control statemachine"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0: Do not resample AIN7 hold previously sampled..,1: Sample AIN7 at start of AD control statemachine"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0: Do not resample AIN6 hold previously sampled..,1: Sample AIN6 at start of AD control statemachine"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0: Sample from analog pin AIN0,1: Sample from analog pin AIN1,2: Sample from analog pin AIN2,3: Sample from analog pin AIN3,4: Sample from analog pin AIN4,5: Sample from analog pin AIN5,6: Sample from analog pin AIN6 (allows..,7: Sample from analog pin AIN7 (allows..,8: Sample from analog pin AIN8 (allows..,?,?,?,?,?,?,15: keep"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay: Delay in steps of 100ns that sampling starts after reaching start_cond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number: 0..14: Pointer to the next task number to be executed in this sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal: The AD task starts 'as fast as possible' after the programmed start event below was reached" "0: wait (do not start until set to other value),1: continuously,2: other ADC at same tasknr and same sequencer,3: other ADC at same tasknr and same sequencer,4: seq_timer,5: irq_raw of comparator0,6: irq_raw of comparator1,7: irq_raw of comparator2,8: irq_raw of comparator3,9: irq_raw of comparator4,10: irq_raw of comparator5,11: irq_raw of comparator6,12: irq_raw of comparator7,13: pwm_cnt0_min,14: pwm_cnt0_max,15: pwm_cnt1_min,16: pwm_cnt1_max,17: posedge pwm_t0,18: negedge pwm_t0,19: posedge pwm_t1,20: negedge pwm_t1,21: posedge pwm_t2,22: negedge pwm_t2,23: posedge pwm_t3,24: negedge pwm_t3,25: posedge pwm_t4,26: negedge pwm_t4,27: posedge pwm_t5,28: negedge pwm_t5,29: posedge pwm_t6,30: negedge pwm_t6,31: posedge pwm_t7,32: negedge pwm_t7,33: posedge enc0_n,34: negedge enc0_n,35: posedge enc1_n,36: negedge enc1_n,37: enc0_edge,38: enc1_edge,39: posedge mp0,40: negedge mp0,41: posedge mp1,42: negedge mp1,43: xpic0_timer0,44: xpic0_timer1,45: xpic0_timer2,46: xpic1_timer0,47: xpic1_timer1,48: xpic1_timer2,49: xpic2_timer0,50: xpic2_timer1,51: xpic2_timer2,52: xpic3_timer0,53: xpic3_timer1,54: xpic3_timer2,55: arm_timer0,56: arm_timer1,57: arm_timer2,?..."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "adc_ctrl_task1,ADC control register for task1: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "adc_ctrl_task2,ADC control register for task2: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "adc_ctrl_task3,ADC control register for task3: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "adc_ctrl_task4,ADC control register for task4: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "adc_ctrl_task5,ADC control register for task5: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "adc_ctrl_task6,ADC control register for task6: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "adc_ctrl_task7,ADC control register for task7: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "adc_ctrl_task8,ADC control register for task8: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "adc_ctrl_task9,ADC control register for task9: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "adc_ctrl_task10,ADC control register for task10: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "adc_ctrl_task11,ADC control register for task11: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "adc_ctrl_task12,ADC control register for task12: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "adc_ctrl_task13,ADC control register for task13: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "adc_ctrl_task14,ADC control register for task14: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "adc_ctrl_seq0_ctrl,Sequencer0 control register: ADC_CTRL allows up to 4 sequences of AD-tasks to be executed in parallel"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
abitfld.long 0x00 8.--15. "timer,Sequence timer preload A sequence timer can be used to delay the start of a specific task" "0x00=0: 1us delay,0x01=1: 2us delay,0xFF=255: 256us delay"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "first_task,First task number of sequence: After setting seq_en this task number will be executed first" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "seq_restart,Restart sequencer: A sequence stops when reaching tasknr=15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq_en,Enable of sequencer" "0: disabled,1: enabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "adc_ctrl_seq1_ctrl,Sequencer1 control register: See seq0_ctrl for details"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "timer,Sequence timer preload"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "first_task,First task number of sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "seq_restart,Restart sequencer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq_en,Enable of sequencer" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "adc_ctrl_seq2_ctrl,Sequencer2 control register: See seq0_ctrl for details"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "timer,Sequence timer preload"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "first_task,First task number of sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "seq_restart,Restart sequencer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq_en,Enable of sequencer" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "adc_ctrl_seq3_ctrl,Sequencer3 control register: See seq0_ctrl for details"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "timer,Sequence timer preload"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "first_task,First task number of sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "seq_restart,Restart sequencer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq_en,Enable of sequencer" "0,1"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "adc_ctrl_seq0_status,Sequence 0 status register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "seq_finished,sequence is finished (reached tasknr=15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "fifo_urun,FIFO underrun occured reset by disabling seq0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "fifo_ovfl,FIFO overflow occured reset by disabling seq0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "fifo_fill,Number of values in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "adc_ctrl_seq1_status,Sequence 1 status register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "seq_finished,sequence is finished (reached tasknr=15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "fifo_urun,FIFO underrun occured reset by disabling seq1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "fifo_ovfl,FIFO overflow occured reset by disabling seq1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "fifo_fill,Number of values in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "adc_ctrl_seq2_status,Sequence 2 status register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "seq_finished,sequence is finished (reached tasknr=15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "fifo_urun,FIFO underrun occured reset by disabling seq2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "fifo_ovfl,FIFO overflow occured reset by disabling seq2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "fifo_fill,Number of values in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "adc_ctrl_seq3_status,Sequence 3 status register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "seq_finished,sequence is finished (reached tasknr=15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "fifo_urun,FIFO underrun occured reset by disabling seq3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "fifo_ovfl,FIFO overflow occured reset by disabling seq3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "fifo_fill,Number of values in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "adc_ctrl_seq0_val,ADC value This register behaves like a FIFO up to 8 output values will be stored"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "tasknr,Number of task that started the appropriate AD-conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "adc_ctrl_seq1_val,ADC value This register behaves like a FIFO up to 8 output values will be stored"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "tasknr,Number of task that started the appropriate AD-conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "adc_ctrl_seq2_val,ADC value This register behaves like a FIFO up to 8 output values will be stored"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "tasknr,Number of task that started the appropriate AD-conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "adc_ctrl_seq3_val,ADC value This register behaves like a FIFO up to 8 output values will be stored"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "tasknr,Number of task that started the appropriate AD-conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "adc_ctrl_compare0_config,Digital comparator 0 config register: Configure comparator in this register restart comparator by writing to irq_raw register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0: always high band (set irq as long as value is..,1: entering high band (set irq when entering high,2: leaving high band (set irq when leaving high..,3: hysteresis always high band (set irq when,4: hysteresis entering high band (set irq when,5: always mid band (set irq as long as value is in,6: once mid band (set irq when entering mid band,7: always low band (set irq as long as value is in,8: entering low band (set irq when entering low..,9: leaving low band (set irq when leaving low..,10: hysteresis always low band (set irq when,11: hysteresis entering low band (set irq when,?..."
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level: ADC-values <= lower_border are in low level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level: ADC-values > upper_border are in high level"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "adc_ctrl_compare1_config,Digital comparator 1 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "adc_ctrl_compare2_config,Digital comparator 2 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "adc_ctrl_compare3_config,Digital comparator 3 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "adc_ctrl_compare4_config,Digital comparator 4 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "adc_ctrl_compare5_config,Digital comparator 5 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "adc_ctrl_compare6_config,Digital comparator 6 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "adc_ctrl_compare7_config,Digital comparator 7 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "adc_ctrl_debug_config,ADC config register for direct control: This register is for debug purposes only! Refer to Renesas ADC documentation for details"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12. "rsb_n,High active reset signal to ADC hardmacro" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "shout8,Sample/hold output control of AIN7" "0: Output of sample/hold is disabled,1: Output of sample/hold is enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "shout7,Sample/hold output control of AIN7" "0: Output of sample/hold is disabled,1: Output of sample/hold is enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "shout6,Sample/hold output control of AIN6" "0: Output of sample/hold is disabled,1: Output of sample/hold is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "shcnt8,Sample/hold control of AIN8" "0: Hold function is available,1: Sampling function is available"
|
|
newline
|
|
bitfld.long 0x00 7. "shcnt7,Sample/hold control of AIN7" "0: Hold function is available,1: Sampling function is available"
|
|
newline
|
|
bitfld.long 0x00 6. "shcnt6,Sample/hold control of AIN6" "0: Hold function is available,1: Sampling function is available"
|
|
newline
|
|
bitfld.long 0x00 5. "conv,AD-conversion start pin: Value will be changed externally with following negedge of ADCCLK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--4. "sel,Select for analog multiplexer of ADC: Value will be changed externally with following negedge of ADCCLK" "0: Sample from analog pin AIN0,1: Sample from analog pin AIN1,2: Sample from analog pin AIN2,3: Sample from analog pin AIN3,4: Sample from analog pin AIN4,5: Sample from analog pin AIN5,6: Sample from analog pin AIN6 (allows..,7: Sample from analog pin AIN7 (allows..,8: Sample from analog pin AIN8 (allows..,?..."
|
|
newline
|
|
bitfld.long 0x00 0. "debug_en,Debug enable" "0: Use task-sequencers to control ADC,1: Use values defined in this register to.."
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "adc_ctrl_debug_status,Debug status register"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "eocb,Inverted End Of Conversion signal of ADC (debug only)" "0,1"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "adc_ctrl_debug_val,ADC value in debug mode"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value changed with negedge of debug_status-eocb"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "adc_ctrl_irq_raw,Raw IRQ: Read access shows status of unmasked IRQs"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "compare7,Comparator 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "compare6,Comparator 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "compare5,Comparator 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "compare4,Comparator 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "compare3,Comparator 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "compare2,Comparator 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "compare1,Comparator 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "compare0,Comparator 0 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "seq3_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "seq3_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "seq3_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "seq3_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "seq2_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "seq2_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "seq2_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "seq2_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "seq1_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "seq1_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "seq1_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "seq1_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "seq0_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "seq0_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "seq0_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq0_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "adc_ctrl_irq_masked,Masked IRQ: Shows status of masked IRQs (as connected to ARM/xPIC)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "compare7,Comparator 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "compare6,Comparator 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "compare5,Comparator 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "compare4,Comparator 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "compare3,Comparator 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "compare2,Comparator 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "compare1,Comparator 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "compare0,Comparator 0 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "seq3_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "seq3_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "seq3_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "seq3_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "seq2_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "seq2_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "seq2_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "seq2_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "seq1_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "seq1_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "seq1_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "seq1_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "seq0_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "seq0_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "seq0_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq0_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "adc_ctrl_irq_mask_set,IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "compare7,Comparator 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "compare6,Comparator 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "compare5,Comparator 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "compare4,Comparator 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "compare3,Comparator 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "compare2,Comparator 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "compare1,Comparator 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "compare0,Comparator 0 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "seq3_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "seq3_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "seq3_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "seq3_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "seq2_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "seq2_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "seq2_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "seq2_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "seq1_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "seq1_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "seq1_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "seq1_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "seq0_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "seq0_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "seq0_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq0_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "adc_ctrl_irq_mask_reset,IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "compare7,Comparator 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "compare6,Comparator 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "compare5,Comparator 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "compare4,Comparator 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "compare3,Comparator 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "compare2,Comparator 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "compare1,Comparator 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "compare0,Comparator 0 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "seq3_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "seq3_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "seq3_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "seq3_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "seq2_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "seq2_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "seq2_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "seq2_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "seq1_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "seq1_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "seq1_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "seq1_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "seq0_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "seq0_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "seq0_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq0_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "adc_ctrl_debug_ctrl0,ADC debug parameters for statemachine: This register is for debug purposes only!"
|
|
bitfld.long 0x00 27.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 23.--26. "tasksm_conv_shcnt1_m2,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19.--22. "tasksm_conv_shcnt1,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "tasksm_shcnt_inactive_m2,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "tasksm_shcnt_inactive,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "tasksm_shcnt_active,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "tasksm_conv,task statemachine timing control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--4. "tasksm_shoutlow2shcnthi,task statemachine timing control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "adc_clk_phase,phase of ADCCLK to change values to ADC" "0: posedge + 20ns,1: posedge + 30ns,2: posedge + 40ns,3: posedge + 10ns"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "adc_ctrl_debug_ctrl1,ADC debug parameters for statemachine: This register is for debug purposes only!"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "quick_seqen_reset,If seq_en=0 directly reset parts of tasksm" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "tasksm_perform_rsb,performing rsb is necessary when restarting with sampling during an unfinished AD conversion" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "tasksm_restart2conv,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "tasksm_shcnt02shout0,task statemachine timing control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "tasksm_shout12conv,task statemachine timing control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "tasksm_shcnt1_shcnt0,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "INTLOGIC_SYSTIME_LT"
|
|
repeat 3. (list 0. 1. 2.) (list ad:0xF409CC00 ad:0xF409CC40 ad:0xF409CC80)
|
|
tree "INTLOGIC_SYSTIME_LT$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "intlogic_lt_systime0_ns,systime0_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime0_ns last latched value"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "intlogic_lt_systime0_s,systime0_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime0_s last latched value"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "intlogic_lt_systime1_ns,systime1_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime1_ns last latched value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "intlogic_lt_systime1_s,systime1_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime1_s last latched value"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "intlogic_lt_systime_uc_ns,systime_uc_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_uc_ns last latched value"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "intlogic_lt_systime_uc_s,systime_uc_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_uc_s last latched value"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "intlogic_lt_systime_rap_ns,systime_rap_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_rap_ns last latched value"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "intlogic_lt_systime_rap_s,systime_rap_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_rap_s last latched value"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "intlogic_lt_systimes_latch,latch systimes by writing 1'b1 to the assigned bit"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "systime_rap_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "systime_rap_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 5. "systime_uc_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_uc_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 3. "systime1_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "systime1_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 1. "systime0_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "systime0_ns,no field descpription" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "ARM_TIMER"
|
|
base ad:0xF40C0380
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "arm_timer_config_timer0,ARM TIMER Config register0"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer0" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "arm_timer_config_timer1,ARM TIMER Config register1"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer1" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "arm_timer_config_timer2,ARM TIMER Config register2"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer2" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x0C)++0x03
|
|
line.long 0x00 "arm_timer_preload_timer$1,ARM TIMER Timer $1"
|
|
hexmask.long 0x00 0.--31. 1. "val,preload value"
|
|
repeat.end
|
|
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "arm_timer_timer$1,ARM TIMER Timer $1"
|
|
hexmask.long 0x00 0.--31. 1. "val,actual value of timer / systime compare value"
|
|
repeat.end
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "arm_timer_systime_s,ARM_TIMER upper SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
|
|
hexmask.long 0x00 0.--31. 1. "val,Systime high: Sample systime_ns at read access to systime_s"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "arm_timer_systime_ns,ARM_TIMER lower SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
|
|
hexmask.long 0x00 0.--31. 1. "val,Systime low: Sample systime_ns at read access to systime_s"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "arm_timer_compare_systime_s_value,SYSTIME sec compare value"
|
|
hexmask.long 0x00 0.--31. 1. "val,Compare value with systime_s (seconds): Systime_s_compare_irq is set if systime_s matches"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "arm_timer_irq_raw,ARM_TIMER Raw IRQ register: Read access shows status of unmasked IRQs"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime sec Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "arm_timer_irq_masked,ARM_TIMER Masked IRQ register: Shows status of masked IRQs (as connected to ARM/xPIC)"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime sec Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "arm_timer_irq_msk_set,ARM_TIMER interrupt mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime sec Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "arm_timer_irq_msk_reset,ARM_TIMER interrupt mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding.."
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime sec Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "arm_timer_systime_config,Select systime for arm_timer_systime_(ns)s functions"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--1. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
tree.end
|
|
tree "XPIC0_DRAM"
|
|
base ad:0xF4100000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_ram_start,xPIC program or data RAM (xPIC TCM) start address: Both xPIC TCMs (program and data) are only accessible by other system masters if xPIC is not running (xpic_debug-xpic_hold_pc-hold=0)"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1FFC++0x03
|
|
line.long 0x00 "xpic_ram_end,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
tree "XPIC1_DRAM"
|
|
base ad:0xF4102000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_ram_start,xPIC program or data RAM (xPIC TCM) start address: Both xPIC TCMs (program and data) are only accessible by other system masters if xPIC is not running (xpic_debug-xpic_hold_pc-hold=0)"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1FFC++0x03
|
|
line.long 0x00 "xpic_ram_end,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
tree "XPIC2_DRAM"
|
|
base ad:0xF4104000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_ram_start,xPIC program or data RAM (xPIC TCM) start address: Both xPIC TCMs (program and data) are only accessible by other system masters if xPIC is not running (xpic_debug-xpic_hold_pc-hold=0)"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1FFC++0x03
|
|
line.long 0x00 "xpic_ram_end,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
tree "XPIC3_DRAM"
|
|
base ad:0xF4106000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_ram_start,xPIC program or data RAM (xPIC TCM) start address: Both xPIC TCMs (program and data) are only accessible by other system masters if xPIC is not running (xpic_debug-xpic_hold_pc-hold=0)"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1FFC++0x03
|
|
line.long 0x00 "xpic_ram_end,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
tree "XPIC0_PRAM"
|
|
base ad:0xF4108000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_ram_start,xPIC program or data RAM (xPIC TCM) start address: Both xPIC TCMs (program and data) are only accessible by other system masters if xPIC is not running (xpic_debug-xpic_hold_pc-hold=0)"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1FFC++0x03
|
|
line.long 0x00 "xpic_ram_end,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
tree "XPIC1_PRAM"
|
|
base ad:0xF410A000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_ram_start,xPIC program or data RAM (xPIC TCM) start address: Both xPIC TCMs (program and data) are only accessible by other system masters if xPIC is not running (xpic_debug-xpic_hold_pc-hold=0)"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1FFC++0x03
|
|
line.long 0x00 "xpic_ram_end,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
tree "XPIC2_PRAM"
|
|
base ad:0xF410C000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_ram_start,xPIC program or data RAM (xPIC TCM) start address: Both xPIC TCMs (program and data) are only accessible by other system masters if xPIC is not running (xpic_debug-xpic_hold_pc-hold=0)"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1FFC++0x03
|
|
line.long 0x00 "xpic_ram_end,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
tree "XPIC3_PRAM"
|
|
base ad:0xF410E000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_ram_start,xPIC program or data RAM (xPIC TCM) start address: Both xPIC TCMs (program and data) are only accessible by other system masters if xPIC is not running (xpic_debug-xpic_hold_pc-hold=0)"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1FFC++0x03
|
|
line.long 0x00 "xpic_ram_end,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
tree "XPIC0_REGS"
|
|
base ad:0xF4110000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_r0,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r0,Work Register 0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "xpic_r1,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r1,Work Register 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_r2,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r2,Work Register 2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_r3,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r3,Work Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_r4,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r4,Work Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_r5,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r5,Work Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_r6,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r6,Work Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_r7,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r7,Work Register 7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "xpic_usr0,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr0,User Register 0"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_usr1,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr1,User Register 1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "xpic_usr2,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr2,User Register 2"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_usr3,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr3,User Register 3"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "xpic_usr4,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr4,User Register 4"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "xpic_pc,xPIC Program Counter Shared in xPIC 64_BIT_MUL_TARGET mode with usr32 (w mode)"
|
|
hexmask.long 0x00 0.--31. 1. "pc,Program Counter (dword address inside DPRAM)"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "xpic_stat,Processor Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "stat,no field descpription"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_zero,Zero Register Shared in xPIC 64_BIT_MUL_TARGET mode with usr10 (w mode)"
|
|
hexmask.long 0x00 0.--31. 1. "zero,Always Zero"
|
|
tree.end
|
|
tree "XPIC0_DEBUG"
|
|
base ad:0xF4110080
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_hold_pc,no Register description"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "reset_xpic,REQUEST reset all internal internal states and the pipeline EXCEPT: the internal register (r0-r7 usr0-4) bank0 and bank1 reset this registers manually EXCEPT: xpic hard_breaker/debug registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "bank_control,control over the register bank selection WARNING: reset this BIT to 0 BEFORE start xPIC (clear hold bits)" "0,1"
|
|
bitfld.long 0x00 5. "bank_select,Select register bank (0: default bank 1: fiq bank) Access registers in xpic_regs area (xpic_r0 .. xpic_r7 xpic_stat)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "misalignment_hold," "0,1"
|
|
bitfld.long 0x00 3. "disable_int,disable interrupts" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "monitor_mode," "0,1"
|
|
bitfld.long 0x00 1. "single_step," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "hold," "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "xpic_break0_addr,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 address value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_break0_addr_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 address mask"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_break0_data,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 data value (for data access only)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_break0_data_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 data mask (for data access only)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_break0_contr,no Register description"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "enable,Breakpoint 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "range,Breakpoint 0 input from Breakpoint 1" "0,1"
|
|
bitfld.long 0x00 6. "chain,Breakpoint 0 input from Breakpoint 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "irq_mode,Breakpoint 0 xPIC in IRQ Mode" "0,1"
|
|
bitfld.long 0x00 4. "fiq_mode,Breakpoint 0 xPIC in FIQ Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "data_access,Breakpoint 0 (1: data access 0: instruction fetch)" "0,1"
|
|
bitfld.long 0x00 1.--2. "mas,Breakpoint 0 memory access size (00: byte. 01: word 10 dword 11 reserved)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "write,Breakpoint 0 write/read access" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_break0_contr_mask,no Register description"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "val,Breakpoint 0 control mask"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_break1_addr,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 address value"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "xpic_break1_addr_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 address mask"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_break1_data,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 data value (for data access only)"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "xpic_break1_data_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 data mask (for data access only)"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_break1_contr,no Register description"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "enable,Breakpoint 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "range,reserved value" "0,1"
|
|
bitfld.long 0x00 6. "chain,reserved value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "irq_mode,Breakpoint 1 xPIC in IRQ Mode" "0,1"
|
|
bitfld.long 0x00 4. "fiq_mode,Breakpoint 1 xPIC in FIQ Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "data_access,Breakpoint 1 (1: data access 0: instruction fetch)" "0,1"
|
|
bitfld.long 0x00 1.--2. "mas,Breakpoint 1 memory access size (00: byte. 01: word 10 dword 11 reserved)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "write,Breakpoint 1 write/read access" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "xpic_break1_contr_mask,no Register description"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "val,Breakpoint 1 control mask"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "xpic_break_last_pc,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,last PC"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "xpic_break_status,Read access shows the reason why xPIC is in HOLD / BREAK"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 9. "xpic_reset_status," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "break1_read_data,Breakpoint 1 last load access (read only)" "0,1"
|
|
bitfld.long 0x00 7. "break0_read_data,Breakpoint 0 last load access (read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "data_misalignment,Data Misaligment is active(read only)" "0,1"
|
|
bitfld.long 0x00 5. "single_step,Single Step Break is active(read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "soft_break,Software Break is active(read only)" "0,1"
|
|
bitfld.long 0x00 3. "break1,Breakpoint 1 is active(read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "break0,Breakpoint 0 is active(read only)" "0,1"
|
|
bitfld.long 0x00 1. "hold,global HOLD BIT status 0- start xPIC 1- hold xPIC (read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "xpic_in_hold,xPIC is in Break or Hold (read only)" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_break_irq_raw,xPIC_DEBUG Raw IRQ register: Read access shows status of unmasked IRQs"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "xpic_break_irq_masked,xPIC_DEBUG Masked IRQ register for other CPU (ARM): Shows status of masked IRQs (as connected to ARM)"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "xpic_break_irq_msk_set,xPIC_DEBUG interrupt mask set for other CPU (ARM): The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "xpic_break_irq_msk_reset,xPIC_DEBUG interrupt mask reset for other CPU (ARM): This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt.."
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "xpic_break_own_irq_masked,xPIC_DEBUG own Masked IRQ register (for xPIC): Shows status of masked IRQs (as connected to xPIC)"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "xpic_break_own_irq_msk_set,xPIC_DEBUG own interrupt mask set (for xPIC): The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "xpic_break_own_irq_msk_reset,xPIC_DEBUG own interrupt mask reset (for XPIC): This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt.."
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "xpic_break_return_fiq_pc,xPIC_DEBUG information FIQ return PC value valid if xPIC is in FIQ"
|
|
hexmask.long 0x00 0.--31. 1. "val,xPIC FIQ return value"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "xpic_break_return_irq_pc,xPIC_DEBUG information last IRQ return PC value valid if xPIC is in IRQ"
|
|
hexmask.long 0x00 0.--31. 1. "val,xPIC last IRQ return value"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "xpic_irq_status,Read access shows the xpic irq status and the xpic irq enable bits"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "fiq_enable,FIQ enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "irq_enable,IRQ enable bit" "0,1"
|
|
bitfld.long 0x00 1. "fiq_status,FIQ status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "irq_status,IRQ status" "0,1"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x64)++0x03
|
|
line.long 0x00 "xpic_com$1,xPIC_DEBUG com register for debug communication"
|
|
hexmask.long 0x00 0.--31. 1. "val,register for debug communication"
|
|
repeat.end
|
|
tree.end
|
|
tree "XPIC1_REGS"
|
|
base ad:0xF4110100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_r0,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r0,Work Register 0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "xpic_r1,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r1,Work Register 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_r2,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r2,Work Register 2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_r3,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r3,Work Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_r4,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r4,Work Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_r5,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r5,Work Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_r6,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r6,Work Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_r7,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r7,Work Register 7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "xpic_usr0,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr0,User Register 0"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_usr1,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr1,User Register 1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "xpic_usr2,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr2,User Register 2"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_usr3,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr3,User Register 3"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "xpic_usr4,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr4,User Register 4"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "xpic_pc,xPIC Program Counter Shared in xPIC 64_BIT_MUL_TARGET mode with usr32 (w mode)"
|
|
hexmask.long 0x00 0.--31. 1. "pc,Program Counter (dword address inside DPRAM)"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "xpic_stat,Processor Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "stat,no field descpription"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_zero,Zero Register Shared in xPIC 64_BIT_MUL_TARGET mode with usr10 (w mode)"
|
|
hexmask.long 0x00 0.--31. 1. "zero,Always Zero"
|
|
tree.end
|
|
tree "XPIC1_DEBUG"
|
|
base ad:0xF4110180
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_hold_pc,no Register description"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "reset_xpic,REQUEST reset all internal internal states and the pipeline EXCEPT: the internal register (r0-r7 usr0-4) bank0 and bank1 reset this registers manually EXCEPT: xpic hard_breaker/debug registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "bank_control,control over the register bank selection WARNING: reset this BIT to 0 BEFORE start xPIC (clear hold bits)" "0,1"
|
|
bitfld.long 0x00 5. "bank_select,Select register bank (0: default bank 1: fiq bank) Access registers in xpic_regs area (xpic_r0 .. xpic_r7 xpic_stat)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "misalignment_hold," "0,1"
|
|
bitfld.long 0x00 3. "disable_int,disable interrupts" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "monitor_mode," "0,1"
|
|
bitfld.long 0x00 1. "single_step," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "hold," "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "xpic_break0_addr,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 address value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_break0_addr_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 address mask"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_break0_data,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 data value (for data access only)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_break0_data_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 data mask (for data access only)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_break0_contr,no Register description"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "enable,Breakpoint 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "range,Breakpoint 0 input from Breakpoint 1" "0,1"
|
|
bitfld.long 0x00 6. "chain,Breakpoint 0 input from Breakpoint 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "irq_mode,Breakpoint 0 xPIC in IRQ Mode" "0,1"
|
|
bitfld.long 0x00 4. "fiq_mode,Breakpoint 0 xPIC in FIQ Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "data_access,Breakpoint 0 (1: data access 0: instruction fetch)" "0,1"
|
|
bitfld.long 0x00 1.--2. "mas,Breakpoint 0 memory access size (00: byte. 01: word 10 dword 11 reserved)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "write,Breakpoint 0 write/read access" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_break0_contr_mask,no Register description"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "val,Breakpoint 0 control mask"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_break1_addr,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 address value"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "xpic_break1_addr_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 address mask"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_break1_data,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 data value (for data access only)"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "xpic_break1_data_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 data mask (for data access only)"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_break1_contr,no Register description"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "enable,Breakpoint 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "range,reserved value" "0,1"
|
|
bitfld.long 0x00 6. "chain,reserved value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "irq_mode,Breakpoint 1 xPIC in IRQ Mode" "0,1"
|
|
bitfld.long 0x00 4. "fiq_mode,Breakpoint 1 xPIC in FIQ Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "data_access,Breakpoint 1 (1: data access 0: instruction fetch)" "0,1"
|
|
bitfld.long 0x00 1.--2. "mas,Breakpoint 1 memory access size (00: byte. 01: word 10 dword 11 reserved)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "write,Breakpoint 1 write/read access" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "xpic_break1_contr_mask,no Register description"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "val,Breakpoint 1 control mask"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "xpic_break_last_pc,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,last PC"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "xpic_break_status,Read access shows the reason why xPIC is in HOLD / BREAK"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 9. "xpic_reset_status," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "break1_read_data,Breakpoint 1 last load access (read only)" "0,1"
|
|
bitfld.long 0x00 7. "break0_read_data,Breakpoint 0 last load access (read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "data_misalignment,Data Misaligment is active(read only)" "0,1"
|
|
bitfld.long 0x00 5. "single_step,Single Step Break is active(read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "soft_break,Software Break is active(read only)" "0,1"
|
|
bitfld.long 0x00 3. "break1,Breakpoint 1 is active(read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "break0,Breakpoint 0 is active(read only)" "0,1"
|
|
bitfld.long 0x00 1. "hold,global HOLD BIT status 0- start xPIC 1- hold xPIC (read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "xpic_in_hold,xPIC is in Break or Hold (read only)" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_break_irq_raw,xPIC_DEBUG Raw IRQ register: Read access shows status of unmasked IRQs"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "xpic_break_irq_masked,xPIC_DEBUG Masked IRQ register for other CPU (ARM): Shows status of masked IRQs (as connected to ARM)"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "xpic_break_irq_msk_set,xPIC_DEBUG interrupt mask set for other CPU (ARM): The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "xpic_break_irq_msk_reset,xPIC_DEBUG interrupt mask reset for other CPU (ARM): This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt.."
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "xpic_break_own_irq_masked,xPIC_DEBUG own Masked IRQ register (for xPIC): Shows status of masked IRQs (as connected to xPIC)"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "xpic_break_own_irq_msk_set,xPIC_DEBUG own interrupt mask set (for xPIC): The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "xpic_break_own_irq_msk_reset,xPIC_DEBUG own interrupt mask reset (for XPIC): This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt.."
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "xpic_break_return_fiq_pc,xPIC_DEBUG information FIQ return PC value valid if xPIC is in FIQ"
|
|
hexmask.long 0x00 0.--31. 1. "val,xPIC FIQ return value"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "xpic_break_return_irq_pc,xPIC_DEBUG information last IRQ return PC value valid if xPIC is in IRQ"
|
|
hexmask.long 0x00 0.--31. 1. "val,xPIC last IRQ return value"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "xpic_irq_status,Read access shows the xpic irq status and the xpic irq enable bits"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "fiq_enable,FIQ enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "irq_enable,IRQ enable bit" "0,1"
|
|
bitfld.long 0x00 1. "fiq_status,FIQ status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "irq_status,IRQ status" "0,1"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x64)++0x03
|
|
line.long 0x00 "xpic_com$1,xPIC_DEBUG com register for debug communication"
|
|
hexmask.long 0x00 0.--31. 1. "val,register for debug communication"
|
|
repeat.end
|
|
tree.end
|
|
tree "XPIC2_REGS"
|
|
base ad:0xF4110200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_r0,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r0,Work Register 0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "xpic_r1,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r1,Work Register 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_r2,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r2,Work Register 2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_r3,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r3,Work Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_r4,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r4,Work Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_r5,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r5,Work Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_r6,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r6,Work Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_r7,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r7,Work Register 7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "xpic_usr0,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr0,User Register 0"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_usr1,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr1,User Register 1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "xpic_usr2,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr2,User Register 2"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_usr3,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr3,User Register 3"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "xpic_usr4,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr4,User Register 4"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "xpic_pc,xPIC Program Counter Shared in xPIC 64_BIT_MUL_TARGET mode with usr32 (w mode)"
|
|
hexmask.long 0x00 0.--31. 1. "pc,Program Counter (dword address inside DPRAM)"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "xpic_stat,Processor Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "stat,no field descpription"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_zero,Zero Register Shared in xPIC 64_BIT_MUL_TARGET mode with usr10 (w mode)"
|
|
hexmask.long 0x00 0.--31. 1. "zero,Always Zero"
|
|
tree.end
|
|
tree "XPIC2_DEBUG"
|
|
base ad:0xF4110280
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_hold_pc,no Register description"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "reset_xpic,REQUEST reset all internal internal states and the pipeline EXCEPT: the internal register (r0-r7 usr0-4) bank0 and bank1 reset this registers manually EXCEPT: xpic hard_breaker/debug registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "bank_control,control over the register bank selection WARNING: reset this BIT to 0 BEFORE start xPIC (clear hold bits)" "0,1"
|
|
bitfld.long 0x00 5. "bank_select,Select register bank (0: default bank 1: fiq bank) Access registers in xpic_regs area (xpic_r0 .. xpic_r7 xpic_stat)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "misalignment_hold," "0,1"
|
|
bitfld.long 0x00 3. "disable_int,disable interrupts" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "monitor_mode," "0,1"
|
|
bitfld.long 0x00 1. "single_step," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "hold," "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "xpic_break0_addr,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 address value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_break0_addr_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 address mask"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_break0_data,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 data value (for data access only)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_break0_data_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 data mask (for data access only)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_break0_contr,no Register description"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "enable,Breakpoint 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "range,Breakpoint 0 input from Breakpoint 1" "0,1"
|
|
bitfld.long 0x00 6. "chain,Breakpoint 0 input from Breakpoint 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "irq_mode,Breakpoint 0 xPIC in IRQ Mode" "0,1"
|
|
bitfld.long 0x00 4. "fiq_mode,Breakpoint 0 xPIC in FIQ Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "data_access,Breakpoint 0 (1: data access 0: instruction fetch)" "0,1"
|
|
bitfld.long 0x00 1.--2. "mas,Breakpoint 0 memory access size (00: byte. 01: word 10 dword 11 reserved)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "write,Breakpoint 0 write/read access" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_break0_contr_mask,no Register description"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "val,Breakpoint 0 control mask"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_break1_addr,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 address value"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "xpic_break1_addr_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 address mask"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_break1_data,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 data value (for data access only)"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "xpic_break1_data_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 data mask (for data access only)"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_break1_contr,no Register description"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "enable,Breakpoint 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "range,reserved value" "0,1"
|
|
bitfld.long 0x00 6. "chain,reserved value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "irq_mode,Breakpoint 1 xPIC in IRQ Mode" "0,1"
|
|
bitfld.long 0x00 4. "fiq_mode,Breakpoint 1 xPIC in FIQ Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "data_access,Breakpoint 1 (1: data access 0: instruction fetch)" "0,1"
|
|
bitfld.long 0x00 1.--2. "mas,Breakpoint 1 memory access size (00: byte. 01: word 10 dword 11 reserved)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "write,Breakpoint 1 write/read access" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "xpic_break1_contr_mask,no Register description"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "val,Breakpoint 1 control mask"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "xpic_break_last_pc,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,last PC"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "xpic_break_status,Read access shows the reason why xPIC is in HOLD / BREAK"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 9. "xpic_reset_status," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "break1_read_data,Breakpoint 1 last load access (read only)" "0,1"
|
|
bitfld.long 0x00 7. "break0_read_data,Breakpoint 0 last load access (read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "data_misalignment,Data Misaligment is active(read only)" "0,1"
|
|
bitfld.long 0x00 5. "single_step,Single Step Break is active(read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "soft_break,Software Break is active(read only)" "0,1"
|
|
bitfld.long 0x00 3. "break1,Breakpoint 1 is active(read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "break0,Breakpoint 0 is active(read only)" "0,1"
|
|
bitfld.long 0x00 1. "hold,global HOLD BIT status 0- start xPIC 1- hold xPIC (read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "xpic_in_hold,xPIC is in Break or Hold (read only)" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_break_irq_raw,xPIC_DEBUG Raw IRQ register: Read access shows status of unmasked IRQs"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "xpic_break_irq_masked,xPIC_DEBUG Masked IRQ register for other CPU (ARM): Shows status of masked IRQs (as connected to ARM)"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "xpic_break_irq_msk_set,xPIC_DEBUG interrupt mask set for other CPU (ARM): The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "xpic_break_irq_msk_reset,xPIC_DEBUG interrupt mask reset for other CPU (ARM): This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt.."
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "xpic_break_own_irq_masked,xPIC_DEBUG own Masked IRQ register (for xPIC): Shows status of masked IRQs (as connected to xPIC)"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "xpic_break_own_irq_msk_set,xPIC_DEBUG own interrupt mask set (for xPIC): The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "xpic_break_own_irq_msk_reset,xPIC_DEBUG own interrupt mask reset (for XPIC): This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt.."
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "xpic_break_return_fiq_pc,xPIC_DEBUG information FIQ return PC value valid if xPIC is in FIQ"
|
|
hexmask.long 0x00 0.--31. 1. "val,xPIC FIQ return value"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "xpic_break_return_irq_pc,xPIC_DEBUG information last IRQ return PC value valid if xPIC is in IRQ"
|
|
hexmask.long 0x00 0.--31. 1. "val,xPIC last IRQ return value"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "xpic_irq_status,Read access shows the xpic irq status and the xpic irq enable bits"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "fiq_enable,FIQ enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "irq_enable,IRQ enable bit" "0,1"
|
|
bitfld.long 0x00 1. "fiq_status,FIQ status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "irq_status,IRQ status" "0,1"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x64)++0x03
|
|
line.long 0x00 "xpic_com$1,xPIC_DEBUG com register for debug communication"
|
|
hexmask.long 0x00 0.--31. 1. "val,register for debug communication"
|
|
repeat.end
|
|
tree.end
|
|
tree "XPIC3_REGS"
|
|
base ad:0xF4110300
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_r0,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r0,Work Register 0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "xpic_r1,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r1,Work Register 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_r2,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r2,Work Register 2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_r3,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r3,Work Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_r4,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r4,Work Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_r5,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r5,Work Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_r6,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r6,Work Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_r7,xPIC work register for indirect addressing"
|
|
hexmask.long 0x00 0.--31. 1. "r7,Work Register 7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "xpic_usr0,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr0,User Register 0"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_usr1,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr1,User Register 1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "xpic_usr2,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr2,User Register 2"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_usr3,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr3,User Register 3"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "xpic_usr4,xPIC user Register additional work register"
|
|
hexmask.long 0x00 0.--31. 1. "usr4,User Register 4"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "xpic_pc,xPIC Program Counter Shared in xPIC 64_BIT_MUL_TARGET mode with usr32 (w mode)"
|
|
hexmask.long 0x00 0.--31. 1. "pc,Program Counter (dword address inside DPRAM)"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "xpic_stat,Processor Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "stat,no field descpription"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_zero,Zero Register Shared in xPIC 64_BIT_MUL_TARGET mode with usr10 (w mode)"
|
|
hexmask.long 0x00 0.--31. 1. "zero,Always Zero"
|
|
tree.end
|
|
tree "XPIC3_DEBUG"
|
|
base ad:0xF4110380
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_hold_pc,no Register description"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "reset_xpic,REQUEST reset all internal internal states and the pipeline EXCEPT: the internal register (r0-r7 usr0-4) bank0 and bank1 reset this registers manually EXCEPT: xpic hard_breaker/debug registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "bank_control,control over the register bank selection WARNING: reset this BIT to 0 BEFORE start xPIC (clear hold bits)" "0,1"
|
|
bitfld.long 0x00 5. "bank_select,Select register bank (0: default bank 1: fiq bank) Access registers in xpic_regs area (xpic_r0 .. xpic_r7 xpic_stat)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "misalignment_hold," "0,1"
|
|
bitfld.long 0x00 3. "disable_int,disable interrupts" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "monitor_mode," "0,1"
|
|
bitfld.long 0x00 1. "single_step," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "hold," "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "xpic_break0_addr,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 address value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_break0_addr_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 address mask"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_break0_data,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 data value (for data access only)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_break0_data_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 data mask (for data access only)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_break0_contr,no Register description"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "enable,Breakpoint 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "range,Breakpoint 0 input from Breakpoint 1" "0,1"
|
|
bitfld.long 0x00 6. "chain,Breakpoint 0 input from Breakpoint 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "irq_mode,Breakpoint 0 xPIC in IRQ Mode" "0,1"
|
|
bitfld.long 0x00 4. "fiq_mode,Breakpoint 0 xPIC in FIQ Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "data_access,Breakpoint 0 (1: data access 0: instruction fetch)" "0,1"
|
|
bitfld.long 0x00 1.--2. "mas,Breakpoint 0 memory access size (00: byte. 01: word 10 dword 11 reserved)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "write,Breakpoint 0 write/read access" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_break0_contr_mask,no Register description"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "val,Breakpoint 0 control mask"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_break1_addr,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 address value"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "xpic_break1_addr_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 address mask"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_break1_data,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 data value (for data access only)"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "xpic_break1_data_mask,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 data mask (for data access only)"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_break1_contr,no Register description"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "enable,Breakpoint 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "range,reserved value" "0,1"
|
|
bitfld.long 0x00 6. "chain,reserved value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "irq_mode,Breakpoint 1 xPIC in IRQ Mode" "0,1"
|
|
bitfld.long 0x00 4. "fiq_mode,Breakpoint 1 xPIC in FIQ Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "data_access,Breakpoint 1 (1: data access 0: instruction fetch)" "0,1"
|
|
bitfld.long 0x00 1.--2. "mas,Breakpoint 1 memory access size (00: byte. 01: word 10 dword 11 reserved)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "write,Breakpoint 1 write/read access" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "xpic_break1_contr_mask,no Register description"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "val,Breakpoint 1 control mask"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "xpic_break_last_pc,no Register description"
|
|
hexmask.long 0x00 0.--31. 1. "val,last PC"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "xpic_break_status,Read access shows the reason why xPIC is in HOLD / BREAK"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 9. "xpic_reset_status," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "break1_read_data,Breakpoint 1 last load access (read only)" "0,1"
|
|
bitfld.long 0x00 7. "break0_read_data,Breakpoint 0 last load access (read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "data_misalignment,Data Misaligment is active(read only)" "0,1"
|
|
bitfld.long 0x00 5. "single_step,Single Step Break is active(read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "soft_break,Software Break is active(read only)" "0,1"
|
|
bitfld.long 0x00 3. "break1,Breakpoint 1 is active(read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "break0,Breakpoint 0 is active(read only)" "0,1"
|
|
bitfld.long 0x00 1. "hold,global HOLD BIT status 0- start xPIC 1- hold xPIC (read only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "xpic_in_hold,xPIC is in Break or Hold (read only)" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_break_irq_raw,xPIC_DEBUG Raw IRQ register: Read access shows status of unmasked IRQs"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "xpic_break_irq_masked,xPIC_DEBUG Masked IRQ register for other CPU (ARM): Shows status of masked IRQs (as connected to ARM)"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "xpic_break_irq_msk_set,xPIC_DEBUG interrupt mask set for other CPU (ARM): The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "xpic_break_irq_msk_reset,xPIC_DEBUG interrupt mask reset for other CPU (ARM): This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt.."
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
|
|
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "xpic_break_own_irq_masked,xPIC_DEBUG own Masked IRQ register (for xPIC): Shows status of masked IRQs (as connected to xPIC)"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "xpic_break_own_irq_msk_set,xPIC_DEBUG own interrupt mask set (for xPIC): The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "xpic_break_own_irq_msk_reset,xPIC_DEBUG own interrupt mask reset (for XPIC): This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt.."
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "xpic_break_return_fiq_pc,xPIC_DEBUG information FIQ return PC value valid if xPIC is in FIQ"
|
|
hexmask.long 0x00 0.--31. 1. "val,xPIC FIQ return value"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "xpic_break_return_irq_pc,xPIC_DEBUG information last IRQ return PC value valid if xPIC is in IRQ"
|
|
hexmask.long 0x00 0.--31. 1. "val,xPIC last IRQ return value"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "xpic_irq_status,Read access shows the xpic irq status and the xpic irq enable bits"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "fiq_enable,FIQ enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "irq_enable,IRQ enable bit" "0,1"
|
|
bitfld.long 0x00 1. "fiq_status,FIQ status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "irq_status,IRQ status" "0,1"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x64)++0x03
|
|
line.long 0x00 "xpic_com$1,xPIC_DEBUG com register for debug communication"
|
|
hexmask.long 0x00 0.--31. 1. "val,register for debug communication"
|
|
repeat.end
|
|
tree.end
|
|
tree "XPIC_VIC0"
|
|
base ad:0xF4200000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_vic_config,XPIC VIC Configuration register"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "table,use far or near Table" "0: Base Pointer Addr for IRQ Jmp Table + (n*4),1: Base Pointer Addr for IRQ Jmp Table + (n*16) 4"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,global enable of xPIC VIC (0: disable/ 1: enable)" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "xpic_vic_raw_intr0,XPIC VIC Raw0 interrupt status register see netx4000_irq doc"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "xpic_vic_raw_intr1,XPIC VIC Raw1 interrupt status register see netx4000_irq doc"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "xpic_vic_raw_intr2,XPIC VIC Raw2 interrupt status register see netx4000_irq doc"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_vic_softint0_set,XPIC VIC Software0 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_vic_softint1_set,XPIC VIC Software1 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_vic_softint2_set,XPIC VIC Software2 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_vic_softint0_reset,XPIC VIC Software0 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "xpic_vic_softint1_reset,XPIC VIC Software1 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_vic_softint2_reset,XPIC VIC Software2 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "xpic_vic_fiq_addr,XPIC VIC FIQ Vector address 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "val,FIQ handler address"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_vic_irq_addr,XPIC VIC normal IRQ address register"
|
|
hexmask.long 0x00 0.--31. 1. "val,IRQ handler address"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "xpic_vic_vector_addr,XPIC VIC IRQ Vector address"
|
|
hexmask.long 0x00 0.--31. 1. "val,IRQ vector address read access get actuel highest prior IRQ read access get adr_xpic_vic_table_base_addr + IRQ Number * (4/16)"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "xpic_vic_table_base_addr,XPIC VIC IRQ TABLE ADDRESS BASE POINTER"
|
|
hexmask.long 0x00 0.--31. 1. "val,IRQ Table base address the Base Pointer Addr for IRQ Jmp Table"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "xpic_vic_fiq_vect_config,no Register description"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
bitfld.long 0x00 30. "select_fiq_default," "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 7.--29. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_vic_vect_config0,highest priority"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
hexmask.long.tbyte 0x00 7.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
|
|
repeat 14. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "xpic_vic_vect_config$1,no Register description"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
hexmask.long.tbyte 0x00 7.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
|
|
repeat.end
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "xpic_vic_vect_config15,XPIC default interrupt vector all interrupt sources (wired-OR) select with default interrupt vector register lowest priority"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
hexmask.long 0x00 0.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "xpic_vic_default0,XPIC default interrupt vector select0"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int0 - int31 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "xpic_vic_default1,XPIC default interrupt vector select1"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int32 - int63 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "xpic_vic_default2,XPIC default interrupt vector select1"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int64 - int95 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "xpic_vic_fiq_default0,XPIC default interrupt vector select0 for fiq"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int0 - int31 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "xpic_vic_fiq_default1,XPIC default interrupt vector select1 for fiq"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int32 - int63 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "xpic_vic_fiq_default2,XPIC default interrupt vector select1 for fiq"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int64 - int95 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "xpic_vic_rap_irq_edges,resets the Renesas edge IRQs"
|
|
bitfld.long 0x00 27.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long 0x00 0.--26. 1. "val,write '1' to reset the bit"
|
|
tree.end
|
|
tree "XPIC_TIMER0"
|
|
base ad:0xF4200100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_timer_config_timer0,xPIC TIMER Config register0"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer0" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "xpic_timer_config_timer1,xPIC TIMER Config register1"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer1" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_timer_config_timer2,xPIC TIMER Config register2"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer2" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_timer_preload_timer0,xPIC TIMER Timer 0 preload"
|
|
hexmask.long 0x00 0.--31. 1. "val,preload value"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_timer_preload_timer1,xPIC TIMER Timer 1 preload"
|
|
hexmask.long 0x00 0.--31. 1. "val,preload value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_timer_preload_timer2,xPIC TIMER Timer 2 preload"
|
|
hexmask.long 0x00 0.--31. 1. "val,preload value"
|
|
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "xpic_timer_timer$1,xPIC TIMER Timer $1"
|
|
hexmask.long 0x00 0.--31. 1. "val,actual value of timer / systime compare value"
|
|
repeat.end
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_timer_irq_raw,xPIC_TIMER Raw IRQ register: Read access shows status of unmasked IRQs"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "xpic_timer_irq_masked,xPIC_TIMER Masked IRQ register: Shows status of masked IRQs (as connected to xPIC)"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_timer_irq_msk_set,xPIC_TIMER interrupt mask enable: The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "xpic_timer_irq_msk_reset,xPIC_TIMER interrupt mask disable: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for.."
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "xpic_timer_systime_s,xPIC_TIMER upper SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
|
|
hexmask.long 0x00 0.--31. 1. "val,Systime high: Sample systime_ns at read access to systime_s"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "xpic_timer_systime_ns,xPIC_TIMER lower SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
|
|
hexmask.long 0x00 0.--31. 1. "val,Systime low: Sample systime_ns at read access to systime_s"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_timer_compare_systime_s_value,xPIC_TIMER SYSTIME sec compare register"
|
|
hexmask.long 0x00 0.--31. 1. "val,Compare value with systime_s (seconds): Systime_s_compare_irq is set if systime_s matches"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "xpic_timer_systime_config,Select systime for xpic_timer_systime_ns(s) functions"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--1. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
tree.end
|
|
tree "XPIC_WDG0"
|
|
base ad:0xF4200180
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_wdg_trig,netX xPIC Watchdog Trigger Register"
|
|
bitfld.long 0x00 31. "write_enable,Write enable bit for timeout register: As long as this bit is not set all write accesses to the timeout register are ignored" "0,1"
|
|
bitfld.long 0x00 29.--30. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "wdg_counter_trigger_w,Watchdog trigger bit: Bit must be set to trigger the watchdog counter" "0,1"
|
|
bitfld.long 0x00 25.--27. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24. "irq_req_watchdog,xPIC IRQ request of watchdog writing 1 deletes IRQ to xPIC" "0,1"
|
|
bitfld.long 0x00 20.--23. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "wdg_access_code,Watchdog access code for triggering"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "xpic_wdg_counter,netX xPIC Watchdog Counter Register The counter value is decremented each 10000 system clock cycles"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
abitfld.long 0x00 0.--16. "val,Actual watchdog counter value: Bit 16 shows" "0x00000=0: Watchdog is counting down from..,0x00001=1: Watchdog is counting down from.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_wdg_xpic_irq_timeout,netX xPIC Watchdog xPIC interrupt timout register: xpic_irq_timeout or arm_irq_timeout must be nonzero to enable watchdog"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "val,Watchdog interrupt timeout The total xpic_irq timeout for a netX clock of 100MHz is: xpic_wdg_xpic_irq_timeout * 100us"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_wdg_arm_irq_timeout,netX xPIC Watchdog ARM interrupt timout register: xpic_irq_timeout or arm_irq_timeout must be nonzero to enable watchdog"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "val,Watchdog ARM interrupt timeout The total arm_irq timeout for a netX clock of 100MHz is: (xpic_wdg_xpic_irq_timeout + xpic_wdg_arm_irq_timeout) * 100us"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_wdg_irq_raw,Read access shows status of unmasked IRQs"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "xpic_wdg_irq_masked,xpic_wdg Masked IRQ register: Shows status of masked IRQs (as connected to xPIC)"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_wdg_irq_msk_set,xpic_wdg interrupt mask enable: The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_wdg_irq_msk_reset,xpic_wdg interrupt mask disable: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding.."
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
tree.end
|
|
tree "XPIC_MULTI_CPU_PING_IRQ0"
|
|
base ad:0xF42001A0
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "hs_irq_set_raw,read: hs_iq_reg value write: hs_iq_reg set bit(s)"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_set_bits,IRQs for Inter-CPU-Communication"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "hs_irq_reset_raw,read: hs_iq_reg value write: hs_iq_reg reset bit(s)"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_bits,IRQs for Inter-CPU-Communication"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "hs_irq_set_mask,read: mask value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_set_mask,IRQs for Inter-CPU-Communication"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "hs_irq_reset_mask,read: mask value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_mask,reset IRQs for Inter-CPU-Communication"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "hs_irq_masked,read: hs_iq_reg masked value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_masked,mask IRQs for Inter-CPU-Communication"
|
|
tree.end
|
|
tree "XPIC_SYSTIME_LT0"
|
|
base ad:0xF42001C0
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "xpic_lt_systime0_ns,systime0_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime0_ns last latched value"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "xpic_lt_systime0_s,systime0_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime0_s last latched value"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "xpic_lt_systime1_ns,systime1_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime1_ns last latched value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "xpic_lt_systime1_s,systime1_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime1_s last latched value"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "xpic_lt_systime_uc_ns,systime_uc_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_uc_ns last latched value"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "xpic_lt_systime_uc_s,systime_uc_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_uc_s last latched value"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "xpic_lt_systime_rap_ns,systime_rap_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_rap_ns last latched value"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "xpic_lt_systime_rap_s,systime_rap_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_rap_s last latched value"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "xpic_lt_systimes_latch,latch systimes by writing 1'b1 to the assigned bit"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "systime_rap_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "systime_rap_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 5. "systime_uc_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_uc_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 3. "systime1_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "systime1_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 1. "systime0_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "systime0_ns,no field descpription" "0,1"
|
|
tree.end
|
|
tree "SIGMA_DELTA_TRIGGER"
|
|
base ad:0xF4200840
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "sigma_delta_trigger_crest0,SIGMA_DELTA_TRIGGER Crest 0 control register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "select,Select start signal for SIGMA DELTA ADC: The AD task starts 'as fast as possible' after the programmed start event below was reached" "0: wait (do not start until set to,1: continuously,2: pwm_cnt0_min,3: pwm_cnt0_max,4: pwm_cnt1_min,5: pwm_cnt1_max,6: posedge pwm_t0,7: negedge pwm_t0,8: posedge pwm_t1,9: negedge pwm_t1,10: posedge pwm_t2,11: negedge pwm_t2,12: posedge pwm_t3,13: negedge pwm_t3,14: posedge pwm_t4,15: negedge pwm_t4,16: posedge pwm_t5,17: negedge pwm_t5,18: posedge pwm_t6,19: negedge pwm_t6,20: posedge pwm_t7,21: negedge pwm_t7,22: posedge enc0_n,23: negedge enc0_n,24: posedge enc1_n,25: negedge enc1_n,26: enc0_edge,27: enc1_edge,28: posedge mp0,29: negedge mp0,30: posedge mp1,31: negedge mp1,32: xpic0_timer0,33: xpic0_timer1,34: xpic0_timer2,35: xpic1_timer0,36: xpic1_timer1,37: xpic1_timer2,38: xpic2_timer0,39: xpic2_timer1,40: xpic2_timer2,41: xpic3_timer0,42: xpic3_timer1,43: xpic3_timer2,44: arm_timer0,45: arm_timer2,?..."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "sigma_delta_trigger_crest1,SIGMA_DELTA_TRIGGER Crest 1 control register s"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "select,Select start signal for SIGMA DELTA ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "sigma_delta_trigger_crest2,SIGMA_DELTA_TRIGGER Crest 2 control register s"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "select,Select start signal for SIGMA DELTA ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "sigma_delta_trigger_crest3,SIGMA_DELTA_TRIGGER Crest 3 control register s"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "select,Select start signal for SIGMA DELTA ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "sigma_delta_trigger_crest4,SIGMA_DELTA_TRIGGER Crest 4 control register s"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "select,Select start signal for SIGMA DELTA ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "sigma_delta_trigger_crest5,SIGMA_DELTA_TRIGGER Crest 5 control register s"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "select,Select start signal for SIGMA DELTA ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "sigma_delta_trigger_valley0,SIGMA_DELTA_TRIGGER Valley 0 control register s"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "select,Select start signal for SIGMA DELTA ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "sigma_delta_trigger_valley1,SIGMA_DELTA_TRIGGER Valley 1 control register s"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "select,Select start signal for SIGMA DELTA ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "sigma_delta_trigger_valley2,SIGMA_DELTA_TRIGGER Valley 2 control register s"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "select,Select start signal for SIGMA DELTA ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "sigma_delta_trigger_valley3,SIGMA_DELTA_TRIGGER Valley 3 control register s"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "select,Select start signal for SIGMA DELTA ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "sigma_delta_trigger_valley4,SIGMA_DELTA_TRIGGER Valley 4 control register s"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "select,Select start signal for SIGMA DELTA ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "sigma_delta_trigger_valley5,SIGMA_DELTA_TRIGGER Valley 5 control register s"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "select,Select start signal for SIGMA DELTA ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree "ADC_CTRL0_MOTION"
|
|
base ad:0xF4200A00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "adc_ctrl_config,ADC general config register: This register is for static config values of ADC"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "systime_shift,shift of sampletime written to FIFO" "0: systime_ns[15:0],1: systime_ns[16:1],?,?,?,?,?,7: systime_ns[22:7]"
|
|
newline
|
|
bitfld.long 0x00 5. "exact_start,Guarantee exact start of AD conversion for highest prior sequencer" "0: Always finish running AD conversion before,1: AD conversions of lower prior sequencers can be"
|
|
newline
|
|
bitfld.long 0x00 4. "shenb8,Sample/hold enable of analog input AIN8" "0: Use analog inputs directly (sample/hold,1: Use sample/hold"
|
|
newline
|
|
bitfld.long 0x00 3. "shenb7,Sample/hold enable of analog input AIN7" "0: Use analog inputs directly (sample/hold,1: Use sample/hold"
|
|
newline
|
|
bitfld.long 0x00 2. "shenb6,Sample/hold enable of analog input AIN6" "0: Use analog inputs directly (sample/hold,1: Use sample/hold"
|
|
newline
|
|
bitfld.long 0x00 1. "power,Power-down mode of ADC" "0: Power-down,1: Power up"
|
|
newline
|
|
bitfld.long 0x00 0. "reset,Soft reset ADC and state machine: There are no constraints on reset length" "0: Reset is inactive,1: Reset is active"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "adc_ctrl_task0,ADC control register for task0: This register contains all information about one AD task different AD tasks can be combined to a sequence using the nxt_task pointer"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable: Generate an IRQ when this ADC task is finished" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select: 0..7: Number of comparator unit to which ADC value is send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 26. "output_disable,Output disable" "0: Send data to output FIFO,1: Dont send data to output FIFO (to only compare"
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newline
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bitfld.long 0x00 25. "timestamp,Sample timestamp: Add sample timestamp (lower 16 bits of systime_ns) to FIFO (before ADC data)" "0,1"
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|
newline
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|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling: Multiple sequential samples can be averaged" "0: no hardware oversampling,1: 2x hardware oversampling,2: 4x hardware oversampling,3: 8x hardware oversampling,4: 16x hardware oversampling,5: 32x hardware oversampling,6: 64x hardware oversampling,?..."
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newline
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bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0: Do not resample AIN8 hold previously sampled..,1: Sample AIN8 at start of AD control statemachine"
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newline
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bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0: Do not resample AIN7 hold previously sampled..,1: Sample AIN7 at start of AD control statemachine"
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newline
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bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0: Do not resample AIN6 hold previously sampled..,1: Sample AIN6 at start of AD control statemachine"
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newline
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bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0: Sample from analog pin AIN0,1: Sample from analog pin AIN1,2: Sample from analog pin AIN2,3: Sample from analog pin AIN3,4: Sample from analog pin AIN4,5: Sample from analog pin AIN5,6: Sample from analog pin AIN6 (allows..,7: Sample from analog pin AIN7 (allows..,8: Sample from analog pin AIN8 (allows..,?,?,?,?,?,?,15: keep"
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newline
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bitfld.long 0x00 11.--14. "start_delay,Sample start delay: Delay in steps of 100ns that sampling starts after reaching start_cond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 7.--10. "nxt_task,Next task number: 0..14: Pointer to the next task number to be executed in this sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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newline
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bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal: The AD task starts 'as fast as possible' after the programmed start event below was reached" "0: wait (do not start until set to other value),1: continuously,2: other ADC at same tasknr and same sequencer,3: other ADC at same tasknr and same sequencer,4: seq_timer,5: irq_raw of comparator0,6: irq_raw of comparator1,7: irq_raw of comparator2,8: irq_raw of comparator3,9: irq_raw of comparator4,10: irq_raw of comparator5,11: irq_raw of comparator6,12: irq_raw of comparator7,13: pwm_cnt0_min,14: pwm_cnt0_max,15: pwm_cnt1_min,16: pwm_cnt1_max,17: posedge pwm_t0,18: negedge pwm_t0,19: posedge pwm_t1,20: negedge pwm_t1,21: posedge pwm_t2,22: negedge pwm_t2,23: posedge pwm_t3,24: negedge pwm_t3,25: posedge pwm_t4,26: negedge pwm_t4,27: posedge pwm_t5,28: negedge pwm_t5,29: posedge pwm_t6,30: negedge pwm_t6,31: posedge pwm_t7,32: negedge pwm_t7,33: posedge enc0_n,34: negedge enc0_n,35: posedge enc1_n,36: negedge enc1_n,37: enc0_edge,38: enc1_edge,39: posedge mp0,40: negedge mp0,41: posedge mp1,42: negedge mp1,43: xpic0_timer0,44: xpic0_timer1,45: xpic0_timer2,46: xpic1_timer0,47: xpic1_timer1,48: xpic1_timer2,49: xpic2_timer0,50: xpic2_timer1,51: xpic2_timer2,52: xpic3_timer0,53: xpic3_timer1,54: xpic3_timer2,55: arm_timer0,56: arm_timer1,57: arm_timer2,?..."
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group.long 0x08++0x03
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line.long 0x00 "adc_ctrl_task1,ADC control register for task1: See task0 for details"
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bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
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newline
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bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
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newline
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bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
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newline
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bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
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newline
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bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
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newline
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bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
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newline
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bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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newline
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bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x0C++0x03
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line.long 0x00 "adc_ctrl_task2,ADC control register for task2: See task0 for details"
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bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
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newline
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bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
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newline
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bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
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newline
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bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
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newline
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bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
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newline
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bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
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newline
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bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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newline
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bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x10++0x03
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line.long 0x00 "adc_ctrl_task3,ADC control register for task3: See task0 for details"
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bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
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newline
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bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
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newline
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bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
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newline
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bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
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newline
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bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
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newline
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bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
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newline
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bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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newline
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bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x14++0x03
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line.long 0x00 "adc_ctrl_task4,ADC control register for task4: See task0 for details"
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bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
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newline
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bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
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newline
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bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
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newline
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bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
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newline
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bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
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newline
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bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
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newline
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bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x18++0x03
|
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line.long 0x00 "adc_ctrl_task5,ADC control register for task5: See task0 for details"
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bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
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newline
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bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
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newline
|
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bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
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|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
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newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
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newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
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newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
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|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x1C++0x03
|
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line.long 0x00 "adc_ctrl_task6,ADC control register for task6: See task0 for details"
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bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
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|
newline
|
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bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
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|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
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|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
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newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
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newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
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|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0x20++0x03
|
|
line.long 0x00 "adc_ctrl_task7,ADC control register for task7: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
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|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
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|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "adc_ctrl_task8,ADC control register for task8: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "adc_ctrl_task9,ADC control register for task9: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "adc_ctrl_task10,ADC control register for task10: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "adc_ctrl_task11,ADC control register for task11: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "adc_ctrl_task12,ADC control register for task12: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "adc_ctrl_task13,ADC control register for task13: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "adc_ctrl_task14,ADC control register for task14: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "adc_ctrl_seq0_ctrl,Sequencer0 control register: ADC_CTRL allows up to 4 sequences of AD-tasks to be executed in parallel"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
abitfld.long 0x00 8.--15. "timer,Sequence timer preload A sequence timer can be used to delay the start of a specific task" "0x00=0: 1us delay,0x01=1: 2us delay,0xFF=255: 256us delay"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "first_task,First task number of sequence: After setting seq_en this task number will be executed first" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "seq_restart,Restart sequencer: A sequence stops when reaching tasknr=15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq_en,Enable of sequencer" "0: disabled,1: enabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "adc_ctrl_seq1_ctrl,Sequencer1 control register: See seq0_ctrl for details"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "timer,Sequence timer preload"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "first_task,First task number of sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "seq_restart,Restart sequencer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq_en,Enable of sequencer" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "adc_ctrl_seq2_ctrl,Sequencer2 control register: See seq0_ctrl for details"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "timer,Sequence timer preload"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "first_task,First task number of sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "seq_restart,Restart sequencer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq_en,Enable of sequencer" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "adc_ctrl_seq3_ctrl,Sequencer3 control register: See seq0_ctrl for details"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "timer,Sequence timer preload"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "first_task,First task number of sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "seq_restart,Restart sequencer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq_en,Enable of sequencer" "0,1"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "adc_ctrl_seq0_status,Sequence 0 status register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "seq_finished,sequence is finished (reached tasknr=15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "fifo_urun,FIFO underrun occured reset by disabling seq0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "fifo_ovfl,FIFO overflow occured reset by disabling seq0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "fifo_fill,Number of values in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "adc_ctrl_seq1_status,Sequence 1 status register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "seq_finished,sequence is finished (reached tasknr=15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "fifo_urun,FIFO underrun occured reset by disabling seq1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "fifo_ovfl,FIFO overflow occured reset by disabling seq1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "fifo_fill,Number of values in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "adc_ctrl_seq2_status,Sequence 2 status register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "seq_finished,sequence is finished (reached tasknr=15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "fifo_urun,FIFO underrun occured reset by disabling seq2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "fifo_ovfl,FIFO overflow occured reset by disabling seq2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "fifo_fill,Number of values in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "adc_ctrl_seq3_status,Sequence 3 status register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "seq_finished,sequence is finished (reached tasknr=15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "fifo_urun,FIFO underrun occured reset by disabling seq3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "fifo_ovfl,FIFO overflow occured reset by disabling seq3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "fifo_fill,Number of values in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "adc_ctrl_seq0_val,ADC value This register behaves like a FIFO up to 8 output values will be stored"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "tasknr,Number of task that started the appropriate AD-conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "adc_ctrl_seq1_val,ADC value This register behaves like a FIFO up to 8 output values will be stored"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "tasknr,Number of task that started the appropriate AD-conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "adc_ctrl_seq2_val,ADC value This register behaves like a FIFO up to 8 output values will be stored"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "tasknr,Number of task that started the appropriate AD-conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "adc_ctrl_seq3_val,ADC value This register behaves like a FIFO up to 8 output values will be stored"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "tasknr,Number of task that started the appropriate AD-conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "adc_ctrl_compare0_config,Digital comparator 0 config register: Configure comparator in this register restart comparator by writing to irq_raw register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0: always high band (set irq as long as value is..,1: entering high band (set irq when entering high,2: leaving high band (set irq when leaving high..,3: hysteresis always high band (set irq when,4: hysteresis entering high band (set irq when,5: always mid band (set irq as long as value is in,6: once mid band (set irq when entering mid band,7: always low band (set irq as long as value is in,8: entering low band (set irq when entering low..,9: leaving low band (set irq when leaving low..,10: hysteresis always low band (set irq when,11: hysteresis entering low band (set irq when,?..."
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level: ADC-values <= lower_border are in low level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level: ADC-values > upper_border are in high level"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "adc_ctrl_compare1_config,Digital comparator 1 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "adc_ctrl_compare2_config,Digital comparator 2 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "adc_ctrl_compare3_config,Digital comparator 3 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "adc_ctrl_compare4_config,Digital comparator 4 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "adc_ctrl_compare5_config,Digital comparator 5 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "adc_ctrl_compare6_config,Digital comparator 6 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "adc_ctrl_compare7_config,Digital comparator 7 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "adc_ctrl_debug_config,ADC config register for direct control: This register is for debug purposes only! Refer to Renesas ADC documentation for details"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12. "rsb_n,High active reset signal to ADC hardmacro" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "shout8,Sample/hold output control of AIN7" "0: Output of sample/hold is disabled,1: Output of sample/hold is enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "shout7,Sample/hold output control of AIN7" "0: Output of sample/hold is disabled,1: Output of sample/hold is enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "shout6,Sample/hold output control of AIN6" "0: Output of sample/hold is disabled,1: Output of sample/hold is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "shcnt8,Sample/hold control of AIN8" "0: Hold function is available,1: Sampling function is available"
|
|
newline
|
|
bitfld.long 0x00 7. "shcnt7,Sample/hold control of AIN7" "0: Hold function is available,1: Sampling function is available"
|
|
newline
|
|
bitfld.long 0x00 6. "shcnt6,Sample/hold control of AIN6" "0: Hold function is available,1: Sampling function is available"
|
|
newline
|
|
bitfld.long 0x00 5. "conv,AD-conversion start pin: Value will be changed externally with following negedge of ADCCLK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--4. "sel,Select for analog multiplexer of ADC: Value will be changed externally with following negedge of ADCCLK" "0: Sample from analog pin AIN0,1: Sample from analog pin AIN1,2: Sample from analog pin AIN2,3: Sample from analog pin AIN3,4: Sample from analog pin AIN4,5: Sample from analog pin AIN5,6: Sample from analog pin AIN6 (allows..,7: Sample from analog pin AIN7 (allows..,8: Sample from analog pin AIN8 (allows..,?..."
|
|
newline
|
|
bitfld.long 0x00 0. "debug_en,Debug enable" "0: Use task-sequencers to control ADC,1: Use values defined in this register to.."
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "adc_ctrl_debug_status,Debug status register"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "eocb,Inverted End Of Conversion signal of ADC (debug only)" "0,1"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "adc_ctrl_debug_val,ADC value in debug mode"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value changed with negedge of debug_status-eocb"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "adc_ctrl_irq_raw,Raw IRQ: Read access shows status of unmasked IRQs"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "compare7,Comparator 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "compare6,Comparator 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "compare5,Comparator 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "compare4,Comparator 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "compare3,Comparator 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "compare2,Comparator 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "compare1,Comparator 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "compare0,Comparator 0 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "seq3_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "seq3_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "seq3_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "seq3_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "seq2_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "seq2_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "seq2_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "seq2_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "seq1_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "seq1_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "seq1_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "seq1_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "seq0_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "seq0_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "seq0_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq0_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "adc_ctrl_irq_masked,Masked IRQ: Shows status of masked IRQs (as connected to ARM/xPIC)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "compare7,Comparator 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "compare6,Comparator 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "compare5,Comparator 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "compare4,Comparator 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "compare3,Comparator 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "compare2,Comparator 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "compare1,Comparator 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "compare0,Comparator 0 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "seq3_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "seq3_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "seq3_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "seq3_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "seq2_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "seq2_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "seq2_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "seq2_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "seq1_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "seq1_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "seq1_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "seq1_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "seq0_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "seq0_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "seq0_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq0_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "adc_ctrl_irq_mask_set,IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "compare7,Comparator 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "compare6,Comparator 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "compare5,Comparator 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "compare4,Comparator 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "compare3,Comparator 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "compare2,Comparator 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "compare1,Comparator 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "compare0,Comparator 0 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "seq3_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "seq3_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "seq3_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "seq3_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "seq2_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "seq2_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "seq2_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "seq2_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "seq1_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "seq1_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "seq1_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "seq1_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "seq0_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "seq0_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "seq0_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq0_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "adc_ctrl_irq_mask_reset,IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "compare7,Comparator 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "compare6,Comparator 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "compare5,Comparator 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "compare4,Comparator 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "compare3,Comparator 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "compare2,Comparator 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "compare1,Comparator 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "compare0,Comparator 0 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "seq3_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "seq3_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "seq3_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "seq3_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "seq2_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "seq2_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "seq2_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "seq2_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "seq1_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "seq1_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "seq1_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "seq1_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "seq0_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "seq0_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "seq0_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq0_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "adc_ctrl_debug_ctrl0,ADC debug parameters for statemachine: This register is for debug purposes only!"
|
|
bitfld.long 0x00 27.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 23.--26. "tasksm_conv_shcnt1_m2,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 19.--22. "tasksm_conv_shcnt1,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "tasksm_shcnt_inactive_m2,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "tasksm_shcnt_inactive,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "tasksm_shcnt_active,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "tasksm_conv,task statemachine timing control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--4. "tasksm_shoutlow2shcnthi,task statemachine timing control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "adc_clk_phase,phase of ADCCLK to change values to ADC" "0: posedge + 20ns,1: posedge + 30ns,2: posedge + 40ns,3: posedge + 10ns"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "adc_ctrl_debug_ctrl1,ADC debug parameters for statemachine: This register is for debug purposes only!"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "quick_seqen_reset,If seq_en=0 directly reset parts of tasksm" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "tasksm_perform_rsb,performing rsb is necessary when restarting with sampling during an unfinished AD conversion" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "tasksm_restart2conv,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "tasksm_shcnt02shout0,task statemachine timing control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "tasksm_shout12conv,task statemachine timing control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "tasksm_shcnt1_shcnt0,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "ADC_CTRL1_MOTION"
|
|
base ad:0xF4200B00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "adc_ctrl_config,ADC general config register: This register is for static config values of ADC"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "systime_shift,shift of sampletime written to FIFO" "0: systime_ns[15:0],1: systime_ns[16:1],?,?,?,?,?,7: systime_ns[22:7]"
|
|
newline
|
|
bitfld.long 0x00 5. "exact_start,Guarantee exact start of AD conversion for highest prior sequencer" "0: Always finish running AD conversion before,1: AD conversions of lower prior sequencers can be"
|
|
newline
|
|
bitfld.long 0x00 4. "shenb8,Sample/hold enable of analog input AIN8" "0: Use analog inputs directly (sample/hold,1: Use sample/hold"
|
|
newline
|
|
bitfld.long 0x00 3. "shenb7,Sample/hold enable of analog input AIN7" "0: Use analog inputs directly (sample/hold,1: Use sample/hold"
|
|
newline
|
|
bitfld.long 0x00 2. "shenb6,Sample/hold enable of analog input AIN6" "0: Use analog inputs directly (sample/hold,1: Use sample/hold"
|
|
newline
|
|
bitfld.long 0x00 1. "power,Power-down mode of ADC" "0: Power-down,1: Power up"
|
|
newline
|
|
bitfld.long 0x00 0. "reset,Soft reset ADC and state machine: There are no constraints on reset length" "0: Reset is inactive,1: Reset is active"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "adc_ctrl_task0,ADC control register for task0: This register contains all information about one AD task different AD tasks can be combined to a sequence using the nxt_task pointer"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable: Generate an IRQ when this ADC task is finished" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select: 0..7: Number of comparator unit to which ADC value is send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0: Send data to output FIFO,1: Dont send data to output FIFO (to only compare"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp: Add sample timestamp (lower 16 bits of systime_ns) to FIFO (before ADC data)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling: Multiple sequential samples can be averaged" "0: no hardware oversampling,1: 2x hardware oversampling,2: 4x hardware oversampling,3: 8x hardware oversampling,4: 16x hardware oversampling,5: 32x hardware oversampling,6: 64x hardware oversampling,?..."
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0: Do not resample AIN8 hold previously sampled..,1: Sample AIN8 at start of AD control statemachine"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0: Do not resample AIN7 hold previously sampled..,1: Sample AIN7 at start of AD control statemachine"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0: Do not resample AIN6 hold previously sampled..,1: Sample AIN6 at start of AD control statemachine"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0: Sample from analog pin AIN0,1: Sample from analog pin AIN1,2: Sample from analog pin AIN2,3: Sample from analog pin AIN3,4: Sample from analog pin AIN4,5: Sample from analog pin AIN5,6: Sample from analog pin AIN6 (allows..,7: Sample from analog pin AIN7 (allows..,8: Sample from analog pin AIN8 (allows..,?,?,?,?,?,?,15: keep"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay: Delay in steps of 100ns that sampling starts after reaching start_cond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number: 0..14: Pointer to the next task number to be executed in this sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal: The AD task starts 'as fast as possible' after the programmed start event below was reached" "0: wait (do not start until set to other value),1: continuously,2: other ADC at same tasknr and same sequencer,3: other ADC at same tasknr and same sequencer,4: seq_timer,5: irq_raw of comparator0,6: irq_raw of comparator1,7: irq_raw of comparator2,8: irq_raw of comparator3,9: irq_raw of comparator4,10: irq_raw of comparator5,11: irq_raw of comparator6,12: irq_raw of comparator7,13: pwm_cnt0_min,14: pwm_cnt0_max,15: pwm_cnt1_min,16: pwm_cnt1_max,17: posedge pwm_t0,18: negedge pwm_t0,19: posedge pwm_t1,20: negedge pwm_t1,21: posedge pwm_t2,22: negedge pwm_t2,23: posedge pwm_t3,24: negedge pwm_t3,25: posedge pwm_t4,26: negedge pwm_t4,27: posedge pwm_t5,28: negedge pwm_t5,29: posedge pwm_t6,30: negedge pwm_t6,31: posedge pwm_t7,32: negedge pwm_t7,33: posedge enc0_n,34: negedge enc0_n,35: posedge enc1_n,36: negedge enc1_n,37: enc0_edge,38: enc1_edge,39: posedge mp0,40: negedge mp0,41: posedge mp1,42: negedge mp1,43: xpic0_timer0,44: xpic0_timer1,45: xpic0_timer2,46: xpic1_timer0,47: xpic1_timer1,48: xpic1_timer2,49: xpic2_timer0,50: xpic2_timer1,51: xpic2_timer2,52: xpic3_timer0,53: xpic3_timer1,54: xpic3_timer2,55: arm_timer0,56: arm_timer1,57: arm_timer2,?..."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "adc_ctrl_task1,ADC control register for task1: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "adc_ctrl_task2,ADC control register for task2: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "adc_ctrl_task3,ADC control register for task3: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "adc_ctrl_task4,ADC control register for task4: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0x18++0x03
|
|
line.long 0x00 "adc_ctrl_task5,ADC control register for task5: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
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|
newline
|
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bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
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|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
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|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
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|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
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|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
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|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0x1C++0x03
|
|
line.long 0x00 "adc_ctrl_task6,ADC control register for task6: See task0 for details"
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|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
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|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
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|
newline
|
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bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
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|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
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|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
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|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
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|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0x20++0x03
|
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line.long 0x00 "adc_ctrl_task7,ADC control register for task7: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
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|
newline
|
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bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
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|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
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|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
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|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0x24++0x03
|
|
line.long 0x00 "adc_ctrl_task8,ADC control register for task8: See task0 for details"
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|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
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|
newline
|
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bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
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|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
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|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
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|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0x28++0x03
|
|
line.long 0x00 "adc_ctrl_task9,ADC control register for task9: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
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|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
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|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
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|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0x2C++0x03
|
|
line.long 0x00 "adc_ctrl_task10,ADC control register for task10: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "adc_ctrl_task11,ADC control register for task11: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "adc_ctrl_task12,ADC control register for task12: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "adc_ctrl_task13,ADC control register for task13: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "adc_ctrl_task14,ADC control register for task14: See task0 for details"
|
|
bitfld.long 0x00 31. "irq_en,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--30. "compare_sel,Comparator select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "output_disable,Output disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "timestamp,Sample timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "oversampling,Hardware oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "sample_ain8,Sample AIN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "sample_ain7,Sample AIN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "sample_ain6,Sample AIN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "analog_sel,Select of analog multiplexer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "start_delay,Sample start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 7.--10. "nxt_task,Next task number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "start_cond,Select ADC start signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "adc_ctrl_seq0_ctrl,Sequencer0 control register: ADC_CTRL allows up to 4 sequences of AD-tasks to be executed in parallel"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
abitfld.long 0x00 8.--15. "timer,Sequence timer preload A sequence timer can be used to delay the start of a specific task" "0x00=0: 1us delay,0x01=1: 2us delay,0xFF=255: 256us delay"
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|
newline
|
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bitfld.long 0x00 4.--7. "first_task,First task number of sequence: After setting seq_en this task number will be executed first" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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|
newline
|
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bitfld.long 0x00 1. "seq_restart,Restart sequencer: A sequence stops when reaching tasknr=15" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "seq_en,Enable of sequencer" "0: disabled,1: enabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "adc_ctrl_seq1_ctrl,Sequencer1 control register: See seq0_ctrl for details"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "timer,Sequence timer preload"
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|
newline
|
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bitfld.long 0x00 4.--7. "first_task,First task number of sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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|
newline
|
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bitfld.long 0x00 1. "seq_restart,Restart sequencer" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "seq_en,Enable of sequencer" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "adc_ctrl_seq2_ctrl,Sequencer2 control register: See seq0_ctrl for details"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "timer,Sequence timer preload"
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|
newline
|
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bitfld.long 0x00 4.--7. "first_task,First task number of sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x00 1. "seq_restart,Restart sequencer" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "seq_en,Enable of sequencer" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "adc_ctrl_seq3_ctrl,Sequencer3 control register: See seq0_ctrl for details"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "timer,Sequence timer preload"
|
|
newline
|
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bitfld.long 0x00 4.--7. "first_task,First task number of sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x00 1. "seq_restart,Restart sequencer" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "seq_en,Enable of sequencer" "0,1"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "adc_ctrl_seq0_status,Sequence 0 status register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "seq_finished,sequence is finished (reached tasknr=15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "fifo_urun,FIFO underrun occured reset by disabling seq0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "fifo_ovfl,FIFO overflow occured reset by disabling seq0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "fifo_fill,Number of values in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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rgroup.long 0x54++0x03
|
|
line.long 0x00 "adc_ctrl_seq1_status,Sequence 1 status register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "seq_finished,sequence is finished (reached tasknr=15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "fifo_urun,FIFO underrun occured reset by disabling seq1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "fifo_ovfl,FIFO overflow occured reset by disabling seq1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "fifo_fill,Number of values in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "adc_ctrl_seq2_status,Sequence 2 status register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "seq_finished,sequence is finished (reached tasknr=15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "fifo_urun,FIFO underrun occured reset by disabling seq2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "fifo_ovfl,FIFO overflow occured reset by disabling seq2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "fifo_fill,Number of values in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "adc_ctrl_seq3_status,Sequence 3 status register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "seq_finished,sequence is finished (reached tasknr=15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "fifo_urun,FIFO underrun occured reset by disabling seq3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "fifo_ovfl,FIFO overflow occured reset by disabling seq3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "fifo_fill,Number of values in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "adc_ctrl_seq0_val,ADC value This register behaves like a FIFO up to 8 output values will be stored"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "tasknr,Number of task that started the appropriate AD-conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "adc_ctrl_seq1_val,ADC value This register behaves like a FIFO up to 8 output values will be stored"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "tasknr,Number of task that started the appropriate AD-conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "adc_ctrl_seq2_val,ADC value This register behaves like a FIFO up to 8 output values will be stored"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "tasknr,Number of task that started the appropriate AD-conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "adc_ctrl_seq3_val,ADC value This register behaves like a FIFO up to 8 output values will be stored"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "tasknr,Number of task that started the appropriate AD-conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "adc_ctrl_compare0_config,Digital comparator 0 config register: Configure comparator in this register restart comparator by writing to irq_raw register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0: always high band (set irq as long as value is..,1: entering high band (set irq when entering high,2: leaving high band (set irq when leaving high..,3: hysteresis always high band (set irq when,4: hysteresis entering high band (set irq when,5: always mid band (set irq as long as value is in,6: once mid band (set irq when entering mid band,7: always low band (set irq as long as value is in,8: entering low band (set irq when entering low..,9: leaving low band (set irq when leaving low..,10: hysteresis always low band (set irq when,11: hysteresis entering low band (set irq when,?..."
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level: ADC-values <= lower_border are in low level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level: ADC-values > upper_border are in high level"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "adc_ctrl_compare1_config,Digital comparator 1 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "adc_ctrl_compare2_config,Digital comparator 2 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "adc_ctrl_compare3_config,Digital comparator 3 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "adc_ctrl_compare4_config,Digital comparator 4 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "adc_ctrl_compare5_config,Digital comparator 5 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "adc_ctrl_compare6_config,Digital comparator 6 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "adc_ctrl_compare7_config,Digital comparator 7 config register"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "mode,IRQ mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "lower_border,border between low and mid level"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "upper_border,border between mid and high level"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "adc_ctrl_debug_config,ADC config register for direct control: This register is for debug purposes only! Refer to Renesas ADC documentation for details"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12. "rsb_n,High active reset signal to ADC hardmacro" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "shout8,Sample/hold output control of AIN7" "0: Output of sample/hold is disabled,1: Output of sample/hold is enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "shout7,Sample/hold output control of AIN7" "0: Output of sample/hold is disabled,1: Output of sample/hold is enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "shout6,Sample/hold output control of AIN6" "0: Output of sample/hold is disabled,1: Output of sample/hold is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "shcnt8,Sample/hold control of AIN8" "0: Hold function is available,1: Sampling function is available"
|
|
newline
|
|
bitfld.long 0x00 7. "shcnt7,Sample/hold control of AIN7" "0: Hold function is available,1: Sampling function is available"
|
|
newline
|
|
bitfld.long 0x00 6. "shcnt6,Sample/hold control of AIN6" "0: Hold function is available,1: Sampling function is available"
|
|
newline
|
|
bitfld.long 0x00 5. "conv,AD-conversion start pin: Value will be changed externally with following negedge of ADCCLK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--4. "sel,Select for analog multiplexer of ADC: Value will be changed externally with following negedge of ADCCLK" "0: Sample from analog pin AIN0,1: Sample from analog pin AIN1,2: Sample from analog pin AIN2,3: Sample from analog pin AIN3,4: Sample from analog pin AIN4,5: Sample from analog pin AIN5,6: Sample from analog pin AIN6 (allows..,7: Sample from analog pin AIN7 (allows..,8: Sample from analog pin AIN8 (allows..,?..."
|
|
newline
|
|
bitfld.long 0x00 0. "debug_en,Debug enable" "0: Use task-sequencers to control ADC,1: Use values defined in this register to.."
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "adc_ctrl_debug_status,Debug status register"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "eocb,Inverted End Of Conversion signal of ADC (debug only)" "0,1"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "adc_ctrl_debug_val,ADC value in debug mode"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value changed with negedge of debug_status-eocb"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "adc_ctrl_irq_raw,Raw IRQ: Read access shows status of unmasked IRQs"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "compare7,Comparator 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "compare6,Comparator 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "compare5,Comparator 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "compare4,Comparator 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "compare3,Comparator 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "compare2,Comparator 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "compare1,Comparator 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "compare0,Comparator 0 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "seq3_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "seq3_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "seq3_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "seq3_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "seq2_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "seq2_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "seq2_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "seq2_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "seq1_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "seq1_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "seq1_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "seq1_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "seq0_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "seq0_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "seq0_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq0_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "adc_ctrl_irq_masked,Masked IRQ: Shows status of masked IRQs (as connected to ARM/xPIC)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "compare7,Comparator 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "compare6,Comparator 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "compare5,Comparator 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "compare4,Comparator 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "compare3,Comparator 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "compare2,Comparator 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "compare1,Comparator 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "compare0,Comparator 0 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "seq3_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "seq3_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "seq3_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "seq3_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "seq2_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "seq2_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "seq2_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "seq2_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "seq1_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "seq1_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "seq1_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "seq1_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "seq0_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "seq0_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "seq0_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq0_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "adc_ctrl_irq_mask_set,IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "compare7,Comparator 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "compare6,Comparator 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "compare5,Comparator 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "compare4,Comparator 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "compare3,Comparator 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "compare2,Comparator 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "compare1,Comparator 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "compare0,Comparator 0 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "seq3_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "seq3_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "seq3_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "seq3_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "seq2_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "seq2_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "seq2_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "seq2_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "seq1_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "seq1_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "seq1_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "seq1_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "seq0_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "seq0_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "seq0_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq0_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "adc_ctrl_irq_mask_reset,IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 23. "compare7,Comparator 7 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "compare6,Comparator 6 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "compare5,Comparator 5 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "compare4,Comparator 4 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "compare3,Comparator 3 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "compare2,Comparator 2 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "compare1,Comparator 1 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "compare0,Comparator 0 IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "seq3_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "seq3_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "seq3_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "seq3_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "seq2_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "seq2_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "seq2_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "seq2_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "seq1_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "seq1_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "seq1_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "seq1_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "seq0_error,Sequence0 error occurred (see seq0_status for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "seq0_fifo_full,Sequence0 value FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "seq0_fifo_available,Sequence0 value FIFO has at least 1 entry to read out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "seq0_task,Sequence0 task IRQ: (ADC task with enabled IRQ is finished)" "0,1"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "adc_ctrl_debug_ctrl0,ADC debug parameters for statemachine: This register is for debug purposes only!"
|
|
bitfld.long 0x00 27.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 23.--26. "tasksm_conv_shcnt1_m2,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19.--22. "tasksm_conv_shcnt1,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "tasksm_shcnt_inactive_m2,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "tasksm_shcnt_inactive,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "tasksm_shcnt_active,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "tasksm_conv,task statemachine timing control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--4. "tasksm_shoutlow2shcnthi,task statemachine timing control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "adc_clk_phase,phase of ADCCLK to change values to ADC" "0: posedge + 20ns,1: posedge + 30ns,2: posedge + 40ns,3: posedge + 10ns"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "adc_ctrl_debug_ctrl1,ADC debug parameters for statemachine: This register is for debug purposes only!"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "quick_seqen_reset,If seq_en=0 directly reset parts of tasksm" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "tasksm_perform_rsb,performing rsb is necessary when restarting with sampling during an unfinished AD conversion" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "tasksm_restart2conv,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "tasksm_shcnt02shout0,task statemachine timing control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "tasksm_shout12conv,task statemachine timing control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "tasksm_shcnt1_shcnt0,task statemachine timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "XPIC_VIC1"
|
|
base ad:0xF4280000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_vic_config,XPIC VIC Configuration register"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "table,use far or near Table" "0: Base Pointer Addr for IRQ Jmp Table + (n*4),1: Base Pointer Addr for IRQ Jmp Table + (n*16) 4"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,global enable of xPIC VIC (0: disable/ 1: enable)" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "xpic_vic_raw_intr0,XPIC VIC Raw0 interrupt status register see netx4000_irq doc"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "xpic_vic_raw_intr1,XPIC VIC Raw1 interrupt status register see netx4000_irq doc"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "xpic_vic_raw_intr2,XPIC VIC Raw2 interrupt status register see netx4000_irq doc"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_vic_softint0_set,XPIC VIC Software0 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_vic_softint1_set,XPIC VIC Software1 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_vic_softint2_set,XPIC VIC Software2 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_vic_softint0_reset,XPIC VIC Software0 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "xpic_vic_softint1_reset,XPIC VIC Software1 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_vic_softint2_reset,XPIC VIC Software2 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "xpic_vic_fiq_addr,XPIC VIC FIQ Vector address 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "val,FIQ handler address"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_vic_irq_addr,XPIC VIC normal IRQ address register"
|
|
hexmask.long 0x00 0.--31. 1. "val,IRQ handler address"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "xpic_vic_vector_addr,XPIC VIC IRQ Vector address"
|
|
hexmask.long 0x00 0.--31. 1. "val,IRQ vector address read access get actuel highest prior IRQ read access get adr_xpic_vic_table_base_addr + IRQ Number * (4/16)"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "xpic_vic_table_base_addr,XPIC VIC IRQ TABLE ADDRESS BASE POINTER"
|
|
hexmask.long 0x00 0.--31. 1. "val,IRQ Table base address the Base Pointer Addr for IRQ Jmp Table"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "xpic_vic_fiq_vect_config,no Register description"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
bitfld.long 0x00 30. "select_fiq_default," "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 7.--29. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_vic_vect_config0,highest priority"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
hexmask.long.tbyte 0x00 7.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
|
|
repeat 14. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "xpic_vic_vect_config$1,no Register description"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
hexmask.long.tbyte 0x00 7.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
|
|
repeat.end
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "xpic_vic_vect_config15,XPIC default interrupt vector all interrupt sources (wired-OR) select with default interrupt vector register lowest priority"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
hexmask.long 0x00 0.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "xpic_vic_default0,XPIC default interrupt vector select0"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int0 - int31 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "xpic_vic_default1,XPIC default interrupt vector select1"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int32 - int63 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "xpic_vic_default2,XPIC default interrupt vector select1"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int64 - int95 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "xpic_vic_fiq_default0,XPIC default interrupt vector select0 for fiq"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int0 - int31 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "xpic_vic_fiq_default1,XPIC default interrupt vector select1 for fiq"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int32 - int63 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "xpic_vic_fiq_default2,XPIC default interrupt vector select1 for fiq"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int64 - int95 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "xpic_vic_rap_irq_edges,resets the Renesas edge IRQs"
|
|
bitfld.long 0x00 27.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long 0x00 0.--26. 1. "val,write '1' to reset the bit"
|
|
tree.end
|
|
tree "XPIC_TIMER1"
|
|
base ad:0xF4280100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_timer_config_timer0,xPIC TIMER Config register0"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer0" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "xpic_timer_config_timer1,xPIC TIMER Config register1"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer1" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_timer_config_timer2,xPIC TIMER Config register2"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer2" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_timer_preload_timer0,xPIC TIMER Timer 0 preload"
|
|
hexmask.long 0x00 0.--31. 1. "val,preload value"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_timer_preload_timer1,xPIC TIMER Timer 1 preload"
|
|
hexmask.long 0x00 0.--31. 1. "val,preload value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_timer_preload_timer2,xPIC TIMER Timer 2 preload"
|
|
hexmask.long 0x00 0.--31. 1. "val,preload value"
|
|
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "xpic_timer_timer$1,xPIC TIMER Timer $1"
|
|
hexmask.long 0x00 0.--31. 1. "val,actual value of timer / systime compare value"
|
|
repeat.end
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_timer_irq_raw,xPIC_TIMER Raw IRQ register: Read access shows status of unmasked IRQs"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "xpic_timer_irq_masked,xPIC_TIMER Masked IRQ register: Shows status of masked IRQs (as connected to xPIC)"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_timer_irq_msk_set,xPIC_TIMER interrupt mask enable: The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "xpic_timer_irq_msk_reset,xPIC_TIMER interrupt mask disable: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for.."
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "xpic_timer_systime_s,xPIC_TIMER upper SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
|
|
hexmask.long 0x00 0.--31. 1. "val,Systime high: Sample systime_ns at read access to systime_s"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "xpic_timer_systime_ns,xPIC_TIMER lower SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
|
|
hexmask.long 0x00 0.--31. 1. "val,Systime low: Sample systime_ns at read access to systime_s"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_timer_compare_systime_s_value,xPIC_TIMER SYSTIME sec compare register"
|
|
hexmask.long 0x00 0.--31. 1. "val,Compare value with systime_s (seconds): Systime_s_compare_irq is set if systime_s matches"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "xpic_timer_systime_config,Select systime for xpic_timer_systime_ns(s) functions"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--1. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
tree.end
|
|
tree "XPIC_WDG1"
|
|
base ad:0xF4280180
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_wdg_trig,netX xPIC Watchdog Trigger Register"
|
|
bitfld.long 0x00 31. "write_enable,Write enable bit for timeout register: As long as this bit is not set all write accesses to the timeout register are ignored" "0,1"
|
|
bitfld.long 0x00 29.--30. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "wdg_counter_trigger_w,Watchdog trigger bit: Bit must be set to trigger the watchdog counter" "0,1"
|
|
bitfld.long 0x00 25.--27. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24. "irq_req_watchdog,xPIC IRQ request of watchdog writing 1 deletes IRQ to xPIC" "0,1"
|
|
bitfld.long 0x00 20.--23. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "wdg_access_code,Watchdog access code for triggering"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "xpic_wdg_counter,netX xPIC Watchdog Counter Register The counter value is decremented each 10000 system clock cycles"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
abitfld.long 0x00 0.--16. "val,Actual watchdog counter value: Bit 16 shows" "0x00000=0: Watchdog is counting down from..,0x00001=1: Watchdog is counting down from.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_wdg_xpic_irq_timeout,netX xPIC Watchdog xPIC interrupt timout register: xpic_irq_timeout or arm_irq_timeout must be nonzero to enable watchdog"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "val,Watchdog interrupt timeout The total xpic_irq timeout for a netX clock of 100MHz is: xpic_wdg_xpic_irq_timeout * 100us"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_wdg_arm_irq_timeout,netX xPIC Watchdog ARM interrupt timout register: xpic_irq_timeout or arm_irq_timeout must be nonzero to enable watchdog"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "val,Watchdog ARM interrupt timeout The total arm_irq timeout for a netX clock of 100MHz is: (xpic_wdg_xpic_irq_timeout + xpic_wdg_arm_irq_timeout) * 100us"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_wdg_irq_raw,Read access shows status of unmasked IRQs"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "xpic_wdg_irq_masked,xpic_wdg Masked IRQ register: Shows status of masked IRQs (as connected to xPIC)"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_wdg_irq_msk_set,xpic_wdg interrupt mask enable: The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_wdg_irq_msk_reset,xpic_wdg interrupt mask disable: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding.."
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
tree.end
|
|
tree "XPIC_MULTI_CPU_PING_IRQ1"
|
|
base ad:0xF42801A0
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "hs_irq_set_raw,read: hs_iq_reg value write: hs_iq_reg set bit(s)"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_set_bits,IRQs for Inter-CPU-Communication"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "hs_irq_reset_raw,read: hs_iq_reg value write: hs_iq_reg reset bit(s)"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_bits,IRQs for Inter-CPU-Communication"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "hs_irq_set_mask,read: mask value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_set_mask,IRQs for Inter-CPU-Communication"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "hs_irq_reset_mask,read: mask value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_mask,reset IRQs for Inter-CPU-Communication"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "hs_irq_masked,read: hs_iq_reg masked value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_masked,mask IRQs for Inter-CPU-Communication"
|
|
tree.end
|
|
tree "XPIC_SYSTIME_LT1"
|
|
base ad:0xF42801C0
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "xpic_lt_systime0_ns,systime0_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime0_ns last latched value"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "xpic_lt_systime0_s,systime0_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime0_s last latched value"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "xpic_lt_systime1_ns,systime1_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime1_ns last latched value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "xpic_lt_systime1_s,systime1_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime1_s last latched value"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "xpic_lt_systime_uc_ns,systime_uc_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_uc_ns last latched value"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "xpic_lt_systime_uc_s,systime_uc_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_uc_s last latched value"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "xpic_lt_systime_rap_ns,systime_rap_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_rap_ns last latched value"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "xpic_lt_systime_rap_s,systime_rap_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_rap_s last latched value"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "xpic_lt_systimes_latch,latch systimes by writing 1'b1 to the assigned bit"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "systime_rap_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "systime_rap_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 5. "systime_uc_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_uc_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 3. "systime1_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "systime1_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 1. "systime0_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "systime0_ns,no field descpription" "0,1"
|
|
tree.end
|
|
tree "XPIC_VIC2"
|
|
base ad:0xF4300000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_vic_config,XPIC VIC Configuration register"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "table,use far or near Table" "0: Base Pointer Addr for IRQ Jmp Table + (n*4),1: Base Pointer Addr for IRQ Jmp Table + (n*16) 4"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,global enable of xPIC VIC (0: disable/ 1: enable)" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "xpic_vic_raw_intr0,XPIC VIC Raw0 interrupt status register see netx4000_irq doc"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "xpic_vic_raw_intr1,XPIC VIC Raw1 interrupt status register see netx4000_irq doc"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "xpic_vic_raw_intr2,XPIC VIC Raw2 interrupt status register see netx4000_irq doc"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_vic_softint0_set,XPIC VIC Software0 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_vic_softint1_set,XPIC VIC Software1 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_vic_softint2_set,XPIC VIC Software2 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_vic_softint0_reset,XPIC VIC Software0 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "xpic_vic_softint1_reset,XPIC VIC Software1 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_vic_softint2_reset,XPIC VIC Software2 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "xpic_vic_fiq_addr,XPIC VIC FIQ Vector address 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "val,FIQ handler address"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_vic_irq_addr,XPIC VIC normal IRQ address register"
|
|
hexmask.long 0x00 0.--31. 1. "val,IRQ handler address"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "xpic_vic_vector_addr,XPIC VIC IRQ Vector address"
|
|
hexmask.long 0x00 0.--31. 1. "val,IRQ vector address read access get actuel highest prior IRQ read access get adr_xpic_vic_table_base_addr + IRQ Number * (4/16)"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "xpic_vic_table_base_addr,XPIC VIC IRQ TABLE ADDRESS BASE POINTER"
|
|
hexmask.long 0x00 0.--31. 1. "val,IRQ Table base address the Base Pointer Addr for IRQ Jmp Table"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "xpic_vic_fiq_vect_config,no Register description"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
bitfld.long 0x00 30. "select_fiq_default," "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 7.--29. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_vic_vect_config0,highest priority"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
hexmask.long.tbyte 0x00 7.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
|
|
repeat 14. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "xpic_vic_vect_config$1,no Register description"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
hexmask.long.tbyte 0x00 7.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
|
|
repeat.end
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "xpic_vic_vect_config15,XPIC default interrupt vector all interrupt sources (wired-OR) select with default interrupt vector register lowest priority"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
hexmask.long 0x00 0.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "xpic_vic_default0,XPIC default interrupt vector select0"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int0 - int31 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "xpic_vic_default1,XPIC default interrupt vector select1"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int32 - int63 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "xpic_vic_default2,XPIC default interrupt vector select1"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int64 - int95 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "xpic_vic_fiq_default0,XPIC default interrupt vector select0 for fiq"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int0 - int31 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "xpic_vic_fiq_default1,XPIC default interrupt vector select1 for fiq"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int32 - int63 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "xpic_vic_fiq_default2,XPIC default interrupt vector select1 for fiq"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int64 - int95 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "xpic_vic_rap_irq_edges,resets the Renesas edge IRQs"
|
|
bitfld.long 0x00 27.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long 0x00 0.--26. 1. "val,write '1' to reset the bit"
|
|
tree.end
|
|
tree "XPIC_TIMER2"
|
|
base ad:0xF4300100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_timer_config_timer0,xPIC TIMER Config register0"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer0" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "xpic_timer_config_timer1,xPIC TIMER Config register1"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer1" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_timer_config_timer2,xPIC TIMER Config register2"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer2" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_timer_preload_timer0,xPIC TIMER Timer 0 preload"
|
|
hexmask.long 0x00 0.--31. 1. "val,preload value"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_timer_preload_timer1,xPIC TIMER Timer 1 preload"
|
|
hexmask.long 0x00 0.--31. 1. "val,preload value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_timer_preload_timer2,xPIC TIMER Timer 2 preload"
|
|
hexmask.long 0x00 0.--31. 1. "val,preload value"
|
|
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "xpic_timer_timer$1,xPIC TIMER Timer $1"
|
|
hexmask.long 0x00 0.--31. 1. "val,actual value of timer / systime compare value"
|
|
repeat.end
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_timer_irq_raw,xPIC_TIMER Raw IRQ register: Read access shows status of unmasked IRQs"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "xpic_timer_irq_masked,xPIC_TIMER Masked IRQ register: Shows status of masked IRQs (as connected to xPIC)"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_timer_irq_msk_set,xPIC_TIMER interrupt mask enable: The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "xpic_timer_irq_msk_reset,xPIC_TIMER interrupt mask disable: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for.."
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "xpic_timer_systime_s,xPIC_TIMER upper SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
|
|
hexmask.long 0x00 0.--31. 1. "val,Systime high: Sample systime_ns at read access to systime_s"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "xpic_timer_systime_ns,xPIC_TIMER lower SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
|
|
hexmask.long 0x00 0.--31. 1. "val,Systime low: Sample systime_ns at read access to systime_s"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_timer_compare_systime_s_value,xPIC_TIMER SYSTIME sec compare register"
|
|
hexmask.long 0x00 0.--31. 1. "val,Compare value with systime_s (seconds): Systime_s_compare_irq is set if systime_s matches"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "xpic_timer_systime_config,Select systime for xpic_timer_systime_ns(s) functions"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--1. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
tree.end
|
|
tree "XPIC_WDG2"
|
|
base ad:0xF4300180
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_wdg_trig,netX xPIC Watchdog Trigger Register"
|
|
bitfld.long 0x00 31. "write_enable,Write enable bit for timeout register: As long as this bit is not set all write accesses to the timeout register are ignored" "0,1"
|
|
bitfld.long 0x00 29.--30. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "wdg_counter_trigger_w,Watchdog trigger bit: Bit must be set to trigger the watchdog counter" "0,1"
|
|
bitfld.long 0x00 25.--27. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24. "irq_req_watchdog,xPIC IRQ request of watchdog writing 1 deletes IRQ to xPIC" "0,1"
|
|
bitfld.long 0x00 20.--23. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "wdg_access_code,Watchdog access code for triggering"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "xpic_wdg_counter,netX xPIC Watchdog Counter Register The counter value is decremented each 10000 system clock cycles"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
abitfld.long 0x00 0.--16. "val,Actual watchdog counter value: Bit 16 shows" "0x00000=0: Watchdog is counting down from..,0x00001=1: Watchdog is counting down from.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_wdg_xpic_irq_timeout,netX xPIC Watchdog xPIC interrupt timout register: xpic_irq_timeout or arm_irq_timeout must be nonzero to enable watchdog"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "val,Watchdog interrupt timeout The total xpic_irq timeout for a netX clock of 100MHz is: xpic_wdg_xpic_irq_timeout * 100us"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_wdg_arm_irq_timeout,netX xPIC Watchdog ARM interrupt timout register: xpic_irq_timeout or arm_irq_timeout must be nonzero to enable watchdog"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "val,Watchdog ARM interrupt timeout The total arm_irq timeout for a netX clock of 100MHz is: (xpic_wdg_xpic_irq_timeout + xpic_wdg_arm_irq_timeout) * 100us"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_wdg_irq_raw,Read access shows status of unmasked IRQs"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "xpic_wdg_irq_masked,xpic_wdg Masked IRQ register: Shows status of masked IRQs (as connected to xPIC)"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_wdg_irq_msk_set,xpic_wdg interrupt mask enable: The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_wdg_irq_msk_reset,xpic_wdg interrupt mask disable: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding.."
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
tree.end
|
|
tree "XPIC_MULTI_CPU_PING_IRQ2"
|
|
base ad:0xF43001A0
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "hs_irq_set_raw,read: hs_iq_reg value write: hs_iq_reg set bit(s)"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_set_bits,IRQs for Inter-CPU-Communication"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "hs_irq_reset_raw,read: hs_iq_reg value write: hs_iq_reg reset bit(s)"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_bits,IRQs for Inter-CPU-Communication"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "hs_irq_set_mask,read: mask value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_set_mask,IRQs for Inter-CPU-Communication"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "hs_irq_reset_mask,read: mask value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_mask,reset IRQs for Inter-CPU-Communication"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "hs_irq_masked,read: hs_iq_reg masked value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_masked,mask IRQs for Inter-CPU-Communication"
|
|
tree.end
|
|
tree "XPIC_SYSTIME_LT2"
|
|
base ad:0xF43001C0
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "xpic_lt_systime0_ns,systime0_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime0_ns last latched value"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "xpic_lt_systime0_s,systime0_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime0_s last latched value"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "xpic_lt_systime1_ns,systime1_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime1_ns last latched value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "xpic_lt_systime1_s,systime1_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime1_s last latched value"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "xpic_lt_systime_uc_ns,systime_uc_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_uc_ns last latched value"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "xpic_lt_systime_uc_s,systime_uc_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_uc_s last latched value"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "xpic_lt_systime_rap_ns,systime_rap_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_rap_ns last latched value"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "xpic_lt_systime_rap_s,systime_rap_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_rap_s last latched value"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "xpic_lt_systimes_latch,latch systimes by writing 1'b1 to the assigned bit"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "systime_rap_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "systime_rap_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 5. "systime_uc_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_uc_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 3. "systime1_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "systime1_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 1. "systime0_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "systime0_ns,no field descpription" "0,1"
|
|
tree.end
|
|
tree "XPIC_VIC3"
|
|
base ad:0xF4380000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_vic_config,XPIC VIC Configuration register"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "table,use far or near Table" "0: Base Pointer Addr for IRQ Jmp Table + (n*4),1: Base Pointer Addr for IRQ Jmp Table + (n*16) 4"
|
|
newline
|
|
bitfld.long 0x00 0. "enable,global enable of xPIC VIC (0: disable/ 1: enable)" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "xpic_vic_raw_intr0,XPIC VIC Raw0 interrupt status register see netx4000_irq doc"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "xpic_vic_raw_intr1,XPIC VIC Raw1 interrupt status register see netx4000_irq doc"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "xpic_vic_raw_intr2,XPIC VIC Raw2 interrupt status register see netx4000_irq doc"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_vic_softint0_set,XPIC VIC Software0 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_vic_softint1_set,XPIC VIC Software1 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_vic_softint2_set,XPIC VIC Software2 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_vic_softint0_reset,XPIC VIC Software0 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "xpic_vic_softint1_reset,XPIC VIC Software1 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_vic_softint2_reset,XPIC VIC Software2 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
|
|
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "xpic_vic_fiq_addr,XPIC VIC FIQ Vector address 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "val,FIQ handler address"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_vic_irq_addr,XPIC VIC normal IRQ address register"
|
|
hexmask.long 0x00 0.--31. 1. "val,IRQ handler address"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "xpic_vic_vector_addr,XPIC VIC IRQ Vector address"
|
|
hexmask.long 0x00 0.--31. 1. "val,IRQ vector address read access get actuel highest prior IRQ read access get adr_xpic_vic_table_base_addr + IRQ Number * (4/16)"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "xpic_vic_table_base_addr,XPIC VIC IRQ TABLE ADDRESS BASE POINTER"
|
|
hexmask.long 0x00 0.--31. 1. "val,IRQ Table base address the Base Pointer Addr for IRQ Jmp Table"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "xpic_vic_fiq_vect_config,no Register description"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
bitfld.long 0x00 30. "select_fiq_default," "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 7.--29. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_vic_vect_config0,highest priority"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
hexmask.long.tbyte 0x00 7.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
|
|
repeat 14. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "xpic_vic_vect_config$1,no Register description"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
hexmask.long.tbyte 0x00 7.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
|
|
repeat.end
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "xpic_vic_vect_config15,XPIC default interrupt vector all interrupt sources (wired-OR) select with default interrupt vector register lowest priority"
|
|
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
|
|
hexmask.long 0x00 0.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "xpic_vic_default0,XPIC default interrupt vector select0"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int0 - int31 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "xpic_vic_default1,XPIC default interrupt vector select1"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int32 - int63 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "xpic_vic_default2,XPIC default interrupt vector select1"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int64 - int95 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "xpic_vic_fiq_default0,XPIC default interrupt vector select0 for fiq"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int0 - int31 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "xpic_vic_fiq_default1,XPIC default interrupt vector select1 for fiq"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int32 - int63 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "xpic_vic_fiq_default2,XPIC default interrupt vector select1 for fiq"
|
|
hexmask.long 0x00 0.--31. 1. "val,select int64 - int95 (wired-OR) 1-selected 0-not selected"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "xpic_vic_rap_irq_edges,resets the Renesas edge IRQs"
|
|
bitfld.long 0x00 27.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long 0x00 0.--26. 1. "val,write '1' to reset the bit"
|
|
tree.end
|
|
tree "XPIC_TIMER3"
|
|
base ad:0xF4380100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_timer_config_timer0,xPIC TIMER Config register0"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer0" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "xpic_timer_config_timer1,xPIC TIMER Config register1"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer1" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_timer_config_timer2,xPIC TIMER Config register2"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mode,Timer2" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_timer_preload_timer0,xPIC TIMER Timer 0 preload"
|
|
hexmask.long 0x00 0.--31. 1. "val,preload value"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_timer_preload_timer1,xPIC TIMER Timer 1 preload"
|
|
hexmask.long 0x00 0.--31. 1. "val,preload value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "xpic_timer_preload_timer2,xPIC TIMER Timer 2 preload"
|
|
hexmask.long 0x00 0.--31. 1. "val,preload value"
|
|
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "xpic_timer_timer$1,xPIC TIMER Timer $1"
|
|
hexmask.long 0x00 0.--31. 1. "val,actual value of timer / systime compare value"
|
|
repeat.end
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "xpic_timer_irq_raw,xPIC_TIMER Raw IRQ register: Read access shows status of unmasked IRQs"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "xpic_timer_irq_masked,xPIC_TIMER Masked IRQ register: Shows status of masked IRQs (as connected to xPIC)"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "xpic_timer_irq_msk_set,xPIC_TIMER interrupt mask enable: The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "xpic_timer_irq_msk_reset,xPIC_TIMER interrupt mask disable: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for.."
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "systime_s_irq,Systime_s Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
|
|
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "xpic_timer_systime_s,xPIC_TIMER upper SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
|
|
hexmask.long 0x00 0.--31. 1. "val,Systime high: Sample systime_ns at read access to systime_s"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "xpic_timer_systime_ns,xPIC_TIMER lower SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
|
|
hexmask.long 0x00 0.--31. 1. "val,Systime low: Sample systime_ns at read access to systime_s"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "xpic_timer_compare_systime_s_value,xPIC_TIMER SYSTIME sec compare register"
|
|
hexmask.long 0x00 0.--31. 1. "val,Compare value with systime_s (seconds): Systime_s_compare_irq is set if systime_s matches"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "xpic_timer_systime_config,Select systime for xpic_timer_systime_ns(s) functions"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--1. "systime_config,systime for timer (2'b00.. systime0 2'b01..systime1 2'b10.. systime_uc 2'b11..systime_rap )" "0,1,2,3"
|
|
tree.end
|
|
tree "XPIC_WDG3"
|
|
base ad:0xF4380180
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "xpic_wdg_trig,netX xPIC Watchdog Trigger Register"
|
|
bitfld.long 0x00 31. "write_enable,Write enable bit for timeout register: As long as this bit is not set all write accesses to the timeout register are ignored" "0,1"
|
|
bitfld.long 0x00 29.--30. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "wdg_counter_trigger_w,Watchdog trigger bit: Bit must be set to trigger the watchdog counter" "0,1"
|
|
bitfld.long 0x00 25.--27. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24. "irq_req_watchdog,xPIC IRQ request of watchdog writing 1 deletes IRQ to xPIC" "0,1"
|
|
bitfld.long 0x00 20.--23. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "wdg_access_code,Watchdog access code for triggering"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "xpic_wdg_counter,netX xPIC Watchdog Counter Register The counter value is decremented each 10000 system clock cycles"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
abitfld.long 0x00 0.--16. "val,Actual watchdog counter value: Bit 16 shows" "0x00000=0: Watchdog is counting down from..,0x00001=1: Watchdog is counting down from.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "xpic_wdg_xpic_irq_timeout,netX xPIC Watchdog xPIC interrupt timout register: xpic_irq_timeout or arm_irq_timeout must be nonzero to enable watchdog"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "val,Watchdog interrupt timeout The total xpic_irq timeout for a netX clock of 100MHz is: xpic_wdg_xpic_irq_timeout * 100us"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "xpic_wdg_arm_irq_timeout,netX xPIC Watchdog ARM interrupt timout register: xpic_irq_timeout or arm_irq_timeout must be nonzero to enable watchdog"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "val,Watchdog ARM interrupt timeout The total arm_irq timeout for a netX clock of 100MHz is: (xpic_wdg_xpic_irq_timeout + xpic_wdg_arm_irq_timeout) * 100us"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "xpic_wdg_irq_raw,Read access shows status of unmasked IRQs"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "xpic_wdg_irq_masked,xpic_wdg Masked IRQ register: Shows status of masked IRQs (as connected to xPIC)"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "xpic_wdg_irq_msk_set,xpic_wdg interrupt mask enable: The IRQ mask enables interrupt requests for corresponding interrupt sources"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "xpic_wdg_irq_msk_reset,xpic_wdg interrupt mask disable: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding.."
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
|
|
tree.end
|
|
tree "XPIC_MULTI_CPU_PING_IRQ3"
|
|
base ad:0xF43801A0
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "hs_irq_set_raw,read: hs_iq_reg value write: hs_iq_reg set bit(s)"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_set_bits,IRQs for Inter-CPU-Communication"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "hs_irq_reset_raw,read: hs_iq_reg value write: hs_iq_reg reset bit(s)"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_bits,IRQs for Inter-CPU-Communication"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "hs_irq_set_mask,read: mask value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_set_mask,IRQs for Inter-CPU-Communication"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "hs_irq_reset_mask,read: mask value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_mask,reset IRQs for Inter-CPU-Communication"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "hs_irq_masked,read: hs_iq_reg masked value"
|
|
hexmask.long 0x00 0.--31. 1. "hs_irq_masked,mask IRQs for Inter-CPU-Communication"
|
|
tree.end
|
|
tree "XPIC_SYSTIME_LT3"
|
|
base ad:0xF43801C0
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "xpic_lt_systime0_ns,systime0_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime0_ns last latched value"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "xpic_lt_systime0_s,systime0_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime0_s last latched value"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "xpic_lt_systime1_ns,systime1_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime1_ns last latched value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "xpic_lt_systime1_s,systime1_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime1_s last latched value"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "xpic_lt_systime_uc_ns,systime_uc_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_uc_ns last latched value"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "xpic_lt_systime_uc_s,systime_uc_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_uc_s last latched value"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "xpic_lt_systime_rap_ns,systime_rap_ns last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_rap_ns last latched value"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "xpic_lt_systime_rap_s,systime_rap_s last latched value"
|
|
hexmask.long 0x00 0.--31. 1. "val,systime_rap_s last latched value"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "xpic_lt_systimes_latch,latch systimes by writing 1'b1 to the assigned bit"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "systime_rap_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "systime_rap_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 5. "systime_uc_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "systime_uc_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 3. "systime1_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "systime1_ns,no field descpription" "0,1"
|
|
bitfld.long 0x00 1. "systime0_s,no field descpription" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "systime0_ns,no field descpription" "0,1"
|
|
tree.end
|
|
tree "RAP_SYSCTRL"
|
|
base ad:0xF8000000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_BOOTMODE,Bootstrap Status Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 8. "SET_PLL_1200,Current PLL speed" "0: 800MHz,1: 1200MHz"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "BOOTMODE_CORE,SQI0 bootstrap options (bit0:MOSI bit1:MISO bit[3:2]: SIO32[1:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_SYSSTAT,System Status Register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "PL310_HWI_DONE,Status of PL310 hardware initialisation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "STANDBYWFI,Status of wait for interrupt [0] CA9#0 [1] CA9#1 [2] CR7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "STANDBYWFE,Status of wait for event [0] CA9#0 [1] CA9#1 [2] CR7" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_ONLY_PORN,Reset Safe Status Register This register is reset by POR_n only"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,General use register which keeps its value during system reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_MUXCFG,DMA Single/Burst Mode Configuration Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DMA_MUX_RX,Defines mode for RX DMA channels (0=SINGLE 1=BURST) [0] SPI0 [1] SPI1 [2] SQI0 [3] SQI1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DMA_MUX_TX,Defines mode for TX DMA channels (0=SINGLE 1=BURST) [0] SPI0 [1] SPI1 [2] SQI0 [3] SQI1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_USB2CFG,USB 2.0 Configuration Register"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 1. "H2MODE,USB interface Port setting signal" "0: Port1 Function Port2 Host,1: Port1 Host Port2 Host"
|
|
newline
|
|
bitfld.long 0x00 0. "DIRPD,Direct power down control" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_PL353CFG,PL353 Configuration Register"
|
|
bitfld.long 0x00 30.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 20.--29. 1. "EBITIMEOUTVALUE_SRAM,Value to be loaded into timeout counter for SRAM port"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 8.--17. 1. "EBITIMEOUTVALUE_NAND,Value to be loaded into timeout counter for NAND port"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SRAM_REMAP,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "SRAM_MW,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3. "NAND_REMAP,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "NAND_MW,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "NAND_CSL,When HIGH the chip select remains asserted between the address phase and data phase of a transfer on the NAND interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "NAND_BOOTEN,Enable NAND booting functionality" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_PCIECFG,PCI Express Configuration Register This register is reset by POR_n only"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12. "CFG_PMCSR_PME_STATUS,Power Management Event Setting (Endpoint only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "TURN_OFF_EVENT_ACK,Acknowledge input Power off was ready (Endpoint only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "D3_EVENT_ACK,Acknowledge input Power off was ready (Endpoint only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "AUX_POWER_DETECT,AUX Power detect" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ALLOW_ENTER_L1,Allows ASPM L1 state change (Root Complex only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "PME_TIM,Clock for PM_PME Message (Input): Only use EP mode It is a toggle signal (clock) of half period 100ms - 150ms" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "MODE_EXT_LBSEL,External serial loop-back bit When asserted serial loopback is enabled between RX and TX for testing" "0: Disable (Normal,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 5. "MODE_CISRREN,Reference Clock Input Termination Setting (Input)" "0: Hi-Z,1: 100ohm"
|
|
newline
|
|
bitfld.long 0x00 4. "MODE_RISRCREN,Receiver termination setting bit" "0: Hi-Z,1: 50Ohm to GND"
|
|
newline
|
|
bitfld.long 0x00 3. "MODE_TX_DRV_EN,This pin forces the transmission buffer (TX Driver) of the SerDes hardmacro to enter the Sleep mode" "0: Sleep,1: Normal"
|
|
newline
|
|
bitfld.long 0x00 2. "MODE_PORT,This pin is used to set the Endpoint mode or Root Complex mode" "0: Endpoint (Upstream Port),1: Root Complex (Downstream Port)"
|
|
newline
|
|
bitfld.long 0x00 1. "MODE_CISRMSEL,Reference clock input buffer mode selector" "0: AC-coupling mode,1: DC-coupling mode"
|
|
newline
|
|
bitfld.long 0x00 0. "MODE_PORT_ENABLE_B,Set to Macro OFF mode" "0: Normal,1: Macro OFF"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_PCIESTAT,PCI Express Status Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 11. "COSPLLOCK,PLL Lock Signal Monitor (Output)" "0: Unlock,1: Lock In At-Speed"
|
|
newline
|
|
bitfld.long 0x00 10. "PMU_POWER_OFF,Report of Power Off possibility (Output): Only use RC mode This signal indicates that UDL can control the macro power off after hand-shake of power down protocol by TURN_OFF_EVENT and TURN_OFF_EVENT_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CFG_PMCSR_PME_STATUS_WRITECLEAR,It is used by CFG_PMCSR_PME_STATUS and a pair" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "D3_EVENT,Non-D0 State change flag (Output): Only use EP mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "TURN_OFF_EVENT,Receive flag of PME_Turn_Off Msg (Output): Only use EP mode It indicates that macro receive the PME_Turn_Off Messag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "CFG_DEVICE_CONTROL_MAX_READREQ_SIZE,Max read request size" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "CFG_LINK_CONTROL_ASPM_CONTROL,Active State Power Management (ASPM) Support" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "CFG_MSI_EN,MSI enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CFG_BUS_MASTER_EN,Bus master enable" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_PIXCLKCFG,PVO Pixel Clock Configuration Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 8. "EXT_CLOCK,When HIGH the external clock is used" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIVIDER,Clock divider setting for pixel clock"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_PCIESTAT_MSG_ADDR_0,PCI Express Message Address Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "MSG_ADDR,Output from Message Address Register (offset: 1054h) value"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_PCIESTAT_MSG_ADDR_1,PCI Express Message Address Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MSG_ADDR,Output from Message Upper Address Register (offset: 1058h) value"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_PCIESTAT_MSG_DATA,PCI Express Message Data Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MSG_DATA,Output from Message Data Register (offset: 105Ch) value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_NOCMODECFG,NoC Mode Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "BOOTMODE_A9,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "MODE_L2CDDR,These bits define the path to DDR (0 = direct path to DDR 1 = path through L2C): [0] CR7 [1] DMA [2] Secure [3] reserved [4] reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_NOCAXICFG,ACP Cache Policy Configuration Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 20.--24. "PCIE,reserved value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15.--19. "DMAC,AXI USER bit configuration for DMA controller [4:1] inner attributes: b0000 Strongly-ordered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10.--14. "USB,reserved value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "GMAC_1,reserved value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "GMAC_0,reserved value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_NOCPWRCTRL,Macro Clock Manager Enable Register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "DDR,DDR clock manager enable bit" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "GFX,TES clock manager enable bit" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "SWITCH,Switch clock manager enable bit" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "GMAC,GMAC clock manager enable bit" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "SDIO,SDIO clock manager enable bit" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "PCIe,PCIe clock manager enable bit" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "USB,USB2 clock manager enable bit" "0: disabled,1: enabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_NOCPWRMASK,Macro Clock Manager Enable Mask Register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "DDR,DDR clock manager enable mask bit" "0: no access to clock manager enable bit,1: clock manager enable bit can be set"
|
|
newline
|
|
bitfld.long 0x00 5. "GFX,TES clock manager enable mask bit" "0: no access to clock manager enable bit,1: clock manager enable bit can be set"
|
|
newline
|
|
bitfld.long 0x00 4. "SWITCH,Switch clock manager enable mask bit" "0: no access to clock manager enable bit,1: clock manager enable bit can be set"
|
|
newline
|
|
bitfld.long 0x00 3. "GMAC,GMAC clock manager enable mask bit" "0: no access to clock manager enable bit,1: clock manager enable bit can be set"
|
|
newline
|
|
bitfld.long 0x00 2. "SDIO,SDIO clock manager enable mask bit" "0: no access to clock manager enable bit,1: clock manager enable bit can be set"
|
|
newline
|
|
bitfld.long 0x00 1. "PCIe,PCIe clock manager enable mask bit" "0: no access to clock manager enable bit,1: clock manager enable bit can be set"
|
|
newline
|
|
bitfld.long 0x00 0. "USB,USB clock manager enable mask bit" "0: no access to clock manager enable bit,1: clock manager enable bit can be set"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_NOCPWRSTAT,Macro Clock Manager Status Register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "DDR,DDR clock manager status" "0: macro disabled,1: macro enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "GFX,TES clock manager status" "0: macro disabled,1: macro enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "SWITCH,Switch clock manager status" "0: macro disabled,1: macro enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "GMAC,GMAC clock manager status" "0: macro disabled,1: macro enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "SDIO,SDIO clock manager status" "0: macro disabled,1: macro enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "PCIe,PCIe clock manager status" "0: macro disabled,1: macro enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "USB,USB clock manager status" "0: macro disabled,1: macro enabled"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_CLKCFG,Macro Clock Enable Register (needs to set before NOCPWRCTRL)"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "DDR,Macro clock enable" "0: clock disabled,1: clock enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "GFX,Macro clock enable" "0: clock disabled,1: clock enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "SWITCH,Macro clock enable" "0: clock disabled,1: clock enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "GMAC,Macro clock enable" "0: clock disabled,1: clock enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "SDIO,Macro clock enable" "0: clock disabled,1: clock enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "PCIe,Macro clock enable" "0: clock disabled,1: clock enabled This bit is reset by POR_n"
|
|
newline
|
|
bitfld.long 0x00 0. "USB,Macro clock enable" "0: clock disabled,1: clock enabled"
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_RSTCTRL,Reset Control Register"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "SWRST_REQ,Software reset request" "0: no reset,1: reset"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_RSTMASK,Reset Mask Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 7. "MASK_EXT,Enable bit for reset requests from external controller" "0: reset request disabled,1: reset request enabled.Reset mask bit for"
|
|
newline
|
|
bitfld.long 0x00 6. "MASK_NETX_USB,Enable bit for reset requests from NetX USB2JTAG" "0: reset request disabled,1: reset request enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "MASK_NETX_WDG,Enable bit for reset requests from NetX Watchdog" "0: reset request disabled,1: reset request enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "MASK_NETX_DPM,Enable bit for reset requests from NetX DPM" "0: reset request disabled,1: reset request enabled"
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|
newline
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bitfld.long 0x00 2.--3. "WDRST_MASK_CA9,Enable bit for ARM Cortex-A9 dual MPCore watchdog mode If a software failure prevents the Watchdog Counter Register from being refreshed the Watchdog Counter Register reaches zero the Watchdog reset status flag is set and the associated.." "0: watchdog reset request disabled,1: watchdog reset request enabled,?..."
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|
newline
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bitfld.long 0x00 1. "WDRST_MASK_CR7,Enable bit for ARM Cortex-R7 Core watchdog mode If a software failure prevents the Watchdog Counter Register from being refreshed the Watchdog Counter Register reaches zero the Watchdog reset status flag is set and the associated.." "0: watchdog reset request disabled,1: watchdog reset request enabled"
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newline
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bitfld.long 0x00 0. "SWRST_MASK,Enable bit for software reset requests from Reset Control Register (RSTCTRL.SWRSTREQ)" "0: software reset request disabled,1: software reset request enabled"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_RSTSTAT,Reset Status Register This register is reset by POR_n only"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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|
newline
|
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bitfld.long 0x00 7. "STAT_EXT,Status bit of external reset request" "0: Device has not received a reset request,1: Device received a reset request"
|
|
newline
|
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bitfld.long 0x00 6. "STAT_NETX_USB,Status bit of NetX USB2JTAG reset request" "0: Device has not received a reset request,1: Device received a reset request"
|
|
newline
|
|
bitfld.long 0x00 5. "STAT_NETX_WDG,Status bit of NetX watchdog reset request" "0: Device has not received a reset request,1: Device received a reset request"
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|
newline
|
|
bitfld.long 0x00 4. "STAT_NETX_DPM,Status bit of NetX DPM reset request" "0: Device has not received a reset request,1: Device received a reset request"
|
|
newline
|
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bitfld.long 0x00 2.--3. "WDRST_STAT_CA9,Status bit of ARM Cortex-A9 dual MPCore watchdog mode If a software failure prevents the Watchdog Counter Register from being refreshed the Watchdog Counter Register reaches zero the Watchdog reset status flag is set and the associated.." "0: Device has not received a watchdog reset..,1: Device received a watchdog reset request,?..."
|
|
newline
|
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bitfld.long 0x00 1. "WDRST_STAT_CR7,Status bit of ARM Cortex-R7 Core watchdog mode If a software failure prevents the Watchdog Counter Register from being refreshed the Watchdog Counter Register reaches zero the Watchdog reset status flag is set and the associated.." "0: Device has not received a watchdog reset..,1: Device received a watchdog reset request"
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|
newline
|
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bitfld.long 0x00 0. "SWRST_STAT,Status bit whether or not software reset requests from Reset Control Register (RSTCTRL.SWRSTREQ) have been received" "0: Device has not received a software reset..,1: Device received a software reset request"
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|
wgroup.long 0x5C++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_RSTSTATCLR,Reset Status Clear Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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|
newline
|
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bitfld.long 0x00 7. "STATCLR_EXT,Bit to clear the status of software reset requests from Reset Control Register (RSTCTRL.SWRESETREQ)" "0: Writing a 0 has no effect,1: Writing a 1 to the SWRESETCLR bit clears the"
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|
newline
|
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bitfld.long 0x00 6. "STATCLR_NETX_USB,Bit to clear the status of software reset requests from Reset Control Register (RSTCTRL.SWRESETREQ)" "0: Writing a 0 has no effect,1: Writing a 1 to the SWRESETCLR bit clears the"
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|
newline
|
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bitfld.long 0x00 5. "STATCLR_NETX_WDG,Bit to clear the status of software reset requests from Reset Control Register (RSTCTRL.SWRESETREQ)" "0: Writing a 0 has no effect,1: Writing a 1 to the SWRESETCLR bit clears the"
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|
newline
|
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bitfld.long 0x00 4. "STATCLR_NETX_DPM,Bit to clear the status of software reset requests from Reset Control Register (RSTCTRL.SWRESETREQ)" "0: Writing a 0 has no effect,1: Writing a 1 to the SWRESETCLR bit clears the"
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|
newline
|
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bitfld.long 0x00 2.--3. "WDRST_STATCLR_CA9,Bit to clear the status of ARM Cortex-A9 dual MPCore watchdog reset requests" "0: Writing a 0 has no effect,1: Writing a 1 to the WDRESETCLR bit clears the,?..."
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|
newline
|
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bitfld.long 0x00 1. "WDRST_STATCLR_CR7,Bit to clear the status of ARM Cortex-R7 Core watchdog reset requests" "0: Writing a 0 has no effect,1: Writing a 1 to the WDRESETCLR bit clears the"
|
|
newline
|
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bitfld.long 0x00 0. "SWRST_STATCLR,Bit to clear the status of software reset requests from Reset Control Register (RSTCTRL.SWRESETREQ)" "0: Writing a 0 has no effect,1: Writing a 1 to the SWRESETCLR bit clears the"
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|
group.long 0x60++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_NETX_RST_REQ,NetX Reset Request Register"
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|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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|
newline
|
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bitfld.long 0x00 1. "NETX_USB_RST_REQ,Register for high active NETX USB reset request This bit is reset by POR_n only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "NETX_RST_REQ,Register for high active NETX reset request" "0,1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_RTC_RSTN,RTC Reset Register"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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|
newline
|
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bitfld.long 0x00 0. "RTC_RSTN,Register for low active RTC reset" "0,1"
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|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_CHIP_ID_0,ChipID Part0"
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|
hexmask.long 0x00 0.--31. 1. "CHIP_ID,CHIP_ID_0"
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rgroup.long 0xB4++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_CHIP_ID_1,ChipID Part1"
|
|
hexmask.long 0x00 0.--31. 1. "CHIP_ID,CHIP_ID_1"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_CHIP_ID_2,ChipID Part2"
|
|
hexmask.long 0x00 0.--31. 1. "CHIP_ID,CHIP_ID_2"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_CHIP_ID_3,ChipID Part3"
|
|
hexmask.long 0x00 0.--31. 1. "CHIP_ID,CHIP_ID_3"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_OTP_CONFIG_0,Hardware Fuse Register"
|
|
abitfld.long 0x00 16.--31. "NETX_HW_FUSE,Bit" "0x0000=0: enabled,0x0001=1: disabled,0x0002=2: NetX Hardware Fuses State of CoreSight,0x0003=3: NetX Hardware Fuses State of CoreSight..,0x0004=4: NetX Hardware Fuses State of CoreSight..,0x0005=5: NetX Hardware Fuses State of Cortex R7..,0x0006=6: NetX Hardware Fuses State of Cortex R7,0x0007=7: NetX Hardware Fuses State of Cortex A9..,0x0008=8: NetX Hardware Fuses State of Cortex A9,0x0009=9: NetX Hardware Fuses State of Cortex A9..,0x000A=10: NetX Hardware Fuses State of PL310/L2..,0x000B=11: NetX Hardware Fuses State of netX..,0x000C=12: NetX Hardware Fuses Reserved Bit,0x000D=13: NetX Hardware Fuses State of Cortex..,0x000E=14: NetX Hardware Fuses State of Cortex..,0x000F=15: NetX Hardware Fuses State of netX.."
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|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CLOCK_MASK,Clock mask (1=IP permanently disabled 0=IP can be enabled) [7] reserved [6] DDR Controller [5] TES [4] SWITCH [3] GMAC [2] SDIO [1] PCIe [0] USB2.0"
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|
newline
|
|
abitfld.long 0x00 0.--7. "MODE,Bit" "0x00=0: USB2JTAG can be enabled by,0x01=1: USB2JTAG permanently disabled,0x02=2: CPU1,0x03=3: USB2JTAG,0x04=4: Reserved Bit,0x05=5: Reserved Bit,0x06=6: Reserved Bit,0x07=7: Reserved"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_OTP_CONFIG_1,Software Fuse Register"
|
|
abitfld.long 0x00 24.--31. "FUSE_120,Bit" "0x00=0: OTP fuse value RSA invalid keys..,0x01=1: OTP fuse value RSA invalid keys..,0x02=2: OTP fuse value RSA invalid keys..,0x03=3: OTP fuse value RSA invalid keys..,0x04=4: OTP fuse value RSA invalid keys..,0x05=5: OTP fuse value RSA Chip Type Bit,0x06=6: OTP fuse value RSA Chip Type Bit,0x07=7: OTP fuse value RSA Chip Type"
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|
newline
|
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abitfld.long 0x00 16.--23. "FUSE_121,Bit" "0x00=0: OTP fuse value RSA key select Bit,0x01=1: OTP fuse value RSA key select Bit,0x02=2: OTP fuse value RSA key select Bit,0x03=3: OTP fuse value RSA key select Bit,0x04=4: OTP fuse value RSA key select Bit,0x05=5: OTP fuse value RSA key select Bit,0x06=6: OTP fuse value RSA key select Bit,0x07=7: OTP fuse value RSA invalid keys.."
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "FUSE_122,OTP fuse value sChipID secure UNIQUE chip ID"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "FUSE_123,OTP fuse value sChipID secure UNIQUE chip ID"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_OTP_CONFIG_2,Software Fuse Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "FUSE_116,OTP fuse value CusID customer ID"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "FUSE_117,OTP fuse value CusID customer ID"
|
|
newline
|
|
abitfld.long 0x00 8.--15. "FUSE_118,Bit" "0x00=0: OTP fuse value LicErr LIC_ERR_TAINT_EN Bit,0x01=1: OTP fuse value LicErr LIC_ERR_ABORT_EN Bit,0x02=2: OTP fuse value LicErr LIC_ERR_IRQ_EN Bit,0x03=3: OTP fuse value LicErr LIC_ERR_DELAY_EN Bit,0x04=4: OTP fuse value LicErr Reserved Bit,0x05=5: OTP fuse value LicErr Reserved Bit,0x06=6: OTP fuse value LicErr Reserved Bit,0x07=7: OTP fuse value LicErr Reserved"
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|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "FUSE_119,OTP fuse value RSA protection Protection against OTP fuse modification over register bits OTP_CONFIG_1[31:16]"
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_OTP_CONFIG_3,Software Fuse Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "FUSE_112,OTP fuse value CusIDLicFlagsProtection protection bits for license flags customer ID flags and customer ID"
|
|
newline
|
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abitfld.long 0x00 16.--23. "FUSE_113,Bit" "0x00=0: OTP fuse value LicFlags license flags Bit,0x01=1: OTP fuse value LicFlags license flags Bit,0x02=2: OTP fuse value LicFlags license flags Bit,0x03=3: OTP fuse value LicFlags license flags Bit,0x04=4: OTP fuse value CusIDLicFlagsProtection,0x05=5: OTP fuse value CusIDLicFlagsProtection,0x06=6: OTP fuse value CusIDLicFlagsProtection,0x07=7: OTP fuse value CusIDLicFlagsProtection"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "FUSE_114,OTP fuse value LicFlags license flags"
|
|
newline
|
|
abitfld.long 0x00 0.--7. "FUSE_115,Bit" "0x00=0: OTP fuse value CusIDFlags customer ID..,0x01=1: OTP fuse value CusIDFlags customer ID..,0x02=2: OTP fuse value CusIDFlags customer ID..,0x03=3: OTP fuse value CusIDFlags customer ID..,0x04=4: OTP fuse value LicFlags license flags Bit,0x05=5: OTP fuse value LicFlags license flags Bit,0x06=6: OTP fuse value LicFlags license flags Bit,0x07=7: OTP fuse value LicFlags license flags"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_OTP_CONFIG_4,Software Fuse Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "FUSE_108,OTP fuse value MCLic master licenses"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "FUSE_109,OTP fuse value MCLic master licenses"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "FUSE_110,OTP fuse value MCLic master licenses"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "FUSE_111,OTP fuse value MCLic master licenses"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_OTP_CONFIG_5,Software Fuse Register"
|
|
abitfld.long 0x00 24.--31. "FUSE_104,Bit" "0x00=0: OTP fuse value SWLic software licenses..,0x01=1: OTP fuse value SWLic software licenses..,0x02=2: OTP fuse value SWLic software licenses..,0x03=3: OTP fuse value SWLic software licenses..,0x04=4: OTP fuse value SWLic software licenses..,0x05=5: OTP fuse value SWLic software licenses..,0x06=6: OTP fuse value SWLic software licenses..,0x07=7: OTP fuse value SWLic software licenses.."
|
|
newline
|
|
abitfld.long 0x00 16.--23. "FUSE_105,Bit" "0x00=0: OTP fuse value SWLic software licenses..,0x01=1: OTP fuse value SWLic software licenses..,0x02=2: OTP fuse value SWLic software licenses..,0x03=3: OTP fuse value SWLic software licenses..,0x04=4: OTP fuse value SWLic software licenses..,0x05=5: OTP fuse value SWLic software licenses..,0x06=6: OTP fuse value SWLic software licenses..,0x07=7: OTP fuse value SWLic software licenses.."
|
|
newline
|
|
abitfld.long 0x00 8.--15. "FUSE_106,Bit" "0x00=0: OTP fuse value MCLicProtection..,0x01=1: OTP fuse value MCLicProtection..,0x02=2: OTP fuse value MCLicProtection..,0x03=3: OTP fuse value MCLicProtection..,0x04=4: OTP fuse value SWLic software licenses..,0x05=5: OTP fuse value SWLic software licenses..,0x06=6: OTP fuse value SWLic software licenses..,0x07=7: OTP fuse value SWLic software licenses.."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "FUSE_107,OTP fuse value MCLicProtection protection for master licenses"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_OTP_CONFIG_6,Software Fuse Register"
|
|
abitfld.long 0x00 24.--31. "FUSE_100,Bit" "0x00=0: OTP fuse value ManID manufacturer ID bit..,0x01=1: OTP fuse value ManID manufacturer ID bit..,0x02=2: OTP fuse value ManID manufacturer ID bit..,0x03=3: OTP fuse value ManID manufacturer ID bit..,0x04=4: OTP fuse value ManID manufacturer ID bit..,0x05=5: OTP fuse value ManID manufacturer ID bit..,0x06=6: OTP fuse value ManID manufacturer ID bit..,0x07=7: OTP fuse value ManID manufacturer ID bit 7"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "FUSE_101,OTP fuse value SWLicProtection protection for software licenses"
|
|
newline
|
|
abitfld.long 0x00 8.--15. "FUSE_102,Bit" "0x00=0: OTP fuse value SWLic software licenses..,0x01=1: OTP fuse value SWLic software licenses..,0x02=2: OTP fuse value SWLic software licenses..,0x03=3: OTP fuse value SWLic software licenses..,0x04=4: OTP fuse value SWLicProtection..,0x05=5: OTP fuse value SWLicProtection..,0x06=6: OTP fuse value SWLicProtection..,0x07=7: OTP fuse value SWLicProtection.."
|
|
newline
|
|
abitfld.long 0x00 0.--7. "FUSE_103,Bit" "0x00=0: OTP fuse value SWLic software licenses..,0x01=1: OTP fuse value SWLic software licenses..,0x02=2: OTP fuse value SWLic software licenses..,0x03=3: OTP fuse value SWLic software licenses..,0x04=4: OTP fuse value SWLic software licenses..,0x05=5: OTP fuse value SWLic software licenses..,0x06=6: OTP fuse value SWLic software licenses..,0x07=7: OTP fuse value SWLic software licenses.."
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_OTP_CONFIG_7,Software Fuse Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "FUSE_96,OTP fuse value ManIDProtection protection for manufacturer ID"
|
|
newline
|
|
abitfld.long 0x00 16.--23. "FUSE_97,Bit" "0x00=0: OTP fuse value ManID manufacturer ID bit..,0x01=1: OTP fuse value ManID manufacturer ID bit..,0x02=2: OTP fuse value ManID manufacturer ID bit..,0x03=3: OTP fuse value ManID manufacturer ID bit..,0x04=4: OTP fuse value ManID manufacturer ID bit..,0x05=5: OTP fuse value ManID manufacturer ID bit..,0x06=6: OTP fuse value ManID manufacturer ID bit..,0x07=7: OTP fuse value ManID manufacturer ID bit.."
|
|
newline
|
|
abitfld.long 0x00 8.--15. "FUSE_98,Bit" "0x00=0: OTP fuse value ManID manufacturer ID bit..,0x01=1: OTP fuse value ManID manufacturer ID bit..,0x02=2: OTP fuse value ManID manufacturer ID bit..,0x03=3: OTP fuse value ManID manufacturer ID bit..,0x04=4: OTP fuse value ManID manufacturer ID bit..,0x05=5: OTP fuse value ManID manufacturer ID bit..,0x06=6: OTP fuse value ManID manufacturer ID bit..,0x07=7: OTP fuse value ManID manufacturer ID bit.."
|
|
newline
|
|
abitfld.long 0x00 0.--7. "FUSE_99,Bit" "0x00=0: OTP fuse value ManID manufacturer ID bit..,0x01=1: OTP fuse value ManID manufacturer ID bit..,0x02=2: OTP fuse value ManID manufacturer ID bit..,0x03=3: OTP fuse value ManID manufacturer ID bit..,0x04=4: OTP fuse value ManID manufacturer ID bit..,0x05=5: OTP fuse value ManID manufacturer ID bit..,0x06=6: OTP fuse value ManID manufacturer ID bit..,0x07=7: OTP fuse value ManID manufacturer ID bit.."
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_OTP_CONFIG_8,Software Fuse Register"
|
|
abitfld.long 0x00 24.--31. "FUSE_92,Bit" "0x00=0: OTP fuse value ProdID product ID bit 20..,0x01=1: OTP fuse value ProdID product ID bit 21..,0x02=2: OTP fuse value ProdID product ID bit 22..,0x03=3: OTP fuse value ProdID product ID bit 23..,0x04=4: OTP fuse value ProdID product ID bit 24..,0x05=5: OTP fuse value ProdID product ID bit 25..,0x06=6: OTP fuse value ProdID product ID bit 26..,0x07=7: OTP fuse value ProdID product ID bit 27"
|
|
newline
|
|
abitfld.long 0x00 16.--23. "FUSE_93,Bit" "0x00=0: OTP fuse value ProdID product ID bit 12..,0x01=1: OTP fuse value ProdID product ID bit 13..,0x02=2: OTP fuse value ProdID product ID bit 14..,0x03=3: OTP fuse value ProdID product ID bit 15..,0x04=4: OTP fuse value ProdID product ID bit 16..,0x05=5: OTP fuse value ProdID product ID bit 17..,0x06=6: OTP fuse value ProdID product ID bit 18..,0x07=7: OTP fuse value ProdID product ID bit 19"
|
|
newline
|
|
abitfld.long 0x00 8.--15. "FUSE_94,Bit" "0x00=0: OTP fuse value ProdID product ID bit 4 Bit,0x01=1: OTP fuse value ProdID product ID bit 5 Bit,0x02=2: OTP fuse value ProdID product ID bit 6 Bit,0x03=3: OTP fuse value ProdID product ID bit 7 Bit,0x04=4: OTP fuse value ProdID product ID bit 8 Bit,0x05=5: OTP fuse value ProdID product ID bit 9 Bit,0x06=6: OTP fuse value ProdID product ID bit 10..,0x07=7: OTP fuse value ProdID product ID bit 11"
|
|
newline
|
|
abitfld.long 0x00 0.--7. "FUSE_95,Bit" "0x00=0: OTP fuse value ManIDProtection..,0x01=1: OTP fuse value ManIDProtection..,0x02=2: OTP fuse value ManIDProtection..,0x03=3: OTP fuse value ManIDProtection..,0x04=4: OTP fuse value ProdID product ID bit 0 Bit,0x05=5: OTP fuse value ProdID product ID bit 1 Bit,0x06=6: OTP fuse value ProdID product ID bit 2 Bit,0x07=7: OTP fuse value ProdID product ID bit 3"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "RAP_SYSCTRL_OTP_CONFIG_9,Software Fuse Register"
|
|
abitfld.long 0x00 24.--31. "FUSE_88,Bit" "0x00=0: otp fuse values are used and the..,0x01=1: booting is stopped at secure booting..,0x02=2: OTP fuse value SecMode bit 2 CA9 secure..,0x03=3: OTP fuse value SecMode bit 3 Console..,0x04=4: OTP fuse value SecMode bit 4 No debug..,0x05=5: OTP fuse value SecMode bit 5 Only allow,0x06=6: OTP fuse value SecMode bit 6 reserved Bit,0x07=7: OTP fuse value SecMode bit 7 validate.."
|
|
newline
|
|
abitfld.long 0x00 16.--23. "FUSE_89,Bit" "0x00=0: default,0x01=1: ignore external boot mode pins and use..,0x02=2: OTP fuse value BootMode bit 2..,0x03=3: OTP fuse value BootMode bit 3..,0x04=4: OTP fuse value BootMode bit 4..,0x05=5: OTP fuse value BootModeProtection..,0x06=6: OTP fuse value BootModeProtection..,0x07=7: OTP fuse value BootModeProtection.."
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "FUSE_90,OTP fuse value ProdIDProtection protection for product ID"
|
|
newline
|
|
abitfld.long 0x00 0.--7. "FUSE_91,Bit" "0x00=0: OTP fuse value ProdID product ID bit 28..,0x01=1: OTP fuse value ProdID product ID bit 29..,0x02=2: OTP fuse value ProdID product ID bit 30..,0x03=3: OTP fuse value ProdID product ID bit 31..,0x04=4: OTP fuse value ProdIDProtection..,0x05=5: OTP fuse value ProdIDProtection..,0x06=6: OTP fuse value ProdIDProtection..,0x07=7: OTP fuse value ProdIDProtection.."
|
|
tree.end
|
|
tree "DDR_CTRL"
|
|
base ad:0xF8001000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL0,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "VERSION,Holds the controller version number"
|
|
bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DRAM_CLASS,Defines the class of DRAM memory which is connected to the controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "START,Initiate command processing in the controller" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL1,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE3,PADDING_BITS"
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "MAX_CS_REG,Holds the maximum number of chip selects available" "0,1"
|
|
bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "MAX_COL_REG,Holds the maximum width of column address in DRAMs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "MAX_ROW_REG,Holds the maximum width of memory address bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL2,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE1,PADDING_BITS"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TINIT,DRAM TINIT value in cycles"
|
|
repeat 3. (strings "3" "4" "5" )(list 0x0 0x4 0x8 )
|
|
rgroup.long ($2+0x0C)++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL$1,NA"
|
|
hexmask.long 0x00 0.--31. 1. "OBSOLETE0,PADDING_BITS"
|
|
repeat.end
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL6,NA"
|
|
hexmask.long 0x00 0.--31. 1. "TRST_PWRON,Duration of memory reset during power-on initialization"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL7,NA"
|
|
hexmask.long 0x00 0.--31. 1. "CKE_INACTIVE,Number of cycles after reset before CKE will be active"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL8,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
hexmask.long.word 0x00 8.--23. 1. "TCPD,DRAM TCPD value in cycles"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "INITAREF,Number of auto-refresh commands to execute during DRAM initialization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL9,NA"
|
|
bitfld.long 0x00 30.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "CASLAT_LIN,Sets latency from read command send to data receive from/to controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "NO_CMD_INIT,Disable DRAM commands until the TDLL parameter has expired during initialization" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "TDLL,DRAM TDLL value in cycles"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL10,NA"
|
|
bitfld.long 0x00 29.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. "TCCD,DRAM CAS-to-CAS value in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 19.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. "TBST_INT_INTERVAL,DRAM burst interrupt interval value in cycles" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. "ADDITIVE_LAT,DRAM additive latency value in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "WRLAT,DRAM WRLAT value in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL11,NA"
|
|
bitfld.long 0x00 30.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "TWTR,DRAM TWTR value in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "TRAS_MIN,DRAM TRAS_MIN value in cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRC,DRAM TRC value in cycles"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TRRD,DRAM TRRD value in cycles"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL12,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TMRD,DRAM TMRD value in cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TRTP,DRAM TRTP value in cycles"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "TFAW,DRAM TFAW value in cycles"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TRP,DRAM TRP value in cycles"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL13,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 8.--24. 1. "TRAS_MAX,DRAM TRAS_MAX value in cycles"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TMOD,Number of cycles after MRS command and before any other command"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL14,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TRCD,DRAM TRCD value in cycles"
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "WRITEINTERP,Allow controller to interrupt a write burst to the DRAMs with a read command" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TCKESR,Minimum CKE low pulse width during a self-refresh"
|
|
newline
|
|
bitfld.long 0x00 3.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. "TCKE,Minimum CKE pulse width" "0,1,2,3,4,5,6,7"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL15,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "CONCURRENTAP,IF the DRAM supports it this allows the controller to issue commands to other banks while a bank is in auto pre-charge" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "AP,Enable auto pre-charge mode of controller" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "OBSOLETE1,PADDING_BITS"
|
|
bitfld.long 0x00 6.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "TWR,DRAM TWR value in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL16,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TRP_AB,DRAM TRP all bank value in cycles"
|
|
bitfld.long 0x00 19.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "BSTLEN,Encoded burst length sent to DRAMs during initialization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TDAL,DRAM TDAL value in cycles"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "TRAS_LOCKOUT,IF the DRAM supports it this allows the controller to execute auto pre-charge commands before the TRAS_MIN parameter expires" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL17,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "RESERVED3,Reserved for future use" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "OPTIMAL_RMODW_EN,Enables optimized RMODW logic in the controller" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "OBSOLETE1,PADDING_BITS"
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "REG_DIMM_ENABLE,Enable registered DIMM operation of the controller" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL18,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE3,PADDING_BITS"
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "TREF_ENABLE,Issue auto-refresh commands to the DRAMs at the interval defined in the TREF parameter" "0,1"
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 8. "RESERVED1,Reserved for future use" "0,1"
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "AREFRESH,Initiate auto-refresh at the end of the current burst boundary" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL19,NA"
|
|
bitfld.long 0x00 30.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--29. 1. "TREF,DRAM TREF value in cycles"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "TRFC,DRAM TRFC value in cycles"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL20,NA"
|
|
hexmask.long 0x00 0.--31. 1. "OBSOLETE0,PADDING_BITS"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL21,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXPDLL,DRAM TXPDLL value in cycles"
|
|
hexmask.long.word 0x00 0.--15. 1. "TPDEX,DRAM TPDEX value in cycles"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL22,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXARDS,DRAM TXARDS value in cycles"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXARD,DRAM TXARD value in cycles"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL23,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXSNR,DRAM TXSNR value in cycles"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXSR,DRAM TXSR value in cycles"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL24,NA"
|
|
bitfld.long 0x00 27.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "CKE_DELAY,Additional cycles to delay CKE for status reporting" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "ENABLE_QUICK_SREFRESH,Allow user to interrupt memory initialization to enter self-refresh mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "SREFRESH_EXIT_NO_REFRESH,Disables the automatic refresh request associated with self-refresh exit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "PWRUP_SREFRESH_EXIT,Allow powerup via self-refresh instead of full memory initialization" "0,1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL25,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "LP_CMD,Low power software command request interface"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKSRX,Clock stable delay on self-refresh exit"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CKSRE,Clock hold delay on self-refresh entry"
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "LOWPOWER_REFRESH_ENABLE,Enable refreshes while in low power mode" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL26,NA"
|
|
bitfld.long 0x00 27.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "LP_AUTO_EXIT_EN,Enable auto exit from each of the low power states when a read or write command enters the command queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. "LP_AUTO_ENTRY_EN,Enable auto entry into each of the low power states when the associated idle timer expires" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "LP_ARB_STATE,Reports on the state of the arbiter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "LP_STATE,Low power state status parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL27,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "LP_AUTO_SR_IDLE,Number of long count sequences until the controller will place memory in self-refresh"
|
|
bitfld.long 0x00 20.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 8.--19. 1. "LP_AUTO_PD_IDLE,Defines the idle time until the controller will place memory in active power-down"
|
|
bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "LP_AUTO_MEM_GATE_EN,Enable memory clock gating when entering a low power state via the auto low power counters" "0,1,2,3"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL28,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
bitfld.long 0x00 15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "RESERVED1,Reserved for future use"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LP_AUTO_SR_MC_GATE_IDLE,Number of long count sequences until the controller will place memory in self-refresh with controller and memory clock gating"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL29,NA"
|
|
bitfld.long 0x00 27.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long 0x00 0.--26. 1. "WRITE_MODEREG,Write memory mode register data to the DRAMs"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL30,NA"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OBSOLETE1,PADDING_BITS"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MRW_STATUS,Write memory mode register status"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL31,NA"
|
|
hexmask.long 0x00 0.--31. 1. "OBSOLETE0,PADDING_BITS"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL32,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "MR1_DATA_0,Data to program into memory mode register 1 for chip select 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "MR0_DATA_0,Data to program into memory mode register 0 for chip select 0"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL33,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "MRSINGLE_DATA_0,Data to program into memory mode register single write to chip select 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "MR2_DATA_0,Data to program into memory mode register 2 for chip select 0"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL34,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "OBSOLETE1,PADDING_BITS"
|
|
hexmask.long.word 0x00 0.--15. 1. "MR3_DATA_0,Data to program into memory mode register 3 for chip select 0"
|
|
repeat 4. (strings "35" "36" "37" "38" )(list 0x0 0x4 0x8 0xC )
|
|
rgroup.long ($2+0x8C)++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL$1,NA"
|
|
hexmask.long 0x00 0.--31. 1. "OBSOLETE0,PADDING_BITS"
|
|
repeat.end
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL39,NA"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OBSOLETE1,PADDING_BITS"
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "FWC,Force a write check" "0,1"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL40,NA"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--27. 1. "XOR_CHECK_BITS,Value to xor with generated ECC codes for forced write check"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL41,NA"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OBSOLETE1,PADDING_BITS"
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "ECC_DISABLE_W_UC_ERR,Controls auto-corruption of ECC when un-correctable errors occur in R/M/W operations" "0,1"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL42,NA"
|
|
hexmask.long 0x00 0.--31. 1. "ECC_U_ADDR,Address of uncorrectable ECC event"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL43,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
bitfld.long 0x00 15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "ECC_U_SYND,Syndrome for uncorrectable ECC event"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OBSOLETE0,PADDING_BITS"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL44,NA"
|
|
hexmask.long 0x00 0.--31. 1. "ECC_U_DATA,Data associated with uncorrectable ECC event"
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL45,NA"
|
|
hexmask.long 0x00 0.--31. 1. "ECC_C_ADDR,Address of correctable ECC event"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL46,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
bitfld.long 0x00 15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "ECC_C_SYND,Syndrome for correctable ECC event"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OBSOLETE0,PADDING_BITS"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL47,NA"
|
|
hexmask.long 0x00 0.--31. 1. "ECC_C_DATA,Data associated with correctable ECC event"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL48,NA"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "ECC_C_ID,Source ID associated with correctable ECC event"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "ECC_U_ID,Source ID associated with the uncorrectable ECC event"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL49,NA"
|
|
bitfld.long 0x00 28.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--27. 1. "ZQCL,Number of cycles needed for a ZQCL command"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ZQINIT,Number of cycles needed for a ZQINIT command"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL50,NA"
|
|
bitfld.long 0x00 26.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 24.--25. "ZQ_ON_SREF_EXIT,Defines the type of ZQ calibration performed at self-refresh exit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--17. "ZQ_REQ,User request to initiate a ZQ calibration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ZQCS,Number of cycles needed for a ZQCS command"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL51,NA"
|
|
hexmask.long 0x00 0.--31. 1. "ZQ_INTERVAL,Number of long count sequences allowed between automatic ZQCS commands"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL52,NA"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OBSOLETE1,PADDING_BITS"
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "ZQ_IN_PROGRESS,Indicates that a ZQ command is currently running" "0,1"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL53,NA"
|
|
bitfld.long 0x00 28.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "COL_DIFF,Difference between number of column pins available and number being used" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. "ROW_DIFF,Difference between number of address pins available and number being used" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--9. "BANK_DIFF,Encoded number of banks on the DRAM(s)" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "OBSOLETE0,PADDING_BITS"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL54,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "ADDR_CMP_EN,Enable address collision detection as a rule for command queue placement" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "COMMAND_AGE_COUNT,Initial value of individual command aging counters for command aging"
|
|
hexmask.long.byte 0x00 8.--15. 1. "AGE_COUNT,Initial value of master aging-rate counter for command aging"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "APREBIT,Location of the auto pre-charge bit in the DRAM address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL55,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "RW_SAME_EN,Enable read/write grouping as a rule for command queue placement" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "PRIORITY_EN,Enable priority as a rule for command queue placement" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "PLACEMENT_EN,Enable placement logic for command queue" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "BANK_SPLIT_EN,Enable bank splitting as a rule for command queue placement" "0,1"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL56,NA"
|
|
bitfld.long 0x00 26.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 24.--25. "DISABLE_RW_GROUP_W_BNK_CONFLICT,Disables placement to read/write group when grouping creates a bank collision" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 8.--23. 1. "OBSOLETE1,PADDING_BITS"
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "RW_SAME_PAGE_EN,Enable page grouping when read/write grouping as a rule for command queue placement" "0,1"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL57,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "INHIBIT_DRAM_CMD,Inhibit read/write command traffic and associated bank commands" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "DISABLE_RD_INTERLEAVE,Disable read data interleaving for commands from the same port regardless of the requestor ID" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "SWAP_EN,Enable command swapping logic in execution unit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. "NUM_Q_ENTRIES_ACT_DISABLE,Number of queue entries in which ACT requests will be disabled" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL58,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE3,PADDING_BITS"
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "REDUC,Enable the half datapath feature of the controller" "0,1"
|
|
bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "BURST_ON_FLY_BIT,Identifies the burst-on-fly bit in the memory mode registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OBSOLETE0,PADDING_BITS"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL59,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "CTRLUPD_REQ,Assert the DFI controller-initiated update request signal dfi_ctrlupd_req" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "CONTROLLER_BUSY,Indicator that the controller is processing a command" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "IN_ORDER_ACCEPT,Forces the controller to accept commands in the order in which they are placed in the command queue" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. "Q_FULLNESS,Quantity that determines command queue full" "0,1,2,3,4,5,6,7"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL60,NA"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OBSOLETE1,PADDING_BITS"
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "CTRLUPD_REQ_PER_AREF_EN,Enable an automatic controller-initiated update (dfi_ctrlupd_req) after every refresh" "0,1"
|
|
repeat 3. (strings "61" "62" "63" )(list 0x0 0x4 0x8 )
|
|
rgroup.long ($2+0xF4)++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL$1,NA"
|
|
hexmask.long 0x00 0.--31. 1. "OBSOLETE0,PADDING_BITS"
|
|
repeat.end
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL64,NA"
|
|
hexmask.long 0x00 0.--31. 1. "OUT_OF_RANGE_ADDR,Address of command that caused an out-of-range interrupt"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL65,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE3,PADDING_BITS"
|
|
bitfld.long 0x00 23. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "OUT_OF_RANGE_TYPE,Type of command that caused an out-of-range interrupt"
|
|
hexmask.long.byte 0x00 8.--15. 1. "OUT_OF_RANGE_LENGTH,Length of command that caused an out-of-range interrupt"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "OBSOLETE0,PADDING_BITS"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL66,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "OBSOLETE1,PADDING_BITS"
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "OUT_OF_RANGE_SOURCE_ID,Source ID of command that caused an out-of-range interrupt"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL67,NA"
|
|
hexmask.long 0x00 0.--31. 1. "PORT_CMD_ERROR_ADDR,Address of command that caused the PORT command error"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL68,NA"
|
|
bitfld.long 0x00 26.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 24.--25. "PORT_CMD_ERROR_TYPE,Type of error and access type that caused the PORT command error" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 19.--23. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 8.--18. 1. "PORT_CMD_ERROR_ID,Source ID of command that caused the PORT command error"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "OBSOLETE0,PADDING_BITS"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL69,NA"
|
|
hexmask.long 0x00 0.--31. 1. "OBSOLETE0,PADDING_BITS"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL70,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "ODT_EN,Enable support of DRAM ODT" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "OBSOLETE2,PADDING_BITS"
|
|
bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TODTH_WR,Defines the DRAM minimum ODT high time after an ODT assertion for a write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TODTL_2CMD,Defines the DRAM delay from an ODT de-assertion to the next non-write non-read command"
|
|
repeat 2. (strings "71" "72" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x11C)++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL$1,NA"
|
|
hexmask.long 0x00 0.--31. 1. "OBSOLETE0,PADDING_BITS"
|
|
repeat.end
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL73,NA"
|
|
bitfld.long 0x00 29.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. "W2W_SAMECS_DLY,Additional delay to insert between two writes to the same chip select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. "W2R_SAMECS_DLY,Additional delay to insert between writes and reads to the same chip select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. "R2W_SAMECS_DLY,Additional delay to insert between reads and writes to the same chip select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "R2R_SAMECS_DLY,Additional delay to insert between two reads to the same chip select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL74,NA"
|
|
bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. "OCD_ADJUST_PUP_CS_0,OCD pull-up adjust setting for DRAMs for chip select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 21.--23. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. "OCD_ADJUST_PDN_CS_0,OCD pull-down adjust setting for DRAMs for chip select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "OBSOLETE0,PADDING_BITS"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL75,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "SWLVL_EXIT,User request to exit software leveling" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "SWLVL_START,User request to initiate software leveling of type in the SW_LEVELING_MODE parameter" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "SWLVL_LOAD,User request to load delays and execute software leveling" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. "SW_LEVELING_MODE,Defines the leveling operation for software leveling" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL76,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SWLVL_RESP_0,Leveling response for data slice 0"
|
|
bitfld.long 0x00 20.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LVL_STATUS,Status of write level data eye training and gate training requests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "OBSOLETE1,PADDING_BITS"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "SWLVL_OP_DONE,Signals that software leveling is currently in progress" "0,1"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL77,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SWLVL_RESP_4,Leveling response for data slice 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SWLVL_RESP_3,Leveling response for data slice 3"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "SWLVL_RESP_2,Leveling response for data slice 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SWLVL_RESP_1,Leveling response for data slice 1"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL78,NA"
|
|
bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "WLMRD,Delay from issuing MRS to first write leveling strobe" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "WLDQSEN,Delay from issuing MRS to first DQS strobe for write leveling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "WRLVL_CS,Specifies the target chip select for the write leveling operation initiated through the WRLVL_REQ parameter" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "WRLVL_REQ,User request to initiate write leveling" "0,1"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL79,NA"
|
|
bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. "RESERVED2,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 8.--23. 1. "WRLVL_INTERVAL,Number of long count sequences counted between automatic write leveling commands"
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "WRLVL_EN,Enable the MC write leveling module" "0,1"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL80,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "WRLVL_REG_EN,Enable the dfi_wrlvl_delay_X signals to be programmed when hardware and software leveling are disabled" "0,1"
|
|
bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "WRLVL_ERROR_STATUS,Holds the error associated with the write level error interrupt"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL81,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "WRLVL_DELAY_1,Number of delay elements for write data slice 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "WRLVL_DELAY_0,Number of delay elements for write data slice 0"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL82,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "WRLVL_DELAY_3,Number of delay elements for write data slice 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "WRLVL_DELAY_2,Number of delay elements for write data slice 2"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL83,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "RDLVL_GATE_REQ,User request to initiate gate training" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "RDLVL_REQ,User request to initiate data eye training" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WRLVL_DELAY_4,Number of delay elements for write data slice 4"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL84,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "RDLVL_REG_EN,Enable the dfi_rdlvl_delay_X signals to be programmed when hardware and software leveling are disabled" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "RDLVL_BEGIN_DELAY_EN,Enable the data eye training logic to find the DQ data eye" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "RDLVL_EDGE,Specifies the read DQS edge positive or negative to be used for the data eye training operation" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "RDLVL_CS,Specifies the target chip select for the data eye training operation initiated through the RDLVL_REQ parameter or the gate training operation initiated through the RDLVL_GATE_REQ parameter" "0,1"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL85,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
hexmask.long.word 0x00 8.--23. 1. "RDLVL_BEGIN_DELAY_0,Number of delay elements for first 1 to 0 DQ transition for data slice 0"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "RDLVL_GATE_REG_EN,Enable the dfi_rdlvl_gate_delay_X signals to be programmed when hardware and software leveling are disabled" "0,1"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL86,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDLVL_MIDPOINT_DELAY_0,Calculated midpoint of DQ delay for data slice 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_END_DELAY_0,Number of delay elements for first 0 to 1 DQ transition for data slice 0"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL87,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "RDLVL_OFFSET_DIR,Direction of the data eye midpoint delay offset for data slice 0" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_OFFSET_DELAY_0,Offset the data eye midpoint delay for data slice 0"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL88,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDLVL_GATE_DELAY_0,Number of delay elements where gate is aligned to rising edge of DQS for data slice 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_DELAY_0,Number of delay elements where read DQS is placed within the DQ data eye for data slice 0"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL89,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDLVL_END_DELAY_1,Number of delay elements for first 0 to 1 DQ transition for data slice 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_BEGIN_DELAY_1,Number of delay elements for first 1 to 0 DQ transition for data slice 1"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL90,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDLVL_OFFSET_DELAY_1,Offset the data eye midpoint delay for data slice 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_MIDPOINT_DELAY_1,Calculated midpoint of DQ delay for data slice 1"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL91,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
hexmask.long.word 0x00 8.--23. 1. "RDLVL_DELAY_1,Number of delay elements where read DQS is placed within the DQ data eye for data slice 1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "RDLVL_OFFSET_DIR,Direction of the data eye midpoint delay offset for data slice 1" "0,1"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL92,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDLVL_BEGIN_DELAY_2,Number of delay elements for first 1 to 0 DQ transition for data slice 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_GATE_DELAY_1,Number of delay elements where gate is aligned to rising edge of DQS for data slice 1"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL93,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDLVL_MIDPOINT_DELAY_2,Calculated midpoint of DQ delay for data slice 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_END_DELAY_2,Number of delay elements for first 0 to 1 DQ transition for data slice 2"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL94,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "RDLVL_OFFSET_DIR,Direction of the data eye midpoint delay offset for data slice 2" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_OFFSET_DELAY_2,Offset the data eye midpoint delay for data slice 2"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL95,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDLVL_GATE_DELAY_2,Number of delay elements where gate is aligned to rising edge of DQS for data slice 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_DELAY_2,Number of delay elements where read DQS is placed within the DQ data eye for data slice 2"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL96,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDLVL_END_DELAY_3,Number of delay elements for first 0 to 1 DQ transition for data slice 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_BEGIN_DELAY_3,Number of delay elements for first 1 to 0 DQ transition for data slice 3"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL97,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDLVL_OFFSET_DELAY_3,Offset the data eye midpoint delay for data slice 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_MIDPOINT_DELAY_3,Calculated midpoint of DQ delay for data slice 3"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL98,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
hexmask.long.word 0x00 8.--23. 1. "RDLVL_DELAY_3,Number of delay elements where read DQS is placed within the DQ data eye for data slice 3"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "RDLVL_OFFSET_DIR,Direction of the data eye midpoint delay offset for data slice 3" "0,1"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL99,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDLVL_BEGIN_DELAY_4,Number of delay elements for first 1 to 0 DQ transition for data slice 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_GATE_DELAY_3,Number of delay elements where gate is aligned to rising edge of DQS for data slice 3"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL100,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDLVL_MIDPOINT_DELAY_4,Calculated midpoint of DQ delay for data slice 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_END_DELAY_4,Number of delay elements for first 0 to 1 DQ transition for data slice 4"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL101,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "RDLVL_OFFSET_DIR,Direction of the data eye midpoint delay offset for data slice 4" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_OFFSET_DELAY_4,Offset the data eye midpoint delay for data slice 4"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL102,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDLVL_GATE_DELAY_4,Number of delay elements where gate is aligned to rising edge of DQS for data slice 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_DELAY_4,Number of delay elements where read DQS is placed within the DQ data eye for data slice 4"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL103,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "AXI1_ALL_STROBES_USED_ENABLE,Enables use of the AWALLSTRB signal for AXI port 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 16.--17. "AXI0_W_PRIORITY,Priority of write commands from AXI port 0" "0,1,2,3"
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|
newline
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bitfld.long 0x00 10.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 8.--9. "AXI0_R_PRIORITY,Priority of read commands from AXI port 0" "0,1,2,3"
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|
newline
|
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hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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|
bitfld.long 0x00 0. "AXI0_ALL_STROBES_USED_ENABLE,Enables use of the AWALLSTRB signal for AXI port 0" "0,1"
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|
group.long 0x1A0++0x03
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|
line.long 0x00 "DDR_CTRL_CTL104,NA"
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|
bitfld.long 0x00 26.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 24.--25. "AXI2_R_PRIORITY,Priority of read commands from AXI port 2" "0,1,2,3"
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|
newline
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hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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|
bitfld.long 0x00 16. "AXI2_ALL_STROBES_USED_ENABLE,Enables use of the AWALLSTRB signal for AXI port 2" "0,1"
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newline
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bitfld.long 0x00 10.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--9. "AXI1_W_PRIORITY,Priority of write commands from AXI port 1" "0,1,2,3"
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|
newline
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bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 0.--1. "AXI1_R_PRIORITY,Priority of read commands from AXI port 1" "0,1,2,3"
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|
group.long 0x1A4++0x03
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|
line.long 0x00 "DDR_CTRL_CTL105,NA"
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|
bitfld.long 0x00 26.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 24.--25. "AXI3_W_PRIORITY,Priority of write commands from AXI port 3" "0,1,2,3"
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newline
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 16.--17. "AXI3_R_PRIORITY,Priority of read commands from AXI port 3" "0,1,2,3"
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newline
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hexmask.long.byte 0x00 9.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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|
bitfld.long 0x00 8. "AXI3_ALL_STROBES_USED_ENABLE,Enables use of the AWALLSTRB signal for AXI port 3" "0,1"
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newline
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bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--1. "AXI2_W_PRIORITY,Priority of write commands from AXI port 2" "0,1,2,3"
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|
group.long 0x1A8++0x03
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|
line.long 0x00 "DDR_CTRL_CTL106,NA"
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|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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|
bitfld.long 0x00 24. "WEIGHTED_ROUND_ROBIN_LATENCY_CONTROL,Free-running or limited WRR latency counters" "0,1"
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newline
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--17. "AXI4_W_PRIORITY,Priority of write commands from AXI port 4" "0,1,2,3"
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|
newline
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bitfld.long 0x00 10.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 8.--9. "AXI4_R_PRIORITY,Priority of read commands from AXI port 4" "0,1,2,3"
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newline
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hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 0. "AXI4_ALL_STROBES_USED_ENABLE,Enables use of the AWALLSTRB signal for AXI port 4" "0,1"
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|
group.long 0x1AC++0x03
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|
line.long 0x00 "DDR_CTRL_CTL107,NA"
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bitfld.long 0x00 28.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "AXI0_PRIORITY1_RELATIVE_PRIORITY,Relative priority of priority 1 commands from port 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x00 20.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 16.--19. "AXI0_PRIORITY0_RELATIVE_PRIORITY,Relative priority of priority 0 commands from port 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. "WRR_PARAM_VALUE_ERR,Errors/warnings related to the WRR parameters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--1. "WEIGHTED_ROUND_ROBIN_WEIGHT_SHARING,Per-port pair shared arbitration for WRR" "0,1,2,3"
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|
group.long 0x1B0++0x03
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|
line.long 0x00 "DDR_CTRL_CTL108,NA"
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|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE3,PADDING_BITS"
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bitfld.long 0x00 19.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 16.--18. "AXI0_PORT_ORDERING,Reassigned port order for port 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 8.--11. "AXI0_PRIORITY3_RELATIVE_PRIORITY,Relative priority of priority 3 commands from port 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x00 0.--3. "AXI0_PRIORITY2_RELATIVE_PRIORITY,Relative priority of priority 2 commands from port 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x1B4++0x03
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|
line.long 0x00 "DDR_CTRL_CTL109,NA"
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|
bitfld.long 0x00 28.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "AXI1_PRIORITY1_RELATIVE_PRIORITY,Relative priority of priority 1 commands from port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x00 20.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "AXI1_PRIORITY0_RELATIVE_PRIORITY,Relative priority of priority 0 commands from port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x00 10.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--9. 1. "AXI0_PRIORITY_RELAX,Counter value to trigger priority relax on port 0"
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|
group.long 0x1B8++0x03
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|
line.long 0x00 "DDR_CTRL_CTL110,NA"
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|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE3,PADDING_BITS"
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|
bitfld.long 0x00 19.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
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bitfld.long 0x00 16.--18. "AXI1_PORT_ORDERING,Reassigned port order for port 1" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 8.--11. "AXI1_PRIORITY3_RELATIVE_PRIORITY,Relative priority of priority 3 commands from port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x00 0.--3. "AXI1_PRIORITY2_RELATIVE_PRIORITY,Relative priority of priority 2 commands from port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x1BC++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL111,NA"
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|
bitfld.long 0x00 28.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 24.--27. "AXI2_PRIORITY1_RELATIVE_PRIORITY,Relative priority of priority 1 commands from port 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 20.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 16.--19. "AXI2_PRIORITY0_RELATIVE_PRIORITY,Relative priority of priority 0 commands from port 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 10.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
hexmask.long.word 0x00 0.--9. 1. "AXI1_PRIORITY_RELAX,Counter value to trigger priority relax on port 1"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL112,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE3,PADDING_BITS"
|
|
bitfld.long 0x00 19.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
|
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bitfld.long 0x00 16.--18. "AXI2_PORT_ORDERING,Reassigned port order for port 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 8.--11. "AXI2_PRIORITY3_RELATIVE_PRIORITY,Relative priority of priority 3 commands from port 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 0.--3. "AXI2_PRIORITY2_RELATIVE_PRIORITY,Relative priority of priority 2 commands from port 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL113,NA"
|
|
bitfld.long 0x00 28.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AXI3_PRIORITY1_RELATIVE_PRIORITY,Relative priority of priority 1 commands from port 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AXI3_PRIORITY0_RELATIVE_PRIORITY,Relative priority of priority 0 commands from port 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "AXI2_PRIORITY_RELAX,Counter value to trigger priority relax on port 2"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL114,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE3,PADDING_BITS"
|
|
bitfld.long 0x00 19.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "AXI3_PORT_ORDERING,Reassigned port order for port 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "AXI3_PRIORITY3_RELATIVE_PRIORITY,Relative priority of priority 3 commands from port 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "AXI3_PRIORITY2_RELATIVE_PRIORITY,Relative priority of priority 2 commands from port 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL115,NA"
|
|
bitfld.long 0x00 28.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AXI4_PRIORITY1_RELATIVE_PRIORITY,Relative priority of priority 1 commands from port 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AXI4_PRIORITY0_RELATIVE_PRIORITY,Relative priority of priority 0 commands from port 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "AXI3_PRIORITY_RELAX,Counter value to trigger priority relax on port 3"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL116,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE3,PADDING_BITS"
|
|
bitfld.long 0x00 19.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "AXI4_PORT_ORDERING,Reassigned port order for port 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "AXI4_PRIORITY3_RELATIVE_PRIORITY,Relative priority of priority 3 commands from port 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "AXI4_PRIORITY2_RELATIVE_PRIORITY,Relative priority of priority 2 commands from port 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL117,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "MEM_RST_VALID,Register access to mem_rst_valid signal" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "CKE_STATUS,Register access to cke_status signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "AXI4_PRIORITY_RELAX,Counter value to trigger priority relax on port 4"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL118,NA"
|
|
bitfld.long 0x00 30.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "TDFI_PHY_WRLAT,Holds the calculated DFI tPHY_WRLAT timing parameter (in DFI PHY clocks) the maximum cycles between a write command and a dfi_wrdata_en assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "DLL_RST_ADJ_DLY,Minimum cycles after setting master delay in DLL until the DLL reset signal dll_rst_n may be asserted"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLL_RST_DELAY,Minimum cycles required for DLL reset signal dll_rst_n to be held"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL119,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "DRAM_CLK_DISABLE,Set value for the dfi_dram_clk_disable signal" "0,1"
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newline
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bitfld.long 0x00 22.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "TDFI_RDDATA_EN,Holds the calculated DFI tRDDATA_EN timing parameter (in DFI PHY clocks) the maximum cycles between a read command and a dfi_rddata_en assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
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bitfld.long 0x00 14.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "TDFI_PHY_RDLAT,Defines the DFI tPHY_RDLAT timing parameter (in DFI PHY clocks) the maximum cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "UPDATE_ERROR_STATUS,Identifies the source of any DFI MC-initiated or PHY-initiated update errors"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL120,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
bitfld.long 0x00 22.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 8.--21. 1. "TDFI_CTRLUPD_MAX,Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks) the maximum cycles that dfi_ctrlupd_req can be asserted"
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bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
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bitfld.long 0x00 0.--3. "TDFI_CTRLUPD_MIN,Reports the DFI tCTRLUPD_MIN timing parameter (in DFI clocks) the minimum cycles that dfi_ctrlupd_req must be asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL121,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "TDFI_PHYUPD_TYPE1,Defines the DFI tPHYUPD_TYPE1 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "TDFI_PHYUPD_TYPE0,Defines the DFI tPHYUPD_TYPE0 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 0"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL122,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "TDFI_PHYUPD_TYPE3,Defines the DFI tPHYUPD_TYPE3 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "TDFI_PHYUPD_TYPE2,Defines the DFI tPHYUPD_TYPE2 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 2"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL123,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "OBSOLETE1,PADDING_BITS"
|
|
bitfld.long 0x00 14.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--13. 1. "TDFI_PHYUPD_RESP,Defines the DFI tPHYUPD_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_phyupd_req assertion and a dfi_phyupd_ack assertion"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL124,NA"
|
|
hexmask.long 0x00 0.--31. 1. "TDFI_CTRLUPD_INTERVAL,Defines the DFI tCTRLUPD_INTERVAL timing parameter (in DFI clocks) the maximum cycles between dfi_ctrlupd_req assertions"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL125,NA"
|
|
bitfld.long 0x00 28.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "TDFI_DRAM_CLK_DISABLE,Defines the DFI tDRAM_CLK_DISABLE timing parameter (in DFI clocks) the delay between a dfi_dram_clock_disable assertion and the memory clock disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 20.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 16.--19. "TDFI_CTRL_DELAY,Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks) the delay between a DFI command change and a memory command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 14.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "WRLAT_ADJ,Adjustment value for PHY write timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
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bitfld.long 0x00 6.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RDLAT_ADJ,Adjustment value for PHY read timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL126,NA"
|
|
bitfld.long 0x00 26.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "TDFI_WRLVL_WW,Defines the DFI tWRLVL_WW timing parameter (in DFI clocks) the minimum cycles between dfi_wrlvl_strobe assertions"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "TDFI_WRLVL_EN,Defines the DFI tWRLVL_EN timing parameter (in DFI clocks) the minimum cycles from a dfi_wrlvl_en assertion to the first dfi_wrlvl_strobe assertion"
|
|
bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 0.--3. "TDFI_DRAM_CLK_ENABLE,Defines the DFI tDRAM_CLK_ENABLE timing parameter (in DFI clocks) the delay between a dfi_dram_clk_disable de-assertion and the memory clock enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL127,NA"
|
|
hexmask.long 0x00 0.--31. 1. "TDFI_WRLVL_RESP,Defines the DFI tWRLVL_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_wrlvl_req assertion and a dfi_wrlvl_en assertion"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL128,NA"
|
|
hexmask.long 0x00 0.--31. 1. "TDFI_WRLVL_MAX,Defines the DFI tWRLVL_MAX timing parameter (in DFI clocks) the maximum cycles between a dfi_wrlvl_en assertion and a valid dfi_wrlvl_resp"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL129,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TDFI_WRLVL_RESPLAT,Defines the DFI tWRLVL_RESPLAT timing parameter (in DFI clocks) the number of cycles between a dfi_wrlvl_strobe assertion and a valid dfi_wrlvl_resp"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TDFI_WRLVL_DLL,Defines the DFI tWRLVL_DLL timing parameter (in DFI clocks) the minimum cycles between a dfi_wrlvl_load assertion and a dfi_wrlvl_strobe assertion"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DFI_WRLVL_MAX_DELAY,Maximum number of elements for the write level delay line"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL130,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TDFI_RDLVL_LOAD,Defines the DFI tRDLVL_LOAD timing parameter (in DFI clocks) the minimum cycles between dfi_rdlvl_delay_X or dfi_rdlvl_gate_delay_X programming and a dfi_rdlvl_load assertion"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TDFI_RDLVL_DLL,Defines the DFI tRDLVL_DLL timing parameter (in DFI clocks) the minimum cycles between a dfi_rdlvl_load assertion and a read or mode register"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "TDFI_RDLVL_EN,Defines the DFI tRDLVL_EN timing parameter (in DFI clocks) the minimum cycles from a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion to the first read or MRR"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TDFI_WRLVL_LOAD,Defines the DFI tWRLVL_LOAD timing parameter (in DFI clocks) the minimum cycles between dfi_wrlvl_delay_X programming and a dfi_wrlvl_load assertion"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL131,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
hexmask.long.word 0x00 8.--23. 1. "RDLVL_MAX_DELAY,Maximum number of elements for the data eye training delay line"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TDFI_RDLVL_RESPLAT,Defines the DFI tRDLVL_RESPLAT timing parameter (in DFI clocks) the maximum cycles between a read or mode register read and a valid dfi_rdlvl_resp"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL132,NA"
|
|
bitfld.long 0x00 26.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "TDFI_RDLVL_RR,Defines the DFI tRDLVL_RR timing parameter (in DFI clocks) the minimum cycles between read commands"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_GATE_MAX_DELAY,Maximum number of elements for the gate delay"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL133,NA"
|
|
hexmask.long 0x00 0.--31. 1. "TDFI_RDLVL_RESP,Defines the DFI tRDLVL_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_rdlvl_req or dfi_rdlvl_gate_req assertion and a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL134,NA"
|
|
hexmask.long 0x00 0.--31. 1. "RDLVL_RESP_MASK,Mask for the dfi_rdlvl_resp signal during data eye training"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL135,NA"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OBSOLETE1,PADDING_BITS"
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "RDLVL_RESP_MASK,Mask for the dfi_rdlvl_resp signal during data eye training"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL136,NA"
|
|
hexmask.long 0x00 0.--31. 1. "RDLVL_GATE_RESP_MASK,Mask for the dfi_rdlvl_resp signal during gate training"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL137,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "RDLVL_GATE_PREAMBLE_CHECK_EN,Enable the preamble check sequence during gate training" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "RDLVL_GATE_EN,Enable the MC gate training module" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "RDLVL_EN,Enable the MC data eye training module" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RDLVL_GATE_RESP_MASK,Mask for the dfi_rdlvl_resp signal during gate training"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL138,NA"
|
|
hexmask.long 0x00 0.--31. 1. "TDFI_RDLVL_MAX,Defines the DFI tRDLVL_MAX timing parameter (in DFI clocks) the maximum cycles between a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion and a valid dfi_rdlvl_resp"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL139,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "OBSOLETE2,PADDING_BITS"
|
|
bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RDLVL_GATE_DQ_0_COUNT,Number of consecutive 0s that defines a 1 to 0 transition for gate training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "RDLVL_DQ_0_COUNT,Number of consecutive 0s that defines a 1 to 0 transition for data eye training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x230++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL140,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OBSOLETE1,PADDING_BITS"
|
|
bitfld.long 0x00 22.--23. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "RDLVL_ERROR_STATUS,Holds the error associated with the data eye training error or gate training error interrupt"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL141,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDLVL_GATE_INTERVAL,Number of long count sequences counted between automatic gate training commands"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVL_INTERVAL,Number of long count sequences counted between automatic data eye training commands"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL142,NA"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OBSOLETE1,PADDING_BITS"
|
|
bitfld.long 0x00 3.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "TDFI_PHY_WRDATA,Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks) the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x23C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL143,NA"
|
|
hexmask.long 0x00 0.--31. 1. "OBSOLETE0,PADDING_BITS"
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL144,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WRITE_DATA_FIFO_PTR_WIDTH,Reports the width of the controller core write data latency queue pointer"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WRITE_DATA_FIFO_DEPTH,Reports the depth of the controller core write data latency queue"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "READ_DATA_FIFO_PTR_WIDTH,Reports the width of the controller core read data queue pointer"
|
|
hexmask.long.byte 0x00 0.--7. 1. "READ_DATA_FIFO_DEPTH,Reports the depth of the controller core read data queue"
|
|
rgroup.long 0x244++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL145,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "AXI0_CMDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 0 command FIFO"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ASYNC_CDC_STAGES,Reports the number of synchronizer delays specified for the asynchronous boundary crossings"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MEMCD_RMODW_FIFO_PTR_WIDTH,Reports the width of the controller core read/modify/write FIFO pointer"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MEMCD_RMODW_FIFO_DEPTH,Reports the depth of the controller core read/modify/write FIFO"
|
|
rgroup.long 0x248++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL146,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "AXI1_CMDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 1 command FIFO"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH,Reports the depth of the AXI port 0 write command processing FIFO"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AXI0_WRFIFO_LOG2_DEPTH,Reports the depth of the AXI port 0 write data FIFO"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AXI0_RDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 0 read data FIFO"
|
|
rgroup.long 0x24C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL147,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "AXI2_CMDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 2 command FIFO"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AXI1_WRCMD_PROC_FIFO_LOG2_DEPTH,Reports the depth of the AXI port 1 write command processing FIFO"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AXI1_WRFIFO_LOG2_DEPTH,Reports the depth of the AXI port 1 write data FIFO"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AXI1_RDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 1 read data FIFO"
|
|
rgroup.long 0x250++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL148,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "AXI3_CMDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 3 command FIFO"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AXI2_WRCMD_PROC_FIFO_LOG2_DEPTH,Reports the depth of the AXI port 2 write command processing FIFO"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AXI2_WRFIFO_LOG2_DEPTH,Reports the depth of the AXI port 2 write data FIFO"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AXI2_RDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 2 read data FIFO"
|
|
rgroup.long 0x254++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL149,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "AXI4_CMDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 4 command FIFO"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AXI3_WRCMD_PROC_FIFO_LOG2_DEPTH,Reports the depth of the AXI port 3 write command processing FIFO"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AXI3_WRFIFO_LOG2_DEPTH,Reports the depth of the AXI port 3 write data FIFO"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AXI3_RDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 3 read data FIFO"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL150,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "RESERVED3,Reserved for future use" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "AXI4_WRCMD_PROC_FIFO_LOG2_DEPTH,Reports the depth of the AXI port 4 write command processing FIFO"
|
|
hexmask.long.byte 0x00 8.--15. 1. "AXI4_WRFIFO_LOG2_DEPTH,Reports the depth of the AXI port 4 write data FIFO"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "AXI4_RDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 4 read data FIFO"
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL151,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "AXI4_TRANS_WRFIFO_LOG2_DEPTH,Reports the depth of the AXI port 4 transition write data FIFO"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AXI3_TRANS_WRFIFO_LOG2_DEPTH,Reports the depth of the AXI port 3 transition write data FIFO"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AXI2_TRANS_WRFIFO_LOG2_DEPTH,Reports the depth of the AXI port 2 transition write data FIFO"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AXI1_TRANS_WRFIFO_LOG2_DEPTH,Reports the depth of the AXI port 1 transition write data FIFO"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL152,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "ECC_SCRUB_IN_PROGRESS,When set indicates controller is in the process of performing scrubbing operations" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "ECC_SCRUB_START,ECC scrubbing control" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "ECC_WRITEBACK_EN,ECC writeback will occur on detection of single bit errors for reads" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "ECC_EN,ECC error checking and correcting control" "0,1"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL153,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "ECC_SCRUB_INTERVAL,The minimum interval between two ECC scrubbing commands in number of controller clock cycles"
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 8. "ECC_SCRUB_MODE,Clear to 0 ECC scrubbing opeartions will be performed at regular intervals as dictated by ECC_SCRUB_INTERVAL" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ECC_SCRUB_LEN,Length of ECC scrubbing read command that the controller will issue"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL154,NA"
|
|
hexmask.long.word 0x00 16.--31. 1. "OBSOLETE1,PADDING_BITS"
|
|
hexmask.long.word 0x00 0.--15. 1. "ECC_SCRUB_IDLE_CNT,The number of controller clock cycles that the scrubbing engine will wait in controller idle state before starting scrubbing operations"
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL155,NA"
|
|
hexmask.long 0x00 0.--31. 1. "ECC_SCRUB_START_ADDR,The starting address from where scrubbing operations will begin"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL156,NA"
|
|
hexmask.long 0x00 0.--31. 1. "ECC_SCRUB_END_ADDR,The end address where scrubbing operations will wrap around to the start address"
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL157,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "RESERVED3,Reserved for future use" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "BANK_ADDR_INTLV_EN,Enables the capability to interleave the bank address within the row address bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. "BANK_START_BIT,Defines the LSbit of the bank address within the page of the user address when the BANK_ADDR_INTLV_EN parameter is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "LONG_COUNT_MASK,Reduces the length of the long counter from 1024 cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x278++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL158,NA"
|
|
bitfld.long 0x00 26.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long 0x00 0.--25. 1. "INT_STATUS,Status of interrupt features in the controller"
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL159,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long 0x00 0.--24. 1. "INT_ACK,Clear mask of the INT_STATUS parameter"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL160,NA"
|
|
bitfld.long 0x00 26.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long 0x00 0.--25. 1. "INT_MASK,Mask for the controller_int signal from the INT_STATUS parameter"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL161,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "AXI2_FIXED_PORT_PRIORITY_ENABLE,Defines the priority control for AXI port 2 as per-port or per-command" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "AXI1_FIXED_PORT_PRIORITY_ENABLE,Defines the priority control for AXI port 1 as per-port or per-command" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "AXI0_FIXED_PORT_PRIORITY_ENABLE,Defines the priority control for AXI port 0 as per-port or per-command" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "WR_TO_ODTH,Defines the delay from a write command to ODT assertion"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "DDR_CTRL_CTL162,NA"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "AXI4_FIXED_PORT_PRIORITY_ENABLE,Defines the priority control for AXI port 4 as per-port or per-command" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "AXI3_FIXED_PORT_PRIORITY_ENABLE,Defines the priority control for AXI port 3 as per-port or per-command" "0,1"
|
|
tree.end
|
|
tree "DDR_PHY"
|
|
base ad:0xF8002000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DDR_PHY_FUNCCTRL,Function control register"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8.--9. "IFSEL,Voltage setting of I/F" "0: DVDDQ 1.8V,1: DVDDQ 1.5V 2'B10,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "FUNCRSTB,Reset setting in functional block" "0: Reset state,1: State of operation"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DDR_PHY_DLLCTRL,MDLL Control Register (The access interval to this register needs to be more than 10 PCLK.)"
|
|
bitfld.long 0x00 26.--31. "Reserved4,Bit" "0: DLLCTRL bit2 Bit,1: DLLCTRL bit3 Bit,2: DLLCTRL bit0 Bit,3: DLLCTRL bit1 Bit,4: DLLCTRL bit2 Bit,5: DLLCTRL bit3,?..."
|
|
bitfld.long 0x00 25. "MDLLOCK,Lock signal of Mater DLL" "0: unclok,1: lock"
|
|
newline
|
|
bitfld.long 0x00 24. "MSATFG,Master DLL Saturation Flag State of" "0: No Saturate (Delay Line control within the,1: Saturate (Maximum/Minimum control of Delay.."
|
|
bitfld.long 0x00 23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "MDACNTM,Write of control code of Master DLL" "0,1"
|
|
bitfld.long 0x00 21. "SDLYCTRL,Control selection of Slave DLL" "0: Controlled by Mastar DLL (default),1: Controlled by MDACNT"
|
|
newline
|
|
bitfld.long 0x00 20. "DACNTUPD,Update of control code of Slave Delay In case of SDLYCTRL = '1' the value of MDACNT is reflected in Slave Delay" "0,1"
|
|
bitfld.long 0x00 18.--19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 8.--17. 1. "MDACNT,Master DLL code monitor signal"
|
|
bitfld.long 0x00 6.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "HSLMODE,High-speed Lock Up mode setting" "0: Detailed Lock Up mode (default),1: High-speed Lock Up mode"
|
|
bitfld.long 0x00 4. "MSATMODE,Saturate mode setting" "0: OFF (self-reset mode),1: ON (Saturate mode: The delay control value.."
|
|
newline
|
|
bitfld.long 0x00 3. "DDMODE,Double Delay mode setting" "0: Normal mode,1: Double Delay Mode (SRCLK/HRCLK"
|
|
bitfld.long 0x00 1.--2. "MFSL,SRCLK/HRCLK frequency band setting" "0: 640MHz < frequency <= 800MHz (default) It is,1: 533MHz < frequency <= 650MHz,2: 450MHz < frequency <= 540MHz,3: 400MHz <= frequency <= 460MHz"
|
|
newline
|
|
bitfld.long 0x00 0. "MDLLSTBY,Master DLLSTBY setting After the frequency of SRCLK/HRCLK is changed it is necessary to execute reset" "0: Operation usually,1: Reset (default)"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DDR_PHY_ZQCALCTRL,ZQ calibration control register"
|
|
bitfld.long 0x00 31. "ZQCALRUN,Signal that indicates the state of ZQ calibration" "0: (default) State of stop,1: The calibration is being executed"
|
|
bitfld.long 0x00 30. "ZQCALEND,Signal that indicates the state of ZQ calibration end" "0: Calibration unfinished (default),1: Calibration end"
|
|
newline
|
|
bitfld.long 0x00 29. "ZQCALGAP,Signal that indicates there is difference between ZQ calibration result and control code" "0: No difference (default),1: There is a difference"
|
|
bitfld.long 0x00 26.--28. "ZQCALPC,Pch calibration rough adjustment code output" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 22.--25. "ZQCALPF,Pch calibration fine-tuning code output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--21. "ZQCALNC,Nch calibration rough adjustment code output" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--18. "ZQCALNF,Nch calibration fine-tuning code output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14. "ZQCALINIT,ZQ calibration initialization end output" "0: Calibration unexecution (default),1: Calibration initialization end"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "ZQCALUPD,Bit" "0: 200MHz to 400MHz 16 DFICLK (default),1: DLLCTRL bit3,2: 50MHz to 100MHz 4 DFICLK,3: reserved (set prohibition) Bit"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "ZQCALFREQ,Setting sampling intervals of ZQ calibration Please set it according to the frequency of SRCLK/HRCLK" "0: Prohibit,1: 333MHz< SRCLK/HRCLK frequency <= 667MHz,2: 300MHz< SRCLK/HRCLK frequency <= 333MHz,3: reserved"
|
|
bitfld.long 0x00 4.--7. "ZQCALITVL,Setting ZQ calibration execution intervals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 2. "ZQCALMODE,ZQ calibration initial code setting" "0: No termination (default),1: Termination is used"
|
|
newline
|
|
bitfld.long 0x00 1. "ZQCALSTRV,ZQ calibration initial value setting" "0: Initial value,1: Last result (default)"
|
|
bitfld.long 0x00 0. "ZQCALRSTB,ZQ calibration circuit reset setting" "0: Reset (default),1: Reset release"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DDR_PHY_ZQODTCTRL,ZQODT control register"
|
|
bitfld.long 0x00 30.--31. "CAPHASE,Command/Address Output Phase setting The output phase of command/Address to MCK is set" "?,?,2: 2/4 tCK setup (default),3: 3/4 tCK setup else"
|
|
bitfld.long 0x00 29. "WRFIFOEN,I/F FIFO mode setting" "0: Prohibited,1: FIFO use (default)"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "FIFORPINIT,I/F FIFO read pointer initializing" "?,1: +-1 DFICLK cycle (default),2: +-2 DFICLK cycle else : Reserved,?..."
|
|
bitfld.long 0x00 23.--26. "ZQDATA,PHY Driver Impedance setting for Data (DQ DM DQS) ZDQ/{ZQDATA}.Range that can be set DDR3 : 3-6 DDR2 : 3-7else : Reserved default=5 ZDQ is (of ZQ automatic calibration and external resistance DDR2=150ohm It is decided by DDR3=120ohm. The target.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19.--22. "ZQCK,PHY Driver Impedance setting for CK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15.--18. "ZQCMDAD,PHY Driver Impedance setting for Command/Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 14. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 12.--13. "SRDQ,Slew Rate setting for Data and DQS" "0: High(default),?,?,3: Low else : Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "SRCK,Slew Rate setting for CK The setting method is same as SRDQ" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "SRCMDAD,Slew Rate setting for Command/Address The setting method is same as SRDQ" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 5.--6. "PHYODT,PHY ODT resistance setting" "0: OFF (Prohibited),1: Rtt_RD/1,2: Rtt_RD/2 (default),3: Rtt_RD/3 Rtt_RD is determined by ZQ auto"
|
|
newline
|
|
bitfld.long 0x00 4. "PHYODTEN,PHY ODT use setting" "0,1"
|
|
bitfld.long 0x00 3. "DNVEN,Mode setting for DNV" "0: DM,1: DM/DNV"
|
|
newline
|
|
bitfld.long 0x00 2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 0.--1. "DRAMIF,DRAM I/F setting" "0: DDR2,1: DDR3 (default),2: Unused,3: Reserved"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DDR_PHY_RDCTRL,Read Control Register"
|
|
bitfld.long 0x00 28.--31. "PHYODTONT,PHY DQS ODT ON Timing setting Effective at PHYODTEN=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PHYODTOFT,PHY DQS ODT OFF Timing setting Effective at PHYODTEN=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PDQODTONT,PHY DQ ODT ON Timing setting 4'hE is recommended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PDQODTOFT,PHY DQ ODT OFF Timing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PHYBENONT,PHY DQS and DQ BEN ON Timing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PHYBENOFT,PHY DQS and DQ BEN OFF Timing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PHYIENONT,PHY DQS and DQ IEN ON Timing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PHYIENOFT,PHY DQS and DQ IEN OFF Timing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DDR_PHY_RDTMG,READ Timing control register"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 9. "MASKSFT,MASK signal adjustment" "0: Normal (Non adjustment),1: 0.5tCK delay"
|
|
newline
|
|
bitfld.long 0x00 8. "RDMODE,DFIRDATA output mode setting" "0: No aliged,1: Aligned (Please use this"
|
|
bitfld.long 0x00 4.--7. "RDENVALID,Read Data transfer setting" "?,?,?,?,?,?,?,?,?,?,?,11: 16 DFICLK(default) (WRFIFOEN=1'b1,?,13: 18 DFICLK (WRFIFOEN=1'b1 FIFORPINIT=2'b10) 0..,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "WDOMODE,Command DQ output mode setting" "0: Normal mode WL,1: Reserved (set prohibition),2: Normal mode WL,3: Reserved (set prohibition)"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DDR_PHY_FIFOINIT,FIFO Initialization register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "RDPTINITEXE,Read FIFO pointer initialization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "WRPTINITEXE,Write FIFO pointer initialization" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DDR_PHY_OUTCTRL,Output Control Register"
|
|
bitfld.long 0x00 29.--31. "bf_align4,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26.--28. "CKOBUFEN,MCK/MCKB output control" "0: Hi-Z,1: output,?..."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "MBL,Setting of BL for DQ calibration" "0: Reserved (Prohibited),1: 4 burst,2: 8 burst (default),3: 16 burst"
|
|
bitfld.long 0x00 21.--23. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "MRL,Setting of RL for DQ calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "MWL,Please set WL(Write Latency) according to the state of initialization of the memory used" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "DISOUT,reserve" "0,1,2,3"
|
|
bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RESETBOE,Outputting enable setting of MRESETB" "0,1"
|
|
bitfld.long 0x00 1. "CKEODTOE,Outputting enable setting of MCKE and MODT" "0: H-Z,1: Output"
|
|
newline
|
|
bitfld.long 0x00 0. "ADCMDOE,Address and Command output enable setting" "0: Hi-Z,1: Output"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DDR_PHY_WLCTRL1,Write leveling control register 1"
|
|
bitfld.long 0x00 31. "WLEN,Write Leveling function use setting" "0: Unused (default),1: Use (FIFO I/F mode limitation)"
|
|
bitfld.long 0x00 30. "WLAUTO,Setting of Write Leveling execution mode (Reseved mode)" "0: Manual setting (default),1: Automatic setting (Prohibited)"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 25.--26. "WLSTATE,Write Leveling status setting (Reserved)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24. "WLSTR,Write Leveling timing adjustment" "0,1"
|
|
hexmask.long.word 0x00 15.--23. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "WL2OFS,The second Byte Write Leveling manual operation offset setting WL2OFS [6]=1'b1 90-90/32* WL2OFS[5:0] [degree] ( 0 to 90degree : 0 <= WL2OFS[5:0] <= 31)"
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "WL1OFS,The first Byte Write Leveling manual operation offset setting WL1OFS [6]=1'b1 90-90/32* WL1OFS[5:0] [degree] ( 0 to 90degree: 0 <= WL1OFS[5:0] <= 31)"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DDR_PHY_WLCTRL2,Write leveling control register 2"
|
|
hexmask.long.word 0x00 23.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--22. 1. "WL5OFS,The fifth Byte Write Leveling manual operation offset setting WL4OFS [6]=1'b1 90-90/32* WL5OFS[5:0] [degree] ( 0~90degree : 0 <= WL5OFS[5:0] <= 31).The setting that is smaller than the minimum SDLY delay will be a minimum delay"
|
|
newline
|
|
bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "WL4OFS,The fourth Byte Write Leveling manual operation offset setting WL4OFS [6]=1'b1 90-90/32* WL4OFS[5:0] [degree] ( 0~90degree : 0 <= WL4OFS[5:0] <= 31) The setting that is smaller than the minimum SDLY delay will be a minimum delay"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "WL3OFS,The third Byte Write Leveling manual operation offset setting WL3OFS [6]=1'b1 90-90/32* WL3OFS[5:0] [degree] ( 0~90degree : 0 <= WL3OFS[5:0] <= 31) The setting that is smaller than the minimum SDLY delay will be a minimum delay"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "DDR_PHY_MASKSDLY1,Mask Signal Offset 1"
|
|
bitfld.long 0x00 31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. "MASKSDL3OFS,Mask signal offset of the 4th BYTE"
|
|
newline
|
|
bitfld.long 0x00 23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "MASKSDL2OFS,Mask signal offset of the 3rd BYTE"
|
|
newline
|
|
bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "MASKSDL1OFS,Mask signal offset of the 2nd BYTE"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "MASKSDL0OFS,Mask signal offset of the 1st BYTE"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "DDR_PHY_MASKSDLY2,Mask Signal Offset 2"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "MASKSDL4OFS,Mask signal offset of the 5th BYTE"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "DDR_PHY_ZQCODE,I/F control register register is not used in DDR-PHY implementation only writable after writing another register with magic cookie"
|
|
bitfld.long 0x00 29.--31. "ZQEPC,Pch rough adjustment code setting Valid at ZQCALECNT= 1'b1 or EODTDQ=1' b1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 25.--28. "ZQEPF,Pch fine-tuning code setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "ZQENC,Nch rough adjustment code setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--21. "ZQENF,Nch fine-tuning code setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 17. "ZQCAL_ERRER,Signal that becomes '1' when a code that the ZQ calibration becomes maximum value/minimum value" "0,1"
|
|
bitfld.long 0x00 16. "ZQUPD,Update of ZQ control code Only manual setting mode (ZQCALECNT=1'b1) is effective" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "ZQCALFL,Setting of ZQ calibration end condition" "0: Four times of threshold change of constant,1: One time of threshold change of constant..,2: Two times of threshold change of constant,3: Three times of threshold change of constant"
|
|
bitfld.long 0x00 13. "ACODTN,ODT enable signal for receiver for address command" "0: ,1: ON"
|
|
newline
|
|
bitfld.long 0x00 12. "CKODTEN,ODT enable signal for CK input receiver" "0: ,1: ON"
|
|
bitfld.long 0x00 11. "RFU1,Reserved (Please write the value of the initial value column when writing it)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "RFU2,Reserved (Please write the value of the initial value column when writing it)" "0,1"
|
|
bitfld.long 0x00 8.--9. "RFU3,Reserved (Please write the value of the initial value column when writing it)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "ACODTSL,ODT range selection signal for input receiver of address command" "0: OFF(default),1: Rtt_RD/1,2: Rtt_RD/2,3: Rtt_RD/3"
|
|
bitfld.long 0x00 4.--5. "RFU4,Reserved (Please write the value of the initial value column when writing it)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3. "RFU5,Reserved (Please write the value of the initial value column when writing it)" "0,1"
|
|
bitfld.long 0x00 2. "RFU6,Reserved (Please write the value of the initial value column when writing it)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EODTDQ,The ODT single and outside settings for DQ" "0: Automatic setting (Recommendation,1: Manual setting"
|
|
bitfld.long 0x00 0. "ZQCALENCNT,The ZQ calibration outside setting" "0: Automatic setting (Recommendation,1: Manual setting"
|
|
tree.end
|
|
tree "PL353"
|
|
base ad:0xF8003000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PL353_memc_status,NA"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "undefined_status,Read undefined"
|
|
bitfld.long 0x00 12. "raw_ecc_int1,Current raw ecc interrupt status for interface 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "raw_ecc_int0,Current raw ecc interrupt status for interface 0" "0,1"
|
|
bitfld.long 0x00 10. "ecc_int1,Current interrupt status for interface 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ecc_int0,Current ecc interrupt status for interface 0" "0,1"
|
|
bitfld.long 0x00 8. "ecc_int1_en,returns the state of ecc interrupt enable on memory interface 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ecc_int0_en,returns the state of ecc interrupt enable on memory interface 0" "0,1"
|
|
bitfld.long 0x00 6. "raw_int_status1,Current raw interrupt status for interface 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "raw_int_status0,Current raw interrupt status for interface 0" "0,1"
|
|
bitfld.long 0x00 4. "int_status1,Current interrupt status for interface 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "int_status0,Current interrupt status for interface 0" "0,1"
|
|
bitfld.long 0x00 2. "int_en1,returns the state of memory interface 1 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "int_en0,returns the state of memory interface 0 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "state,returns the state of the memory controller" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PL353_memif_cfg,NA"
|
|
hexmask.long.word 0x00 18.--31. 1. "undefined_status,Read undefined"
|
|
bitfld.long 0x00 16.--17. "exclusive_monitors,returns the number of exclusive access monitors implemented in SMC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 15. "none1,reserved value" "0,1"
|
|
bitfld.long 0x00 14. "remap1,Returns the value of the interface 1 remap pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "memory_width1,returns the max width of the SMC memory data bus for interface 1" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "memory_chips1,returns the number of different chips selects on memory interface 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "memory_type1,returns the memory interface 1 type" "0,1,2,3"
|
|
bitfld.long 0x00 7. "none0,reserved value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "remap0,returns the value of the interface 0 remap pin" "0,1"
|
|
bitfld.long 0x00 4.--5. "memory_width0,returns the max width of the SMC memory data bus for interface 0" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "memory_chips0,returns the number of different chips selects on memory interface 0" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "memory_type0,returns the memory interface 0 type" "0,1,2,3"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "PL353_mem_cfg_set,NA"
|
|
hexmask.long 0x00 7.--31. 1. "undefined_status1,Read undefined"
|
|
bitfld.long 0x00 6. "ecc_int_enable1,NA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ecc_int_enable0,NA" "0,1"
|
|
bitfld.long 0x00 3.--4. "undefined_status0,Read undefined" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2. "low_power_req,NA" "0,1"
|
|
bitfld.long 0x00 1. "int_enable1,NA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "int_enable0,NA" "0,1"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "PL353_mem_cfg_clr,NA"
|
|
hexmask.long 0x00 7.--31. 1. "undefined_status,Read undefined"
|
|
bitfld.long 0x00 6. "ecc_int_disable1,NA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ecc_int_disable0,NA" "0,1"
|
|
bitfld.long 0x00 4. "int_clr1,NA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "int_clr0,NA" "0,1"
|
|
bitfld.long 0x00 2. "low_power_exit,NA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "int_disable1,NA" "0,1"
|
|
bitfld.long 0x00 0. "int_disable0,NA" "0,1"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "PL353_direct_cmd,NA"
|
|
bitfld.long 0x00 26.--31. "undefined_status,Read undefined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23.--25. "chip_select,address field of direct_cmd register" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "cmd_type,access_type field of direct_cmd register" "0,1,2,3"
|
|
bitfld.long 0x00 20. "set_cre,CRE field of direct command regsiter" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "addr,address field of direct_cmd register"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "PL353_set_cycles,NA"
|
|
hexmask.long.word 0x00 23.--31. 1. "undefined_status,Read undefined"
|
|
bitfld.long 0x00 20.--22. "set_t6,value to be written to chip tRC field" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "set_t5,value to be written to chip tRC field" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 14.--16. "set_t4,value to be written to chip tRC field" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11.--13. "set_t3,value to be written to chip tWP field" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "set_t2,value to be written to chip tCEOE or tREA field" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "set_t1,value to be written to chip tWC field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "set_t0,value to be written to chip tRC field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "PL353_set_opmode,NA"
|
|
bitfld.long 0x00 30.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--29. 1. "undefined_status,Read undefined"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "set_burst_align,value written to specific SRAM opmode register burst align field reserved for NAND" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "set_bls,value written to specific SRAM opmode register byte lane strobe reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "set_adv,value written to specific SRAM opmode register burst address advance reserved for NAND" "0,1"
|
|
bitfld.long 0x00 10. "set_baa,value written to specific SRAM opmode register burst address advance reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--9. "set_wr_bl,value written to specific SRAM opmode register bls field reserved for NAND" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6. "set_wr_sync,value written to specific SRAM opmode register wr_sync reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "set_rd_bl,value written to specific SRAM opmode register bls field reserved for NAND" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "set_rd_sync,value written to specific SRAM opmode register rd_sync reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "set_mw,value written to specific opmode register mem width" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PL353_refresh_period_0,NA"
|
|
hexmask.long 0x00 4.--31. 1. "unused,Read undefined"
|
|
bitfld.long 0x00 0.--3. "period,NA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "PL353_sram_cycles0_0,NA"
|
|
hexmask.long.word 0x00 21.--31. 1. "undefined_status,Read undefined"
|
|
bitfld.long 0x00 20. "we_time,Controls assertion os we during async mux_mode writes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "t_tr,turnaround time for SRAM chip config" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 14.--16. "t_pc,page cycle time for SRAM chip config" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11.--13. "t_wp,we_n assertion delay" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "t_ceoe,oe_n assertion delay for SRAM chip config" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "t_wc,write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "t_rc,read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "PL353_opmode0_0,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "address_match,returns value of address match tie-off"
|
|
hexmask.long.byte 0x00 16.--23. 1. "address_mask,returns value of address mask tie-off"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "burst_align,value written to specific SRAM opmode register burst align field reserved for NAND" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "bls,affects the assertion of the byte lane strobe reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "adv,mem uses address adv signal when set reserved for NAND" "0,1"
|
|
bitfld.long 0x00 10. "baa,mem uses burst advance signal when set reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--9. "wr_bl,determines the mem burst length for writes reserved for NAND" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6. "wr_sync,when set mem operates in wr_sync mode reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "rd_bl,determines the mem burst length for reads reserved for NAND" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "rd_sync,when set memory operates in read sync mode reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mw,determines SMC mem data bus width" "0,1,2,3"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "PL353_sram_cycles0_1,NA"
|
|
hexmask.long.word 0x00 21.--31. 1. "undefined_status,Read undefined"
|
|
bitfld.long 0x00 20. "we_time,Controls assertion os we during async mux_mode writes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "t_tr,turnaround time for SRAM chip config" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 14.--16. "t_pc,page cycle time for SRAM chip config" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11.--13. "t_wp,we_n assertion delay" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "t_ceoe,oe_n assertion delay for SRAM chip config" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "t_wc,write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "t_rc,read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "PL353_opmode0_1,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "address_match,returns value of address match tie-off"
|
|
hexmask.long.byte 0x00 16.--23. 1. "address_mask,returns value of address mask tie-off"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "burst_align,value written to specific SRAM opmode register burst align field reserved for NAND" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "bls,affects the assertion of the byte lane strobe reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "adv,mem uses address adv signal when set reserved for NAND" "0,1"
|
|
bitfld.long 0x00 10. "baa,mem uses burst advance signal when set reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--9. "wr_bl,determines the mem burst length for writes reserved for NAND" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6. "wr_sync,when set mem operates in wr_sync mode reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "rd_bl,determines the mem burst length for reads reserved for NAND" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "rd_sync,when set memory operates in read sync mode reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mw,determines SMC mem data bus width" "0,1,2,3"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "PL353_nand_cycles1_0,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "undefined_status,Read undefined"
|
|
bitfld.long 0x00 20.--23. "t_rr,bust to re_n for NAND chip config" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "t_ar,ID read time for NAND chip config" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 14.--16. "t_clr,status read time for NAND chip config" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11.--13. "t_wp,we_n assertion delay" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "t_rea,re_n assertion delay for NAND chip config" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "t_wc,write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "t_rc,read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "PL353_opmode1_0,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "address_match,returns value of address match tie-off"
|
|
hexmask.long.byte 0x00 16.--23. 1. "address_mask,returns value of address mask tie-off"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "burst_align,value written to specific SRAM opmode register burst align field reserved for NAND" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "bls,affects the assertion of the byte lane strobe reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "adv,mem uses address adv signal when set reserved for NAND" "0,1"
|
|
bitfld.long 0x00 10. "baa,mem uses burst advance signal when set reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--9. "wr_bl,determines the mem burst length for writes reserved for NAND" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6. "wr_sync,when set mem operates in wr_sync mode reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "rd_bl,determines the mem burst length for reads reserved for NAND" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "rd_sync,when set memory operates in read sync mode reserved for NAND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "mw,determines SMC mem data bus width" "0,1,2,3"
|
|
rgroup.long 0x200++0x03
|
|
line.long 0x00 "PL353_user_status,NA"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "undefined,read undefined"
|
|
hexmask.long.byte 0x00 0.--7. 1. "user_status,NA"
|
|
wgroup.long 0x204++0x03
|
|
line.long 0x00 "PL353_user_config,NA"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "undefined,read undefined"
|
|
hexmask.long.byte 0x00 0.--7. 1. "user_config,NA"
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "PL353_ecc_status,NA"
|
|
bitfld.long 0x00 30.--31. "undefined,read undefined" "0,1,2,3"
|
|
bitfld.long 0x00 25.--29. "ecc_read,Indicates if the ecc blocks have been" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 20.--24. "ecc_can_correct,Indicates if the ecc blocks can be corrected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15.--19. "ecc_fail,Pass fail flags for ecc blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10.--14. "ecc_value_valid,Indicates if the ecc block registers are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. "ecc_read_n_write,Indicates direction of current ecc access" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "ecc_last_status,Indicates what happened during the last ecc block access" "0,1,2,3"
|
|
bitfld.long 0x00 6. "ecc_status,Status of the ecc block" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "raw_int_status,Status of ecc interrupt flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "PL353_ecc_memcfg,NA"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "undefined,read undefined"
|
|
bitfld.long 0x00 10.--12. "ecc_extra_block,Bit" "0: Use extra block Bit,1: Ecc extra block size Bit,2: Ecc extra block size,?..."
|
|
newline
|
|
bitfld.long 0x00 9. "ecc_int_abort,Interrupt on ecc abort" "0,1"
|
|
bitfld.long 0x00 8. "ecc_int_pass,Interrupt on ecc pass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ecc_ignore_add_eight,Indicates if the ecc block registers are valid" "0,1"
|
|
bitfld.long 0x00 5.--6. "ecc_jump,Sets how the controller jumps when accessing codes" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4. "ecc_read_end,Sets when ecc_codes are read from memory" "0,1"
|
|
bitfld.long 0x00 2.--3. "ecc_mode,Set the mode of th ecc block" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "page_size,Number of 512 byte blocks in page" "0,1,2,3"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "PL353_ecc_memcommand1,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "undefined,read undefined"
|
|
bitfld.long 0x00 24. "nand_rd_cmd_end_valid,Indicates an end command is required on a" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "nand_rd_cmd_end,Command used to end a"
|
|
hexmask.long.byte 0x00 8.--15. 1. "nand_rd_cmd,Command used to start/detect a"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "nand_wr_cmd,Command used to start/detect a"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "PL353_ecc_memcommand2,NA"
|
|
hexmask.long.byte 0x00 25.--31. 1. "undefined,read undefined"
|
|
bitfld.long 0x00 24. "nand_rd_cmd_end_valid,Indicates an end command is required on a read col change" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "nand_rd_col_change_end,Command used to end a read column change command"
|
|
hexmask.long.byte 0x00 8.--15. 1. "nand_rd_col_change,Command used to change column during a"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "nand_wr_col_change,Command used to change col during a"
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "PL353_ecc_addr0,NA"
|
|
hexmask.long 0x00 0.--31. 1. "ecc_addr,Page address being used for ECC"
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "PL353_ecc_addr1,NA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "undefined,undefined"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "ecc_addr,Page address being used for ECC"
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
rgroup.long ($2+0x418)++0x03
|
|
line.long 0x00 "PL353_ecc_value$1,NA"
|
|
bitfld.long 0x00 31. "ecc_int,Indicates the status of the block interrupt" "0,1"
|
|
bitfld.long 0x00 30. "ecc_valid,Indicates block data has been read/written" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "ecc_read,Indicates block code has been" "0,1"
|
|
bitfld.long 0x00 28. "ecc_fail,Indicates block failed" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "ecc_correct,Indicates block can be corrected" "0,1"
|
|
bitfld.long 0x00 24.--26. "undefined,undefined" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "ecc_value,Page address being used for ECC"
|
|
repeat.end
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "PL353_integration_test,NA"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "PL353_periph_id_n,NA"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "PL353_pcell_id_n,NA"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
tree "USB_FUNC"
|
|
base ad:0xF8004000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USB_FUNC_USB_CONTROL,This register is used to control the basic EPC features and the USB device status"
|
|
hexmask.long.word 0x00 19.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16.--18. "USBTESTMODE,Set these bits after the status stage of the SET_FEATURE_TEST_MODE request has finished normally" "0: Normal,1: Test_J,2: Test_K,3: Test_SE0_NAK,4: Test_Packet,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. "SOF_CLK_MODE,Select the operating mode of the SOF output pin in HS mode" "0: Invert signal when SOF/uSOF packet is received,1: Invert signal when SOF packet is received (do"
|
|
newline
|
|
bitfld.long 0x00 10. "INT_SEL,Select the level of the U2F_EPC_INT interrupt output signal" "0: Pulse output,1: Level output If there are multiple interrupt"
|
|
bitfld.long 0x00 9. "FORCEFS,By setting this bit to 1b when executing simulation the subsystem is forced to operate in FS mode" "0: Do not fix the operating mode to FS mode,1: Fix the operating mode to FS mode (during"
|
|
newline
|
|
bitfld.long 0x00 8. "SOF_RCV,Select whether to enable automatic recovery when an SOF reception error occurs" "0: Disable,1: Enable"
|
|
bitfld.long 0x00 7. "RSUM_IN,Specify whether to send the resume signal when using the remote wakeup feature" "0: Do not send the resume signal,1: Send the resume signal"
|
|
newline
|
|
bitfld.long 0x00 6. "SUSPEND,If this bit is set to 1b while the USB device is in the Suspend state as defined in the USB specification the clock supply to the EPC SIE and UTMI-PHY blocks is stopped to reduce power consumption" "0: Do not stop the clock supply,1: Stop the clock supply"
|
|
bitfld.long 0x00 5. "CONF,Set this bit to enable endpoints other than endpoint 0" "0: Disable endpoints other than endpoint 0,1: Enable endpoints other than endpoint 0"
|
|
newline
|
|
bitfld.long 0x00 4. "DEFAULT,Set this bit to enable endpoint 0" "0: Disable,1: Enable"
|
|
bitfld.long 0x00 3. "CONNECTB,Set this bit to 1b when Un-Plug a USB device to prevent the occurrence of a pseudo bus reset or suspend signal due to an unstable D+/D- signal operation on the USB port" "0: Enable the USB signal sent to the UTMI-PHY..,1: Disable the USB signal sent to the UTMI-PHY"
|
|
newline
|
|
bitfld.long 0x00 2. "PUE2,Specify whether to pull up the D+ signal" "0: Do not pull up the D+ signal,1: Pull up the D+ signal"
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "USB_FUNC_USB_STATUS,This is a read-only register that indicates the USB status and SIE core status"
|
|
bitfld.long 0x00 31. "SOF_DELAY_STATUS,This bit is set to 1 if an SOF is ignored because it has been received in a period in which SOFs are not accepted" "0: SOF was received normally,1: SOF was ignored"
|
|
hexmask.long.tbyte 0x00 7.--30. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "SPEED_MODE,Indicates the USB port speed" "0: FS (Full-Speed),1: HS (High-Speed)"
|
|
bitfld.long 0x00 5. "CONF,Indicates whether endpoints other than endpoint 0 are enabled" "0: Disabled (No,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "DEFAULT,Indicates whether endpoint 0 is enabled" "0: Disabled (No,1: Enabled"
|
|
bitfld.long 0x00 3. "USB_RST,Indicates the bus reset signal status" "0: The bus reset signal is inactive,1: The bus reset signal is active"
|
|
newline
|
|
bitfld.long 0x00 2. "SPND_OUT,Indicates the status of SIE and UTMI + transceiver" "0: SIE and UTMI + transceiver are not in the,1: SIE and UTMI + transceiver are in the Suspend"
|
|
bitfld.long 0x00 1. "RSUM_OUT,Indicates the resume signal reception status on the SIE and UTMI+ transceiver" "0: The resume is not being received,1: The resume signal is being received"
|
|
newline
|
|
bitfld.long 0x00 0. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USB_FUNC_USB_ADDRESS,Frame number & USB address register"
|
|
bitfld.long 0x00 31. "SOF_DELAY_MODE,Specify whether to enable a period in which an SOF is not accepted" "0: An SOF is accepted regardless of when it is,1: Enable a period in which an SOF is not accepted"
|
|
hexmask.long.byte 0x00 23.--30. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--22. 1. "USB_ADDR,The value written to this field is determined as the device address after the status stage of the Set Address request completes normally"
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|
bitfld.long 0x00 15. "SOF_STATUS,Indicates the SOF (uSOF) reception status" "0: The SOF (uSOF) was received normally,1: An SOF (uSOF) reception error occurred"
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bitfld.long 0x00 12.--14. "UFRAME,Indicates the number of times the uSOF packet is received within a frame" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 11. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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|
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hexmask.long.word 0x00 0.--10. 1. "FRAME,Indicates the frame number of the SOF"
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|
group.long 0x10++0x03
|
|
line.long 0x00 "USB_FUNC_TEST_CONTROL,This register is used to control the USB test mode and operations on the UDL side such as hardware loopbacks"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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|
bitfld.long 0x00 2. "FORCEHS,By setting this bit to 1b when executing simulation the subsystem is forced to operate in HS mode" "0: Normal operating mode,1: Fix the operating mode to HS mode (during"
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bitfld.long 0x00 1. "CS_TESTMODEEN,As soon as this bit is set to 1b the settings of bits 18 to 16 (USBTESTMODE[2:0]) of the USB control register become valid" "0: Normal operating mode,1: Enable USB test mode"
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|
bitfld.long 0x00 0. "LOOPBACK,Enable use of hardware loopbacks on the UDL side" "0: Normal operating mode,1: Hardware loopback on the UDL side"
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|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "USB_FUNC_SETUP_DATA0,This register is used to store the first 4 bytes of 8-byte data received in a setup transaction"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SETUP4,Stores the 4th byte of the received setup data"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SETUP3,Stores the 3rd byte of the received setup data"
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|
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hexmask.long.byte 0x00 8.--15. 1. "SETUP2,Stores the 2nd byte of the received setup data"
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|
hexmask.long.byte 0x00 0.--7. 1. "SETUP1,Stores the 1st byte of the received setup data"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USB_FUNC_SETUP_DATA1,This register is used to store the last 4 bytes of 8-byte data received in a setup transaction"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SETUP8,Stores the 8th byte of the received setup data"
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|
hexmask.long.byte 0x00 16.--23. 1. "SETUP7,Stores the 7th byte of the received setup data"
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|
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hexmask.long.byte 0x00 8.--15. 1. "SETUP6,Stores the 6th byte of the received setup data"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SETUP5,Stores the 5th byte of the received setup data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "USB_FUNC_USB_INT_STA,This register indicates the source of an interrupt output from the U2F_EPC_INT pin"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 23. "EP15_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
|
|
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bitfld.long 0x00 22. "EP14_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
|
|
bitfld.long 0x00 21. "EP13_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
|
|
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bitfld.long 0x00 20. "EP12_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
|
|
bitfld.long 0x00 19. "EP11_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
|
|
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bitfld.long 0x00 18. "EP10_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
|
|
bitfld.long 0x00 17. "EP9_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
|
|
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bitfld.long 0x00 16. "EP8_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
|
|
bitfld.long 0x00 15. "EP7_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
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|
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bitfld.long 0x00 14. "EP6_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
|
|
bitfld.long 0x00 13. "EP5_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
|
|
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bitfld.long 0x00 12. "EP4_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
|
|
bitfld.long 0x00 11. "EP3_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
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|
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bitfld.long 0x00 10. "EP2_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
|
|
bitfld.long 0x00 9. "EP1_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
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bitfld.long 0x00 8. "EP0_INT,Indicates whether an interrupt related to endpoint 0 or n has occurred" "0: No interrupt related to endpoint 0 or n has,1: An interrupt related to endpoint 0 or n has"
|
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bitfld.long 0x00 7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 6. "SPEED_MODE_INT,Indicates a change in the speed mode" "0: The speed mode has not changed from FS to HS,1: The speed mode has changed from FS to HS"
|
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bitfld.long 0x00 5. "SOF_ERROR_INT,Indicates whether an SOF or uSOF reception error has occurred" "0: No SOF or uSOF reception error has occurred,1: An SOF or uSOF reception error has occurred"
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|
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bitfld.long 0x00 4. "SOF_INT,Indicates whether an SOF or uSOF has been received" "0: No SOF or uSOF has been received,1: An SOF or uSOF has been received"
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|
bitfld.long 0x00 3. "USB_RST_INT,Indicates whether a bus reset has been issued" "0: A bus reset has not been issued,1: A bus reset has been issued"
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bitfld.long 0x00 2. "SPND_INT,Indicates whether the USB device is in the Suspend state" "0: The USB device is not in the Suspend state,1: The USB device is in the Suspend state"
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|
bitfld.long 0x00 1. "RSUM_INT,Indicates whether the resume signal sent from the corresponding USB host has been received" "0: The resume signal has not been received,1: The resume signal has been received"
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bitfld.long 0x00 0. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "USB_FUNC_USB_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the USB interrupt status register"
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|
hexmask.long.byte 0x00 24.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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|
bitfld.long 0x00 23. "EP15_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
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bitfld.long 0x00 22. "EP14_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 21. "EP13_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
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bitfld.long 0x00 20. "EP12_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 19. "EP11_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
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bitfld.long 0x00 18. "EP10_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 17. "EP9_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
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bitfld.long 0x00 16. "EP8_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
|
|
bitfld.long 0x00 15. "EP7_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
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bitfld.long 0x00 14. "EP6_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 13. "EP5_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
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bitfld.long 0x00 12. "EP4_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 11. "EP3_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
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bitfld.long 0x00 10. "EP2_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 9. "EP1_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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bitfld.long 0x00 8. "EP0_EN,Specify whether to enable bits [23:8] (EPn_INT/EP0_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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|
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|
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bitfld.long 0x00 6. "SPEED_MODE_EN,Specify whether to enable bit 6 (SPEED_MODE_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 5. "SOF_ERROR_EN,Specify whether to enable bit 5 (SOF_ERROR_INT) of the USB interrupt status register" "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x00 4. "SOF_EN,Specify whether to enable bit 4 (SOF_INT) of the USB interrupt status register" "0: Disable,1: Enable"
|
|
bitfld.long 0x00 3. "USB_RST_EN,Specify whether to enable bit 3 (USB_RST_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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bitfld.long 0x00 2. "SPND_EN,Specify whether to enable bit 2 (SPND_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 1. "RSUM_EN,Specify whether to enable bit 1 (RSUM_INT) of the USB interrupt status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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|
group.long 0x28++0x03
|
|
line.long 0x00 "USB_FUNC_EP0_CONTROL,This register is used to control endpoint 0"
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hexmask.long.word 0x00 19.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 18. "EP0_STGSEL,Select the operation when data other than null data is received at a status stage" "0: Perform reception normally,1: Return a STALL"
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bitfld.long 0x00 17. "EP0_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT token is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP0_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND),1: Set bit 7 (EPn_DEND)"
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bitfld.long 0x00 10.--15. "RESERVED01,EP0_AUTO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 9. "EP0_PIDCLR,Write 1b to this bit to initialize the data PID for endpoint 0" "0,1"
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bitfld.long 0x00 8. "EP0_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers)" "0,1"
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|
bitfld.long 0x00 7. "EP0_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP0_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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|
bitfld.long 0x00 4. "EP0_INAK_EN,Write 1b to this bit to enable writing to bit 1 (EPn_INAK)" "0,1"
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|
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bitfld.long 0x00 3. "EP0_PERR_NAK_CLR,Write 1b to this bit to cancel the NAK returned when a token that indicates an unrecognized request configuration error is received" "0,1"
|
|
bitfld.long 0x00 2. "EP0_STL,Use this bit to control the STALL returned in response to an IN OUT or PING token for endpoint 0" "0: Do not return a STALL,1: Return a STALL"
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|
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bitfld.long 0x00 1. "EP0_INAK,Use this bit to control the NAK returned in response to an IN token for endpoint 0" "0: Transmit data if data exists in the..,1: Return a NAK even if data exists in the"
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bitfld.long 0x00 0. "EP0_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint 0" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0x2C++0x03
|
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line.long 0x00 "USB_FUNC_EP0_STATUS,This register indicates the source of an interrupt related to endpoint 0 among the sources of interrupts output from the U2F_EPC_INT pin"
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|
hexmask.long.word 0x00 19.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 18. "EP0_PID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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|
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|
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bitfld.long 0x00 17. "EP0_PERR_NAK,This bit is set to 1b when a NAK is forcibly returned due to reception of a token that indicates a request configuration error for endpoint 0" "0: A NAK has not been sent even though a request,1: A NAK was sent due to reception of a request"
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|
bitfld.long 0x00 16. "EP0_PERR_NAK_INT,This bit is set to 1b when a NAK is sent in response to a request configuration error token for endpoint 0" "0: No request configuration error token has been,1: A NAK was sent in response to a request"
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bitfld.long 0x00 15. "EP0_OUT_NAK_INT,This bit is set to 1b when a NAK is sent in response to an OUT or PING token for endpoint 0" "0: NAK has not been sent in response to an OUT or,1: A NAK was sent in response to an OUT or PING.."
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|
bitfld.long 0x00 14. "EP0_OUT_NULL,This bit is set to 1b when null data for endpoint 0 is received" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 13. "EP0_OUT_FULL,This bit is set to 1b if data of the maximum packet size (64 bytes) exists in the EP0 read register (reception buffer)" "0: The reception buffer is not full,1: The reception buffer is full"
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|
bitfld.long 0x00 12. "EP0_OUT_EMPTY,This bit is set to 1b if the EP0 read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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|
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bitfld.long 0x00 11. "EP0_IN_NAK_INT,This bit is set to 1b when a NAK is sent in response to an IN token for endpoint 0" "0: A NAK has not been sent in response to an IN..,1: A NAK was sent in response to an IN token"
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|
bitfld.long 0x00 10. "EP0_IN_DATA,This bit is set to 1b if there is data to be sent in the EP0 write register (transmission buffer) while bit 7 (EP0_DEND) of the EP0 control register is set" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 9. "EP0_IN_FULL,This bit is set to 1b if the EP0 write register (transmission buffer) is full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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|
bitfld.long 0x00 8. "EP0_IN_EMPTY,This bit is set to 1b if the EP0 write register (transmission buffer) is empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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bitfld.long 0x00 7. "EP0_OUT_NULL_INT,This bit is set to 1b when received null data is stored in the EP0 read register (reception buffer)" "0: Null data has not been received,1: Null data was received"
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|
bitfld.long 0x00 6. "EP0_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint 0" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 5. "EP0_OUT_INT,This bit is set to 1b when storing valid data in the EP0 read register (reception buffer) has finished and the data can be" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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|
bitfld.long 0x00 4. "EP0_IN_INT,This bit is set to 1b when data in the EP0 write register (transmission buffer) has been sent normally and the next data can be written" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 3. "EP0_STALL_INT,This bit is set to 1b when processing at endpoint 0 is stalled" "0: Processing at endpoint 0 is not stalled,1: Processing at endpoint 0 is stalled"
|
|
bitfld.long 0x00 2. "STG_END_INT,This bit is set to 1b when the status stage of a control transfer completes normally" "0: The status stage has not completed,1: The status stage completed normally"
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|
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|
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bitfld.long 0x00 1. "STG_START_INT,This bit is set to 1b when the status stage of a control transfer starts" "0: The status stage has not started,1: The status stage has started"
|
|
bitfld.long 0x00 0. "SETUP_INT,This bit is set to 1b when valid setup data is received" "0: Valid setup data has not been received,1: Valid setup data was received"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "USB_FUNC_EP0_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP0 status register"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "EP0_PERR_NAK_EN,Specify whether to enable bit 16 (EP0_PERR_NAK_INT) of the EP0 status register" "0,1"
|
|
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|
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bitfld.long 0x00 15. "EP0_OUT_NAK_EN,Specify whether to enable bit 15 (EP0_OUT_NAK_INT) of the EP0 status register" "0,1"
|
|
bitfld.long 0x00 12.--14. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 11. "EP0_IN_NAK_EN,Specify whether to enable bit 11 (EP0_IN_NAK_EN) of the EP0 status register" "0,1"
|
|
bitfld.long 0x00 8.--10. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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|
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|
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bitfld.long 0x00 7. "EP0_OUT_NULL_EN,Specify whether to enable bit 7 (EP0_OUT_NULL_INT) of the EP0 status register" "0,1"
|
|
bitfld.long 0x00 6. "EP0_OUT_OR_EN,Specify whether to enable bit 6 (EP0_OUT_OR_INT) of the EP0 status register" "0,1"
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|
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|
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bitfld.long 0x00 5. "EP0_OUT_EN,Specify whether to enable bit 5 (EP0_OUT_INT) of the EP0 status register" "0,1"
|
|
bitfld.long 0x00 4. "EP0_IN_EN,Specify whether to enable bit 4 (EP0_IN_INT) of the EP0 status register" "0,1"
|
|
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|
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bitfld.long 0x00 3. "EP0_STALL_EN,Specify whether to enable bit 3 (EP0_STALL_INT) of the EP0 status register" "0,1"
|
|
bitfld.long 0x00 2. "STG_END_EN,Specify whether to enable bit 2 (STG_END_INT) of the EP0 status register" "0,1"
|
|
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|
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bitfld.long 0x00 1. "STG_START_EN,Specify whether to enable bit 1 (STG_START_INT) of the EP0 status register" "0,1"
|
|
bitfld.long 0x00 0. "SETUP_EN,Specify whether to enable bit 0 (SETUP_INT) of the EP0 status register" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "USB_FUNC_EP0_LENGTH,This register indicates the number of bytes in the OUT data received at endpoint 0"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "EP0_LDATA,If OUT data is received normally in the EP0 read register (reception buffer) this field indicates the number of received bytes"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "USB_FUNC_EP0_READ,EP0 read register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EP0_RDATA4,Data received at endpoint 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP0_RDATA3,Data received at endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP0_RDATA2,Data received at endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP0_RDATA1,Data received at endpoint 0"
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wgroup.long 0x3C++0x03
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line.long 0x00 "USB_FUNC_EP0_WRITE,This register is used as a 64-byte transmission buffer for endpoint 0"
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hexmask.long.byte 0x00 24.--31. 1. "EP0_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP0_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP0_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP0_WDATA1,Data transmitted from endpoint 0"
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group.long 0x40++0x03
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line.long 0x00 "USB_FUNC_EP1_CONTROL,This register is used to control endpoint 1"
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bitfld.long 0x00 31. "EP1_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP1_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP1_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP1_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP1_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP1_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "EP1_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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bitfld.long 0x00 10. "EP1_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
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bitfld.long 0x00 9. "EP1_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP1_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP1_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP1_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP1_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP1_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP1_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0. "EP1_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0x44++0x03
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line.long 0x00 "USB_FUNC_EP1_STATUS,This register indicates the source of an interrupt related to endpoint 1 among the sources of interrupts output from the U2F_EPC_INT pin"
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bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP1_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP1_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP1_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP1_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24. "EP1_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP1_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP1_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP1_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP1_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP1_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP1_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP1_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP1_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP1_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP1_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP1_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP1_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP1_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP1_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP1_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP1_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP1_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP1_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0x48++0x03
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line.long 0x00 "USB_FUNC_EP1_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP1 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP1_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP1_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP1_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 20. "EP1_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 19. "EP1_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 18. "EP1_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "EP1_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP1_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 4. "EP1_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 3. "EP1_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x4C++0x03
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line.long 0x00 "USB_FUNC_EP1_DMA_CTRL,This register is used to set up DMA at endpoint 1"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP1_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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bitfld.long 0x00 10. "EP1_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP1_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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bitfld.long 0x00 8. "EP1_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "EP1_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0. "EP1_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0x50++0x03
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line.long 0x00 "USB_FUNC_EP1_PCKT_ADRS,This register indicates the number of bytes received in the EP1 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP1_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP1_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0x54++0x03
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line.long 0x00 "USB_FUNC_EP1_LEN_DCNT,This register indicates the number of bytes received in the EP1 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP1_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP1_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0x58++0x03
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line.long 0x00 "USB_FUNC_EP1_READ,This register is used as a reception buffer for endpoint 1"
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hexmask.long.byte 0x00 24.--31. 1. "EP1_RDATA4,Data received at endpoint 1"
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hexmask.long.byte 0x00 16.--23. 1. "EP1_RDATA3,Data received at endpoint 1"
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hexmask.long.byte 0x00 8.--15. 1. "EP1_RDATA2,Data received at endpoint 1"
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hexmask.long.byte 0x00 0.--7. 1. "EP1_RDATA1,Data received at endpoint 1"
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wgroup.long 0x5C++0x03
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line.long 0x00 "USB_FUNC_EP1_WRITE,This register is used as a transmission buffer for endpoint 1"
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hexmask.long.byte 0x00 24.--31. 1. "EP1_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP1_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP1_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP1_WDATA1,Data transmitted from endpoint 0"
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group.long 0x60++0x03
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line.long 0x00 "USB_FUNC_EP2_CONTROL,This register is used to control endpoint 2"
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bitfld.long 0x00 31. "EP2_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP2_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP2_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP2_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP2_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP2_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "EP2_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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bitfld.long 0x00 10. "EP2_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
|
|
bitfld.long 0x00 9. "EP2_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP2_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP2_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP2_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP2_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP2_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP2_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 0. "EP2_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0x64++0x03
|
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line.long 0x00 "USB_FUNC_EP2_STATUS,This register indicates the source of an interrupt related to endpoint 2 among the sources of interrupts output from the U2F_EPC_INT pin"
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|
bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP2_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP2_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP2_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP2_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24. "EP2_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP2_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP2_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP2_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP2_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP2_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP2_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP2_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP2_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP2_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP2_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP2_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP2_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP2_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP2_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP2_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP2_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP2_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP2_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0x68++0x03
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line.long 0x00 "USB_FUNC_EP2_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP2 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP2_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP2_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP2_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 20. "EP2_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 19. "EP2_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 18. "EP2_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "EP2_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP2_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 4. "EP2_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 3. "EP2_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x6C++0x03
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line.long 0x00 "USB_FUNC_EP2_DMA_CTRL,This register is used to set up DMA at endpoint 2"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP2_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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bitfld.long 0x00 10. "EP2_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP2_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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bitfld.long 0x00 8. "EP2_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "EP2_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "EP2_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0x70++0x03
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line.long 0x00 "USB_FUNC_EP2_PCKT_ADRS,This register indicates the number of bytes received in the EP2 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP2_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP2_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0x74++0x03
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line.long 0x00 "USB_FUNC_EP2_LEN_DCNT,This register indicates the number of bytes received in the EP2 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP2_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP2_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0x78++0x03
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line.long 0x00 "USB_FUNC_EP2_READ,This register is used as a reception buffer for endpoint 2"
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hexmask.long.byte 0x00 24.--31. 1. "EP2_RDATA4,Data received at endpoint 2"
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hexmask.long.byte 0x00 16.--23. 1. "EP2_RDATA3,Data received at endpoint 2"
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hexmask.long.byte 0x00 8.--15. 1. "EP2_RDATA2,Data received at endpoint 2"
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hexmask.long.byte 0x00 0.--7. 1. "EP2_RDATA1,Data received at endpoint 2"
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wgroup.long 0x7C++0x03
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line.long 0x00 "USB_FUNC_EP2_WRITE,This register is used as a transmission buffer for endpoint 2"
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hexmask.long.byte 0x00 24.--31. 1. "EP2_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP2_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP2_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP2_WDATA1,Data transmitted from endpoint 0"
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group.long 0x80++0x03
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line.long 0x00 "USB_FUNC_EP3_CONTROL,This register is used to control endpoint 3"
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bitfld.long 0x00 31. "EP3_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP3_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP3_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP3_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP3_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP3_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "EP3_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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bitfld.long 0x00 10. "EP3_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
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bitfld.long 0x00 9. "EP3_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP3_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP3_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP3_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP3_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP3_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP3_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0. "EP3_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0x84++0x03
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line.long 0x00 "USB_FUNC_EP3_STATUS,This register indicates the source of an interrupt related to endpoint 3 among the sources of interrupts output from the U2F_EPC_INT pin"
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bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP3_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP3_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP3_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP3_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24. "EP3_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP3_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP3_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP3_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP3_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP3_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP3_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP3_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP3_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP3_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP3_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP3_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP3_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP3_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP3_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP3_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP3_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP3_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP3_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0x88++0x03
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line.long 0x00 "USB_FUNC_EP3_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP3 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP3_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP3_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP3_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 20. "EP3_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 19. "EP3_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 18. "EP3_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "EP3_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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newline
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bitfld.long 0x00 5. "EP3_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 4. "EP3_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 3. "EP3_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x8C++0x03
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line.long 0x00 "USB_FUNC_EP3_DMA_CTRL,This register is used to set up DMA at endpoint 3"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP3_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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bitfld.long 0x00 10. "EP3_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP3_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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bitfld.long 0x00 8. "EP3_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "EP3_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0. "EP3_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0x90++0x03
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line.long 0x00 "USB_FUNC_EP3_PCKT_ADRS,This register indicates the number of bytes received in the EP3 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP3_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP3_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0x94++0x03
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line.long 0x00 "USB_FUNC_EP3_LEN_DCNT,This register indicates the number of bytes received in the EP3 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP3_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP3_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0x98++0x03
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line.long 0x00 "USB_FUNC_EP3_READ,This register is used as a reception buffer for endpoint 3"
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hexmask.long.byte 0x00 24.--31. 1. "EP3_RDATA4,Data received at endpoint 3"
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hexmask.long.byte 0x00 16.--23. 1. "EP3_RDATA3,Data received at endpoint 3"
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hexmask.long.byte 0x00 8.--15. 1. "EP3_RDATA2,Data received at endpoint 3"
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hexmask.long.byte 0x00 0.--7. 1. "EP3_RDATA1,Data received at endpoint 3"
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wgroup.long 0x9C++0x03
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line.long 0x00 "USB_FUNC_EP3_WRITE,This register is used as a transmission buffer for endpoint 3"
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hexmask.long.byte 0x00 24.--31. 1. "EP3_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP3_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP3_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP3_WDATA1,Data transmitted from endpoint 0"
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group.long 0xA0++0x03
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line.long 0x00 "USB_FUNC_EP4_CONTROL,This register is used to control endpoint 4"
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bitfld.long 0x00 31. "EP4_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP4_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP4_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP4_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP4_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP4_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "EP4_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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bitfld.long 0x00 10. "EP4_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
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bitfld.long 0x00 9. "EP4_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP4_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP4_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP4_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP4_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP4_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP4_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0. "EP4_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0xA4++0x03
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line.long 0x00 "USB_FUNC_EP4_STATUS,This register indicates the source of an interrupt related to endpoint 4 among the sources of interrupts output from the U2F_EPC_INT pin"
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bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP4_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP4_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP4_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP4_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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newline
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bitfld.long 0x00 24. "EP4_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP4_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP4_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP4_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP4_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP4_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP4_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP4_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP4_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP4_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP4_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP4_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP4_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP4_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP4_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP4_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP4_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP4_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP4_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0xA8++0x03
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line.long 0x00 "USB_FUNC_EP4_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP4 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP4_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP4_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP4_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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newline
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bitfld.long 0x00 20. "EP4_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 19. "EP4_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 18. "EP4_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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newline
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bitfld.long 0x00 7. "EP4_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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newline
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bitfld.long 0x00 5. "EP4_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 4. "EP4_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 3. "EP4_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0xAC++0x03
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line.long 0x00 "USB_FUNC_EP4_DMA_CTRL,This register is used to set up DMA at endpoint 4"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP4_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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bitfld.long 0x00 10. "EP4_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP4_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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newline
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bitfld.long 0x00 8. "EP4_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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|
bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 4. "EP4_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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|
bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0. "EP4_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0xB0++0x03
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line.long 0x00 "USB_FUNC_EP4_PCKT_ADRS,This register indicates the number of bytes received in the EP4 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP4_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP4_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0xB4++0x03
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line.long 0x00 "USB_FUNC_EP4_LEN_DCNT,This register indicates the number of bytes received in the EP4 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP4_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP4_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0xB8++0x03
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line.long 0x00 "USB_FUNC_EP4_READ,This register is used as a reception buffer for endpoint 4"
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hexmask.long.byte 0x00 24.--31. 1. "EP4_RDATA4,Data received at endpoint 4"
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hexmask.long.byte 0x00 16.--23. 1. "EP4_RDATA3,Data received at endpoint 4"
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hexmask.long.byte 0x00 8.--15. 1. "EP4_RDATA2,Data received at endpoint 4"
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hexmask.long.byte 0x00 0.--7. 1. "EP4_RDATA1,Data received at endpoint 4"
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wgroup.long 0xBC++0x03
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line.long 0x00 "USB_FUNC_EP4_WRITE,This register is used as a transmission buffer for endpoint 4"
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hexmask.long.byte 0x00 24.--31. 1. "EP4_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP4_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP4_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP4_WDATA1,Data transmitted from endpoint 0"
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group.long 0xC0++0x03
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line.long 0x00 "USB_FUNC_EP5_CONTROL,This register is used to control endpoint 5"
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bitfld.long 0x00 31. "EP5_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP5_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP5_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP5_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP5_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP5_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "EP5_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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bitfld.long 0x00 10. "EP5_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
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bitfld.long 0x00 9. "EP5_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP5_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP5_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP5_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP5_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP5_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP5_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0. "EP5_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0xC4++0x03
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line.long 0x00 "USB_FUNC_EP5_STATUS,This register indicates the source of an interrupt related to endpoint 5 among the sources of interrupts output from the U2F_EPC_INT pin"
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bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP5_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP5_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP5_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP5_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24. "EP5_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP5_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP5_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP5_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP5_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP5_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP5_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP5_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP5_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP5_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP5_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP5_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP5_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP5_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP5_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP5_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP5_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP5_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP5_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0xC8++0x03
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line.long 0x00 "USB_FUNC_EP5_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP5 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP5_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP5_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP5_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 20. "EP5_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 19. "EP5_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 18. "EP5_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "EP5_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP5_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 4. "EP5_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 3. "EP5_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0xCC++0x03
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line.long 0x00 "USB_FUNC_EP5_DMA_CTRL,This register is used to set up DMA at endpoint 5"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP5_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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bitfld.long 0x00 10. "EP5_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP5_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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bitfld.long 0x00 8. "EP5_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "EP5_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "EP5_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0xD0++0x03
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line.long 0x00 "USB_FUNC_EP5_PCKT_ADRS,This register indicates the number of bytes received in the EP5 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP5_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP5_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0xD4++0x03
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line.long 0x00 "USB_FUNC_EP5_LEN_DCNT,This register indicates the number of bytes received in the EP5 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP5_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP5_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0xD8++0x03
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line.long 0x00 "USB_FUNC_EP5_READ,This register is used as a reception buffer for endpoint 5"
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hexmask.long.byte 0x00 24.--31. 1. "EP5_RDATA4,Data received at endpoint 5"
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hexmask.long.byte 0x00 16.--23. 1. "EP5_RDATA3,Data received at endpoint 5"
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hexmask.long.byte 0x00 8.--15. 1. "EP5_RDATA2,Data received at endpoint 5"
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hexmask.long.byte 0x00 0.--7. 1. "EP5_RDATA1,Data received at endpoint 5"
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wgroup.long 0xDC++0x03
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line.long 0x00 "USB_FUNC_EP5_WRITE,This register is used as a transmission buffer for endpoint 5"
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hexmask.long.byte 0x00 24.--31. 1. "EP5_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP5_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP5_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP5_WDATA1,Data transmitted from endpoint 0"
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group.long 0xE0++0x03
|
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line.long 0x00 "USB_FUNC_EP6_CONTROL,This register is used to control endpoint 6"
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bitfld.long 0x00 31. "EP6_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP6_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP6_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP6_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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|
bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP6_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP6_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 11. "EP6_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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bitfld.long 0x00 10. "EP6_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
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bitfld.long 0x00 9. "EP6_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP6_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP6_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP6_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP6_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP6_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP6_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0. "EP6_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0xE4++0x03
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line.long 0x00 "USB_FUNC_EP6_STATUS,This register indicates the source of an interrupt related to endpoint 6 among the sources of interrupts output from the U2F_EPC_INT pin"
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bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP6_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP6_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP6_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP6_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24. "EP6_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP6_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP6_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP6_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP6_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP6_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP6_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP6_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP6_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP6_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP6_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP6_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP6_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP6_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP6_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP6_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP6_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP6_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP6_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0xE8++0x03
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line.long 0x00 "USB_FUNC_EP6_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP6 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP6_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP6_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP6_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 20. "EP6_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 19. "EP6_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 18. "EP6_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "EP6_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP6_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 4. "EP6_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 3. "EP6_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0xEC++0x03
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line.long 0x00 "USB_FUNC_EP6_DMA_CTRL,This register is used to set up DMA at endpoint 6"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP6_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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bitfld.long 0x00 10. "EP6_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP6_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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bitfld.long 0x00 8. "EP6_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "EP6_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0. "EP6_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0xF0++0x03
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line.long 0x00 "USB_FUNC_EP6_PCKT_ADRS,This register indicates the number of bytes received in the EP6 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP6_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP6_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0xF4++0x03
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line.long 0x00 "USB_FUNC_EP6_LEN_DCNT,This register indicates the number of bytes received in the EP6 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP6_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP6_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0xF8++0x03
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line.long 0x00 "USB_FUNC_EP6_READ,This register is used as a reception buffer for endpoint 6"
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hexmask.long.byte 0x00 24.--31. 1. "EP6_RDATA4,Data received at endpoint 6"
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hexmask.long.byte 0x00 16.--23. 1. "EP6_RDATA3,Data received at endpoint 6"
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hexmask.long.byte 0x00 8.--15. 1. "EP6_RDATA2,Data received at endpoint 6"
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hexmask.long.byte 0x00 0.--7. 1. "EP6_RDATA1,Data received at endpoint 6"
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wgroup.long 0xFC++0x03
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line.long 0x00 "USB_FUNC_EP6_WRITE,This register is used as a transmission buffer for endpoint 6"
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hexmask.long.byte 0x00 24.--31. 1. "EP6_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP6_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP6_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP6_WDATA1,Data transmitted from endpoint 0"
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group.long 0x100++0x03
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line.long 0x00 "USB_FUNC_EP7_CONTROL,This register is used to control endpoint 7"
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bitfld.long 0x00 31. "EP7_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP7_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP7_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP7_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP7_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP7_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "EP7_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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bitfld.long 0x00 10. "EP7_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
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bitfld.long 0x00 9. "EP7_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP7_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP7_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP7_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP7_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP7_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP7_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0. "EP7_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0x104++0x03
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line.long 0x00 "USB_FUNC_EP7_STATUS,This register indicates the source of an interrupt related to endpoint 7 among the sources of interrupts output from the U2F_EPC_INT pin"
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bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP7_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP7_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP7_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP7_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24. "EP7_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP7_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP7_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP7_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP7_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP7_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP7_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP7_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP7_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP7_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP7_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP7_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP7_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP7_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP7_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP7_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP7_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP7_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP7_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0x108++0x03
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line.long 0x00 "USB_FUNC_EP7_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP7 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP7_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP7_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP7_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 20. "EP7_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 19. "EP7_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 18. "EP7_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "EP7_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP7_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 4. "EP7_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 3. "EP7_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x10C++0x03
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line.long 0x00 "USB_FUNC_EP7_DMA_CTRL,This register is used to set up DMA at endpoint 7"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP7_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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bitfld.long 0x00 10. "EP7_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP7_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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bitfld.long 0x00 8. "EP7_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "EP7_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "EP7_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0x110++0x03
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line.long 0x00 "USB_FUNC_EP7_PCKT_ADRS,This register indicates the number of bytes received in the EP7 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP7_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP7_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0x114++0x03
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line.long 0x00 "USB_FUNC_EP7_LEN_DCNT,This register indicates the number of bytes received in the EP7 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP7_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP7_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0x118++0x03
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line.long 0x00 "USB_FUNC_EP7_READ,This register is used as a reception buffer for endpoint 7"
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hexmask.long.byte 0x00 24.--31. 1. "EP7_RDATA4,Data received at endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP7_RDATA3,Data received at endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP7_RDATA2,Data received at endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP7_RDATA1,Data received at endpoint 0"
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wgroup.long 0x11C++0x03
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line.long 0x00 "USB_FUNC_EP7_WRITE,This register is used as a transmission buffer for endpoint 7"
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hexmask.long.byte 0x00 24.--31. 1. "EP7_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP7_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP7_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP7_WDATA1,Data transmitted from endpoint 0"
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group.long 0x120++0x03
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line.long 0x00 "USB_FUNC_EP8_CONTROL,This register is used to control endpoint 8"
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bitfld.long 0x00 31. "EP8_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP8_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP8_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP8_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP8_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP8_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "EP8_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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bitfld.long 0x00 10. "EP8_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
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bitfld.long 0x00 9. "EP8_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP8_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP8_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP8_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP8_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP8_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP8_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0. "EP8_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0x124++0x03
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line.long 0x00 "USB_FUNC_EP8_STATUS,This register indicates the source of an interrupt related to endpoint 8 among the sources of interrupts output from the U2F_EPC_INT pin"
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bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP8_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP8_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP8_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP8_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24. "EP8_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP8_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP8_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP8_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP8_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP8_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP8_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP8_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP8_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP8_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP8_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP8_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP8_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP8_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP8_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP8_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP8_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP8_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP8_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0x128++0x03
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line.long 0x00 "USB_FUNC_EP8_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP8 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP8_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP8_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP8_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 20. "EP8_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 19. "EP8_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 18. "EP8_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "EP8_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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newline
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bitfld.long 0x00 5. "EP8_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 4. "EP8_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 3. "EP8_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x12C++0x03
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line.long 0x00 "USB_FUNC_EP8_DMA_CTRL,This register is used to set up DMA at endpoint 8"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP8_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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newline
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bitfld.long 0x00 10. "EP8_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP8_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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newline
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bitfld.long 0x00 8. "EP8_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 4. "EP8_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0. "EP8_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0x130++0x03
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line.long 0x00 "USB_FUNC_EP8_PCKT_ADRS,This register indicates the number of bytes received in the EP8 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP8_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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newline
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP8_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0x134++0x03
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line.long 0x00 "USB_FUNC_EP8_LEN_DCNT,This register indicates the number of bytes received in the EP8 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP8_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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newline
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP8_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0x138++0x03
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line.long 0x00 "USB_FUNC_EP8_READ,This register is used as a reception buffer for endpoint 8"
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hexmask.long.byte 0x00 24.--31. 1. "EP8_RDATA4,Data received at endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP8_RDATA3,Data received at endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP8_RDATA2,Data received at endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP8_RDATA1,Data received at endpoint 0"
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wgroup.long 0x13C++0x03
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line.long 0x00 "USB_FUNC_EP8_WRITE,This register is used as a transmission buffer for endpoint 8"
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hexmask.long.byte 0x00 24.--31. 1. "EP8_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP8_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP8_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP8_WDATA1,Data transmitted from endpoint 0"
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group.long 0x140++0x03
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line.long 0x00 "USB_FUNC_EP9_CONTROL,This register is used to control endpoint 9"
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bitfld.long 0x00 31. "EP9_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP9_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP9_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP9_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 17. "EP9_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP9_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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newline
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "EP9_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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newline
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bitfld.long 0x00 10. "EP9_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
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bitfld.long 0x00 9. "EP9_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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newline
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bitfld.long 0x00 8. "EP9_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP9_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP9_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP9_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP9_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP9_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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newline
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0. "EP9_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0x144++0x03
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line.long 0x00 "USB_FUNC_EP9_STATUS,This register indicates the source of an interrupt related to endpoint 9 among the sources of interrupts output from the U2F_EPC_INT pin"
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bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP9_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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newline
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bitfld.long 0x00 28. "EP9_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP9_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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newline
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bitfld.long 0x00 26. "EP9_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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newline
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bitfld.long 0x00 24. "EP9_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP9_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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newline
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bitfld.long 0x00 22. "EP9_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP9_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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newline
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bitfld.long 0x00 20. "EP9_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP9_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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newline
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bitfld.long 0x00 18. "EP9_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP9_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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newline
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bitfld.long 0x00 16. "EP9_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 10. "EP9_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP9_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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newline
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bitfld.long 0x00 8. "EP9_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP9_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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newline
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP9_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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newline
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bitfld.long 0x00 4. "EP9_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP9_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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newline
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bitfld.long 0x00 2. "EP9_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP9_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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newline
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bitfld.long 0x00 0. "EP9_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0x148++0x03
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line.long 0x00 "USB_FUNC_EP9_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP9 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP9_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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newline
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bitfld.long 0x00 22. "EP9_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP9_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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newline
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bitfld.long 0x00 20. "EP9_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 19. "EP9_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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newline
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bitfld.long 0x00 18. "EP9_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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newline
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bitfld.long 0x00 7. "EP9_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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newline
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bitfld.long 0x00 5. "EP9_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 4. "EP9_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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newline
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bitfld.long 0x00 3. "EP9_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x14C++0x03
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line.long 0x00 "USB_FUNC_EP9_DMA_CTRL,This register is used to set up DMA at endpoint 9"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP9_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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newline
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bitfld.long 0x00 10. "EP9_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP9_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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newline
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bitfld.long 0x00 8. "EP9_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 4. "EP9_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0. "EP9_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0x150++0x03
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line.long 0x00 "USB_FUNC_EP9_PCKT_ADRS,This register indicates the number of bytes received in the EP9 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP9_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP9_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0x154++0x03
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line.long 0x00 "USB_FUNC_EP9_LEN_DCNT,This register indicates the number of bytes received in the EP9 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP9_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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newline
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP9_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0x158++0x03
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line.long 0x00 "USB_FUNC_EP9_READ,This register is used as a reception buffer for endpoint 9"
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hexmask.long.byte 0x00 24.--31. 1. "EP9_RDATA4,Data received at endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP9_RDATA3,Data received at endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP9_RDATA2,Data received at endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP9_RDATA1,Data received at endpoint 0"
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wgroup.long 0x15C++0x03
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line.long 0x00 "USB_FUNC_EP9_WRITE,This register is used as a transmission buffer for endpoint 9"
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|
hexmask.long.byte 0x00 24.--31. 1. "EP9_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP9_WDATA3,Data transmitted from endpoint 0"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "EP9_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP9_WDATA1,Data transmitted from endpoint 0"
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group.long 0x160++0x03
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line.long 0x00 "USB_FUNC_EP10_CONTROL,This register is used to control endpoint 10"
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bitfld.long 0x00 31. "EP10_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP10_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP10_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP10_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP10_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP10_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "EP10_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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bitfld.long 0x00 10. "EP10_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
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bitfld.long 0x00 9. "EP10_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP10_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP10_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP10_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP10_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP10_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP10_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0. "EP10_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0x164++0x03
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line.long 0x00 "USB_FUNC_EP10_STATUS,This register indicates the source of an interrupt related to endpoint 10 among the sources of interrupts output from the U2F_EPC_INT pin"
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bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP10_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP10_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP10_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP10_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24. "EP10_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP10_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP10_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP10_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP10_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP10_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP10_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP10_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP10_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP10_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP10_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP10_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP10_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP10_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP10_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP10_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP10_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP10_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP10_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0x168++0x03
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line.long 0x00 "USB_FUNC_EP10_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP10 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP10_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP10_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP10_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 20. "EP10_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 19. "EP10_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 18. "EP10_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "EP10_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP10_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 4. "EP10_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 3. "EP10_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x16C++0x03
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line.long 0x00 "USB_FUNC_EP10_DMA_CTRL,This register is used to set up DMA at endpoint 10"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP10_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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bitfld.long 0x00 10. "EP10_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP10_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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bitfld.long 0x00 8. "EP10_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "EP10_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "EP10_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0x170++0x03
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line.long 0x00 "USB_FUNC_EP10_PCKT_ADRS,EP10 max packet & base address register"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP10_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP10_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0x174++0x03
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line.long 0x00 "USB_FUNC_EP10_LEN_DCNT,This register indicates the number of bytes received in the EP10 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP10_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP10_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0x178++0x03
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line.long 0x00 "USB_FUNC_EP10_READ,This register is used as a reception buffer for endpoint 10"
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hexmask.long.byte 0x00 24.--31. 1. "EP10_RDATA4,Data received at endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP10_RDATA3,Data received at endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP10_RDATA2,Data received at endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP10_RDATA1,Data received at endpoint 0"
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wgroup.long 0x17C++0x03
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line.long 0x00 "USB_FUNC_EP10_WRITE,This register is used as a transmission buffer for endpoint 10"
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hexmask.long.byte 0x00 24.--31. 1. "EP10_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP10_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP10_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP10_WDATA1,Data transmitted from endpoint 0"
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group.long 0x180++0x03
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line.long 0x00 "USB_FUNC_EP11_CONTROL,This register is used to control endpoint 11"
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bitfld.long 0x00 31. "EP11_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP11_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP11_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP11_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP11_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP11_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "EP11_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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bitfld.long 0x00 10. "EP11_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
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bitfld.long 0x00 9. "EP11_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP11_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP11_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP11_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP11_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP11_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP11_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0. "EP11_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0x184++0x03
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line.long 0x00 "USB_FUNC_EP11_STATUS,This register indicates the source of an interrupt related to endpoint 11 among the sources of interrupts output from the U2F_EPC_INT pin"
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bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP11_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP11_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP11_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP11_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24. "EP11_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP11_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP11_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP11_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP11_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP11_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP11_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP11_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP11_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP11_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP11_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP11_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP11_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP11_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP11_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP11_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP11_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP11_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP11_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0x188++0x03
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line.long 0x00 "USB_FUNC_EP11_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP11 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP11_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP11_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP11_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 20. "EP11_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 19. "EP11_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 18. "EP11_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "EP11_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP11_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 4. "EP11_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 3. "EP11_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x18C++0x03
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line.long 0x00 "USB_FUNC_EP11_DMA_CTRL,This register is used to set up DMA at endpoint 11"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP11_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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bitfld.long 0x00 10. "EP11_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP11_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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bitfld.long 0x00 8. "EP11_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "EP11_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "EP11_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0x190++0x03
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line.long 0x00 "USB_FUNC_EP11_PCKT_ADRS,This register indicates the number of bytes received in the EP11 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP11_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP11_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0x194++0x03
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line.long 0x00 "USB_FUNC_EP11_LEN_DCNT,This register indicates the number of bytes received in the EP11 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP11_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP11_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0x198++0x03
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line.long 0x00 "USB_FUNC_EP11_READ,This register is used as a reception buffer for endpoint 11"
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hexmask.long.byte 0x00 24.--31. 1. "EP11_RDATA4,Data received at endpoint 11"
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hexmask.long.byte 0x00 16.--23. 1. "EP11_RDATA3,Data received at endpoint 11"
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hexmask.long.byte 0x00 8.--15. 1. "EP11_RDATA2,Data received at endpoint 11"
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hexmask.long.byte 0x00 0.--7. 1. "EP11_RDATA1,Data received at endpoint 11"
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wgroup.long 0x19C++0x03
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line.long 0x00 "USB_FUNC_EP11_WRITE,This register is used as a transmission buffer for endpoint 11"
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hexmask.long.byte 0x00 24.--31. 1. "EP11_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP11_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP11_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP11_WDATA1,Data transmitted from endpoint 0"
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group.long 0x1A0++0x03
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line.long 0x00 "USB_FUNC_EP12_CONTROL,This register is used to control endpoint 12"
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bitfld.long 0x00 31. "EP12_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP12_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP12_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP12_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP12_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP12_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "EP12_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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bitfld.long 0x00 10. "EP12_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
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bitfld.long 0x00 9. "EP12_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP12_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP12_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP12_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP12_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP12_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP12_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0. "EP12_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0x1A4++0x03
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line.long 0x00 "USB_FUNC_EP12_STATUS,This register indicates the source of an interrupt related to endpoint 12 among the sources of interrupts output from the U2F_EPC_INT pin"
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bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP12_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP12_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP12_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP12_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24. "EP12_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP12_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP12_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP12_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP12_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP12_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP12_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP12_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP12_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP12_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP12_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP12_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP12_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP12_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP12_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP12_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP12_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP12_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP12_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0x1A8++0x03
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line.long 0x00 "USB_FUNC_EP12_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP12 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP12_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP12_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 21. "EP12_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 20. "EP12_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
|
|
bitfld.long 0x00 19. "EP12_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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|
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bitfld.long 0x00 18. "EP12_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "EP12_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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|
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bitfld.long 0x00 5. "EP12_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 4. "EP12_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 3. "EP12_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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|
group.long 0x1AC++0x03
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|
line.long 0x00 "USB_FUNC_EP12_DMA_CTRL,This register is used to set up DMA at endpoint 12"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP12_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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bitfld.long 0x00 10. "EP12_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP12_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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bitfld.long 0x00 8. "EP12_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "EP12_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "EP12_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0x1B0++0x03
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line.long 0x00 "USB_FUNC_EP12_PCKT_ADRS,This register indicates the number of bytes received in the EP12 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP12_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
hexmask.long.word 0x00 0.--10. 1. "EP12_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0x1B4++0x03
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line.long 0x00 "USB_FUNC_EP12_LEN_DCNT,This register indicates the number of bytes received in the EP12 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP12_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP12_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0x1B8++0x03
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line.long 0x00 "USB_FUNC_EP12_READ,This register is used as a reception buffer for endpoint 12"
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hexmask.long.byte 0x00 24.--31. 1. "EP12_RDATA4,Data received at endpoint 12"
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hexmask.long.byte 0x00 16.--23. 1. "EP12_RDATA3,Data received at endpoint 12"
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hexmask.long.byte 0x00 8.--15. 1. "EP12_RDATA2,Data received at endpoint 12"
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hexmask.long.byte 0x00 0.--7. 1. "EP12_RDATA1,Data received at endpoint 12"
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wgroup.long 0x1BC++0x03
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line.long 0x00 "USB_FUNC_EP12_WRITE,This register is used as a transmission buffer for endpoint 12"
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hexmask.long.byte 0x00 24.--31. 1. "EP12_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP12_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP12_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP12_WDATA1,Data transmitted from endpoint 0"
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group.long 0x1C0++0x03
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line.long 0x00 "USB_FUNC_EP13_CONTROL,This register is used to control endpoint 13"
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bitfld.long 0x00 31. "EP13_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP13_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP13_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP13_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP13_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP13_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "EP13_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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bitfld.long 0x00 10. "EP13_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
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bitfld.long 0x00 9. "EP13_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP13_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP13_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP13_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP13_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP13_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP13_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0. "EP13_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0x1C4++0x03
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line.long 0x00 "USB_FUNC_EP13_STATUS,This register indicates the source of an interrupt related to endpoint 13 among the sources of interrupts output from the U2F_EPC_INT pin"
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bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP13_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP13_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP13_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP13_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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newline
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bitfld.long 0x00 24. "EP13_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP13_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP13_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP13_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP13_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP13_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP13_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP13_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP13_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP13_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP13_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP13_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP13_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP13_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP13_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP13_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP13_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP13_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP13_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0x1C8++0x03
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line.long 0x00 "USB_FUNC_EP13_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP13 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP13_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP13_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP13_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 20. "EP13_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 19. "EP13_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 18. "EP13_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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newline
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bitfld.long 0x00 7. "EP13_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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newline
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bitfld.long 0x00 5. "EP13_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 4. "EP13_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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newline
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bitfld.long 0x00 3. "EP13_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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|
bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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|
group.long 0x1CC++0x03
|
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line.long 0x00 "USB_FUNC_EP13_DMA_CTRL,This register is used to set up DMA at endpoint 13"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP13_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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bitfld.long 0x00 10. "EP13_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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|
bitfld.long 0x00 9. "EP13_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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newline
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bitfld.long 0x00 8. "EP13_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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|
bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 4. "EP13_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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|
bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0. "EP13_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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|
group.long 0x1D0++0x03
|
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line.long 0x00 "USB_FUNC_EP13_PCKT_ADRS,This register indicates the number of bytes received in the EP13 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
|
|
bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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|
hexmask.long.word 0x00 16.--28. 1. "EP13_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
hexmask.long.word 0x00 0.--10. 1. "EP13_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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|
group.long 0x1D4++0x03
|
|
line.long 0x00 "USB_FUNC_EP13_LEN_DCNT,This register indicates the number of bytes received in the EP13 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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|
hexmask.long.byte 0x00 16.--23. 1. "EP13_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
hexmask.long.word 0x00 0.--10. 1. "EP13_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0x1D8++0x03
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line.long 0x00 "USB_FUNC_EP13_READ,This register is used as a reception buffer for endpoint 13"
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|
hexmask.long.byte 0x00 24.--31. 1. "EP13_RDATA4,Data received at endpoint 13"
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hexmask.long.byte 0x00 16.--23. 1. "EP13_RDATA3,Data received at endpoint 13"
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hexmask.long.byte 0x00 8.--15. 1. "EP13_RDATA2,Data received at endpoint 13"
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hexmask.long.byte 0x00 0.--7. 1. "EP13_RDATA1,Data received at endpoint 13"
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wgroup.long 0x1DC++0x03
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|
line.long 0x00 "USB_FUNC_EP13_WRITE,This register is used as a transmission buffer for endpoint 13"
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|
hexmask.long.byte 0x00 24.--31. 1. "EP13_WDATA4,Data transmitted from endpoint 0"
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|
hexmask.long.byte 0x00 16.--23. 1. "EP13_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP13_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP13_WDATA1,Data transmitted from endpoint 0"
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group.long 0x1E0++0x03
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line.long 0x00 "USB_FUNC_EP14_CONTROL,This register is used to control endpoint 14"
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bitfld.long 0x00 31. "EP14_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
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bitfld.long 0x00 30. "EP14_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26. "EP14_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP14_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
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bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP14_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
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bitfld.long 0x00 16. "EP14_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "EP14_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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bitfld.long 0x00 10. "EP14_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
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bitfld.long 0x00 9. "EP14_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP14_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
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bitfld.long 0x00 7. "EP14_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP14_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
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bitfld.long 0x00 4. "EP14_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP14_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP14_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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|
bitfld.long 0x00 0. "EP14_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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|
group.long 0x1E4++0x03
|
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line.long 0x00 "USB_FUNC_EP14_STATUS,This register indicates the source of an interrupt related to endpoint 14 among the sources of interrupts output from the U2F_EPC_INT pin"
|
|
bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 29. "EP14_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP14_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP14_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP14_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24. "EP14_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP14_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP14_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP14_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP14_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP14_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP14_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP14_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP14_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP14_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP14_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP14_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP14_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP14_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP14_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP14_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP14_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP14_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP14_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0x1E8++0x03
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line.long 0x00 "USB_FUNC_EP14_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP14 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP14_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP14_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP14_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 20. "EP14_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 19. "EP14_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 18. "EP14_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "EP14_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP14_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 4. "EP14_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 3. "EP14_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x1EC++0x03
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line.long 0x00 "USB_FUNC_EP14_DMA_CTRL,This register is used to set up DMA at endpoint 14"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP14_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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bitfld.long 0x00 10. "EP14_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP14_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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bitfld.long 0x00 8. "EP14_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "EP14_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0. "EP14_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0x1F0++0x03
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line.long 0x00 "USB_FUNC_EP14_PCKT_ADRS,This register indicates the number of bytes received in the EP14 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP14_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP14_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0x1F4++0x03
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line.long 0x00 "USB_FUNC_EP14_LEN_DCNT,This register indicates the number of bytes received in the EP14 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP14_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP14_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0x1F8++0x03
|
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line.long 0x00 "USB_FUNC_EP14_READ,This register is used as a reception buffer for endpoint 14"
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hexmask.long.byte 0x00 24.--31. 1. "EP14_RDATA4,Data received at endpoint 14"
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hexmask.long.byte 0x00 16.--23. 1. "EP14_RDATA3,Data received at endpoint 14"
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hexmask.long.byte 0x00 8.--15. 1. "EP14_RDATA2,Data received at endpoint 14"
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|
hexmask.long.byte 0x00 0.--7. 1. "EP14_RDATA1,Data received at endpoint 14"
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wgroup.long 0x1FC++0x03
|
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line.long 0x00 "USB_FUNC_EP14_WRITE,This register is used as a transmission buffer for endpoint 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EP14_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP14_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP14_WDATA2,Data transmitted from endpoint 0"
|
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hexmask.long.byte 0x00 0.--7. 1. "EP14_WDATA1,Data transmitted from endpoint 0"
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group.long 0x200++0x03
|
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line.long 0x00 "USB_FUNC_EP15_CONTROL,This register is used to control endpoint 15"
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|
bitfld.long 0x00 31. "EP15_EN,Specify whether to enable or disable endpoint n" "0: Disable endpoint n,1: Enable endpoint n"
|
|
bitfld.long 0x00 30. "EP15_BUF_TYPE,Indicates the type of EPn buffering" "0: Single buffering,1: Double buffering"
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bitfld.long 0x00 27.--29. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "EP15_DIR0,Specify the direction of transfer at endpoint n" "0: Input,1: Output"
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bitfld.long 0x00 24.--25. "EP15_MODE,Indicates the type of transfer performed at endpoint n" "0: Bulk,1: Interrupt,2: Isochronous,3: Reserved"
|
|
bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "EP15_OVERSEL,Select the operation when an overrun occurs during an OUT transfer and an OUT is subsequently received" "0: Return a STALL for the next packet,1: Handle the next packet as a retry"
|
|
bitfld.long 0x00 16. "EP15_AUTO,Select whether to automatically send a packet when a packet of the maximum packet size (64 bytes) is written to the EPn write register (transmission buffer)" "0: Do not set bit 7 (EPn_DEND) automatically,1: Set bit 7 (EPn_DEND) automatically"
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. "EP15_IPIDCLR,Write 1b to this bit to initialize the transmission data PID for endpoint n" "0,1"
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|
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bitfld.long 0x00 10. "EP15_OPIDCLR,Write 1b to this bit to initialize the reception data PID for endpoint n" "0,1"
|
|
bitfld.long 0x00 9. "EP15_BCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on both the USB and CPU sides" "0,1"
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bitfld.long 0x00 8. "EP15_CBCLR,Write 1b to this bit to clear the EPn write and EPn read registers (transmission and reception buffers) on the CPU side" "0,1"
|
|
bitfld.long 0x00 7. "EP15_DEND,Write 1b to this bit to enable transmission of the data written to the EPn write register (transmission buffer)" "0,1"
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bitfld.long 0x00 5.--6. "EP15_DW,Specify the number of valid bytes that were written last to the EPn write register (transmission buffer)" "0: 4,1: 1,2: 2,3: 3"
|
|
bitfld.long 0x00 4. "EP15_OSTL_EN,Write 1b to this bit to enable writing to bit 2 (EPn_OSTL)" "0,1"
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bitfld.long 0x00 3. "EP15_ISTL,Specify whether to return a STALL in response to an IN token for endpoint n" "0: Do not return a STALL in response to an IN..,1: Return a STALL in response to an IN token"
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bitfld.long 0x00 2. "EP15_OSTL,Specify whether to return a STALL in response to OUT or PING tokens for endpoint n" "0: Do not return a STALL in response to an OUT or,1: Return a STALL in response to an OUT or PING.."
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bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0. "EP15_ONAK,Use this bit to control the NAK returned in response to an OUT or PING token for endpoint n" "0: Receive data if there is available space in the,1: Return a NAK even if there is available space.."
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group.long 0x204++0x03
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line.long 0x00 "USB_FUNC_EP15_STATUS,This register indicates the source of an interrupt related to endpoint 15 among the sources of interrupts output from the U2F_EPC_INT pin"
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bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 29. "EP15_ISO_PIDERR,Indicates whether endpoint n has received an invalid data PID during an isochronous transfer" "0: No invalid data PID has been received,1: An invalid data PID was received"
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bitfld.long 0x00 28. "EP15_OPID,Indicates the value of the normal data PID to be received next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 27. "EP15_OUT_NOTKN,This bit is set to 1b if no OUT tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An OUT token was received,1: No OUT tokens have been received"
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bitfld.long 0x00 26. "EP15_ISO_OR,This bit is set to 1b when OUT data is received at endpoint n during an isochronous transfer but the data is discarded because no space is available in the EPn read register" "0: No OUT data has been discarded,1: The received OUT data was discarded"
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bitfld.long 0x00 25. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24. "EP15_ISO_CRC,This bit is set to 1b if the data received at endpoint n during an isochronous transfer includes a CRC error" "0: The received data does not include a CRC error,1: The received data includes a CRC error"
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bitfld.long 0x00 23. "EP15_OUT_END_INT,This bit is set to 1b when an OUT-direction DMA transfer to read the buffer at endpoint n completes" "0: A DMA transfer to read the buffer is in..,1: A DMA transfer to read the buffer has completed"
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bitfld.long 0x00 22. "EP15_OUT_OR_INT,This bit is set to 1b if an overrun occurs while data is being received at endpoint n" "0: No overrun has occurred,1: An overrun occurred"
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bitfld.long 0x00 21. "EP15_OUT_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an OUT or PING token during an interrupt or bulk transfer" "0: No reception error has occurred,1: A reception error occurred"
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bitfld.long 0x00 20. "EP15_OUT_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 1b (OUT direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 19. "EP15_OUT_INT,This bit is set to 1b when data other than normally received null data is stored in the EPn read register (reception buffer) and the data can be read from the buffer on the CPU side" "0: Data cannot be read from the reception buffer,1: Data can be read from the reception buffer"
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bitfld.long 0x00 18. "EP15_OUT_NULL_INT,This bit is set to 1b when null data is received and stored in the EPn read register (reception buffer) normally" "0: Null data has not been received,1: Null data was received"
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bitfld.long 0x00 17. "EP15_OUT_FULL,This bit is set to 1b if the EPn read register (reception buffer) is full" "0: The reception buffer is not full,1: The reception buffer is full"
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bitfld.long 0x00 16. "EP15_OUT_EMPTY,This bit is set to 1b if the EPn read register (reception buffer) is empty" "0: The reception buffer is not empty,1: The reception buffer is empty"
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bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "EP15_IPID,Indicates the value of the data PID to be sent next" "0: DATA0,1: DATA1"
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bitfld.long 0x00 9. "EP15_IN_NOTKN,This bit is set to 1b if no IN tokens are received at endpoint n in the interval between SOF or uSOF packets received during an isochronous transfer" "0: An IN token was received,1: No IN tokens have been received"
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bitfld.long 0x00 8. "EP15_ISO_UR,This bit is set to 1b when an IN token is received and null data is sent at endpoint n before data is written to the EPn write register (transmission buffer) during an isochronous transfer" "0: Null data has not been sent,1: Null data was sent"
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bitfld.long 0x00 7. "EP15_IN_END_INT,This bit is set to 1b when an IN-direction DMA transfer to write to the buffer at endpoint n completes" "0: A DMA transfer to write to the buffer is in,1: A DMA transfer to write to the buffer has"
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bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP15_IN_NAK_ERR_INT,This bit is set to 1b when a NAK is sent from endpoint n in response to an IN token during an interrupt or bulk transfer" "0: No transmission error has occurred,1: A transmission error occurred"
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bitfld.long 0x00 4. "EP15_IN_STALL_INT,This bit is set to 1b when processing at endpoint n is stalled while bit 26 (EPn_DIR0) of the USB control register is 0b (IN direction)" "0: Processing at endpoint n is not stalled,1: Processing at endpoint n is stalled"
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bitfld.long 0x00 3. "EP15_IN_INT,This bit is set to 1b when data in the EPn write register (transmission buffer) has been sent normally and the next data can be written to the buffer on the CPU side" "0: Data cannot be written to the transmission..,1: Data can be written to the transmission buffer"
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bitfld.long 0x00 2. "EP15_IN_DATA,This bit is set to 1b if there is data to be sent in the EPn write register (transmission buffer)" "0: Data to be sent does not exist in the,1: Data to be sent exists in the transmission.."
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bitfld.long 0x00 1. "EP15_IN_FULL,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes full" "0: The transmission buffer is not full,1: The transmission buffer is full"
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bitfld.long 0x00 0. "EP15_IN_EMPTY,This bit is set to 1b when the EPn write register (transmission buffer) on the CPU side becomes empty" "0: The transmission buffer is not empty,1: The transmission buffer is empty"
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group.long 0x208++0x03
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line.long 0x00 "USB_FUNC_EP15_INT_ENA,This register is used to specify whether to enable or disable the interrupt sources assigned to the EP15 status register"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 23. "EP15_OUT_END_EN,Specify whether to enable bit 23 (EPn_OUT_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 22. "EP15_OUT_OR_EN,Specify whether to enable bit 22 (EPn_OUT_OR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 21. "EP15_OUT_NAK_ERR_EN,Specify whether to enable bit 21 (EPn_OUT_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 20. "EP15_OUT_STALL_EN,Specify whether to enable bit 20 (EPn_OUT_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 19. "EP15_OUT_EN,Specify whether to enable bit 19 (EPn_OUT_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 18. "EP15_OUT_NULL_EN,Specify whether to enable bit 18 (EPn_OUT_NULL_INT) of the EPn status register" "0: Disable,1: Enable"
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hexmask.long.word 0x00 8.--17. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "EP15_IN_END_EN,Specify whether to enable bit 7 (EPn_IN_END_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5. "EP15_IN_NAK_ERR_EN,Specify whether to enable bit 5 (EPn_IN_NAK_ERR_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 4. "EP15_IN_STALL_EN,Specify whether to enable bit 4 (EPn_IN_STALL_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 3. "EP15_IN_EN,Specify whether to enable bit 3 (EPn_IN_INT) of the EPn status register" "0: Disable,1: Enable"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x20C++0x03
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line.long 0x00 "USB_FUNC_EP15_DMA_CTRL,This register is used to set up DMA at endpoint 15"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "EP15_STOP_MODE,Specify the DMA stop conditions when bit 8 (EPn_STOP_SET) is 1b" "0: DMA transfer stops when a short packet is,1: DMA transfer stops when a short packet is"
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bitfld.long 0x00 10. "EP15_DEND_SET,Specify whether to enable setting bit 7 (EPn_DEND) of the EPn control register to 1b when a DMA completion signal sent from the AHB-EPC bridge is received during an IN transaction (when bit 26 (EPn_DIR0) of the USB control register is 0)" "0: Disable,1: Enable"
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bitfld.long 0x00 9. "EP15_BURST_SET,Specify whether to enable clearing bit 4 (EPn_DMA_EN) to 0b each time one packet is transferred by using DMA" "0: Disable,1: Enable"
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bitfld.long 0x00 8. "EP15_STOP_SET,Select whether to clear bit 4 (EPn_DMA_EN) 0b and send the DMA completion signal to the AHB-EPC bridge to stop a DMA transfer if a short packet that includes null data is received while bit 26 (EPn_DIR0) of the USB control register is 1b.." "0: Do not clear bit 4 (EPn_DMA_EN) and do not send,1: Clear bit 4 (EPn_DMA_EN) and send the DMA"
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bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "EP15_DMA_EN,Specify whether to use DMA at endpoint n" "0: Do not use DMA,1: Use DMA"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0. "EP15_DMAMODE0,Select the DMA mode" "0: Single mode,1: Demand mode"
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group.long 0x210++0x03
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line.long 0x00 "USB_FUNC_EP15_PCKT_ADRS,This register indicates the number of bytes received in the EP15 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--28. 1. "EP15_BASEAD,Specify the address to which the buffers of endpoint n are mapped to the RAM"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP15_MPKT,Specify the maximum packet size to be transferred at endpoint n"
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group.long 0x214++0x03
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line.long 0x00 "USB_FUNC_EP15_LEN_DCNT,This register indicates the number of bytes received in the EP15 read register (reception buffer) and is used to specify the number of packets to be sent by DMA"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "EP15_DMACNT,Specify the number of packets to be transferred successively by using DMA (burst DMA transfer)"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--10. 1. "EP15_LDATA,Indicates the number of bytes stored in the EPn read register (reception buffer) on the CPU side that are ready to be read"
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rgroup.long 0x218++0x03
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line.long 0x00 "USB_FUNC_EP15_READ,This register is used as a reception buffer for endpoint 15"
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hexmask.long.byte 0x00 24.--31. 1. "EP15_RDATA4,Data received at endpoint 15"
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hexmask.long.byte 0x00 16.--23. 1. "EP15_RDATA3,Data received at endpoint 15"
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hexmask.long.byte 0x00 8.--15. 1. "EP15_RDATA2,Data received at endpoint 15"
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hexmask.long.byte 0x00 0.--7. 1. "EP15_RDATA1,Data received at endpoint 15"
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wgroup.long 0x21C++0x03
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line.long 0x00 "USB_FUNC_EP15_WRITE,This register is used as a transmission buffer for endpoint 15"
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hexmask.long.byte 0x00 24.--31. 1. "EP15_WDATA4,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 16.--23. 1. "EP15_WDATA3,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 8.--15. 1. "EP15_WDATA2,Data transmitted from endpoint 0"
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hexmask.long.byte 0x00 0.--7. 1. "EP15_WDATA1,Data transmitted from endpoint 0"
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group.long 0x1000++0x03
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line.long 0x00 "USB_FUNC_AHBSCTR,This register is used to set up the AHB slave features of the function controller"
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hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 0. "WAIT_MODE,Control the wait operation when the subsystem is operating as an AHB slave" "0,1"
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group.long 0x1004++0x03
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line.long 0x00 "USB_FUNC_AHBMCTR,This register is used to set up the AHB master features of the function controller"
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bitfld.long 0x00 31. "ARBITER_CTR,Select the arbitration method for the endpoint that is the target of DMA transfer" "0,1"
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hexmask.long.tbyte 0x00 13.--30. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 12. "MCYCLE_RST,Set this bit to 1 to reset the cycle if the cycle for AHB has entered an infinite loop due to retry or split processing" "0,1"
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bitfld.long 0x00 10.--11. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 8.--9. "ENDIAN_CTR,Select the data conversion method when performing DMA transfer" "0,1,2,3"
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bitfld.long 0x00 3.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 2. "WBURST_TYPE,Specify the conditions for using variable-length burst transfer when the AHB master transfer write data" "0,1"
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bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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group.long 0x1008++0x03
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line.long 0x00 "USB_FUNC_AHBBINT,This register indicates the source of interrupts to the AHB-EPC bridge"
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bitfld.long 0x00 31. "DMA_ENDINT_EP15,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 30. "DMA_ENDINT_EP14,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 29. "DMA_ENDINT_EP13,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 28. "DMA_ENDINT_EP12,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 27. "DMA_ENDINT_EP11,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 26. "DMA_ENDINT_EP10,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 25. "DMA_ENDINT_EP9,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 24. "DMA_ENDINT_EP8,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 23. "DMA_ENDINT_EP7,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 22. "DMA_ENDINT_EP6,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 21. "DMA_ENDINT_EP5,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 20. "DMA_ENDINT_EP4,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 19. "DMA_ENDINT_EP3,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 18. "DMA_ENDINT_EP2,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 17. "DMA_ENDINT_EP1,When a DMA transfer completes the bit corresponding to the relevant endpoint number is set to 1b" "0,1"
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bitfld.long 0x00 14.--16. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 13. "VBUS_INT,Indicates that the VBUS signal level has changed" "0,1"
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bitfld.long 0x00 7.--12. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "MBUS_ERRINT,ndicates whether an error response was received during AHB master operation" "0,1"
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bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 4. "SBUS_ERRINT0,Indicates whether an error was returned in response to an AHB slave access in 32-bit or larger units" "0,1"
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bitfld.long 0x00 0.--3. "ERR_MASTER,Use this field to store the number of the master that returned an error when bit 4 (SBUS_ERRINT0) is 1b" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x100C++0x03
|
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line.long 0x00 "USB_FUNC_AHBBINTEN,This register is used to specify whether to enable or disable the interrupt sources assigned to the AHBBINT register"
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bitfld.long 0x00 31. "DMA_ENDINTEN_EP15,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
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bitfld.long 0x00 30. "DMA_ENDINTEN_EP14,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
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bitfld.long 0x00 29. "DMA_ENDINTEN_EP13,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
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|
bitfld.long 0x00 28. "DMA_ENDINTEN_EP12,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
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bitfld.long 0x00 27. "DMA_ENDINTEN_EP11,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
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bitfld.long 0x00 26. "DMA_ENDINTEN_EP10,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
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bitfld.long 0x00 25. "DMA_ENDINTEN_EP9,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
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bitfld.long 0x00 24. "DMA_ENDINTEN_EP8,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
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bitfld.long 0x00 23. "DMA_ENDINTEN_EP7,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
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|
bitfld.long 0x00 22. "DMA_ENDINTEN_EP6,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
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bitfld.long 0x00 21. "DMA_ENDINTEN_EP5,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
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|
bitfld.long 0x00 20. "DMA_ENDINTEN_EP4,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
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bitfld.long 0x00 19. "DMA_ENDINTEN_EP3,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
|
|
bitfld.long 0x00 18. "DMA_ENDINTEN_EP2,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
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bitfld.long 0x00 17. "DMA_ENDINTEN_EP1,Specify whether to enable bits 31 to 17 (DMA_ENDINT) of the AHBBINT register" "0,1"
|
|
bitfld.long 0x00 14.--16. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 13. "VBUS_INTEN,Specify whether to enable bit 13 (VBUS_INT) of the AHBBINT register" "0,1"
|
|
bitfld.long 0x00 7.--12. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6. "MBUS_ERRINTEN,Specify whether to enable bit 6 (MBUS_ERRINT) of the AHBBINT register" "0,1"
|
|
bitfld.long 0x00 5. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SBUS_ERRINT0EN,Specify whether to enable bit 4 (SBUS_ERRINT0) of the AHBBINT register" "0,1"
|
|
bitfld.long 0x00 0.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1010++0x03
|
|
line.long 0x00 "USB_FUNC_EPCTR,This register is used to specify various items for controlling the EPC and transceiver"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align4,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 12. "DIRPD,Set this bit to 1b to set the direct power-down mode" "0: Normal operation,1: Direct power-down mode"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. "VBUS_LEVEL,Indicates the status of the VBUS input pin" "0: VBUS = 0,1: VBUS = 1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 5. "PLL_RESUME,When the clock supply to the function controller has been stopped while the SIE is in the Suspend state set this bit to 1b to resume clock supply" "0: Normal operation,1: Resume clock supply"
|
|
newline
|
|
bitfld.long 0x00 4. "PLL_LOCK,Indicates whether the PLL circuit has been locked up" "0: The PLL has not been locked up,1: The PLL has been locked up"
|
|
bitfld.long 0x00 3. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PLL_RST,Control the reset signal to be issued to the PLL" "0: Cancel PLL reset,1: Issue PLL reset"
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "EPC_RST,Control the reset signal to be issued to the EPC block" "0: Deassert the EPC reset signal,1: Issue the EPC reset signal"
|
|
rgroup.long 0x1020++0x03
|
|
line.long 0x00 "USB_FUNC_USBSSVER,This register indicates the versions of the implemented macros and USB function controller"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AHBB_VER,Indicates the AHB bridge version"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "EPC_VER,Indicates the EPC version"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SS_VER,Indicates the USB function controller version"
|
|
rgroup.long 0x1024++0x03
|
|
line.long 0x00 "USB_FUNC_USBSSCONF,This register shows the configuration of each endpoint"
|
|
abitfld.long 0x00 16.--31. "EP_AVAILABLE,Indicates the implemented endpoint modules" "0x0000=0: Not available,0x0001=1: Available"
|
|
abitfld.long 0x00 0.--15. "DMA_AVAILABLE,Indicates an endpoint that can be used for DMA transfers" "0x0000=0: Not usable,0x0001=1: Usable"
|
|
group.long 0x1110++0x03
|
|
line.long 0x00 "USB_FUNC_EP1DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP1_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP1_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP1_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x1114++0x03
|
|
line.long 0x00 "USB_FUNC_EP1DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 1"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP1_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP1_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x1118++0x03
|
|
line.long 0x00 "USB_FUNC_EP1TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 1"
|
|
hexmask.long 0x00 0.--31. 1. "EP1_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x1120++0x03
|
|
line.long 0x00 "USB_FUNC_EP2DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP2_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP2_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP2_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x1124++0x03
|
|
line.long 0x00 "USB_FUNC_EP2DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 2"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP2_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP2_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "USB_FUNC_EP2TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 2"
|
|
hexmask.long 0x00 0.--31. 1. "EP2_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x1130++0x03
|
|
line.long 0x00 "USB_FUNC_EP3DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP3_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP3_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP3_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x1134++0x03
|
|
line.long 0x00 "USB_FUNC_EP3DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 3"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP3_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP3_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x1138++0x03
|
|
line.long 0x00 "USB_FUNC_EP3TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 3"
|
|
hexmask.long 0x00 0.--31. 1. "EP3_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x1140++0x03
|
|
line.long 0x00 "USB_FUNC_EP4DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP4_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP4_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP4_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x1144++0x03
|
|
line.long 0x00 "USB_FUNC_EP4DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 4"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP4_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP4_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "USB_FUNC_EP4TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 4"
|
|
hexmask.long 0x00 0.--31. 1. "EP4_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x1150++0x03
|
|
line.long 0x00 "USB_FUNC_EP5DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP5_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP5_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP5_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x1154++0x03
|
|
line.long 0x00 "USB_FUNC_EP5DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 5"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP5_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP5_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x1158++0x03
|
|
line.long 0x00 "USB_FUNC_EP5TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 5"
|
|
hexmask.long 0x00 0.--31. 1. "EP5_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x1160++0x03
|
|
line.long 0x00 "USB_FUNC_EP6DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP6_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP6_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP6_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x1164++0x03
|
|
line.long 0x00 "USB_FUNC_EP6DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 6"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP6_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP6_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "USB_FUNC_EP6TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 6"
|
|
hexmask.long 0x00 0.--31. 1. "EP6_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x1170++0x03
|
|
line.long 0x00 "USB_FUNC_EP7DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP7_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP7_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP7_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x1174++0x03
|
|
line.long 0x00 "USB_FUNC_EP7DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 7"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP7_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP7_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x1178++0x03
|
|
line.long 0x00 "USB_FUNC_EP7TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 7"
|
|
hexmask.long 0x00 0.--31. 1. "EP7_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x1180++0x03
|
|
line.long 0x00 "USB_FUNC_EP8DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 8"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP8_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP8_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP8_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x1184++0x03
|
|
line.long 0x00 "USB_FUNC_EP8DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 8"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP8_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP8_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "USB_FUNC_EP8TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 8"
|
|
hexmask.long 0x00 0.--31. 1. "EP8_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x1190++0x03
|
|
line.long 0x00 "USB_FUNC_EP9DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 9"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP9_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP9_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP9_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x1194++0x03
|
|
line.long 0x00 "USB_FUNC_EP9DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 9"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP9_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP9_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x1198++0x03
|
|
line.long 0x00 "USB_FUNC_EP9TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 9"
|
|
hexmask.long 0x00 0.--31. 1. "EP9_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x11A0++0x03
|
|
line.long 0x00 "USB_FUNC_EP10DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP10_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP10_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP10_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x11A4++0x03
|
|
line.long 0x00 "USB_FUNC_EP10DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 10"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP10_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP10_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "USB_FUNC_EP10TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 10"
|
|
hexmask.long 0x00 0.--31. 1. "EP10_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x11B0++0x03
|
|
line.long 0x00 "USB_FUNC_EP11DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 11"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP11_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP11_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP11_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x11B4++0x03
|
|
line.long 0x00 "USB_FUNC_EP11DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 11"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP11_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP11_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x11B8++0x03
|
|
line.long 0x00 "USB_FUNC_EP11TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 11"
|
|
hexmask.long 0x00 0.--31. 1. "EP11_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x11C0++0x03
|
|
line.long 0x00 "USB_FUNC_EP12DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 12"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP12_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP12_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP12_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x11C4++0x03
|
|
line.long 0x00 "USB_FUNC_EP12DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 12"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP12_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP12_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "USB_FUNC_EP12TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 12"
|
|
hexmask.long 0x00 0.--31. 1. "EP12_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x11D0++0x03
|
|
line.long 0x00 "USB_FUNC_EP13DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 13"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP13_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP13_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP13_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x11D4++0x03
|
|
line.long 0x00 "USB_FUNC_EP13DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 13"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP13_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP13_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x11D8++0x03
|
|
line.long 0x00 "USB_FUNC_EP13TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 13"
|
|
hexmask.long 0x00 0.--31. 1. "EP13_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x11E0++0x03
|
|
line.long 0x00 "USB_FUNC_EP14DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP14_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP14_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP14_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x11E4++0x03
|
|
line.long 0x00 "USB_FUNC_EP14DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 14"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP14_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP14_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "USB_FUNC_EP14TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 14"
|
|
hexmask.long 0x00 0.--31. 1. "EP14_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
group.long 0x11F0++0x03
|
|
line.long 0x00 "USB_FUNC_EP15DCR1,This register is used to specify the parameters related to DMA transfers at endpoint 15"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EP15_DMACNT,Specify the number of packets (not bytes) to be sent by using a DMA transfer"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "EP15_DIR0,Specify the DMA transfer direction" "0: IN direction (from AHB to EPC),1: OUT direction (from EPC to AHB)"
|
|
newline
|
|
bitfld.long 0x00 0. "EP15_REQEN,Specify whether to enable DMA transfer requests from the endpoint controller" "0: Disabled (DMA transfer is disabled),1: Enabled (DMA transfer is enabled)"
|
|
group.long 0x11F4++0x03
|
|
line.long 0x00 "USB_FUNC_EP15DCR2,This register is used to specify the parameters related to DMA transfers at endpoint 15"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "EP15_LMPKT,Indicates or used to specify the number of bytes in the last packet transferred by using DMA"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "EP15_MPKT,Specify the maximum packet size to be transferred at endpoint n"
|
|
group.long 0x11F8++0x03
|
|
line.long 0x00 "USB_FUNC_EP15TADR,This register is used to specify the transfer start address on the AHB bus for DMA transfers at endpoint 15"
|
|
hexmask.long 0x00 0.--31. 1. "EP15_TADR,Specify the transfer start address on the AHB bus for DMA transfers"
|
|
tree.end
|
|
tree "GMAC"
|
|
repeat 2. (list 0. 1.) (list ad:0xF8010000 ad:0xF8014000)
|
|
tree "GMAC$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GMAC_MAC_Configuration,The MAC Configuration Register establishes the operating mode of the MAC"
|
|
bitfld.long 0x00 31. "ARPEN,ARP Offload Enable When this bit is set then in addition to providing status and forwarding the packet to application the transmitter generates an ARP reply for a valid ARP request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--30. "SARC,Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted packets" "?,?,2: - If Bit 30 is set to 0 the MAC inserts the,3: - If Bit 30 is set to 0 the MAC replaces the,?..."
|
|
newline
|
|
bitfld.long 0x00 27. "IPC,Checksum Offload When this bit is set the MAC calculates the 16-bit one's complement of one's complement sum of all received Ethernet packet payloads" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IPG,Inter-Packet Gap These bits control the minimum IPG between packets during transmission" "0: 96 bit times,1: 88 bit times,2: 80 bit times,?,?,?,?,7: 40 bit times In the half-duplex mode the"
|
|
newline
|
|
bitfld.long 0x00 23. "GPSLCE,Giant Packet Size Limit Control Enable When this bit is set the MAC considers the value in GPSL field in MAC_Ext_Configuration register to declare a received packet as Giant packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "S2KP,IEEE 802.3as Support for 2K Packets When this bit is set the MAC considers all packets with up to 2 000 bytes length as normal packets" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "CST,CRC stripping for Type packets When this bit is set the last four bytes (FCS) of all packets of Ether type (type field greater than 1 536) are stripped and dropped before forwarding the packet to the application" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "ACS,Automatic Pad or CRC Stripping When this bit is set the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1 536 bytes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "WD,Watchdog Disable When this bit is set the MAC disables the watchdog timer on the receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "BE,Packet Burst Enable When this bit is set the MAC allows packet bursting during transmission in the GMII half-duplex mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "JD,Jabber Disable When this bit is set the MAC disables the jabber timer on the transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "JE,Jumbo Packet Enable When this bit is set the MAC allows jumbo packets of 9 018 bytes (9 022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "PS,Port Select This bit selects the Ethernet line speed" "0: For 1000 Mbps operations,1: For 10 or 100 Mbps operations In 10 or 100 Mbps"
|
|
newline
|
|
bitfld.long 0x00 14. "FES,Speed This bit selects the speed in the 10/100 Mbps mode" "0: 10 Mbps,1: 100 Mbps In the 1000"
|
|
newline
|
|
bitfld.long 0x00 13. "DM,Duplex Mode When this bit is set the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "LM,Loopback Mode When this bit is set the MAC operates in the loopback mode at GMII or MII" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "DO,Disable Receive Own When this bit is set the MAC disables the reception of packets when the gmii_txen_o is asserted in the half-duplex mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "DCRS,Disable Carrier Sense During Transmission When this bit is set the MAC transmitter ignores the (G)MII CRS signal during packet transmission in the half-duplex mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DR,Disable Retry When this bit is set the MAC attempts only one transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "BL,Back-Off Limit The back-off limit determines the random integer number (r) of slot time delays (4 096 bit times for 1000 Mbps 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a.." "0: k= min (n 10),1: k = min (n 8),2: k = min (n 4),3: k = min (n 1) where - = retransmission"
|
|
newline
|
|
bitfld.long 0x00 4. "DC,Deferral Check When this bit is set the deferral check function is enabled in the MAC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "PRELEN,Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 1. "TE,Transmitter Enable When this bit is set the Tx state machine of the MAC is enabled for transmission on the GMII or MII interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RE,Receiver Enable When this bit is set the Rx state machine of the MAC is enabled for receiving packets from the GMII or MII interface" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GMAC_MAC_Ext_Configuration,The MAC Extended Configuration Register establishes the operating mode of the MAC"
|
|
bitfld.long 0x00 30.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 25.--29. "EIPG,NA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 24. "EIPGEN,NA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "HDSMS,Maximum Size for Splitting the Header Data These bits indicate the maximum header size allowed for splitting the header data in the received packet" "0: 64 bytes,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes - 3'b101-3'b111,?..."
|
|
newline
|
|
bitfld.long 0x00 19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "USP,Unicast Slow Protocol Packet Detect When this bit is set the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC_Address0_High and MAC_Address0_Low registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "SPEN,Slow Protocol Detection Enable When this bit is set MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Rx status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DCRCC,Disable CRC Checking for Received Packets When this bit is set the MAC receiver does not check the CRC field in the received packets" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--13. 1. "GPSL,Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes the MAC declares the received packet as Giant packet"
|
|
group.long 0x08++0x03
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line.long 0x00 "GMAC_MAC_Packet_Filter,The MAC Packet Filter register contains the filter controls for receiving packets"
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bitfld.long 0x00 31. "RA,Receive All When this bit is set the MAC Receiver module passes all received packets to the application irrespective of whether they pass the address filter or not" "0,1"
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hexmask.long.word 0x00 22.--30. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 21. "DNTU,Drop Non-TCP/UDP over IP Packets When this bit is set the MAC drops the non-TCP or UDP over IP packets" "0,1"
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bitfld.long 0x00 20. "IPFE,Layer 3 and Layer 4 Filter Enable When this bit is set the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters" "0,1"
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bitfld.long 0x00 17.--19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "VTFE,VLAN Tag Filter Enable When this bit is set the MAC drops the VLAN tagged packets that do not match the VLAN Tag" "0,1"
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bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "HPF,Hash or Perfect Filter When this bit is set the address filter passes a packet if it matches either the perfect filtering or hash filtering as set by the HMC or HUC bit" "0,1"
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bitfld.long 0x00 9. "SAF,Source Address Filter Enable When this bit is set the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers" "0,1"
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bitfld.long 0x00 8. "SAIF,SA Inverse Filtering When this bit is set the Address Check block operates in the inverse filtering mode for SA address comparison" "0,1"
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bitfld.long 0x00 6.--7. "PCF,Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets)" "0: The MAC filters all control packets from,1: The MAC forwards all control packets except,2: The MAC forwards all control packets to the,3: The MAC forwards the control packets that pass"
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bitfld.long 0x00 5. "DBF,Disable Broadcast Packets When this bit is set the AFM module blocks all incoming broadcast packets" "0,1"
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bitfld.long 0x00 4. "PM,Pass All Multicast When this bit is set it indicates that all received packets with a multicast destination address (first bit in the destination address field is '1') are passed" "0,1"
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bitfld.long 0x00 3. "DAIF,DA Inverse Filtering When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets" "0,1"
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bitfld.long 0x00 2. "HMC,Hash Multicast When this bit is set the MAC performs the destination address filtering of received multicast packets according to the hash table" "0,1"
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bitfld.long 0x00 1. "HUC,Hash Unicast When this bit is set the MAC performs the destination address filtering of unicast packets according to the hash table" "0,1"
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bitfld.long 0x00 0. "PR,Promiscuous Mode When this bit is set the Address Filtering module passes all incoming packets irrespective of the destination or source address" "0,1"
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group.long 0x0C++0x03
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line.long 0x00 "GMAC_MAC_Watchdog_Timeout,The Watchdog Timeout register controls the watchdog timeout for received packets"
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hexmask.long.tbyte 0x00 9.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 8. "PWE,Programmable Watchdog Enable When this bit is set and the WD bit of the MAC_Configuration register is reset the WTO field is used as watchdog timeout for a received packet" "0,1"
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bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "WTO,Watchdog Timeout When the PWE bit is set and the WD bit of the MAC_Configuration register is reset this field is used as watchdog timeout for a received packet" "0: 2 KB,1: 3 KB,2: 4 KB,3: 5 KB,?,?,?,?,?,?,?,?,12: 14 KB,13: 15 KB,14: 16383 Bytes,15: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "GMAC_MAC_Hash_Table_Reg0,The Hash Table Register 0 contains the first 32 bits of the hash table when the width of the Hash table is 128 bits or 256 bits"
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hexmask.long 0x00 0.--31. 1. "HT31T0,Next 32 bits of Hash Table"
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group.long 0x14++0x03
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line.long 0x00 "GMAC_MAC_Hash_Table_Reg1,The Hash Table Register 0 contains the first 32 bits of the hash table when the width of the Hash table is 128 bits or 256 bits"
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hexmask.long 0x00 0.--31. 1. "HT63T32,Next 32 bits of Hash Table"
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group.long 0x50++0x03
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line.long 0x00 "GMAC_MAC_VLAN_Tag,The VLAN Tag register identifies the IEEE 802.1Q VLAN type packets"
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bitfld.long 0x00 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status When this bit is set the MAC provides the inner VLAN Tag in the Rx status" "0,1"
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bitfld.long 0x00 30. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
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bitfld.long 0x00 27. "ERIVLT,Enable Inner VLAN Tag When this bit and the EDVLP field are set the MAC receiver enables operation on the inner VLAN Tag (if present)" "0,1"
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bitfld.long 0x00 26. "EDVLP,Enable Double VLAN Processing When this bit is set the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present)" "0,1"
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bitfld.long 0x00 25. "VTHM,VLAN Tag Hash Table Match Enable When this bit is set the most significant four bits of CRC of VLAN Tag are used to index the content of the MAC_VLAN_Hash_Table register" "0,1"
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bitfld.long 0x00 24. "EVLRXS,Enable VLAN Tag in Rx status When this bit is set MAC provides the outer VLAN Tag in the Rx status" "0,1"
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bitfld.long 0x00 23. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
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bitfld.long 0x00 20. "DOVLTC,Disable VLAN Type Check When this bit is set the MAC does not check whether the VLAN Tag specified by the ERIVLT bit is of type S-VLAN or C-VLAN" "0,1"
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bitfld.long 0x00 19. "ERSVLM,Enable Receive S-VLAN Match When this bit is set the MAC receiver enables filtering or matching for S-VLAN (Type = 0x88A8) packets" "0,1"
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bitfld.long 0x00 18. "ESVL,Enable S-VLAN When this bit is set the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets" "0,1"
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bitfld.long 0x00 17. "VTIM,VLAN Tag Inverse Match Enable When this bit is set this bit enables the VLAN Tag inverse matching" "0,1"
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bitfld.long 0x00 16. "ETV,Enable 12-Bit VLAN Tag Comparison When this bit is set a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag" "0,1"
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hexmask.long.word 0x00 0.--15. 1. "VL,VLAN Tag Identifier for Receive Packets This field contains the 802.1Q VLAN tag to identify the VLAN packets"
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group.long 0x58++0x03
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line.long 0x00 "GMAC_MAC_VLAN_Hash_Table,When the ERSVLM bit of MAC_Hash_Table_Reg1 register is set the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag"
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hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.word 0x00 0.--15. 1. "VLHT,VLAN Hash Table This field contains the 16-bit VLAN Hash Table"
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group.long 0x70++0x03
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line.long 0x00 "GMAC_MAC_Q0_Tx_Flow_Ctrl,The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC"
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hexmask.long.word 0x00 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet"
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hexmask.long.byte 0x00 8.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0,1"
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bitfld.long 0x00 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot..,1: Pause Time minus 28 Slot Times (PT -28 slot..,2: Pause Time minus 36 Slot Times (PT -36 slot..,3: Pause Time minus 144 Slot Times (PT -144 slot,4: Pause Time minus 256 Slot Times (PT -256 slot,5: Pause Time minus 512 Slot Times (PT -512 slot,?..."
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bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 1. "TFE,Transmit Flow Control Enable Full-Duplex Mode: In the full-duplex mode when this bit is set the MAC enables the flow control operation to Tx Pause packets" "0,1"
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bitfld.long 0x00 0. "FCB_BPA,Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set" "0,1"
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group.long 0x90++0x03
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line.long 0x00 "GMAC_MAC_Rx_Flow_Ctrl,The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet"
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hexmask.long.tbyte 0x00 9.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 8. "PFCE,Priority Based Flow Control Enable When this bit is set it enables generation and reception of priority-based flow control (PFC) packets" "0,1"
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bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "UP,Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802.3" "0,1"
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bitfld.long 0x00 0. "RFE,Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex mode the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time" "0,1"
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rgroup.long 0xB0++0x03
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line.long 0x00 "GMAC_MAC_Interrupt_Status,The Interrupt Status register contains the status of interrupts"
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hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 15. "GPIIS,GPI Interrupt Status When the GPIO feature is enabled this bit is set when any active event (LL or LH) occurs on the GPIS field of the MAC_GPIO_Status register and the corresponding GPIE bit is enabled in the MAC_GPIO_Control register" "0,1"
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bitfld.long 0x00 14. "RXSTSIS,Receive Status Interrupt This bit indicates the status of received packets" "0,1"
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bitfld.long 0x00 13. "TXSTSIS,Transmit Status Interrupt This bit indicates the status of transmitted packets" "0,1"
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bitfld.long 0x00 12. "TSIS,Timestamp Interrupt Status If the Timestamp feature is enabled this bit is set when any of the following conditions is true: - The system time value is equal to or exceeds the value specified in the Target Time High and Low registers" "0,1"
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bitfld.long 0x00 11. "MMCRXIPIS,MMC Receive Checksum Offload Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register" "0,1"
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bitfld.long 0x00 10. "MMCTXIS,MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register" "0,1"
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bitfld.long 0x00 9. "MMCRXIS,MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register" "0,1"
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bitfld.long 0x00 8. "MMCIS,MMC Interrupt Status This bit is set high when Bit 11 Bit 10 or Bit 9 is set high" "0,1"
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bitfld.long 0x00 6.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 5. "LPIIS,LPI Interrupt Status When the Energy Efficient Ethernet feature is enabled this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver" "0,1"
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bitfld.long 0x00 4. "PMTIS,PMT Interrupt Status This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (RWKPRCVD and MGKPRCVD bits in MAC_PMT_Control_Status register)" "0,1"
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bitfld.long 0x00 3. "PHYIS,PHY Interrupt This bit is set when rising edge is detected on the phy_intr_i input" "0,1"
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bitfld.long 0x00 2. "PCSANCIS,PCS Auto-Negotiation Complete This bit is set when auto-negotiation is completed in the TBI RTBI or SGMII PHY interface (see ANC bit in the MAC_AN_Status register)" "0,1"
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bitfld.long 0x00 1. "PCSLCHGIS,PCS Link Status Changed This bit is set because of any change in Link Status in the TBI RTBI or SGMII PHY interface (See LS bit in MAC_AN_Status register)" "0,1"
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bitfld.long 0x00 0. "RGSMIIIS,RGMII or SMII Interrupt Status This bit is set because of any change in value of the Link Status of RGMII or SMII interface (LNKSTS bit in MAC_PHYIF_Control_Status register)" "0,1"
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group.long 0xB4++0x03
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line.long 0x00 "GMAC_MAC_Interrupt_Enable,The Interrupt Enable register contains the masks for generating the interrupts"
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hexmask.long.tbyte 0x00 15.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 14. "RXSTSIE,Receive Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the MAC_Interrupt_Status register" "0,1"
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bitfld.long 0x00 13. "TXSTSIE,Transmit Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the MAC_Interrupt_Status register" "0,1"
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bitfld.long 0x00 12. "TSIE,Timestamp Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TSIS bit in MAC_Interrupt_Status register" "0,1"
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bitfld.long 0x00 6.--11. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 5. "LPIIE,LPI Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of LPIIS bit in MAC_Interrupt_Status register" "0,1"
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bitfld.long 0x00 4. "PMTIE,PMT Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PMTIS bit in MAC_Interrupt_Status register" "0,1"
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bitfld.long 0x00 3. "PHYIE,PHY Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PHYIS bit in MAC_Interrupt_Status register" "0,1"
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bitfld.long 0x00 2. "PCSANCIE,PCS AN Completion Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of the PCSANCIS bit in MAC_Interrupt_Status register" "0,1"
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bitfld.long 0x00 1. "PCSLCHGIE,PCS Link Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of the PCSLCHGIS bit in MAC_Interrupt_Status register" "0,1"
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bitfld.long 0x00 0. "RGSMIIIE,RGMII or SMII Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RGSMIIIS bit in MAC_Interrupt_Status register" "0,1"
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rgroup.long 0xB8++0x03
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line.long 0x00 "GMAC_MAC_Rx_Tx_Status,The Receive Transmit Status register contains the Receive and Transmit Error status"
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hexmask.long.tbyte 0x00 9.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 8. "RWT,Receive Watchdog Timeout This bit is set when a packet with length greater than 2 048 bytes is received (10 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_Configuration register" "0,1"
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bitfld.long 0x00 6.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 5. "EXCOL,Excessive Collisions When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet" "0,1"
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bitfld.long 0x00 4. "LCOL,Late Collision When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode 512 bytes.." "0,1"
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bitfld.long 0x00 3. "EXDEF,Excessive Deferral When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the MAC_Configuration register this bit indicates that the transmission ended because of excessive deferral of over 24 288 bit times (155 680.." "0,1"
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bitfld.long 0x00 2. "LCARR,Loss of Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the loss of carrier occurred during packet transmission that is the phy_crs_i signal was inactive for one or more transmission clock periods.." "0,1"
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bitfld.long 0x00 1. "NCARR,No Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission" "0,1"
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bitfld.long 0x00 0. "TJT,Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2 048 bytes (10 240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_Configuration register" "0,1"
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group.long 0xD0++0x03
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line.long 0x00 "GMAC_MAC_LPI_Control_Status,The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status"
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hexmask.long.word 0x00 22.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 21. "LPITCSE,NA" "0,1"
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bitfld.long 0x00 20. "LPIATE,NA" "0,1"
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bitfld.long 0x00 19. "LPITXA,LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side" "0,1"
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bitfld.long 0x00 18. "PLSEN,PHY Link Status Enable This bit enables the link status received on the RGMII SGMII or SMII Receive paths to be used for activating the LPI LS TIMER" "0,1"
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bitfld.long 0x00 17. "PLS,PHY Link Status This bit indicates the link status of the PHY" "0,1"
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bitfld.long 0x00 16. "LPIEN,LPI Enable When this bit is set it instructs the MAC Transmitter to enter the LPI state" "0,1"
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bitfld.long 0x00 10.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 9. "RLPIST,Receive LPI State When this bit is set it indicates that the MAC is receiving the LPI pattern on the GMII or MII interface" "0,1"
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bitfld.long 0x00 8. "TLPIST,Transmit LPI State When this bit is set it indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface" "0,1"
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bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "RLPIEX,Receive LPI Exit When this bit is set it indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface exited the LPI state and resumed the normal reception" "0,1"
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bitfld.long 0x00 2. "RLPIEN,Receive LPI Entry When this bit is set it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state" "0,1"
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bitfld.long 0x00 1. "TLPIEX,Transmit LPI Exit When this bit is set it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired" "0,1"
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bitfld.long 0x00 0. "TLPIEN,Transmit LPI Entry When this bit is set it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit" "0,1"
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group.long 0xD4++0x03
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line.long 0x00 "GMAC_MAC_LPI_Timers_Control,The LPI Timers Control register controls the timeout values in the LPI states"
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bitfld.long 0x00 26.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 16.--25. 1. "LST,LPI LS TIMER This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY"
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hexmask.long.word 0x00 0.--15. 1. "TWT,LPI TW TIMER This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission"
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group.long 0xD8++0x03
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line.long 0x00 "GMAC_MAC_LPI_Entry_Timer,NA"
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hexmask.long.word 0x00 20.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.tbyte 0x00 3.--19. 1. "LPIET,LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter LPI mode after it has transmitted all the frames"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0xDC++0x03
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line.long 0x00 "GMAC_MAC_1US_Tic_Counter,NA"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.word 0x00 0.--11. 1. "TIC_1US_CNTR,1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us"
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group.long 0xF8++0x03
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line.long 0x00 "GMAC_MAC_PHYIF_Control_Status,The PHY Interface Control and Status register indicates the status signals received by the SGMII RGMII or SMII interface (selected at reset) from the PHY"
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hexmask.long.word 0x00 22.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 21. "FALSCARDET,False Carrier Detected This bit indicates whether the SMII PHY detected false carrier (1'b1)" "0,1"
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bitfld.long 0x00 20. "JABTO,Jabber Timeout This bit indicates the jabber timeout error (1'b1) in the received packet" "0,1"
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bitfld.long 0x00 19. "LNKSTS,Link Status This bit indicates whether the link is up (1'b1) or down (1'b0)" "0,1"
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bitfld.long 0x00 17.--18. "LNKSPEED,Link Speed This bit indicates the current speed of the link" "0: 2.5 MHz,1: 25 MHz,2: 125 MHz Bit 2 is,?..."
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bitfld.long 0x00 16. "LNKMOD,Link Mode This bit indicates the current mode of operation of the link" "0: Half-duplex mode,1: Full-duplex mode"
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hexmask.long.word 0x00 5.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 4. "SMIDRXS,Delay SMII Rx Data Sampling with respect to the SMII SYNC Signal When this bit is set the first bit of the SMII Rx data is sampled one cycle after the SMII SYNC signal" "0,1"
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bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 2. "SFTERR,SMII Force Transmit Error When set this bit indicates to the PHY to force a transmit error in the SMII packet being transmitted" "0,1"
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bitfld.long 0x00 1. "LUD,Link Up or Down This bit indicates whether the link is up or down during transmission of configuration in the RGMII SGMII or SMII interface" "0: Link Down,1: Link Up This bit is reserved"
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bitfld.long 0x00 0. "TC,Transmit Configuration in RGMII SGMII or SMII When set this bit enables the transmission of duplex mode link speed and link up or down information to the PHY in the RGMII SMII or SGMII port" "0,1"
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rgroup.long 0x110++0x03
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line.long 0x00 "GMAC_MAC_Version,The version register identifies the version of the DWC_ether_qos"
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hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 8.--15. 1. "USERVER,User-defined Version (configured with coreConsultant)"
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hexmask.long.byte 0x00 0.--7. 1. "SNPSVER,Synopsys-defined Version (3.7)"
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rgroup.long 0x114++0x03
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line.long 0x00 "GMAC_MAC_Debug,The Debug register provides the debug status of various MAC blocks"
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hexmask.long.word 0x00 19.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 17.--18. "TFCSTS,MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module" "0: Idle state,1: Waiting for one of the following,2: Generating and transmitting a Pause control,3: Transferring input packet for transmission"
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bitfld.long 0x00 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and it is not in the Idle state" "0,1"
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hexmask.long.word 0x00 3.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status When this bit is set this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module" "0,1,2,3"
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bitfld.long 0x00 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII receive protocol engine is actively receiving data and it is not in the Idle state" "0,1"
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rgroup.long 0x11C++0x03
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line.long 0x00 "GMAC_MAC_HW_Feature0,This register indicates the presence of the optional features or functions of the DWC_ether_qos"
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bitfld.long 0x00 31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 28.--30. "ACTPHYSEL,Active PHY Selected When you have multiple PHY interfaces in your configuration this field indicates the sampled value of phy_intf_sel_i during reset de-assertion" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,7: RevMII - All Others"
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bitfld.long 0x00 27. "SAVLANINS,Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is" "0,1"
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bitfld.long 0x00 25.--26. "TSSTSSEL,Timestamp System Time Source This bit indicates the source of the Timestamp system time" "0: Reserved This bit is set,1: Internal,2: External,3: Both"
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bitfld.long 0x00 24. "MACADR64SEL,MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is" "0,1"
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bitfld.long 0x00 23. "MACADR32SEL,MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is" "0,1"
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bitfld.long 0x00 18.--22. "ADDMACADRSEL,MAC Addresses 16-31 Selected This bit is set to 1 when the Enable Additional 1-31 MAC Address Registers option is" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 17. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 16. "RXCOESEL,Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is" "0,1"
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bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 14. "TXCOESEL,Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is" "0,1"
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bitfld.long 0x00 13. "EEESEL,Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is" "0,1"
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bitfld.long 0x00 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is" "0,1"
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bitfld.long 0x00 10.--11. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 9. "ARPOFFSEL,ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is" "0,1"
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bitfld.long 0x00 8. "MMCSEL,RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is" "0,1"
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bitfld.long 0x00 7. "MGKSEL,PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is" "0,1"
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bitfld.long 0x00 6. "RWKSEL,PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is" "0,1"
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bitfld.long 0x00 5. "SMASEL,SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is" "0,1"
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bitfld.long 0x00 4. "VLHASH,VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is" "0,1"
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bitfld.long 0x00 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface) This bit is set to 1 when the TBI SGMII or RTBI PHY interface option is" "0,1"
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bitfld.long 0x00 2. "HDSEL,Half-duplex Support This bit is set to 1 when the half-duplex mode is" "0,1"
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bitfld.long 0x00 1. "GMIISEL,1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of" "0,1"
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bitfld.long 0x00 0. "MIISEL,10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of" "0,1"
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rgroup.long 0x120++0x03
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line.long 0x00 "GMAC_MAC_HW_Feature1,This register indicates the presence of the optional features or functions of the DWC_ether_qos"
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bitfld.long 0x00 31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 27.--30. "L3L4FNUM,Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters" "0: No L3 or L4 Filter,1: 1 L3 or L4 Filter,2: 2 L3 or L4 Filters,?,?,?,?,?,8: 8 L3 or L4,?..."
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bitfld.long 0x00 26. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24.--25. "HASHTBLSZ,Hash Table Size This field indicates the size of the hash table: - 00- No hash table - 0" "0,1,2,3"
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bitfld.long 0x00 23. "LPMODEEN,Low Power Mode Enabled This bit is set to 1 when the Enable UPF-Based Low-Power Support option is" "0,1"
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bitfld.long 0x00 21.--22. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 20. "AVSEL,AV Feature Enabled This bit is set to 1 when the Enable Audio Video Bridging option is" "0,1"
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bitfld.long 0x00 19. "DBGMEMA,DMA Debug Registers Enabled This bit is set to 1 when the Debug Mode Enable option is" "0,1"
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bitfld.long 0x00 18. "TSOEN,TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is" "0,1"
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bitfld.long 0x00 17. "SPHEN,Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is" "0,1"
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bitfld.long 0x00 16. "DCBEN,DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is" "0,1"
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bitfld.long 0x00 14.--15. "ADDR64,Address Width" "0: ,1: ,2: ,?..."
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bitfld.long 0x00 13. "ADVTHWORD,IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is" "0,1"
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bitfld.long 0x00 12. "PTOEN,NA" "0,1"
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bitfld.long 0x00 11. "OSTEN,NA" "0,1"
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bitfld.long 0x00 6.--10. "TXFIFOSIZE,MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(TXFIFO_SIZE)" "0: 128 bytes,1: 256 bytes,2: 512 bytes,3: 1 024 bytes,4: 2 048 bytes,5: 4 096 bytes,6: 8 192 bytes,7: 16 384 bytes,8: 32 KB,9: 64 KB,10: 128 KB - 01011-11111,?..."
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bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0.--4. "RXFIFOSIZE,MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(RXFIFO_SIZE)" "0: 128 bytes,1: 256 bytes,2: 512 bytes,3: 1 024 bytes,4: 2 048 bytes,5: 4 096 bytes,6: 8 192 bytes,7: 16 384 bytes,8: 32 KB,9: 64 KB,10: 128 KB,11: 256 KB - 01100-11111,?..."
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rgroup.long 0x124++0x03
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line.long 0x00 "GMAC_MAC_HW_Feature2,This register indicates the presence of the optional features or functions of the DWC_ether_qos"
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bitfld.long 0x00 31. "bf_align5,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary inputs,3: 3 auxiliary inputs,4: 4 auxiliary inputs - 101-111,?..."
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bitfld.long 0x00 27. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 24.--26. "PPSOUTNUM,Number of PPS Outputs This field indicates the number of PPS outputs" "0: No PPS output,1: 1 PPS output,2: 2 PPS outputs,3: 3 PPS outputs,4: 4 PPS outputs - 101-111,?..."
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bitfld.long 0x00 22.--23. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 18.--21. "TXCHCNT,Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels" "0: 1 DMA Tx Channel,1: 2 DMA Tx Channels,?,?,?,?,?,7: 8 DMA Tx,?..."
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bitfld.long 0x00 16.--17. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 12.--15. "RXCHCNT,Number of DMA Receive Channels This field indicates the number of DMA Receive channels" "0: 1 DMA Rx Channel,1: 2 DMA Rx Channels,?,?,?,?,?,7: 8 DMA Rx,?..."
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bitfld.long 0x00 10.--11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 6.--9. "TXQCNT,Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues" "0: 1 MTL Tx Queue,1: 2 MTL Tx Queues,?,?,?,?,?,7: 8 MTL Tx,?..."
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bitfld.long 0x00 4.--5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 0.--3. "RXQCNT,Number of MTL Receive Queues This field indicates the number of MTL Receive queues" "0: 1 MTL Rx Queue,1: 2 MTL Rx Queues,?,?,?,?,?,7: 8 MTL Rx,?..."
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group.long 0x200++0x03
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line.long 0x00 "GMAC_MAC_MDIO_Address,The MDIO Address register controls the management cycles to external PHY through a management interface"
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bitfld.long 0x00 28.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 27. "PSE,NA" "0,1"
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bitfld.long 0x00 26. "BTB,NA" "0,1"
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bitfld.long 0x00 21.--25. "PA,Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. "RDA,GMII Register These bits select the PHY register in selected Clause 22 PHY device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 12.--14. "NTC,NA" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "CR,CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design" "0: CSR clock = 60-100 MHz MDC clock = CSR clock/42,1: CSR clock = 100-150 MHz MDC clock = CSR..,2: CSR clock = 20-35 MHz MDC clock = CSR clock/16,3: CSR clock = 35-60 MHz MDC clock = CSR clock/26,4: CSR clock = 150-250 MHz MDC clock = CSR..,5: 0) ensures that the MDC clock is approximately,?,7: Reserved The CSR clock corresponding to,8: CSR clock/4,9: CSR clock/6,10: CSR clock/8,11: CSR clock/10,12: CSR clock/12,13: CSR clock/14,14: CSR clock/16,15: CSR clock/18 These bits are not used for"
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bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "SKAP,Skip Address Packet When this bit is set the SMA does not send the address packets before read write or post-read increment address packets" "0,1"
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bitfld.long 0x00 2.--3. "GOC,Bit" "0: Reserved,1: NA,2: Post Read Increment Address for Clause 45 PHY,3: Read When Clause 22 PHY or RevMII is enabled"
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bitfld.long 0x00 1. "C45E,Clause 45 PHY Enable When this bit is set Clause 45 capable PHY is connected to MDIO" "0,1"
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bitfld.long 0x00 0. "GB,GMII Busy This bit should read logic 0 before writing to MAC Register 128 and MAC Register 129" "0,1"
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group.long 0x204++0x03
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line.long 0x00 "GMAC_MAC_MDIO_Data,The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in MAC_MDIO_Address"
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hexmask.long.word 0x00 16.--31. 1. "RA,Register Address When using Clause 45 packets this field selects the register in the selected MMD"
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hexmask.long.word 0x00 0.--15. 1. "GD,GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation"
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group.long 0x300++0x03
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line.long 0x00 "GMAC_MAC_Address0_High,The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station"
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bitfld.long 0x00 31. "AE,Address Enable This bit is always set to 1" "0,1"
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hexmask.long.word 0x00 17.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address0 content is routed" "0,1"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address"
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group.long 0x304++0x03
|
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line.long 0x00 "GMAC_MAC_Address0_Low,The MAC Address0 Low register holds the lower 32 bits of the 6-byte first MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address0[31:0] This field contains the lower 32 bits of the first 6-byte MAC address"
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|
group.long 0x308++0x03
|
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line.long 0x00 "GMAC_MAC_Address1_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
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|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
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|
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "GMAC_MAC_Address1_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "GMAC_MAC_Address2_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "GMAC_MAC_Address2_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "GMAC_MAC_Address3_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "GMAC_MAC_Address3_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "GMAC_MAC_Address4_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "GMAC_MAC_Address4_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "GMAC_MAC_Address5_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "GMAC_MAC_Address5_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "GMAC_MAC_Address6_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "GMAC_MAC_Address6_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "GMAC_MAC_Address7_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "GMAC_MAC_Address7_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "GMAC_MAC_Address8_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "GMAC_MAC_Address8_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "GMAC_MAC_Address9_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "GMAC_MAC_Address9_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "GMAC_MAC_Address10_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "GMAC_MAC_Address10_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "GMAC_MAC_Address11_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "GMAC_MAC_Address11_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "GMAC_MAC_Address12_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "GMAC_MAC_Address12_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "GMAC_MAC_Address13_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x36C++0x03
|
|
line.long 0x00 "GMAC_MAC_Address13_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "GMAC_MAC_Address14_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x374++0x03
|
|
line.long 0x00 "GMAC_MAC_Address14_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "GMAC_MAC_Address15_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x37C++0x03
|
|
line.long 0x00 "GMAC_MAC_Address15_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "GMAC_MAC_Address16_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "GMAC_MAC_Address16_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "GMAC_MAC_Address17_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "GMAC_MAC_Address17_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "GMAC_MAC_Address18_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "GMAC_MAC_Address18_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "GMAC_MAC_Address19_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "GMAC_MAC_Address19_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "GMAC_MAC_Address20_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "GMAC_MAC_Address20_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "GMAC_MAC_Address21_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "GMAC_MAC_Address21_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "GMAC_MAC_Address22_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "GMAC_MAC_Address22_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "GMAC_MAC_Address23_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "GMAC_MAC_Address23_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "GMAC_MAC_Address24_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3C4++0x03
|
|
line.long 0x00 "GMAC_MAC_Address24_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3C8++0x03
|
|
line.long 0x00 "GMAC_MAC_Address25_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "GMAC_MAC_Address25_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "GMAC_MAC_Address26_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "GMAC_MAC_Address26_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3D8++0x03
|
|
line.long 0x00 "GMAC_MAC_Address27_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3DC++0x03
|
|
line.long 0x00 "GMAC_MAC_Address27_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "GMAC_MAC_Address28_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
|
|
newline
|
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hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
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group.long 0x3E4++0x03
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line.long 0x00 "GMAC_MAC_Address28_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
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hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
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group.long 0x3E8++0x03
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line.long 0x00 "GMAC_MAC_Address29_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
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bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
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hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
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group.long 0x3EC++0x03
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line.long 0x00 "GMAC_MAC_Address29_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
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hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
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group.long 0x3F0++0x03
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line.long 0x00 "GMAC_MAC_Address30_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
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bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
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hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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newline
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bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
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newline
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
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group.long 0x3F4++0x03
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line.long 0x00 "GMAC_MAC_Address30_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
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hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
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group.long 0x3F8++0x03
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line.long 0x00 "GMAC_MAC_Address31_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
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bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0,1"
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newline
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0,1"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: Register 195[7:0] You can filter a group of,?,?,27: Register 195[31:24],28: Register 194[7:0] - Bit,29: Register 194[15:8] - Bit,?..."
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hexmask.long.byte 0x00 17.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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newline
|
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bitfld.long 0x00 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address1 content is routed" "0,1"
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newline
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
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group.long 0x3FC++0x03
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line.long 0x00 "GMAC_MAC_Address31_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
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hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
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group.long 0x700++0x03
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line.long 0x00 "GMAC_MMC_Control,NA"
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hexmask.long.tbyte 0x00 9.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets l When set the MAC updates all related MMC Counters for Broadcast packets that are dropped because of the setting of the DBF bit of MAC_Packet_Filter register" "0,1"
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bitfld.long 0x00 6.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 5. "CNTPRSTLVL,Full-Half Preset When this bit is low and the CNTPRST bit is set all MMC counters get preset to almost-half value" "0,1"
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bitfld.long 0x00 4. "CNTPRST,Counters Preset When this bit is set all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit" "0,1"
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bitfld.long 0x00 3. "CNTFREEZ,MMC Counter Freeze When this bit is set it freezes all MMC counters to their current value" "0,1"
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bitfld.long 0x00 2. "RSTONRD,Reset on Read When this bit is set the MMC counters are reset to zero after Read (self-clearing after reset)" "0,1"
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bitfld.long 0x00 1. "CNTSTOPRO,Counter Stop Rollover When this bit is set the counter does not roll over to zero after reaching the maximum value" "0,1"
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bitfld.long 0x00 0. "CNTRST,Counters Reset When this bit is set all counters are reset" "0,1"
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rgroup.long 0x704++0x03
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line.long 0x00 "GMAC_MMC_Rx_Interrupt,NA"
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bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 27. "RXLPITRCIS,NA" "0,1"
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bitfld.long 0x00 26. "RXLPIUSCIS,NA" "0,1"
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bitfld.long 0x00 25. "RXCTRLPIS,MMC Receive Control Packet Counter Interrupt Status This bit is set when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 24. "RXRCVERRPIS,MMC Receive Error Packet Counter Interrupt Status This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 23. "RXWDOGPIS,MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 22. "RXVLANGBPIS,MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 21. "RXFOVPIS,MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 20. "RXPAUSPIS,MMC Receive Pause Packet Counter Interrupt Status This bit is set when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 19. "RXORANGEPIS,MMC Receive Out Of Range Error Packet Counter Interrupt Status" "0,1"
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bitfld.long 0x00 18. "RXLENERPIS,MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 16. "RX1024TMAXOCTGBPIS,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 15. "RX512T1023OCTGBPIS,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 14. "RX256T511OCTGBPIS,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 13. "RX128T255OCTGBPIS,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 12. "RX65T127OCTGBPIS,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 11. "RX64OCTGBPIS,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 10. "RXOSIZEGPIS,MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 9. "RXUSIZEGPIS,MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 8. "RXJABERPIS,MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 7. "RXRUNTPIS,MMC Receive Runt Packet Counter Interrupt Status This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 4. "RXMCGPIS,MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 3. "RXBCGPIS,MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 2. "RXGOCTIS,MMC Receive Good Octet Counter Interrupt Status This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0,1"
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newline
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bitfld.long 0x00 1. "RXGBOCTIS,MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 0. "RXGBPKTIS,MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0,1"
|
|
rgroup.long 0x708++0x03
|
|
line.long 0x00 "GMAC_MMC_Tx_Interrupt,NA"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 27. "TXLPITRCIS,NA" "0,1"
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bitfld.long 0x00 26. "TXLPIUSCIS,NA" "0,1"
|
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|
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bitfld.long 0x00 25. "TXOSIZEGPIS,MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 24. "TXVLANGPIS,MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 23. "TXPAUSPIS,MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the txpausepacketserror counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 22. "TXEXDEFPIS,MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value" "0,1"
|
|
newline
|
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bitfld.long 0x00 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 20. "TXGOCTIS,MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 19. "TXCARERPIS,MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 18. "TXEXCOLPIS,MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value" "0,1"
|
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newline
|
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bitfld.long 0x00 17. "TXLATCOLPIS,MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value" "0,1"
|
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newline
|
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bitfld.long 0x00 16. "TXDEFPIS,MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value" "0,1"
|
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newline
|
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bitfld.long 0x00 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 13. "TXUFLOWERPIS,MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 12. "TXBCGBPIS,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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|
newline
|
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bitfld.long 0x00 11. "TXMCGBPIS,MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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|
newline
|
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bitfld.long 0x00 10. "TXUCGBPIS,MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "TX1024TMAXOCTGBPIS,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TX512T1023OCTGBPIS,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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|
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bitfld.long 0x00 7. "TX256T511OCTGBPIS,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 6. "TX128T255OCTGBPIS,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 5. "TX65T127OCTGBPIS,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half the maximum value and also when it reaches the maximum value" "0,1"
|
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|
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bitfld.long 0x00 4. "TX64OCTGBPIS,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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|
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bitfld.long 0x00 3. "TXMCGPIS,MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 2. "TXBCGPIS,MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 1. "TXGBPKTIS,MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0,1"
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|
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bitfld.long 0x00 0. "TXGBOCTIS,MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0,1"
|
|
group.long 0x70C++0x03
|
|
line.long 0x00 "GMAC_MMC_Rx_Interrupt_Mask,NA"
|
|
bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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|
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bitfld.long 0x00 27. "RXLPITRCIM,NA" "0,1"
|
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|
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bitfld.long 0x00 26. "RXLPIUSCIM,NA" "0,1"
|
|
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|
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bitfld.long 0x00 25. "RXCTRLPIM,MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
|
|
newline
|
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bitfld.long 0x00 24. "RXRCVERRPIM,MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value" "0,1"
|
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newline
|
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bitfld.long 0x00 23. "RXWDOGPIM,MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value" "0,1"
|
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newline
|
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bitfld.long 0x00 22. "RXVLANGBPIM,MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 21. "RXFOVPIM,MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0,1"
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newline
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bitfld.long 0x00 20. "RXPAUSPIM,MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0,1"
|
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newline
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bitfld.long 0x00 19. "RXORANGEPIM,MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value" "0,1"
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newline
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bitfld.long 0x00 18. "RXLENERPIM,MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0,1"
|
|
newline
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bitfld.long 0x00 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
|
|
newline
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bitfld.long 0x00 16. "RX1024TMAXOCTGBPIM,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x00 15. "RX512T1023OCTGBPIM,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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newline
|
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bitfld.long 0x00 14. "RX256T511OCTGBPIM,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 13. "RX128T255OCTGBPIM,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 12. "RX65T127OCTGBPIM,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 11. "RX64OCTGBPIM,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 10. "RXOSIZEGPIM,MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 9. "RXUSIZEGPIM,MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 8. "RXJABERPIM,MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 7. "RXRUNTPIM,MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 4. "RXMCGPIM,MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 3. "RXBCGPIM,MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 2. "RXGOCTIM,MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 1. "RXGBOCTIM,MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 0. "RXGBPKTIM,MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0,1"
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group.long 0x710++0x03
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line.long 0x00 "GMAC_MMC_Tx_Interrupt_Mask,NA"
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bitfld.long 0x00 28.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 27. "TXLPITRCIM,NA" "0,1"
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bitfld.long 0x00 26. "TXLPIUSCIM,NA" "0,1"
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bitfld.long 0x00 25. "TXOSIZEGPIM,MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 24. "TXVLANGPIM,MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 23. "TXPAUSPIM,MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 22. "TXEXDEFPIM,MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 20. "TXGOCTIM,MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 19. "TXCARERPIM,MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 18. "TXEXCOLPIM,MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 17. "TXLATCOLPIM,MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 16. "TXDEFPIM,MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 13. "TXUFLOWERPIM,MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 12. "TXBCGBPIM,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 11. "TXMCGBPIM,MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 10. "TXUCGBPIM,MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 9. "TX1024TMAXOCTGBPIM,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 8. "TX512T1023OCTGBPIM,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 7. "TX256T511OCTGBPIM,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 6. "TX128T255OCTGBPIM,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 5. "TX65T127OCTGBPIM,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 4. "TX64OCTGBPIM,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 3. "TXMCGPIM,MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 2. "TXBCGPIM,MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 1. "TXGBPKTIM,MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0,1"
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bitfld.long 0x00 0. "TXGBOCTIM,MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0,1"
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rgroup.long 0x714++0x03
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line.long 0x00 "GMAC_Tx_Octet_Count_Good_Bad,NA"
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hexmask.long 0x00 0.--31. 1. "TXOCTGB,NA"
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rgroup.long 0x718++0x03
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line.long 0x00 "GMAC_Tx_Packet_Count_Good_Bad,NA"
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hexmask.long 0x00 0.--31. 1. "TXPKTGB,NA"
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rgroup.long 0x73C++0x03
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line.long 0x00 "GMAC_Tx_Unicast_Packets_Good_Bad,NA"
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hexmask.long 0x00 0.--31. 1. "TXUCASTGB,NA"
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rgroup.long 0x748++0x03
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line.long 0x00 "GMAC_Tx_Underflow_Error_Packets,NA"
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hexmask.long 0x00 0.--31. 1. "TXUNDRFLW,NA"
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rgroup.long 0x74C++0x03
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line.long 0x00 "GMAC_Tx_Single_Collision_Good_Packets,NA"
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hexmask.long 0x00 0.--31. 1. "TXSNGLCOLG,NA"
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rgroup.long 0x750++0x03
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line.long 0x00 "GMAC_Tx_Multiple_Collision_Good_Packets,NA"
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hexmask.long 0x00 0.--31. 1. "TXMULTCOLG,NA"
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rgroup.long 0x754++0x03
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line.long 0x00 "GMAC_Tx_Deferred_Packets,NA"
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hexmask.long 0x00 0.--31. 1. "TXDEFRD,NA"
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rgroup.long 0x758++0x03
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line.long 0x00 "GMAC_Tx_Late_Collision_Packets,NA"
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hexmask.long 0x00 0.--31. 1. "TXLATECOL,NA"
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rgroup.long 0x75C++0x03
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line.long 0x00 "GMAC_Tx_Excessive_Collision_Packets,NA"
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hexmask.long 0x00 0.--31. 1. "TXEXSCOL,NA"
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rgroup.long 0x760++0x03
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line.long 0x00 "GMAC_Tx_Carrier_Error_Packets,NA"
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hexmask.long 0x00 0.--31. 1. "TXCARR,NA"
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rgroup.long 0x770++0x03
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line.long 0x00 "GMAC_Tx_Pause_Packets,NA"
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hexmask.long 0x00 0.--31. 1. "TXPAUSE,NA"
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rgroup.long 0x780++0x03
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line.long 0x00 "GMAC_Rx_Packets_Count_Good_Bad,NA"
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hexmask.long 0x00 0.--31. 1. "RXPKTGB,NA"
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rgroup.long 0x784++0x03
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line.long 0x00 "GMAC_Rx_Octet_Count_Good_Bad,NA"
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hexmask.long 0x00 0.--31. 1. "RXOCTGB,NA"
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rgroup.long 0x788++0x03
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line.long 0x00 "GMAC_Rx_Octet_Count_Good,NA"
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hexmask.long 0x00 0.--31. 1. "RXOCTG,NA"
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rgroup.long 0x78C++0x03
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line.long 0x00 "GMAC_Rx_Broadcast_Packets_Good,NA"
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hexmask.long 0x00 0.--31. 1. "RXBCASTG,NA"
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rgroup.long 0x790++0x03
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line.long 0x00 "GMAC_Rx_Multicast_Packets_Good,NA"
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hexmask.long 0x00 0.--31. 1. "RXMCASTG,NA"
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rgroup.long 0x794++0x03
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line.long 0x00 "GMAC_Rx_CRC_Error_Packets,NA"
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hexmask.long 0x00 0.--31. 1. "RXCRCERR,NA"
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rgroup.long 0x798++0x03
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line.long 0x00 "GMAC_Rx_Alignment_Error_Packets,NA"
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hexmask.long 0x00 0.--31. 1. "RXALGNERR,NA"
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rgroup.long 0x7C4++0x03
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line.long 0x00 "GMAC_Rx_Unicast_Packets_Good,NA"
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hexmask.long 0x00 0.--31. 1. "RXUCASTG,NA"
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rgroup.long 0x7D0++0x03
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line.long 0x00 "GMAC_Rx_Pause_Packets,NA"
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hexmask.long 0x00 0.--31. 1. "RXPAUSEPKT,NA"
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rgroup.long 0x7D4++0x03
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line.long 0x00 "GMAC_Rx_FIFO_Overflow_Packets,NA"
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hexmask.long 0x00 0.--31. 1. "RXFIFOOVFL,NA"
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group.long 0xB00++0x03
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line.long 0x00 "GMAC_MAC_Timestamp_Control,This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver"
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bitfld.long 0x00 29.--31. "bf_align4,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 28. "AV8021ASMEN,AV 802.1AS Mode Enable When this bit is set the MAC processes only untagged PTP over Ethernet packets for providing PTP status and capturing timestamp snapshots that is IEEE 802.1AS mode of operation" "0,1"
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bitfld.long 0x00 25.--27. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24. "TXTSSTSM,Transmit Timestamp Status Mode When this bit is set the MAC overwrites the earlier transmit timestamp status even if it is not read by the software" "0,1"
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bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "ESTI,External System Time Input When this bit is set the MAC uses the external 64-bit reference System Time input for the following: - To take the timestamp provided as status - To insert the timestamp in transmit PTP packets when One-step Timestamp or.." "0,1"
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bitfld.long 0x00 19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering When this bit is set the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet" "0,1"
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bitfld.long 0x00 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken" "0,1,2,3"
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bitfld.long 0x00 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master When this bit is set the snapshot is taken only for the messages that are relevant to the master node" "0,1"
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bitfld.long 0x00 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages When this bit is set the timestamp snapshot is taken only for event messages (SYNC Delay_Req Pdelay_Req or Pdelay_Resp)" "0,1"
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bitfld.long 0x00 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets" "0,1"
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bitfld.long 0x00 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets" "0,1"
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bitfld.long 0x00 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets When this bit is set the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets" "0,1"
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bitfld.long 0x00 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format When this bit is set the IEEE 1588 version 2 format is used to process the PTP packets" "0,1"
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bitfld.long 0x00 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control When this bit is set the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is 1 nanosecond accuracy) and increments the timestamp (High) seconds" "0,1"
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bitfld.long 0x00 8. "TSENALL,Enable Timestamp for All Packets When this bit is set the timestamp snapshot is enabled for all packets received by the MAC" "0,1"
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bitfld.long 0x00 6.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 5. "TSADDREG,Update Addend Register When this bit is set the content of the Timestamp Addend register is updated in the PTP block for fine correction" "0,1"
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bitfld.long 0x00 4. "TSTRIG,Enable Timestamp Interrupt Trigger When this bit is set the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register" "0,1"
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bitfld.long 0x00 3. "TSUPDT,Update Timestamp When this bit is set the system time is updated (added or subtracted) with the value specified in MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update" "0,1"
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bitfld.long 0x00 2. "TSINIT,Initialize Timestamp When this bit is set the system time is initialized (overwritten) with the value specified in the MAC Register 80 (System Time Seconds Update Register) and MAC Register 81 (System Time Nanoseconds Update Register)" "0,1"
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bitfld.long 0x00 1. "TSCFUPDT,Fine or Coarse Timestamp Update When this bit is set the Fine method is used to update system timestamp" "0,1"
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bitfld.long 0x00 0. "TSENA,Enable Timestamp When this bit is set the timestamp is added for Transmit and Receive packets" "0,1"
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group.long 0xB04++0x03
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line.long 0x00 "GMAC_MAC_Sub_Second_Increment,The Sub-Second Increment register is present only when the IEEE 1588 timestamp feature is selected without an external timestamp input"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 16.--23. 1. "SSINC,Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register"
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hexmask.long.byte 0x00 8.--15. 1. "SNSINC,NA"
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hexmask.long.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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rgroup.long 0xB08++0x03
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line.long 0x00 "GMAC_MAC_System_Time_Seconds,The System Time Seconds register along with System Time Nanoseconds register indicates the current value of the system time maintained by the MAC"
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hexmask.long 0x00 0.--31. 1. "TSS,Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC"
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rgroup.long 0xB0C++0x03
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line.long 0x00 "GMAC_MAC_System_Time_Nanoseconds,The System Time Nanoseconds register along with System Time Seconds register indicates the current value of the system time maintained by the MAC"
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bitfld.long 0x00 31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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hexmask.long 0x00 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field has the sub-second representation of time with an accuracy of 0.46 ns"
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group.long 0xB10++0x03
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line.long 0x00 "GMAC_MAC_System_Time_Seconds_Update,The System Time Seconds Update register along with the System Time Nanoseconds Update register initializes or updates the system time maintained by the MAC"
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hexmask.long 0x00 0.--31. 1. "TSS,Timestamp Second The value in this field indicates the time in seconds to be initialized or added to the system time"
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group.long 0xB14++0x03
|
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line.long 0x00 "GMAC_MAC_System_Time_Nanoseconds_Update,This register is present only when the IEEE 1588 timestamp feature is selected without external timestamp input"
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bitfld.long 0x00 31. "ADDSUB,Add or Subtract Time When this bit is set the time value is subtracted with the contents of the update register" "0,1"
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hexmask.long 0x00 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field has the sub second representation of time with an accuracy of 0.46 ns"
|
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group.long 0xB18++0x03
|
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line.long 0x00 "GMAC_MAC_Timestamp_Addend,The Timestamp Addend register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input"
|
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hexmask.long 0x00 0.--31. 1. "TSAR,Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization"
|
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rgroup.long 0xB20++0x03
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line.long 0x00 "GMAC_MAC_Timestamp_Status,The Timestamp Status register is present only when the IEEE 1588 Timestamp feature is selected"
|
|
bitfld.long 0x00 30.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 25.--29. "ATSNS,Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set" "0,1"
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bitfld.long 0x00 20.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable" "0: Bit,1: Bit,2: Bit,?..."
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bitfld.long 0x00 15. "TXTSSIS,Tx Timestamp Status Interrupt Status When the Timestamp feature is enabled in non EQOS-CORE configuration and Tx Status dropping is enabled the Timestamp captured for Tx packet is provided in MAC_Tx_Timestamp_Status_Seconds and.." "0,1"
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bitfld.long 0x00 10.--14. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 9. "TSTRGTERR3,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds registers elapses" "0,1"
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bitfld.long 0x00 8. "TSTARGT3,Timestamp Target Time Reached for Target Time PPS3 When this bit is set it indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds registers" "0,1"
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bitfld.long 0x00 7. "TSTRGTERR2,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers elapses" "0,1"
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bitfld.long 0x00 6. "TSTARGT2,Timestamp Target Time Reached for Target Time PPS2 When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers" "0,1"
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bitfld.long 0x00 5. "TSTRGTERR1,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers elapses" "0,1"
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bitfld.long 0x00 4. "TSTARGT1,Timestamp Target Time Reached for Target Time PPS1 When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers" "0,1"
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bitfld.long 0x00 3. "TSTRGTERR0,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses" "0,1"
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bitfld.long 0x00 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO" "0,1"
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bitfld.long 0x00 1. "TSTARGT0,Timestamp Target Time Reached When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers" "0,1"
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bitfld.long 0x00 0. "TSSOVF,Timestamp Seconds Overflow When this bit is set it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF" "0,1"
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rgroup.long 0xB30++0x03
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line.long 0x00 "GMAC_MAC_Tx_Timestamp_Status_Nanoseconds,This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled"
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bitfld.long 0x00 31. "TXTSSMIS,Transmit Timestamp Status Missed When this bit is set it indicates one of the following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the MAC_Timestamp_Control register is reset - The timestamp of the previous packet is.." "0,1"
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hexmask.long 0x00 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp"
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rgroup.long 0xB34++0x03
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line.long 0x00 "GMAC_MAC_Tx_Timestamp_Status_Seconds,The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted"
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hexmask.long 0x00 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp"
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group.long 0xB58++0x03
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line.long 0x00 "GMAC_MAC_Timestamp_Ingress_Corr_Nanosecond,NA"
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hexmask.long 0x00 0.--31. 1. "TSIC,Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression"
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group.long 0xB5C++0x03
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line.long 0x00 "GMAC_MAC_Timestamp_Egress_Corr_Nanosecond,NA"
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hexmask.long 0x00 0.--31. 1. "TSEC,Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression"
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group.long 0xB80++0x03
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line.long 0x00 "GMAC_MAC_PPS0_Target_Time_Seconds,The PPS Target Time Seconds register along with PPS Target Time Nanoseconds register is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these.."
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hexmask.long 0x00 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register This field stores the time in seconds"
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group.long 0xB84++0x03
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line.long 0x00 "GMAC_MAC_PPS0_Target_Time_Nanoseconds,The PPS0 Target Time Nanoseconds register is present only when more than one Flexible PPS output is selected"
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bitfld.long 0x00 31. "TRGTBUSY0,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0,1"
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hexmask.long 0x00 0.--30. 1. "TTSL0,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
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group.long 0xC00++0x03
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line.long 0x00 "GMAC_MTL_Operation_Mode,The Operation Mode register establishes the Transmit and Receive operating modes and commands"
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hexmask.long.tbyte 0x00 10.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 9. "CNTCLR,NA" "0,1"
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bitfld.long 0x00 8. "CNTPRST,NA" "0,1"
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bitfld.long 0x00 7. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 5.--6. "SCHALG,Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling" "0: WRR algorithm,1: WFQ algorithm when DCB feature is selected,2: DWRR algorithm when DCB feature is selected,3: Strict priority algorithm"
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bitfld.long 0x00 3.--4. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 2. "RAA,Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side" "0: Strict priority (SP) Queue 0 has the lowest,1: Weighted Strict Priority (WSP) This bit is"
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bitfld.long 0x00 1. "DTXSTS,Drop Transmit Status When this bit is set the Tx packet status received from the MAC is dropped in the MTL" "0,1"
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bitfld.long 0x00 0. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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rgroup.long 0xC20++0x03
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line.long 0x00 "GMAC_MTL_Interrupt_Status,The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC"
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hexmask.long.word 0x00 18.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 17. "DBGIS,Debug Interrupt status This bit indicates an interrupt event during the slave access" "0,1"
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bitfld.long 0x00 16. "MACIS,MAC Interrupt Status This bit indicates an interrupt event in the MAC" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "Q7IS,Queue 7 Interrupt status This bit indicates that there is an interrupt from Queue 7" "0,1"
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bitfld.long 0x00 6. "Q6IS,Queue 6 Interrupt status This bit indicates that there is an interrupt from Queue 6" "0,1"
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bitfld.long 0x00 5. "Q5IS,Queue 5 Interrupt status This bit indicates that there is an interrupt from Queue 5" "0,1"
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bitfld.long 0x00 4. "Q4IS,Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4" "0,1"
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bitfld.long 0x00 3. "Q3IS,Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3" "0,1"
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bitfld.long 0x00 2. "Q2IS,Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2" "0,1"
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bitfld.long 0x00 1. "Q1IS,Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1" "0,1"
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bitfld.long 0x00 0. "Q0IS,Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0" "0,1"
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group.long 0xD00++0x03
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line.long 0x00 "GMAC_MTL_TxQ0_Operation_Mode,The Queue Transmit Operation Mode register establishes the Transmit queue operating modes and commands"
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hexmask.long.word 0x00 20.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16.--19. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 7.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: ,1: ,2: ,3: ,4: ,5: ,6: ,7: 512"
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bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 1" "0: Not enabled,1: Enable in AV mode (Reserved,2: Enabled,3: Reserved"
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bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0,1"
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bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0,1"
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rgroup.long 0xD04++0x03
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line.long 0x00 "GMAC_MTL_TxQ0_Underflow,The Queue Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0,1"
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hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
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rgroup.long 0xD08++0x03
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line.long 0x00 "GMAC_MTL_TxQ0_Debug,The Queue Transmit Debug register gives the debug status of various blocks related to the Transmit queue"
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hexmask.long.word 0x00 23.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0,1"
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bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0,1"
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bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0,1"
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bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC,2: Waiting for pending Tx Status from the MAC,3: Flushing the Tx queue because of the Packet"
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bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0,1"
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rgroup.long 0xD14++0x03
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line.long 0x00 "GMAC_MTL_TxQ0_ETS_Status,The Queue ETS Status register controls the Queue credit shaping or enhanced transmission selection operation in the Transmit path"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
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group.long 0xD18++0x03
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line.long 0x00 "GMAC_MTL_TxQ0_Quantum_Weight,The Queue idleSlopeCredit Quantum or Weights register provides the average traffic transmitted in the Queue"
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hexmask.long.word 0x00 21.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1"
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group.long 0xD2C++0x03
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line.long 0x00 "GMAC_MTL_Q0_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue interrupts"
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hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0,1"
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hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0,1"
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bitfld.long 0x00 10.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0,1"
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bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0,1"
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bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0,1"
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bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0,1"
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group.long 0xD30++0x03
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line.long 0x00 "GMAC_MTL_RxQ0_Operation_Mode,The Queue Receive Operation Mode register establishes the Receive queue operating modes and command"
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hexmask.long.word 0x00 23.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 20.--22. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--19. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 14.--16. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL-1 KB,1: Full minus 2 KB that is FULL-2 KB,2: Full minus 4 KB that is FULL-4 KB,3: Full minus 5 KB that is FULL-5 KB,4: Full minus 6 KB that is FULL-6 KB,5: Full minus 8 KB that is FULL-8 KB,6: Full minus 16 KB that is FULL-16 KB,7: Full minus 24 KB that is FULL-24 KB The"
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bitfld.long 0x00 11.--13. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is activated" "0: Full minus 1 KB that is FULL-1 KB,1: Full minus 2 KB that is FULL-2 KB,2: Full minus 4 KB that is FULL-4 KB,3: Full minus 5 KB that is FULL-5 KB,4: Full minus 6 KB that is FULL-6 KB,5: Full minus 8 KB that is FULL-8 KB,6: Full minus 16 KB that is FULL-16 KB,7: Full minus 24 KB that is FULL-24 KB When the.."
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bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0,1"
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bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0,1"
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bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0,1"
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bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0,1"
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bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0,1"
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bitfld.long 0x00 2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes)" "0: ,1: ,2: ,3: 128 The"
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rgroup.long 0xD34++0x03
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line.long 0x00 "GMAC_MTL_RxQ0_Overflow_Cnt,The Queue Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0,1"
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hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
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rgroup.long 0xD38++0x03
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line.long 0x00 "GMAC_MTL_RxQ0_Debug,The Queue Receive Debug register gives the debug status of various blocks related to the Receive queue"
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bitfld.long 0x00 30.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
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hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
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hexmask.long.word 0x00 6.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control,2: Rx Queue fill-level above flow-control activate,3: Rx Queue full"
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bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
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bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0,1"
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group.long 0xD40++0x03
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line.long 0x00 "GMAC_MTL_TxQ1_Operation_Mode,The Queue Transmit Operation Mode register establishes the Transmit queue operating modes and commands"
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hexmask.long.word 0x00 20.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16.--19. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 7.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: ,1: ,2: ,3: ,4: ,5: ,6: ,7: 512"
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bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 1" "0: Not enabled,1: Enable in AV mode (Reserved,2: Enabled,3: Reserved"
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bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0,1"
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bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0,1"
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rgroup.long 0xD44++0x03
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line.long 0x00 "GMAC_MTL_TxQ1_Underflow,The Queue Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow"
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0,1"
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hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
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rgroup.long 0xD48++0x03
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line.long 0x00 "GMAC_MTL_TxQ1_Debug,The Queue Transmit Debug register gives the debug status of various blocks related to the Transmit queue"
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hexmask.long.word 0x00 23.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 6.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0,1"
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bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0,1"
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bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0,1"
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bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC,2: Waiting for pending Tx Status from the MAC,3: Flushing the Tx queue because of the Packet"
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bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0,1"
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group.long 0xD50++0x03
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line.long 0x00 "GMAC_MTL_TxQ1_ETS_Control,The Queue ETS Control register controls the enhanced transmission selection operation"
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hexmask.long 0x00 7.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of 125 us duration) over which the average transmitted bits per slot provided in the MTL_TxQ1_ETS_Status register need to be computed for Queue 1" "0: 1 Slot,1: 2 Slots,2: 4 Slots,3: 8 Slots,4: 16 Slots - 3'b101-3'b111,?..."
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bitfld.long 0x00 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0,1"
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bitfld.long 0x00 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0,1"
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bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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rgroup.long 0xD54++0x03
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line.long 0x00 "GMAC_MTL_TxQ1_ETS_Status,The Queue ETS Status register controls the Queue credit shaping or enhanced transmission selection operation in the Transmit path"
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hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
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group.long 0xD58++0x03
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line.long 0x00 "GMAC_MTL_TxQ1_Quantum_Weight,The Queue idleSlopeCredit Quantum or Weights register provides the average traffic transmitted in the Queue"
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hexmask.long.word 0x00 21.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1"
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group.long 0xD5C++0x03
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line.long 0x00 "GMAC_MTL_TxQ1_SendSlopeCredit,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue"
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hexmask.long.tbyte 0x00 14.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.word 0x00 0.--13. 1. "SSC,sendSlopeCredit When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1"
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group.long 0xD60++0x03
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line.long 0x00 "GMAC_MTL_TxQ1_HiCredit,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue"
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bitfld.long 0x00 29.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long 0x00 0.--28. 1. "HC,hiCredit When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm"
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group.long 0xD64++0x03
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line.long 0x00 "GMAC_MTL_TxQ1_LoCredit,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue"
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bitfld.long 0x00 29.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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hexmask.long 0x00 0.--28. 1. "LC,loCredit When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm"
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group.long 0xD6C++0x03
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line.long 0x00 "GMAC_MTL_Q1_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue interrupts"
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hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0,1"
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hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0,1"
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bitfld.long 0x00 10.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0,1"
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bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0,1"
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bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0,1"
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bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0,1"
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group.long 0x1000++0x03
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line.long 0x00 "GMAC_DMA_Mode,The Bus Mode register establishes the bus operating modes for the DMA"
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hexmask.long.word 0x00 18.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16.--17. "INTM,NA" "0,1,2,3"
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bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 12.--14. "PR,Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA" "0: The priority ratio is 1:1,1: The priority ratio is 2:1,2: The priority ratio is 3:1,3: The priority ratio is 4:1,4: The priority ratio is 5:1,5: The priority ratio is 6:1,6: The priority ratio is 7:1,7: The priority ratio is 8:1 In the EQOS-AXI"
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bitfld.long 0x00 11. "TXPR,Transmit Priority When set this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus" "0,1"
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bitfld.long 0x00 5.--10. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 2.--4. "TAA,Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for the Transmit side when multiple Tx DMAs are selected" "0: Fixed priority In fixed priority Channel 0 has,1: Weighted Strict Priority (WSP),2: Weighted Round-Robin (WRR) - 3'b011-3'b111,?..."
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bitfld.long 0x00 1. "DA,DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the Transmit and Receive paths of all channels" "0: Weighted Round-Robin with Rx,1: Fixed Priority The Tx path has priority over.."
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bitfld.long 0x00 0. "SWR,Software Reset When this bit is set the MAC and the DMA controller reset the logic and all internal registers of the DMA MTL and MAC" "0,1"
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group.long 0x1004++0x03
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line.long 0x00 "GMAC_DMA_SysBus_Mode,The System Bus mode register controls the behavior of the AHB or AXI master"
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bitfld.long 0x00 31. "EN_LPI,Enable Low Power Interface (LPI) When set to 1 this bit enables the LPI mode supported by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock controller" "0,1"
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bitfld.long 0x00 30. "LPI_XIT_PKT,Unlock on Magic Packet or Remote Wake-Up Packet When set to 1 this bit enables the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet is received" "0,1"
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bitfld.long 0x00 28.--29. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 24.--27. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit This value limits the maximum outstanding request on the AXI write interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RB,Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT RETRY or Early Burst Termination (EBT) response the AHB master interface rebuilds the pending beats of any initiated burst transfer with INCRx and SINGLE transfers" "0,1"
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bitfld.long 0x00 14. "MB,Mixed Burst When this bit is set high and the FB bit is low the AHB master performs undefined bursts transfers (INCR) for burst length of 16 or more" "0,1"
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bitfld.long 0x00 13. "ONEKBBE,1 KB Boundary Crossing Enable for the EQOS-AXI Master When set the burst transfers performed by the EQOS-AXI master do not cross 1 KB boundary" "0,1"
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bitfld.long 0x00 12. "AAL,Address-Aligned Beats When this bit is set to 1 the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels" "0,1"
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bitfld.long 0x00 11. "EAME,Enhanced Address Mode Enable" "0,1"
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bitfld.long 0x00 8.--10. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 7. "BLEN256,AXI Burst Length 256 When this bit is set to 1 the EQOS-AXI master can select a burst length of 256 on the AXI interface" "0,1"
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bitfld.long 0x00 6. "BLEN128,AXI Burst Length 128 When this bit is set to 1 the EQOS-AXI master can select a burst length of 128 on the AXI interface" "0,1"
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bitfld.long 0x00 5. "BLEN64,AXI Burst Length 64 When this bit is set to 1 the EQOS-AXI master can select a burst length of 64 on the AXI interface" "0,1"
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bitfld.long 0x00 4. "BLEN32,AXI Burst Length 32 When this bit is set to 1 the EQOS-AXI master can select a burst length of 32 on the AXI interface" "0,1"
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bitfld.long 0x00 3. "BLEN16,AXI Burst Length 16 When this bit is set to 1 and the FB bit is set to 1 the EQOS-AXI master can select a burst length of 16 on the AXI interface" "0,1"
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bitfld.long 0x00 2. "BLEN8,AXI Burst Length 8 When this bit is set to 1 and the FB bit is set to 1 the EQOS-AXI master can select a burst length of 8 on the AXI interface" "0,1"
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bitfld.long 0x00 1. "BLEN4,AXI Burst Length 4 When this bit is set to 1 and the FB bit is set to 1 the EQOS-AXI master can select a burst length of 4 on the AXI interface" "0,1"
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bitfld.long 0x00 0. "FB,Fixed Burst Length For EQOS-AXI Configurations: When this bit is set to 1 the EQOS-AXI master will initiate burst transfers of specified lengths as given below" "0,1"
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rgroup.long 0x1008++0x03
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line.long 0x00 "GMAC_DMA_Interrupt_Status,The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels MTL queues and the MAC"
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hexmask.long.word 0x00 18.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 17. "MACIS,MAC Interrupt Status This bit indicates an interrupt event in the MAC" "0,1"
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bitfld.long 0x00 16. "MTLIS,MTL Interrupt Status This bit indicates an interrupt event in the MTL" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 7. "DC7IS,DMA Channel 7 Interrupt Status This bit indicates an interrupt event in DMA Channel 7" "0,1"
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bitfld.long 0x00 6. "DC6IS,DMA Channel 6 Interrupt Status This bit indicates an interrupt event in DMA Channel 6" "0,1"
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bitfld.long 0x00 5. "DC5IS,DMA Channel 5 Interrupt Status This bit indicates an interrupt event in DMA Channel 5" "0,1"
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bitfld.long 0x00 4. "DC4IS,DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4" "0,1"
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bitfld.long 0x00 3. "DC3IS,DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3" "0,1"
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bitfld.long 0x00 2. "DC2IS,DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2" "0,1"
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bitfld.long 0x00 1. "DC1IS,DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1" "0,1"
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bitfld.long 0x00 0. "DC0IS,DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0" "0,1"
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rgroup.long 0x100C++0x03
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line.long 0x00 "GMAC_DMA_Debug_Status0,The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0-Channel 2 for debugging purpose"
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bitfld.long 0x00 28.--31. "TPS2,DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "RPS2,DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "TPS1,DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "RPS1,DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "TPS0,DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory buffer,4: Timestamp write state,5: Reserved for future use,6: Suspended (Tx Descriptor Unavailable or Tx,7: Running (Closing Tx Descriptor) This field does,?..."
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bitfld.long 0x00 8.--11. "RPS0,DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),2: Reserved for future use,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet data,?..."
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bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "AXRHSTS,AXI Master Read Channel Status When high this bit indicates that the read channel of the AXI master is active and it is transferring the data" "0,1"
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bitfld.long 0x00 0. "AXWHSTS,AXI Master Write Channel or AHB Master Status EQOS-AXI Configuration: When high this bit indicates that the write channel of the AXI master is active and it is transferring data" "0,1"
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group.long 0x1100++0x03
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line.long 0x00 "GMAC_DMA_CH0_Control,The DMA Channel 0 Control register specifies the MSS value for segmentation length to skip between two descriptors and also the features such as header splitting and 8xPBL mode"
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hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0,1"
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bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control is multiplied eight times" "0,1"
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bitfld.long 0x00 14.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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hexmask.long.word 0x00 0.--13. 1. "MSS,Maximum Segment Size This field specifies the maximum segment size that should be used while segmenting the packet"
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group.long 0x1104++0x03
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line.long 0x00 "GMAC_DMA_CH0_Tx_Control,The DMA Channel 0 Transmit Control register controls the Tx features such as PBL TCP segmentation and Tx Channel weights"
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hexmask.long.word 0x00 22.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0,1"
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bitfld.long 0x00 13.--14. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 12. "TSE,TCP Segmentation Enabled When this bit is set the DMA performs the TCP segmentation for packets in Channel 0" "0,1"
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bitfld.long 0x00 6.--11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 5. "RTS,NA" "0,1"
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bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0,1"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0,1"
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group.long 0x1108++0x03
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line.long 0x00 "GMAC_DMA_CH0_Rx_Control,The DMA Channel 0 Receive Control register controls the Rx features such as PBL buffer size and extended status"
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bitfld.long 0x00 31. "RPF,DMA Rx Channel0 Packet Flush When this bit is set to 1 the DMA will automatically flush the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is stopped after a system bus error has occurred" "0,1"
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hexmask.long.word 0x00 22.--30. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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hexmask.long.word 0x00 4.--14. 1. "RBSZ,Receive Buffer size This field indicates the size of the Rx buffers specified in bytes"
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bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0,1"
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group.long 0x1114++0x03
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line.long 0x00 "GMAC_DMA_CH0_TxDesc_List_Address,The Channel 0 Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list"
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hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x111C++0x03
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line.long 0x00 "GMAC_DMA_CH0_RxDesc_List_Address,The Channel 0 Rx Descriptor List Address register points the DMA to the start of Receive descriptor list"
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hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x1120++0x03
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line.long 0x00 "GMAC_DMA_CH0_TxDesc_Tail_Pointer,The Channel 0 Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor"
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hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x1128++0x03
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line.long 0x00 "GMAC_DMA_CH0_RxDesc_Tail_Pointer,The Channel 0 Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor"
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hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x112C++0x03
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line.long 0x00 "GMAC_DMA_CH0_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring"
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hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
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group.long 0x1130++0x03
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line.long 0x00 "GMAC_DMA_CH0_RxDesc_Ring_Length,The Channel 0 Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring"
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hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
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group.long 0x1134++0x03
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line.long 0x00 "GMAC_DMA_CH0_Interrupt_Enable,The Channel 0 Interrupt Enable register enables the interrupts reported by the Status register"
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hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0,1"
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bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0,1"
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bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Context Descriptor error interrupt is enabled" "0,1"
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bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0,1"
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bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0,1"
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bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0,1"
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bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0,1"
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bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0,1"
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bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0,1"
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bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0,1"
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bitfld.long 0x00 3.--5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0,1"
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bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0,1"
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bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0,1"
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group.long 0x1138++0x03
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line.long 0x00 "GMAC_DMA_CH0_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA"
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hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set"
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group.long 0x113C++0x03
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line.long 0x00 "GMAC_DMA_CH0_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path"
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hexmask.long.word 0x00 20.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0,1"
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bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0,1"
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rgroup.long 0x1144++0x03
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line.long 0x00 "GMAC_DMA_CH0_Current_App_TxDesc,The Channel 0 Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA"
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hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
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rgroup.long 0x114C++0x03
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line.long 0x00 "GMAC_DMA_CH0_Current_App_RxDesc,The Channel 0 Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA"
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hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
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rgroup.long 0x1150++0x03
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line.long 0x00 "GMAC_DMA_CH0_Current_App_TxBuffer_H,The Channeli Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA"
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hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 0.--7. 1. "CURTBUFAPTRH,NA"
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rgroup.long 0x1154++0x03
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line.long 0x00 "GMAC_DMA_CH0_Current_App_TxBuffer,The Channel 0 Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA"
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hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
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rgroup.long 0x1158++0x03
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line.long 0x00 "GMAC_DMA_CH0_Current_App_RxBuffer_H,The Channeli Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA"
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hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 0.--7. 1. "CURRBUFAPTRH,NA"
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rgroup.long 0x115C++0x03
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line.long 0x00 "GMAC_DMA_CH0_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA"
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hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
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group.long 0x1160++0x03
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line.long 0x00 "GMAC_DMA_CH0_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA"
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hexmask.long.word 0x00 19.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16.--18. "EB,DMA Error Bits This field indicates the type of error that caused a Bus Error" "0: Error during write transfer This field is valid,1: Error during read transfer,?..."
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bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit" "0,1"
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bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit" "0,1"
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bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx engine received a context descriptor in the middle of a packet (in an intermediate descriptor) and the DMA Tx engine ignored it" "0,1"
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bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0,1"
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bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet" "0,1"
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bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO" "0,1"
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bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0,1"
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bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0,1"
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bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0,1"
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bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0,1"
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bitfld.long 0x00 3.--5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0,1"
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bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0,1"
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bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0,1"
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rgroup.long 0x116C++0x03
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line.long 0x00 "GMAC_DMA_CH0_Miss_Frame_Cnt,NA"
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hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 15. "MFCO,NA" "0,1"
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bitfld.long 0x00 11.--14. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--10. 1. "MFC,NA"
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group.long 0x1180++0x03
|
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line.long 0x00 "GMAC_DMA_CH1_Control,The DMA Channel 0 Control register specifies the MSS value for segmentation length to skip between two descriptors and also the features such as header splitting and 8xPBL mode"
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hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0,1"
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bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control is multiplied eight times" "0,1"
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bitfld.long 0x00 14.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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hexmask.long.word 0x00 0.--13. 1. "MSS,Maximum Segment Size This field specifies the maximum segment size that should be used while segmenting the packet"
|
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group.long 0x1184++0x03
|
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line.long 0x00 "GMAC_DMA_CH1_Tx_Control,The DMA Channel 0 Transmit Control register controls the Tx features such as PBL TCP segmentation and Tx Channel weights"
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hexmask.long.word 0x00 22.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0,1"
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bitfld.long 0x00 13.--14. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
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bitfld.long 0x00 12. "TSE,TCP Segmentation Enabled When this bit is set the DMA performs the TCP segmentation for packets in Channel 0" "0,1"
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bitfld.long 0x00 6.--11. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 5. "RTS,NA" "0,1"
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|
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bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0,1"
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bitfld.long 0x00 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0,1"
|
|
group.long 0x1194++0x03
|
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line.long 0x00 "GMAC_DMA_CH1_TxDesc_List_Address,The Channel 0 Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list"
|
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hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11A0++0x03
|
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line.long 0x00 "GMAC_DMA_CH1_TxDesc_Tail_Pointer,The Channel 0 Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor"
|
|
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
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bitfld.long 0x00 0.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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group.long 0x11AC++0x03
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|
line.long 0x00 "GMAC_DMA_CH1_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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|
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hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
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|
group.long 0x11B4++0x03
|
|
line.long 0x00 "GMAC_DMA_CH1_Interrupt_Enable,The Channel 0 Interrupt Enable register enables the interrupts reported by the Status register"
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|
hexmask.long.word 0x00 16.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0,1"
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bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0,1"
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bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Context Descriptor error interrupt is enabled" "0,1"
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bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0,1"
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bitfld.long 0x00 11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0,1"
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|
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hexmask.long.byte 0x00 3.--9. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0,1"
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bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0,1"
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bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0,1"
|
|
group.long 0x11BC++0x03
|
|
line.long 0x00 "GMAC_DMA_CH1_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path"
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hexmask.long.word 0x00 20.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0,1"
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bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0,1"
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rgroup.long 0x11C4++0x03
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line.long 0x00 "GMAC_DMA_CH1_Current_App_TxDesc,The Channel 0 Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA"
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|
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
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|
rgroup.long 0x11D0++0x03
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|
line.long 0x00 "GMAC_DMA_CH1_Current_App_TxBuffer_H,The Channeli Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA"
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hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 0.--7. 1. "CURTBUFAPTRH,NA"
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|
rgroup.long 0x11D4++0x03
|
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line.long 0x00 "GMAC_DMA_CH1_Current_App_TxBuffer,The Channel 0 Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA"
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|
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
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|
rgroup.long 0x11D8++0x03
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line.long 0x00 "GMAC_DMA_CH1_Current_App_RxBuffer_H,The Channeli Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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|
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hexmask.long.byte 0x00 0.--7. 1. "CURRBUFAPTRH,NA"
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|
group.long 0x11E0++0x03
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line.long 0x00 "GMAC_DMA_CH1_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA"
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hexmask.long.word 0x00 19.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16.--18. "EB,DMA Error Bits This field indicates the type of error that caused a Bus Error" "0: Error during write transfer This field is valid,1: Error during read transfer,?..."
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newline
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bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit" "0,1"
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newline
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bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit" "0,1"
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newline
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bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx engine received a context descriptor in the middle of a packet (in an intermediate descriptor) and the DMA Tx engine ignored it" "0,1"
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newline
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bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0,1"
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newline
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bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet" "0,1"
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newline
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bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO" "0,1"
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|
newline
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bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0,1"
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bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0,1"
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bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0,1"
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|
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bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0,1"
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|
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|
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bitfld.long 0x00 3.--5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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|
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|
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bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0,1"
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|
newline
|
|
bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
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tree "RAP_DMAC0_CH"
|
|
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7.) (list ad:0xF8019000 ad:0xF8019040 ad:0xF8019080 ad:0xF80190C0 ad:0xF8019100 ad:0xF8019140 ad:0xF8019180 ad:0xF80191C0)
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|
tree "RAP_DMAC0_CH$1"
|
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base $2
|
|
group.long 0x00++0x03
|
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line.long 0x00 "RAP_DMAC_CH_N0SA,Next0 Source Address Register This register sets the DMA transfer source address (32 bits)"
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hexmask.long 0x00 0.--31. 1. "SA,Source Address Sets the start address of the DMA transfer source"
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group.long 0x04++0x03
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line.long 0x00 "RAP_DMAC_CH_N0DA,Next0 Destination Address Register This register sets the DMA transfer destination address (32 bits)"
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hexmask.long 0x00 0.--31. 1. "DA,Destination Address Sets the start address of the DMA transfer destination"
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|
group.long 0x08++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_N0TB,Next0 Transaction Byte Register This register sets the total transfer byte count (DMA transaction)"
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|
hexmask.long 0x00 0.--31. 1. "TB,Transaction Byte Sets the total transfer byte count"
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group.long 0x0C++0x03
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line.long 0x00 "RAP_DMAC_CH_N1SA,Next1 Source Address Register This register sets the DMA transfer source address (32 bits)"
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hexmask.long 0x00 0.--31. 1. "SA,Source Address Sets the start address of the DMA transfer source"
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group.long 0x10++0x03
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line.long 0x00 "RAP_DMAC_CH_N1DA,Next1 Destination Address Resister This register sets the DMA transfer destination address (32 bits)"
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hexmask.long 0x00 0.--31. 1. "DA,Destination Address Sets the start address of the DMA transfer destination"
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group.long 0x14++0x03
|
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line.long 0x00 "RAP_DMAC_CH_N1TB,Next1 Transaction Byte Register This register sets the total transfer byte count (DMA transaction)"
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hexmask.long 0x00 0.--31. 1. "TB,Transaction Byte Sets the total transfer byte count"
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rgroup.long 0x18++0x03
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line.long 0x00 "RAP_DMAC_CH_CRSA,Current Source Address Register This register indicates the DMA transfer source address"
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hexmask.long 0x00 0.--31. 1. "CRSA,Current Source Address Register Indicates the read address of the next DMA transaction"
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rgroup.long 0x1C++0x03
|
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line.long 0x00 "RAP_DMAC_CH_CRDA,Current Destination Address Register This register indicates the DMA transfer destination address"
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hexmask.long 0x00 0.--31. 1. "CRDA,Current Destination Address Register Indicates the write address of the next DMA transaction"
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rgroup.long 0x20++0x03
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line.long 0x00 "RAP_DMAC_CH_CRTB,Current Transaction Byte Register This register indicates the total transfer byte count"
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hexmask.long 0x00 0.--31. 1. "CRTB,Current Transaction Byte Register Indicates the remaining transfer byte count of the currently executed DMA transaction"
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rgroup.long 0x24++0x03
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line.long 0x00 "RAP_DMAC_CH_CHSTAT,Channel Status Register This register indicates the status"
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hexmask.long.word 0x00 17.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16. "INTMASK,Indicates the temporary mask status of the DMAEND[n] interrupt pin output" "0: Unmasked temporarily Set condition(s),1: When SWRST is set to 1"
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newline
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bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "MODE,DMA Mode Indicates the DMA mode" "0: Register mode,1: Link mode"
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newline
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bitfld.long 0x00 10. "DER,Descriptor Error Indicates whether the link valid value of the read descriptor is invalid (LV = 0) (this is not dependent on the DIM level of the CHCFG register)" "0: Descriptor Error not detected,1: Descriptor Error detected Set condition(s)"
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bitfld.long 0x00 9. "DW,Descriptor WriteBack Indicates the descriptor writeback status" "0: Operation other than writeback is being,1: (ER = 0) Writeback is being performed for the"
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newline
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bitfld.long 0x00 8. "DL,Descriptor Load Indicates whether the descriptor is being loaded" "0: Operation other than descriptor load,1: (ER = 0) Descriptor load is in progress in link"
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bitfld.long 0x00 7. "SR,Selected Register Set Indicates the register set currently selected in register mode" "0: Next0 Register Set,1: Next1 Register Set Set condition(s)"
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newline
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bitfld.long 0x00 6. "TC,Terminal Count Indicates whether the DMA transaction is completed" "0: DMA transfer not completed,1: When the SWRST (CHCTRL) bit is set to 1"
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bitfld.long 0x00 5. "END,DMAEND Interrupted Indicates whether the DMA transaction is completed and whether the DMAEND interrupt has occurred" "0: DMA transfer not completed,1: When SWRST (CHCTRL) is set to 1"
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newline
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bitfld.long 0x00 4. "ER,Error bit Indicates whether an ERROR response has been received and whether the DMAERR interrupt has occurred during the DMA transfer" "0: ERROR response not received,1: ERROR response received Set condition(s)"
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bitfld.long 0x00 3. "SUS,Suspend Indicates whether the channel is suspended" "0: Channel_n not suspended,1: When CLREN is set to 1"
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newline
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bitfld.long 0x00 2. "TACT,Transaction Active Indicates whether the DMAC is active" "0: DMA on Channel_n inactive,1: DMA on Channel_n active Set condition(s)"
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bitfld.long 0x00 1. "RQST,Request Indicates whether a transfer request is being received" "0: When the master interface receives a bus error,1: When a transfer is executed on the side"
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newline
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bitfld.long 0x00 0. "EN,Enable Indicates whether the operation of DMA channel n is enabled or disabled" "0: Operation disabled,1: When an error response is received during the"
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group.long 0x28++0x03
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line.long 0x00 "RAP_DMAC_CH_CHCTRL,Channel Control Register This register controls the DMA transfer operation"
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hexmask.long.word 0x00 18.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 17. "CLRINTMSK,When this bit is set to 1 the mask of the DMAEND[n] pin output is cleared" "0: Does not affect the operation,1: Clears the mask set by SETINTMSK"
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newline
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bitfld.long 0x00 16. "SETINTMSK,When this bit is set to 1 the DMAEND[n] pin output is temporarily masked" "0: Does not affect the operation,1: Masks DMAEND[n]"
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bitfld.long 0x00 10.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
|
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bitfld.long 0x00 9. "CLRSUS,Clear Suspend Clears the suspend status" "0: Does not affect the operation,1: Clears the suspend status of the current DMA"
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bitfld.long 0x00 8. "SETSUS,Set Suspend Suspends the current DMA transfer" "0: Does not affect the operation,1: Suspends the current DMA transfer"
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newline
|
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bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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|
bitfld.long 0x00 6. "CLRTC,Clear TC bit Setting this bit to 1 can clear the TC bit of the CHSTAT register" "0: Does not affect the operation,1: Clears the TC bit"
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newline
|
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bitfld.long 0x00 5. "CLREND,Clear End bit Setting this bit to 1 can clear the END bit of the CHSTAT register" "0: Does not affect the operation,1: Clears the END bit"
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bitfld.long 0x00 4. "CLRRQ,Clear Request bit Setting this bit to 1 can clear the RQST bit of the CHSTAT register" "0: Does not affect the operation,1: Clears the RQST bit"
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newline
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bitfld.long 0x00 3. "SWRST,Software Reset Setting this bit to 1 can clear the status register" "0: Does not affect the operation,1: Resets the channel status register"
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bitfld.long 0x00 2. "STG,Software Trigger Setting this bit to 1 sets an internal transfer request (software trigger)" "0: Does not affect the operation,1: Sets a software-triggered transfer request.."
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newline
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bitfld.long 0x00 1. "CLREN,Clear Enable Setting this bit to 1 can clear the EN bit (for details see Section 8.10.3)" "0: Does not affect the operation,1: Stops the DMA transfer (clears the EN bit)"
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bitfld.long 0x00 0. "SETEN,Set Enable Enables a DMA transfer on DMA channel n" "0: Does not affect the operation,1: Enables a DMA transfer (sets 1 in the EN bit)"
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group.long 0x2C++0x03
|
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line.long 0x00 "RAP_DMAC_CH_CHCFG,Channel Configuration Register This register controls the DMA transfer operation"
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bitfld.long 0x00 31. "DMS,DMA Mode Select Sets the DMA mode" "0: Register mode (initial,1: Link mode"
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bitfld.long 0x00 30. "REN,Register Set Enable After a DMA transaction is completed DMA transfers are continued using the Next register set selected by RSEL" "0: Does not continue DMA transfers,1: Continues DMA transfers"
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newline
|
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bitfld.long 0x00 29. "RSW,Register Select Switch Inverts RSEL automatically after a DMA transaction is completed" "0: Does not invert RSEL automatically after a DMA,1: Inverts RSEL automatically after a DMA.."
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|
bitfld.long 0x00 28. "RSEL,Register Set Select Selects the Next register set to be executed next" "0: Executes the Next0 Register Set (initial value),1: Executes the Next1 Register Set"
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newline
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bitfld.long 0x00 27. "SBE,Sweep Buffer Enable Selects whether to sweep (write) the data already read into the buffer and stop the DMA transfer if the Enable bit is cleared to 0 during a DMA transaction" "0: Stops the DMA transfer without sweeping the,1: Stops the DMA transfer after sweeping the.."
|
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bitfld.long 0x00 26. "bf_align3,bitField alignment value for aeabi compatibility" "0,1"
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|
newline
|
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bitfld.long 0x00 25. "TCM,DMATCO Mask Masks the DMATCO[n] interrupt pin output" "0: Does not mask DMATCO (initial value),1: Masks DMATCO"
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bitfld.long 0x00 24. "DEM,DMAEND Mask Masks the interrupt pin output of DMAEND[m] (where m is the pin selected by SEL) for register mode transfer" "0: Does not mask DMAEND (initial value),1: Masks DMAEND"
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newline
|
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bitfld.long 0x00 23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 22. "TM,Transfer Mode Sets the DMA transfer mode" "0: Single transfer mode (initial value),1: Block transfer mode"
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newline
|
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bitfld.long 0x00 21. "DAD,Sets the destination address counting direction of DMA channel n" "0: Increment (initial value),1: Fixed Do not set 1 (fixed) in DAD when the SKIP"
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bitfld.long 0x00 20. "SAD,Sets the source address counting direction of DMA channel n" "0: Increment (initial value),1: Fixed Do not set 1 (fixed) in SAD when the SKIP"
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newline
|
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bitfld.long 0x00 16.--19. "DDS,Destination Data Size Sets the DMA transfer size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "SDS,Source Data Size Sets the DMA transfer size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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bitfld.long 0x00 11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 8.--10. "AM,ACK Mode Sets the DMAACK[n] output mode" "0: Pulse mode (active for the duration of a clock),1: Level mode (active until the selected DMAREQ,?..."
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newline
|
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bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 6. "LVL,Level Selects whether to detect a DMA request based on the level or edge of the signal" "0: Detects based on the edge (initial value),1: Detects based on the level"
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newline
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bitfld.long 0x00 5. "HIEN,High Enable Selects whether to detect a DMA request using the High level or rising edge of the signal" "0: Does not detect a request even when the signal,1: Detects a request when the signal is at the.."
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bitfld.long 0x00 4. "LOEN,Low Enable Selects whether to detect a DMA request using the Low level or falling edge of the signal" "0: Does not detect a request even when the signal,1: Detects a request when the signal is at the Low"
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newline
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bitfld.long 0x00 3. "REQD,Request Direction Selects whether DMAREQ selected by the SEL bit is the source or destination" "0: Source DMAACK is to become active when read,1: Destination DMAACK is to become active when"
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|
bitfld.long 0x00 0.--2. "SEL,Terminal Select Selects one of the eight DMAREQ/DMAACK/DMATCO signals" "0,1,2,3,4,5,6,7"
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|
group.long 0x30++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_CHITVL,Channel Interval Register This register sets the transfer interval"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "ITVL,Sets the channel transfer interval"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_CHEXT,Channel Extension Register This is an extension register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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|
bitfld.long 0x00 12.--15. "DCA,Destination CACHE Sets the value to be output to CACHE[3:0] for DMA write transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 8.--10. "DPR,Destination PROT Sets the value to be output to PROT[2:0] for DMA write transfer" "0,1,2,3,4,5,6,7"
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|
newline
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bitfld.long 0x00 4.--7. "SCA,Source CACHE Sets the value to be output to CACHE[3:0] for DMA read transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
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bitfld.long 0x00 0.--2. "SPR,Source PROT Sets the value to be output to PROT[2:0] for DMA read transfer" "0,1,2,3,4,5,6,7"
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|
group.long 0x38++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_NXLA,Next Link Address Resister This is a 32-bit register that stores the link address of DMA channel n (n = 3 to 0)"
|
|
hexmask.long 0x00 0.--31. 1. "NXLA,Sets a link address"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_CRLA,Current Link Address Resister This is a 32-bit register that stores the link address of DMA channel n (n = 3 to 0)"
|
|
hexmask.long 0x00 0.--31. 1. "CRLA,Indicates the address of the currently executed descriptor"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "RAP_DMAC0_REG"
|
|
base ad:0xF8019300
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RAP_DMAC_REG_DCTRL,DMA Control Register This register sets the transfer type for descriptor access and the arbitration between channels"
|
|
bitfld.long 0x00 28.--31. "LWCA,Link WriteBack CACHE Sets the value to be output to CACHE[3:0] during descriptor writeback in link mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "LWPR,Link WriteBack PROT Sets the value to be output to MHPROT[2:0] during descriptor writeback in link mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--23. "LDCA,Link Descriptor CACHE Sets the value to be output to CACHE[3:0] during descriptor load in link mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 16.--18. "LDPR,Link Descriptor PROT Sets the value to be output to MHPROT[2:0] during descriptor load in link mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "LVINT,Sets whether to use pulse output or level output for DMAEND[7:0] and DMAERR" "0: Pulse output (initial value),1: Level output"
|
|
newline
|
|
bitfld.long 0x00 0. "PR,Sets the transfer priority control mode between channels (see 'Priority Control for DMA Channels')" "0: Fixed priority mode (initial value),1: Round robin mode"
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|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RAP_DMAC_REG_DST_EN,DMA Status EN Register This register indicates the EN bit status of all channels"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EN,Indicates the EN bit status of DMA channels 0-7"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RAP_DMAC_REG_DST_ER,DMA Status ER Register This register indicates the ER bit status of all channels"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ER,Indicates the ER bit status of DMA channels 0-7"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RAP_DMAC_REG_DST_END,DMA Status END Register This register indicates the END bit status of all channels"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "END,Indicates the END bit status of DMA channels 0-7"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RAP_DMAC_REG_DST_TC,DMA Status TC Register This register indicates the TC bit status of all channels"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TC,Indicates the TC bit status of DMA channels 0-7"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RAP_DMAC_REG_DST_SUS,DMA Status SUS Register This register indicates the SUS bit status of all channels"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SUS,Indicates the SUS bit status of DMA channels 0-7"
|
|
tree.end
|
|
tree "RAP_DMAC1_CH"
|
|
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7.) (list ad:0xF8019400 ad:0xF8019440 ad:0xF8019480 ad:0xF80194C0 ad:0xF8019500 ad:0xF8019540 ad:0xF8019580 ad:0xF80195C0)
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|
tree "RAP_DMAC1_CH$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_N0SA,Next0 Source Address Register This register sets the DMA transfer source address (32 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "SA,Source Address Sets the start address of the DMA transfer source"
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|
group.long 0x04++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_N0DA,Next0 Destination Address Register This register sets the DMA transfer destination address (32 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "DA,Destination Address Sets the start address of the DMA transfer destination"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_N0TB,Next0 Transaction Byte Register This register sets the total transfer byte count (DMA transaction)"
|
|
hexmask.long 0x00 0.--31. 1. "TB,Transaction Byte Sets the total transfer byte count"
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|
group.long 0x0C++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_N1SA,Next1 Source Address Register This register sets the DMA transfer source address (32 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "SA,Source Address Sets the start address of the DMA transfer source"
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|
group.long 0x10++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_N1DA,Next1 Destination Address Resister This register sets the DMA transfer destination address (32 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "DA,Destination Address Sets the start address of the DMA transfer destination"
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|
group.long 0x14++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_N1TB,Next1 Transaction Byte Register This register sets the total transfer byte count (DMA transaction)"
|
|
hexmask.long 0x00 0.--31. 1. "TB,Transaction Byte Sets the total transfer byte count"
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|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_CRSA,Current Source Address Register This register indicates the DMA transfer source address"
|
|
hexmask.long 0x00 0.--31. 1. "CRSA,Current Source Address Register Indicates the read address of the next DMA transaction"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_CRDA,Current Destination Address Register This register indicates the DMA transfer destination address"
|
|
hexmask.long 0x00 0.--31. 1. "CRDA,Current Destination Address Register Indicates the write address of the next DMA transaction"
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|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_CRTB,Current Transaction Byte Register This register indicates the total transfer byte count"
|
|
hexmask.long 0x00 0.--31. 1. "CRTB,Current Transaction Byte Register Indicates the remaining transfer byte count of the currently executed DMA transaction"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_CHSTAT,Channel Status Register This register indicates the status"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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|
bitfld.long 0x00 16. "INTMASK,Indicates the temporary mask status of the DMAEND[n] interrupt pin output" "0: Unmasked temporarily Set condition(s),1: When SWRST is set to 1"
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|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. "MODE,DMA Mode Indicates the DMA mode" "0: Register mode,1: Link mode"
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|
newline
|
|
bitfld.long 0x00 10. "DER,Descriptor Error Indicates whether the link valid value of the read descriptor is invalid (LV = 0) (this is not dependent on the DIM level of the CHCFG register)" "0: Descriptor Error not detected,1: Descriptor Error detected Set condition(s)"
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|
bitfld.long 0x00 9. "DW,Descriptor WriteBack Indicates the descriptor writeback status" "0: Operation other than writeback is being,1: (ER = 0) Writeback is being performed for the"
|
|
newline
|
|
bitfld.long 0x00 8. "DL,Descriptor Load Indicates whether the descriptor is being loaded" "0: Operation other than descriptor load,1: (ER = 0) Descriptor load is in progress in link"
|
|
bitfld.long 0x00 7. "SR,Selected Register Set Indicates the register set currently selected in register mode" "0: Next0 Register Set,1: Next1 Register Set Set condition(s)"
|
|
newline
|
|
bitfld.long 0x00 6. "TC,Terminal Count Indicates whether the DMA transaction is completed" "0: DMA transfer not completed,1: When the SWRST (CHCTRL) bit is set to 1"
|
|
bitfld.long 0x00 5. "END,DMAEND Interrupted Indicates whether the DMA transaction is completed and whether the DMAEND interrupt has occurred" "0: DMA transfer not completed,1: When SWRST (CHCTRL) is set to 1"
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|
newline
|
|
bitfld.long 0x00 4. "ER,Error bit Indicates whether an ERROR response has been received and whether the DMAERR interrupt has occurred during the DMA transfer" "0: ERROR response not received,1: ERROR response received Set condition(s)"
|
|
bitfld.long 0x00 3. "SUS,Suspend Indicates whether the channel is suspended" "0: Channel_n not suspended,1: When CLREN is set to 1"
|
|
newline
|
|
bitfld.long 0x00 2. "TACT,Transaction Active Indicates whether the DMAC is active" "0: DMA on Channel_n inactive,1: DMA on Channel_n active Set condition(s)"
|
|
bitfld.long 0x00 1. "RQST,Request Indicates whether a transfer request is being received" "0: When the master interface receives a bus error,1: When a transfer is executed on the side"
|
|
newline
|
|
bitfld.long 0x00 0. "EN,Enable Indicates whether the operation of DMA channel n is enabled or disabled" "0: Operation disabled,1: When an error response is received during the"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_CHCTRL,Channel Control Register This register controls the DMA transfer operation"
|
|
hexmask.long.word 0x00 18.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 17. "CLRINTMSK,When this bit is set to 1 the mask of the DMAEND[n] pin output is cleared" "0: Does not affect the operation,1: Clears the mask set by SETINTMSK"
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|
newline
|
|
bitfld.long 0x00 16. "SETINTMSK,When this bit is set to 1 the DMAEND[n] pin output is temporarily masked" "0: Does not affect the operation,1: Masks DMAEND[n]"
|
|
bitfld.long 0x00 10.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 9. "CLRSUS,Clear Suspend Clears the suspend status" "0: Does not affect the operation,1: Clears the suspend status of the current DMA"
|
|
bitfld.long 0x00 8. "SETSUS,Set Suspend Suspends the current DMA transfer" "0: Does not affect the operation,1: Suspends the current DMA transfer"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 6. "CLRTC,Clear TC bit Setting this bit to 1 can clear the TC bit of the CHSTAT register" "0: Does not affect the operation,1: Clears the TC bit"
|
|
newline
|
|
bitfld.long 0x00 5. "CLREND,Clear End bit Setting this bit to 1 can clear the END bit of the CHSTAT register" "0: Does not affect the operation,1: Clears the END bit"
|
|
bitfld.long 0x00 4. "CLRRQ,Clear Request bit Setting this bit to 1 can clear the RQST bit of the CHSTAT register" "0: Does not affect the operation,1: Clears the RQST bit"
|
|
newline
|
|
bitfld.long 0x00 3. "SWRST,Software Reset Setting this bit to 1 can clear the status register" "0: Does not affect the operation,1: Resets the channel status register"
|
|
bitfld.long 0x00 2. "STG,Software Trigger Setting this bit to 1 sets an internal transfer request (software trigger)" "0: Does not affect the operation,1: Sets a software-triggered transfer request.."
|
|
newline
|
|
bitfld.long 0x00 1. "CLREN,Clear Enable Setting this bit to 1 can clear the EN bit (for details see Section 8.10.3)" "0: Does not affect the operation,1: Stops the DMA transfer (clears the EN bit)"
|
|
bitfld.long 0x00 0. "SETEN,Set Enable Enables a DMA transfer on DMA channel n" "0: Does not affect the operation,1: Enables a DMA transfer (sets 1 in the EN bit)"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_CHCFG,Channel Configuration Register This register controls the DMA transfer operation"
|
|
bitfld.long 0x00 31. "DMS,DMA Mode Select Sets the DMA mode" "0: Register mode (initial,1: Link mode"
|
|
bitfld.long 0x00 30. "REN,Register Set Enable After a DMA transaction is completed DMA transfers are continued using the Next register set selected by RSEL" "0: Does not continue DMA transfers,1: Continues DMA transfers"
|
|
newline
|
|
bitfld.long 0x00 29. "RSW,Register Select Switch Inverts RSEL automatically after a DMA transaction is completed" "0: Does not invert RSEL automatically after a DMA,1: Inverts RSEL automatically after a DMA.."
|
|
bitfld.long 0x00 28. "RSEL,Register Set Select Selects the Next register set to be executed next" "0: Executes the Next0 Register Set (initial value),1: Executes the Next1 Register Set"
|
|
newline
|
|
bitfld.long 0x00 27. "SBE,Sweep Buffer Enable Selects whether to sweep (write) the data already read into the buffer and stop the DMA transfer if the Enable bit is cleared to 0 during a DMA transaction" "0: Stops the DMA transfer without sweeping the,1: Stops the DMA transfer after sweeping the.."
|
|
bitfld.long 0x00 26. "bf_align3,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "TCM,DMATCO Mask Masks the DMATCO[n] interrupt pin output" "0: Does not mask DMATCO (initial value),1: Masks DMATCO"
|
|
bitfld.long 0x00 24. "DEM,DMAEND Mask Masks the interrupt pin output of DMAEND[m] (where m is the pin selected by SEL) for register mode transfer" "0: Does not mask DMAEND (initial value),1: Masks DMAEND"
|
|
newline
|
|
bitfld.long 0x00 23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 22. "TM,Transfer Mode Sets the DMA transfer mode" "0: Single transfer mode (initial value),1: Block transfer mode"
|
|
newline
|
|
bitfld.long 0x00 21. "DAD,Sets the destination address counting direction of DMA channel n" "0: Increment (initial value),1: Fixed Do not set 1 (fixed) in DAD when the SKIP"
|
|
bitfld.long 0x00 20. "SAD,Sets the source address counting direction of DMA channel n" "0: Increment (initial value),1: Fixed Do not set 1 (fixed) in SAD when the SKIP"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "DDS,Destination Data Size Sets the DMA transfer size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "SDS,Source Data Size Sets the DMA transfer size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 8.--10. "AM,ACK Mode Sets the DMAACK[n] output mode" "0: Pulse mode (active for the duration of a clock),1: Level mode (active until the selected DMAREQ,?..."
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 6. "LVL,Level Selects whether to detect a DMA request based on the level or edge of the signal" "0: Detects based on the edge (initial value),1: Detects based on the level"
|
|
newline
|
|
bitfld.long 0x00 5. "HIEN,High Enable Selects whether to detect a DMA request using the High level or rising edge of the signal" "0: Does not detect a request even when the signal,1: Detects a request when the signal is at the.."
|
|
bitfld.long 0x00 4. "LOEN,Low Enable Selects whether to detect a DMA request using the Low level or falling edge of the signal" "0: Does not detect a request even when the signal,1: Detects a request when the signal is at the Low"
|
|
newline
|
|
bitfld.long 0x00 3. "REQD,Request Direction Selects whether DMAREQ selected by the SEL bit is the source or destination" "0: Source DMAACK is to become active when read,1: Destination DMAACK is to become active when"
|
|
bitfld.long 0x00 0.--2. "SEL,Terminal Select Selects one of the eight DMAREQ/DMAACK/DMATCO signals" "0,1,2,3,4,5,6,7"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_CHITVL,Channel Interval Register This register sets the transfer interval"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "ITVL,Sets the channel transfer interval"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_CHEXT,Channel Extension Register This is an extension register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 12.--15. "DCA,Destination CACHE Sets the value to be output to CACHE[3:0] for DMA write transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 8.--10. "DPR,Destination PROT Sets the value to be output to PROT[2:0] for DMA write transfer" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "SCA,Source CACHE Sets the value to be output to CACHE[3:0] for DMA read transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SPR,Source PROT Sets the value to be output to PROT[2:0] for DMA read transfer" "0,1,2,3,4,5,6,7"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_NXLA,Next Link Address Resister This is a 32-bit register that stores the link address of DMA channel n (n = 3 to 0)"
|
|
hexmask.long 0x00 0.--31. 1. "NXLA,Sets a link address"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "RAP_DMAC_CH_CRLA,Current Link Address Resister This is a 32-bit register that stores the link address of DMA channel n (n = 3 to 0)"
|
|
hexmask.long 0x00 0.--31. 1. "CRLA,Indicates the address of the currently executed descriptor"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "RAP_DMAC1_REG"
|
|
base ad:0xF8019700
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RAP_DMAC_REG_DCTRL,DMA Control Register This register sets the transfer type for descriptor access and the arbitration between channels"
|
|
bitfld.long 0x00 28.--31. "LWCA,Link WriteBack CACHE Sets the value to be output to CACHE[3:0] during descriptor writeback in link mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "LWPR,Link WriteBack PROT Sets the value to be output to MHPROT[2:0] during descriptor writeback in link mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--23. "LDCA,Link Descriptor CACHE Sets the value to be output to CACHE[3:0] during descriptor load in link mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 16.--18. "LDPR,Link Descriptor PROT Sets the value to be output to MHPROT[2:0] during descriptor load in link mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "LVINT,Sets whether to use pulse output or level output for DMAEND[7:0] and DMAERR" "0: Pulse output (initial value),1: Level output"
|
|
newline
|
|
bitfld.long 0x00 0. "PR,Sets the transfer priority control mode between channels (see 'Priority Control for DMA Channels')" "0: Fixed priority mode (initial value),1: Round robin mode"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RAP_DMAC_REG_DST_EN,DMA Status EN Register This register indicates the EN bit status of all channels"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EN,Indicates the EN bit status of DMA channels 0-7"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RAP_DMAC_REG_DST_ER,DMA Status ER Register This register indicates the ER bit status of all channels"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ER,Indicates the ER bit status of DMA channels 0-7"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RAP_DMAC_REG_DST_END,DMA Status END Register This register indicates the END bit status of all channels"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "END,Indicates the END bit status of DMA channels 0-7"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RAP_DMAC_REG_DST_TC,DMA Status TC Register This register indicates the TC bit status of all channels"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TC,Indicates the TC bit status of DMA channels 0-7"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RAP_DMAC_REG_DST_SUS,DMA Status SUS Register This register indicates the SUS bit status of all channels"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SUS,Indicates the SUS bit status of DMA channels 0-7"
|
|
tree.end
|
|
tree "RAP_I2C"
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5.) (list ad:0xF801B800 ad:0xF801B900 ad:0xF801BA00 ad:0xF801BB00 ad:0xF801BC00 ad:0xF801BD00)
|
|
tree "RAP_I2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "i2c_mcr,I2C master control register"
|
|
hexmask.long.word 0x00 19.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 18. "en_timeout,Enable I2C command timeout detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "rst_i2c,Reset the I2C bus-state-detection logic" "0,1"
|
|
bitfld.long 0x00 16. "pio_mode,If this bit is set SCL and SDA can be controlled directly by register i2c_pio (e.g. to access devices being incompatible with I2C)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 4.--10. 1. "sadr,7-bit slave address sent after (r)START: For 10-bit addressing the first byte (10-bit start '11110' address bits[9:8] must be programmed here. The second start byte (lower slave address bits) must be on top of the master FIFO (i2c_mdr). This.."
|
|
newline
|
|
bitfld.long 0x00 1.--3. "mode,I2C-speed-mode: If this device is used as a slave only the mode should be set to the data rate generated by the fastest master on the I2C-bus for appropriate input filtering and spike suppression" "0: Fast/Standard mode 50 kbit/s,1: Fast/Standard mode 100 kbit/s,2: Fast/Standard mode 200 kbit/s,3: Fast/Standard mode 400 kbit/s,4: High-speed mode 800 kbit/s,5: High-speed mode 1.2 Mbit/s,6: High-speed mode 1.7 Mbit/s,7: High-speed mode 3.4 Mbit/s)"
|
|
bitfld.long 0x00 0. "en_i2c,Global I2C controller enable" "0: Disable I2C controller Disabling the I2C module,1: Enable I2C controller"
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|
group.long 0x04++0x03
|
|
line.long 0x00 "i2c_scr,I2C slave control register"
|
|
hexmask.long.word 0x00 21.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 20. "autoreset_ac_start,Auto reset ac_start (ac_start must be set again after any (r)START)" "0: ac_start will not be reset automatically (netX,1: Reset ac_start after this slave acknowledged a"
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|
newline
|
|
bitfld.long 0x00 19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 18. "ac_gcall,General call acknowledge" "0: Do not generate an acknowledge after a general,1: Generate an acknowledge after a general call"
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|
newline
|
|
bitfld.long 0x00 17. "ac_start,Enable start sequence acknowledge: If the received address matches the sid-bits the start-byte (2 bytes if sid10 is set) will be acknowledged" "0: Do not generate an acknowledge after the start,1: Generate an acknowledge after the start.."
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|
bitfld.long 0x00 16. "ac_srx,Enable slave-receive-data acknowledge" "0: Do not acknowledge receive bytes,1: Acknowledge receive bytes If the slave FIFO is"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 10. "sid10,10-bit slave device ID/address" "0: Wait for 7-bit slave address after (r)START,1: Wait for 10-bit slave address after (r)START"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "sid,Slave device ID/address: External masters can address this device (this I2C module in slave mode) by the ID/address programmed here"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "i2c_cmd,I2C master command register"
|
|
bitfld.long 0x00 28.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
hexmask.long.byte 0x00 20.--27. 1. "acpollmax,Number of tries (acpollmax+1 i.e. 1 to 256) for start sequence acknowledge polling: For 7-bit addressing acknowledge polling START and the first byte containing the slave address (i2c_mcr.sadr) will be repeated up to acpollmax+1 times until a.."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
hexmask.long.word 0x00 8.--17. 1. "tsize,Transfer tsize+1 bytes (1...1024): If no acknowledge is generated by the slave (receiver) write transfers will be terminated and IRQ cmd_err will be generated"
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|
newline
|
|
bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 1.--3. "cmd,I2C sequence command: All commands will generate IRQ cmd_ok or IRQ cmd_err" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "nwr,Transfer direction (not-write/read)" "0: cmd will be executed as,1: cmd will be executed as read Master"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "i2c_mdr,I2C master data register (master FIFO): There is only one FIFO for both receive and transmit master data with a depth of 16 bytes"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "mdata,I2C master transmit or receive data: Write data will be removed from the FIFO after the receiving slave has generated the corresponding acknowledge"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "i2c_sdr,I2C slave data register (slave FIFO): There is only one FIFO for both receive and transmit slave data with a depth of 16 bytes"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "sdata,I2C slave transmit or receive data: The software must handle i2c_scr.ac_start correctly to avoid FIFO errors after (r)START"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "i2c_mfifo_cr,I2C master FIFO control register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "mfifo_clr,Clear master data FIFO write only bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "mfifo_wm,Master FIFO watermark for the generation of IRQ mfifo_req: If the master is the transmitter (enabled and i2c_cmd.nwr is 0) IRQ mfifo_req is generated if mfifo_level<mfifo_wm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "i2c_sfifo_cr,I2C slave FIFO control register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "sfifo_clr,Clear slave data FIFO write only bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "sfifo_wm,Slave FIFO watermark for the generation of IRQ sfifo_req: If the slave is the transmitter (start sequence with set read bit was acknowledged by this slave) IRQ sfifo_req is generated if sfifo_level<sfifo_wm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "i2c_sr,I2C status register"
|
|
bitfld.long 0x00 31. "sda_state,SDA signal state sampled and filtered from bus (e.g. to detect bus blockings) This is a read-only status bit" "0,1"
|
|
bitfld.long 0x00 30. "scl_state,SCL signal state sampled and filtered from bus (e.g. to detect bus blockings) This is a read-only status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 28. "timeout,I2C command timeout detection (for I2C master)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "sid10_aced,10-bit slave address acknowledge state" "0: There was no 10-bit slave address or it was not,1: A 10-bit slave address was broadcasted and a"
|
|
bitfld.long 0x00 26. "gcall_aced,General call acknowledge state" "0: No general call start-byte or general call,1: The slave side of the i2c module received and"
|
|
newline
|
|
bitfld.long 0x00 25. "nwr_aced,Transfer direction (nwr-bit) of the last acknowledged start-byte (or 2-byte start sequence for 10-bit addressing)" "0: The last acknowledged start-byte defined a..,1: The last acknowledged start-byte defined a read"
|
|
bitfld.long 0x00 24. "last_ac,Last acknowledge detected on bus" "0: SDA was high at the last acknowledge i.e,1: SDA was low at the last acknowledge i.e"
|
|
newline
|
|
bitfld.long 0x00 23. "slave_access,Slave access state" "0: No slave access to this device,1: A master addressed this slave device"
|
|
bitfld.long 0x00 22. "started,START condition detection" "0: The bus is idle (STOP was detected not started),1: (r)START was detected on the bus"
|
|
newline
|
|
bitfld.long 0x00 21. "nwr,Transfer direction detected after last (r)START" "0: The last start-byte defined a write transfer,1: The last start-byte defined a read transfer"
|
|
bitfld.long 0x00 20. "bus_master,Bus arbitration state" "0: Master lost I2C bus arbitration bus is busy by,1: Master gains I2C bus arbitration or bus is idle"
|
|
newline
|
|
bitfld.long 0x00 19. "sfifo_err_undr,Slave FIFO underrun error occurred" "0,1"
|
|
bitfld.long 0x00 18. "sfifo_err_ovfl,Slave FIFO overflow error occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "sfifo_full,Slave FIFO is full (1 if full) This is a read-only status bit" "0,1"
|
|
bitfld.long 0x00 16. "sfifo_empty,Slave FIFO is empty (1 if empty) This is a read-only status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 10.--14. "sfifo_level,Slave FIFO level (0..16) This is a read-only status bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 9. "mfifo_err_undr,Master FIFO underrun error occurred" "0,1"
|
|
bitfld.long 0x00 8. "mfifo_err_ovfl,Master FIFO overflow error occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "mfifo_full,Master FIFO is full (1 if full) This is a read-only status bit" "0,1"
|
|
bitfld.long 0x00 6. "mfifo_empty,Master FIFO is empty (1 if empty) This is a read-only status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 0.--4. "mfifo_level,Master FIFO level (0..16) This is a read-only status bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "i2c_irqmsk,I2C interrupt mask set or clear register: These bits have AND-mask character"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 6. "sreq,Slave request interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "sfifo_req,Slave FIFO action request interrupt mask" "0,1"
|
|
bitfld.long 0x00 4. "mfifo_req,Master FIFO action request interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "bus_busy,External I2C-bus is busy interrupt mask" "0,1"
|
|
bitfld.long 0x00 2. "fifo_err,FIFO error interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "cmd_err,Command error interrupt mask" "0,1"
|
|
bitfld.long 0x00 0. "cmd_ok,Command OK interrupt mask" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "i2c_irqsr,I2C interrupt state register (raw interrupt before masking): Writing '1' will clear the corresponding IRQ"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 6. "sreq,Unmasked slave request interrupt state: Purpose: Set up slave FIFO" "0: Slave is not requested,1: External master was running START-sequence and"
|
|
newline
|
|
bitfld.long 0x00 5. "sfifo_req,Unmasked slave FIFO action request interrupt state: Purpose: Slave FIFO should be updated" "0: Slave FIFO state not critical,1: Slave FIFO request"
|
|
bitfld.long 0x00 4. "mfifo_req,Unmasked master FIFO action request interrupt state: Purpose: Master FIFO should be updated" "0: Master FIFO state not critical,1: Master FIFO request"
|
|
newline
|
|
bitfld.long 0x00 3. "bus_busy,Unmasked external I2C-bus is busy interrupt state: Purpose: Detect I2C-bus arbitration loss" "0: Bus is idle or no transfer is requested by this,1: Master did not gain the requested bus access"
|
|
bitfld.long 0x00 2. "fifo_err,Unmasked FIFO error interrupt state: Purpose: Detect FIFO errors/transfer failures" "0: FIFOs ok,1: FIFO error occurred"
|
|
newline
|
|
bitfld.long 0x00 1. "cmd_err,Unmasked command error interrupt state: Purpose: Check last command termination" "0: Command not finished no command or command,1: Last command finished erroneously"
|
|
bitfld.long 0x00 0. "cmd_ok,Unmasked command OK interrupt state: Purpose: Check last command termination" "0: Command not finished no command or command,1: Last command finished successfully"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "i2c_irqmsked,I2C masked interrupt state register: If one of these bits is set the I2C IRQ will be set to the interrupt controller"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 6. "sreq,Masked slave request interrupt state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "sfifo_req,Masked slave FIFO action request interrupt state" "0,1"
|
|
bitfld.long 0x00 4. "mfifo_req,Masked master FIFO action request interrupt state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "bus_busy,Masked external I2C-bus is busy interrupt state" "0,1"
|
|
bitfld.long 0x00 2. "fifo_err,Masked FIFO error interrupt state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "cmd_err,Masked command error interrupt state" "0,1"
|
|
bitfld.long 0x00 0. "cmd_ok,Masked command OK interrupt state" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "i2c_dmacr,I2C DMA control register: Required settings for the DMA controller: - DMA transfer size to/from I2C module: Byte - DMA burst length to/from I2C module: 4 DMA burst requests will be generated if the corresponding FIFO contains more than 4 bytes.."
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "sdmab_en,Enable DMA burst requests for I2C slave data" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "sdmas_en,Enable DMA single requests for I2C slave data" "0,1"
|
|
bitfld.long 0x00 1. "mdmab_en,Enable DMA burst requests for I2C master data" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "mdmas_en,Enable DMA single requests for I2C master data" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "i2c_pio,PIO mode register: This register can directly control the I2C signals SCL and SDA if pio_mode is enabled in register i2c_mcr"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 6. "sda_in_ro,SDA input state (read-only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "sda_oe,SDA output enable" "0: Do not drive SDA switch pad to high-z,1: Drive SDA switch pad to programmed.."
|
|
bitfld.long 0x00 4. "sda_out,Driving level of SDA (1: high 0: low) if output is enabled (sda_oe is set)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 2. "scl_in_ro,SCL input state (read-only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "scl_oe,SCL output enable" "0: Do not drive SCL switch pad to high-z,1: Drive SCL switch pad to programmed.."
|
|
bitfld.long 0x00 0. "scl_out,Driving level of SCL (1: high 0: low) if output is enabled (scl_oe is set)" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "IIS"
|
|
repeat 3. (list 0. 1. 2.) (list ad:0xF801C400 ad:0xF801C500 ad:0xF801C600)
|
|
tree "IIS$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "IIS_IISA0CTL,IISA Control Register"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 13.--14. "IISA0SLFS,Serial Clock cycles in 1 Frame (IISA0SLFS) (00: 32 01: 48 10 : 64 11: 128)" "?,1: 48,2: 64,3: 128)"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "IISA0DLG,Data Length Selection (IISA0DLG) (8 16 18 20 or 24 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "IISA0MD,Master / Slave Mode Selection (0: Slave mode 1: Master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "IISA0IDL,Invalid Data Selection" "0,1"
|
|
bitfld.long 0x00 5. "IISA0SLTF,Transfer Format Selection (0: Standard format 1: IIS format)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "IISA0WSL,Word Select (IISATWS) Polarity (0: Word select (IISATWS) for left channel is low level)" "0,1"
|
|
bitfld.long 0x00 3. "IISA0SLDF,Data Format Selection (0: MSB left justified 1: LSB right justified)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "IISA0TXE,Transmission Enable / Disable" "0,1"
|
|
bitfld.long 0x00 1. "IISA0RXE,Reception Enable / Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IIS_IISA0OPT,IISA Option Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 12.--15. "IISA0TTGS,Transmission FIFO Trigger Level (IISA0TTGS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "IISA0RTGS,Reception FIFO Trigger Level (IISA0RTGS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4. "IISA0FEM,Framing Error Interrupt Request Enabled/Disabled (0: enabled)" "0,1"
|
|
bitfld.long 0x00 3. "IISA0TUM,Transmission FIFO Underrun Interrupt Request Enable/Disable (0: enabled)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "IISA0TTM,Transmission FIFO Trigger Level Interrupt Request Enable/Disable (0: enabled)" "0,1"
|
|
bitfld.long 0x00 1. "IISA0ROM,Reception FIFO Overrun Interrupt Request Enable/Disable (0: enabled)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IISA0RTM,Reception FIFO Trigger Level Interrupt Request Enable/Disable (0: enabled)" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "IIS_IISA0STR0,IISA Status Register 0"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 6. "IISA0FE,Framing Error Interrupt Request generated" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IISA0TUE,Transmission FIFO Underrun Interrupt Request generated" "0,1"
|
|
bitfld.long 0x00 4. "IISA0TTF,Transmission FIFO Trigger Level Interrupt Request generated" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IISA0ROE,Reception FIFO Overrun Interrupt Request generated" "0,1"
|
|
bitfld.long 0x00 2. "IISA0RTF,Reception FIFO Trigger Level Interrupt Request generated" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "IISA0TFF,Transmission FIFO Full (16 words) Status" "0,1"
|
|
bitfld.long 0x00 0. "IISA0REF,Reception FIFO Empty (No Data) Status" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "IIS_IISA0STR1,IISA Status Register 1"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8.--12. "IISA0TPF,Number of Transmission FIFO Unsent Data (IISA0TPF) (00000 to 10000)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "IISA0RPF,Number of Reception FIFO Unread Data (IISA0RPF) (00000 to 10000)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IIS_IISA0STC,IISA Status Clear Register"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 12. "IISA0FEC,Framing Error Interrupt Request Clear (IISA0FE bit of IISA0STR0 register is cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IISA0TUC,Transmission FIFO Underrun Interrupt Request Clear (IISA0TUE bit of IISA0STR0 register is cleared)" "0,1"
|
|
bitfld.long 0x00 10. "IISA0TTC,Transmission FIFO Trigger Level Interrupt Request Clear (IISA0TTF bit of IISA0STR0 register is cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "IISA0ROC,Reception FIFO Overrun Interrupt Request Clear (IISA0ROE bit of IISA0STR0 register is cleared)" "0,1"
|
|
bitfld.long 0x00 8. "IISA0RTC,Reception FIFO Trigger Level Interrupt Request Clear (IISA0RTF bit of IISA0STR0 register is cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 1. "IISA0CLTP,Transmission FIFO initialization (Pointer and data of transmission FIFO and IISA0TFF bit of IISA0STR0 register are cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IISA0CLRP,Reception FIFO initialization (Pointer and data of reception FIFO and IISA0REF bit of IISA0STR0 register are cleared)" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "IIS_IISA0RX,IISA Reception Data Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "IISA0RX,Reception Data (IISA0RX)"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IIS_IISA0TX,IISA Transmission Data Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "IISA0TX,Transmission Data (IISA0TX)"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IIS_IISA0EMU,IISA Emulation Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "IISA0SVSDIS,SVSTOP disable (0: SVSTOP stops the macro in supervicer mode)" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "IISCLK_CTL"
|
|
base ad:0xF801C800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "IISCLK_CTL_CLK_DIV0,Clock division factor to generate IIS0 clock from internal CLK source"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--9. 1. "CLK_FACTOR0,CLK division factor bit for IIS0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IISCLK_CTL_CLK_DIV1,Clock division factor to generate IIS1 clock from internal CLK source"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--9. 1. "CLK_FACTOR1,CLK division factor bit for IIS1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IISCLK_CTL_CLK_DIV2,Clock division factor to generate IIS2 clock from internal CLK source"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--9. 1. "CLK_FACTOR2,CLK division factor bit for IIS2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IISCLK_CTL_CLK_DIV3,Clock division factor to generate IIS3 clock from internal CLK source"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--9. 1. "CLK_FACTOR3,CLK division factor bit for IIS3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IISCLK_CTL_ACLK_DIV0,Clock division factor to generate IIS0 clock from external ACLK"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "ACLK_FACTOR0,ACLK division factor bit for IIS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IISCLK_CTL_ACLK_DIV1,Clock division factor to generate IIS1 clock from external ACLK"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "ACLK_FACTOR1,ACLK division factor bit for IIS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IISCLK_CTL_ACLK_DIV2,Clock division factor to generate IIS2 clock from external ACLK"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "ACLK_FACTOR2,ACLK division factor bit for IIS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IISCLK_CTL_ACLK_DIV3,Clock division factor to generate IIS3 clock from external ACLK"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "ACLK_FACTOR3,ACLK division factor bit for IIS3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IISCLK_CTL_ENABLE_IISCLK,enable clk generation for IIS0-IIS4"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "ENABLE_IISCLK3,disable CLK = 0 enable CLK = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ENABLE_IISCLK2,disable CLK = 0 enable CLK = 1" "0,1"
|
|
bitfld.long 0x00 1. "ENABLE_IISCLK1,disable CLK = 0 enable CLK = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE_IISCLK0,disable CLK = 0 enable CLK = 1" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IISCLK_CTL_SEL_CONFIGURE_REG,set the select registers for the inverted clk edge- and external audio clk selection"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "SEL_ACLK3,for internal CLK = 0 and for external ACLK = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEL_ACLK2,for internal CLK = 0 and for external ACLK = 1" "0,1"
|
|
bitfld.long 0x00 5. "SEL_ACLK1,for internal CLK = 0 and for external ACLK = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SEL_ACLK0,for internal CLK = 0 and for external ACLK = 1" "0,1"
|
|
bitfld.long 0x00 3. "SEL_INV_CLK3,select rising edge or falling edge of the serial clock output for IIS0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SEL_INV_CLK2,select rising edge or falling edge of the serial clock output for IIS0" "0,1"
|
|
bitfld.long 0x00 1. "SEL_INV_CLK1,select rising edge or falling edge of the serial clock output for IIS0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SEL_INV_CLK0,select rising edge or falling edge of the serial clock output for IIS0" "0,1"
|
|
tree.end
|
|
tree "RTC"
|
|
base ad:0xF801CE00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_CTL0,RTC control register 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "RTCA0CE,QLAPBRTCA enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTCA0CEST,QLAPBRTCA enable status" "0,1"
|
|
bitfld.long 0x00 5. "RTCA0AMPM,RTCA0HOUR RTCA0ALH display format selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RTCA0SLSB,RTCA0SUBU and RTCA0SCMP enable/disable setting" "0,1"
|
|
bitfld.long 0x00 0.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RTC_CTL1,RTC control register 1"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 5. "RTCA01HZE,1 Hz pulse (RTCAT1HZ) output enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RTCA0ALME,Alarm interrupt (RTCATINTAL) output enable bit" "0,1"
|
|
bitfld.long 0x00 3. "RTCA01SE,1 second interrupt (RTCATINT1S) output enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RTCA0CT2,Fixed interval interrupt output setting bit2" "0,1"
|
|
bitfld.long 0x00 1. "RTCA0CT1,Fixed interval interrupt output setting bit1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RTCA0CT0,Fixed interval interrupt output setting bit0" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_CTL2,RTC control register 2"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 5. "RTCA0WUST,RTCA0SUBU write status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RTCA0WSST,RTCA0SCMP write status" "0,1"
|
|
bitfld.long 0x00 3. "RTCA0RSST,RTCA0SRBU transfer status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RTCA0RSUB,RTCA0SUBC data transfer control" "0,1"
|
|
bitfld.long 0x00 1. "RTCA0WST,QLAPBRTCA counter wait status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RTCA0WAIT,QLAPBRTCA counter wait control" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "RTC_SUBC,RTC Sub count register"
|
|
hexmask.long.word 0x00 22.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "RTCA0SUBC,RTCA0SUBC is a register that counts the 1 second reference time"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RTC_SRBU,RTC Sub count register read buffer"
|
|
hexmask.long.word 0x00 22.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "RTCA0SRBU,RTCA0SRBU is the read buffer register of RTCA0SUBC"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_SEC,RTC Sec count register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RTCA0SEC,RTCA0SEC is a buffer register to read/write second count register"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RTC_MIN,RTC Min count register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RTCA0MIN,RTCA0MIN is a buffer register to read/write min count register"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_HOUR,RTC Hour count register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "RTCA0HOUR,RTCA0HOUR is a buffer register to read/write hour count register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_WEEK,RTC Week count register"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--2. "RTCA0WEEK,RTCA0WEEK is a buffer register to read/write week count register" "0,1,2,3,4,5,6,7"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RTC_DAY,RTC Day count register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "RTCA0DAY,RTCA0DAY is a buffer register to read/write day count register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RTC_MONTH,RTC Month count register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--4. "RTCA0MONTH,RTCA0MONTH is a buffer register to read/write month count register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RTC_YEAR,RTC Year count register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RTCA0YEAR,RTCA0YEAR is a buffer register to read/write year count register"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RTC_TIME,RTC Time set register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RTCA0HOUR,RTCA0TIME is a register for accessing the RTCA0HOUR RTCA0MIN and RTCA0SEC registers simultaneously"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RTCA0MIN,RTCA0TIME is a register for accessing the RTCA0HOUR RTCA0MIN and RTCA0SEC registers simultaneously"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RTCA0SEC,RTCA0TIME is a register for accessing the RTCA0HOUR RTCA0MIN and RTCA0SEC registers simultaneously"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "RTC_CAL,RTCA0 Calender set register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RTCA0YEAR,RTCA0CAL is a register for accessing the RTCA0YEAR RTCA0MONTH RTCA0DAY and RTCA0WEEK registers simultaneously.By using this register the RTCA0YEAR RTCA0MONTH RTCA0DAY and RTCA0WEEK registers can be read or written simultaneously"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RTCA0MONTH,RTCA0CAL is a register for accessing the RTCA0YEAR RTCA0MONTH RTCA0DAY and RTCA0WEEK registers simultaneously.By using this register the RTCA0YEAR RTCA0MONTH RTCA0DAY and RTCA0WEEK registers can be read or written simultaneously"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RTCA0DAY,RTCA0CAL is a register for accessing the RTCA0YEAR RTCA0MONTH RTCA0DAY and RTCA0WEEK registers simultaneously.By using this register the RTCA0YEAR RTCA0MONTH RTCA0DAY and RTCA0WEEK registers can be read or written simultaneously"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RTCA0WEEK,RTCA0CAL is a register for accessing the RTCA0YEAR RTCA0MONTH RTCA0DAY and RTCA0WEEK registers simultaneously.By using this register the RTCA0YEAR RTCA0MONTH RTCA0DAY and RTCA0WEEK registers can be read or written simultaneously"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "RTC_SUBU,RTC Clock error correction register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "RTCA0DEV,Bit Sets clock error correction timing" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "RTCA0F,Clock error correction value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "RTC_SCMP,RTC Subcount compare regsiter"
|
|
hexmask.long.word 0x00 22.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "RTCA0SCMP,RTCA0SCMP is a register that sets the compare value of RTCA0SUBC (sub-counter)"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RTC_ALM,RTC Alarm Min set register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RTCA0ALM,RTCA0ALM"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "RTC_ALH,RTCA0 Alarm Hour set register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "RTCA0ALH,RTCA0ALH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RTC_ALW,RTC Alarm Week set register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RTCA0ALW,Alarm interrupt day of the week setting"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "RTC_SECC,RTC Second count register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RTCA0SECC,RTCA0SECC"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "RTC_MINC,RTC Minute count register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RTCA0MINC,RTCA0MINC"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "RTC_HOURC,RTC Hour count register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "RTCA0HOURC,RTCA0HOURC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "RTC_WEEKC,RTC Week count register"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--2. "RTCA0WEEKC,RTCA0WEEKC is a register that counts weeks" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "RTC_DAYC,RTC Day count register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "RTCA0DAYC,RTCA0DAYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "RTC_MONC,RTC Month count register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--4. "RTCA0MONC,RTCA0MONC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "RTC_YEARC,RTC Year count register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RTCA0YEARC,RTCA0YEARC"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "RTC_TIMEC,RTC Time count register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
abitfld.long 0x00 16.--23. "RTCA0HOURC,Bit" "0x00=0: RTCA0TIMEC bit16 Bit,0x01=1: RTCA0TIMEC bit17 Bit,0x02=2: RTCA0TIMEC bit18 Bit,0x03=3: RTCA0TIMEC bit19 Bit,0x04=4: RTCA0TIMEC bit20 Bit,0x05=5: RTCA0TIMEC bit21 Bit,0x06=6: RTCA0TIMEC bit22 Bit,0x07=7: RTCA0TIMEC bit23"
|
|
newline
|
|
abitfld.long 0x00 8.--15. "RTCA0MINC,Bit" "0x00=0: RTCA0TIMEC bit8 Bit,0x01=1: RTCA0TIMEC bit9 Bit,0x02=2: RTCA0TIMEC bit10 Bit,0x03=3: RTCA0TIMEC bit11 Bit,0x04=4: RTCA0TIMEC bit12 Bit,0x05=5: RTCA0TIMEC bit13 Bit,0x06=6: RTCA0TIMEC bit14 Bit,0x07=7: RTCA0TIMEC bit15"
|
|
abitfld.long 0x00 0.--7. "RTCA0SECC,Bit" "0x00=0: RTCA0TIMEC bit0 Bit,0x01=1: RTCA0TIMEC bit1 Bit,0x02=2: RTCA0TIMEC bit2 Bit,0x03=3: RTCA0TIMEC bit3 Bit,0x04=4: RTCA0TIMEC bit4 Bit,0x05=5: RTCA0TIMEC bit5 Bit,0x06=6: RTCA0TIMEC bit6 Bit,0x07=7: RTCA0TIMEC bit7"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "RTC_CALC,calendar count register"
|
|
abitfld.long 0x00 24.--31. "RTCA0YEARC,Bit" "0x00=0: RTCA0CALC bit24 Bit,0x01=1: RTCA0CALC bit25 Bit,0x02=2: RTCA0CALC bit26 Bit,0x03=3: RTCA0CALC bit27 Bit,0x04=4: RTCA0CALC bit28 Bit,0x05=5: RTCA0CALC bit29 Bit,0x06=6: RTCA0CALC bit30 Bit,0x07=7: RTCA0CALC bit31"
|
|
abitfld.long 0x00 16.--23. "RTCA0MONC,Bit" "0x00=0: RTCA0CALC bit16 Bit,0x01=1: RTCA0CALC bit17 Bit,0x02=2: RTCA0CALC bit18 Bit,0x03=3: RTCA0CALC bit19 Bit,0x04=4: RTCA0CALC bit20 Bit,0x05=5: RTCA0CALC bit21 Bit,0x06=6: RTCA0CALC bit22 Bit,0x07=7: RTCA0CALC bit23"
|
|
newline
|
|
abitfld.long 0x00 8.--15. "RTCA0DAYC,Bit" "0x00=0: RTCA0CALC bit8 Bit,0x01=1: RTCA0CALC bit9 Bit,0x02=2: RTCA0CALC bit10 Bit,0x03=3: RTCA0CALC bit11 Bit,0x04=4: RTCA0CALC bit12 Bit,0x05=5: RTCA0CALC bit13 Bit,0x06=6: RTCA0CALC bit14 Bit,0x07=7: RTCA0CALC bit15"
|
|
abitfld.long 0x00 0.--7. "RTCA0WEEKC,Bit" "0x00=0: RTCA0CALC bit0 Bit,0x01=1: RTCA0CALC bit1 Bit,0x02=2: RTCA0CALC bit2 Bit,0x03=3: RTCA0CALC bit3 Bit,0x04=4: RTCA0CALC bit4 Bit,0x05=5: RTCA0CALC bit5 Bit,0x06=6: RTCA0CALC bit6 Bit,0x07=7: RTCA0CALC bit7"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "RTC_TCR,Test Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "RTCA0OSE,This bit enables and disables the output substitution latch" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 4.--14. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "RTCA0OS3,This bit is the output substitution latch of output pin RTCATINTAL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RTCA0OS2,This bit is the output substitution latch of output pin RTCATINT1S" "0,1"
|
|
bitfld.long 0x00 1. "RTCA0OS1,This bit is the output substitution latch of output pin RTCATINTR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RTCA0OS0,This bit is the output substitution latch of output pin RTCA0T1HZ" "0,1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "RTC_EMU,RTC Emulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "RTCA0SVSDIS,SVSTOPR enable disable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
tree "RAP_ECC_CTRL"
|
|
repeat 3. (list 0. 1. 2.) (list ad:0xF801D000 ad:0xF801D100 ad:0xF801D200)
|
|
tree "RAP_ECC_CTRL$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM0_CTRL,RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "ENABLE,Enables automatic correction of SBE faults" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SYNDROME_INV,Inverts syndrome bits for ECC testing"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM1_CTRL,RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "ENABLE,Enables automatic correction of SBE faults" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SYNDROME_INV,Inverts syndrome bits for ECC testing"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM2_CTRL,RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "ENABLE,Enables automatic correction of SBE faults" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SYNDROME_INV,Inverts syndrome bits for ECC testing"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM3_CTRL,RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "ENABLE,Enables automatic correction of SBE faults" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SYNDROME_INV,Inverts syndrome bits for ECC testing"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM4_CTRL,RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "ENABLE,Enables automatic correction of SBE faults" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SYNDROME_INV,Inverts syndrome bits for ECC testing"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM5_CTRL,RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "ENABLE,Enables automatic correction of SBE faults" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SYNDROME_INV,Inverts syndrome bits for ECC testing"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM6_CTRL,RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "ENABLE,Enables automatic correction of SBE faults" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SYNDROME_INV,Inverts syndrome bits for ECC testing"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM7_CTRL,RAM syndrome manipulation register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "ENABLE,Enables automatic correction of SBE faults" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SYNDROME_INV,Inverts syndrome bits for ECC testing"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM0_ADDR_SBE,Logs address of ECC SBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM1_ADDR_SBE,Logs address of ECC SBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM2_ADDR_SBE,Logs address of ECC SBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM3_ADDR_SBE,Logs address of ECC SBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM4_ADDR_SBE,Logs address of ECC SBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM5_ADDR_SBE,Logs address of ECC SBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM6_ADDR_SBE,Logs address of ECC SBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM7_ADDR_SBE,Logs address of ECC SBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM0_ADDR_DBE,Logs address of ECC DBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM1_ADDR_DBE,Logs address of ECC DBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM2_ADDR_DBE,Logs address of ECC DBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM3_ADDR_DBE,Logs address of ECC DBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM4_ADDR_DBE,Logs address of ECC DBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM5_ADDR_DBE,Logs address of ECC DBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM6_ADDR_DBE,Logs address of ECC DBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM7_ADDR_DBE,Logs address of ECC DBE error"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,N/A"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM_STATUS_SBE,N/A"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "RAM7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RAM6,N/A" "0,1"
|
|
bitfld.long 0x00 5. "RAM5,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RAM4,N/A" "0,1"
|
|
bitfld.long 0x00 3. "RAM3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RAM2,N/A" "0,1"
|
|
bitfld.long 0x00 1. "RAM1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RAM0,N/A" "0,1"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "RAP_ECC_CTRL_RAM_STATUS_DBE,N/A"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "RAM7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RAM6,N/A" "0,1"
|
|
bitfld.long 0x00 5. "RAM5,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RAM4,N/A" "0,1"
|
|
bitfld.long 0x00 3. "RAM3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RAM2,N/A" "0,1"
|
|
bitfld.long 0x00 1. "RAM1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RAM0,N/A" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SQI1"
|
|
base ad:0xF801D400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "sqi_cr0,SQI control register 0 This register is compatible to netX50 and netX10 SPI module"
|
|
bitfld.long 0x00 28.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. "filter_in,Receive-data is sampled every 10ns (100MHz system clock)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22.--23. "sio_cfg,SQI IO configuration" "0: only SIO2 3 are controllable as PIOs (2-bit SPI,1: all SQP IOs are used for transfers (4-bit..,2: reserved,3: all SQI IOs are controllable as PIOs"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
hexmask.long.word 0x00 8.--19. 1. "sck_muladd,Serial clock rate multiply add value for sck generation"
|
|
newline
|
|
bitfld.long 0x00 7. "sck_phase,Serial clock phase" "0: sample data at first clock edge data is,1: sample data at second clock edge data is"
|
|
bitfld.long 0x00 6. "sck_pol,Serial clock polarity" "0: idle,1: idle"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "datasize,Data size select for standard Motorola SPI mode" "?,?,?,3: 4 bit,4: 5 bit,?,?,7: 8 bit,?,?,?,?,?,?,?,15: 16 bit"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "sqi_cr1,SQI control register 1 This register is compatible to netX50 and netX10 SPI module"
|
|
bitfld.long 0x00 29.--31. "bf_align4,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "rx_fifo_clr,Writing '1' to this bit will clear the receive FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "rx_fifo_wm,Receive FIFO watermark for IRQ generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21.--23. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20. "tx_fifo_clr,Writing '1' to this bit will clear the transmit FIFO" "0,1"
|
|
bitfld.long 0x00 16.--19. "tx_fifo_wm,Transmit FIFO watermark for IRQ generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "spi_trans_ctrl,Transfer Control for standard Motorola SPI (default: disabled) This bit is only used for standard Motorola SPI (register 'sqi_tcr' 'mode'-bits) in full- and half-duplex modes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "fss_static,SQI static chip-select" "0: chip-select will be generated automatically at,1: chip-select will be set statically according to"
|
|
bitfld.long 0x00 8.--10. "fss,Frame slave select (up to 3 devices can be assigned directly up to 8 devices can be assigned if an external de-multiplexer is used)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 1. "sqi_en,SQI enable" "0: interface disabled,1: interface enabled"
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|
newline
|
|
bitfld.long 0x00 0. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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|
group.long 0x08++0x03
|
|
line.long 0x00 "sqi_dr,SQI data register (DR) Read access: received data word is delivered from receive FIFO"
|
|
hexmask.long 0x00 0.--31. 1. "data,Transmit data must be right aligned on writing"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "sqi_sr,Read only SQI status register Shows the current status of the SQI interface"
|
|
bitfld.long 0x00 31. "rx_fifo_err_undr,Receive FIFO underrun error occurred unexpected data has been" "0,1"
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|
bitfld.long 0x00 30. "rx_fifo_err_ovfl,Receive FIFO overflow error occurred data is lost" "0,1"
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|
newline
|
|
bitfld.long 0x00 29. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
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|
bitfld.long 0x00 24.--28. "rx_fifo_level,Receive FIFO level (number of received words to read out from FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
|
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bitfld.long 0x00 23. "tx_fifo_err_undr,Transmit FIFO underrun error occurred unexpected data has been sent" "0,1"
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|
bitfld.long 0x00 22. "tx_fifo_err_ovfl,Transmit FIFO overflow error occurred data is lost" "0,1"
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|
newline
|
|
bitfld.long 0x00 21. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 16.--20. "tx_fifo_level,Transmit FIFO level (number of words to transmit are left in FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
|
|
bitfld.long 0x00 15. "sqirom_disabled_err,Access to SQIROM area detected while SQIROM was disabled" "0,1"
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|
bitfld.long 0x00 14. "sqirom_write_err,Write access to SQIROM area detected" "0,1"
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|
newline
|
|
bitfld.long 0x00 13. "sqirom_timeout_err,Timeout during SQIROM area read detected" "0,1"
|
|
hexmask.long.byte 0x00 5.--12. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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|
newline
|
|
bitfld.long 0x00 4. "busy,Device is busy (1 if data is currently transmitted/received or the transmit FIFO is not empty)" "0,1"
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|
bitfld.long 0x00 3. "rx_fifo_full,Receive FIFO is full (1 if full)" "0,1"
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|
newline
|
|
bitfld.long 0x00 2. "rx_fifo_not_empty,Receive FIFO is not empty (0 if empty)" "0,1"
|
|
bitfld.long 0x00 1. "tx_fifo_not_full,Transmit FIFO is not full (0 if full)" "0,1"
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|
newline
|
|
bitfld.long 0x00 0. "tx_fifo_empty,Transmit FIFO is empty (1 if empty)" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "sqi_tcr,SQI transfer control (module address offset 0x10 is reserved in netX10/50 SPI module. No compatibility problems by using this address for new register)"
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|
bitfld.long 0x00 30.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 29. "ms_byte_first,Most significant byte first 2- and 4-bit mode: Writing '1' to this bit will use most significant byte first in DWords (big endian)" "0,1"
|
|
newline
|
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bitfld.long 0x00 28. "ms_bit_first,Most significant bit first 2- and 4-bit mode: Writing '1' to this bit will transfer most significant bit first (default)" "0,1"
|
|
bitfld.long 0x00 26.--27. "duplex,Transfer type selection (default is '11' for standard SPI compatibility)" "0: dummy Generates 'transfer_size' + 1 serial..,1: half-duplex receive Receives 'transfer_size'..,2: half-duplex transmit Transmits..,3: full-duplex (Standard Motorola SPI mode only"
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newline
|
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bitfld.long 0x00 24.--25. "mode,SPI/SQI mode selection" "0: Standard Motorola SPI mode,1: 2-bit SPI mode,2: 4-bit SPI mode,3: reserved"
|
|
bitfld.long 0x00 23. "start_transfer,Transfer start signal Writing a '1' starts the transfer of transfer_size bytes" "0,1"
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|
newline
|
|
bitfld.long 0x00 22. "tx_oe,Output driver enable in dummy or standard SPI receive-only mode Writing a '1' enables the output drivers of the data pins in dummy mode" "0,1"
|
|
bitfld.long 0x00 21. "tx_out,Output level in dummy or standard SPI receive-only mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
abitfld.long 0x00 0.--18. "transfer_size,Number of bytes within the current SQI transaction (transfer_size+1)" "0x00000=0: one byte / dummy cycle,0x7FFFF=524287: 512k bytes / dummy cycles This.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "sqi_irq_mask,SQI interrupt mask set or clear register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "sqirom_error,SQIROM error interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trans_end,Transfer end interrupt mask" "0,1"
|
|
bitfld.long 0x00 6. "txeim,Transmit FIFO empty interrupt mask (for netx100/500 compliance)" "0,1"
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|
newline
|
|
bitfld.long 0x00 5. "rxfim,Receive FIFO full interrupt mask (for netx100/500 compliance)" "0,1"
|
|
bitfld.long 0x00 4. "rxneim,Receive FIFO not empty interrupt mask (for netx100/500 compliance)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TXIM,Transmit FIFO interrupt mask" "0,1"
|
|
bitfld.long 0x00 2. "RXIM,Receive FIFO interrupt mask" "0,1"
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|
newline
|
|
bitfld.long 0x00 1. "RTIM,Receive timeout interrupt mask" "0,1"
|
|
bitfld.long 0x00 0. "RORIM,Receive FIFO overrun interrupt mask" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "sqi_irq_raw,SQI interrupt state before masking register (raw interrupt)"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "sqirom_error,Unmaksed SQIROM error interrupt state" "0: no SQIROM error detected,1: SQIROM access error detected"
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|
newline
|
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bitfld.long 0x00 7. "trans_end,Unmasked transfer end interrupt state (related to bit 'busy' of 'sqi_sr' register)" "0: transfer finished not finished,1: transfer finished"
|
|
bitfld.long 0x00 6. "txeris,Unmasked transmit FIFO empty interrupt state (for netx100/500 compliance)" "0: transmit FIFO is not empty,1: transmit FIFO is empty"
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|
newline
|
|
bitfld.long 0x00 5. "rxfris,Unmasked receive FIFO full interrupt state (for netx100/500 compliance)" "0: receive FIFO is not full,1: receive FIFO is full"
|
|
bitfld.long 0x00 4. "rxneris,Unmasked receive FIFO not empty interrupt state (for netx100/500 compliance)" "0: receive FIFO is empty,1: receive FIFO is not empty"
|
|
newline
|
|
bitfld.long 0x00 3. "TXRIS,Unmasked transmit FIFO interrupt state" "0: transmit FIFO equals or is higher than,1: transmit FIFO level is below sqi_cr1.tx_fifo_wm"
|
|
bitfld.long 0x00 2. "RXRIS,Unmasked receive FIFO interrupt state" "0: receive FIFO is equals or is below,1: receive FIFO is higher than sqi_cr1.rx_fifo_wm"
|
|
newline
|
|
bitfld.long 0x00 1. "RTRIS,Unmasked receive timeout interrupt state Timeout period is 32 serial clock periods (depending on adr_sqi_cr0.sck_muladd)" "0: receive FIFO is empty or read during the last,1: receive FIFO is not empty and has not been read"
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|
bitfld.long 0x00 0. "RORRIS,Unmasked receive FIFO overrun interrupt state" "0: no receive FIFO overrun error occurred,1: receive FIFO overrun error occurred"
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|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "sqi_irq_masked,SQI masked interrupt status register For detailed IRQ behavior and function view 'sqi_irq_raw' register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "sqirom_error,Masked SQIROM error interrupt state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trans_end,Masked transfer end interrupt state" "0,1"
|
|
bitfld.long 0x00 6. "txemis,Masked transmit FIFO empty interrupt state (for netx100/500 compliance)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "rxfmis,Masked receive FIFO full interrupt state (for netx100/500 compliance)" "0,1"
|
|
bitfld.long 0x00 4. "rxnemis,Masked receive FIFO not empty interrupt state (for netx100/500 compliance)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TXMIS,Masked transmit FIFO interrupt state" "0,1"
|
|
bitfld.long 0x00 2. "RXMIS,Masked receive FIFO interrupt state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RTMIS,Masked receive timeout interrupt state" "0,1"
|
|
bitfld.long 0x00 0. "RORMIS,Masked receive FIFO overrun interrupt state" "0,1"
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|
group.long 0x20++0x03
|
|
line.long 0x00 "sqi_irq_clear,SQI interrupt clear register (for compatibility to netX10/50 SPI module)"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "sqirom_error,Clear SQIROM error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "trans_end,Clear transfer end interrupt" "0,1"
|
|
bitfld.long 0x00 6. "txeic,Clear transmit FIFO empty interrupt (for netx100/500 compliance)" "0,1"
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|
newline
|
|
bitfld.long 0x00 5. "rxfic,Clear receive FIFO full interrupt (for netx100/500 compliance)" "0,1"
|
|
bitfld.long 0x00 4. "rxneic,Clear receive FIFO not empty interrupt (for netx100/500 compliance)" "0,1"
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|
newline
|
|
bitfld.long 0x00 3. "TXIC,Clear transmit FIFO interrupt" "0,1"
|
|
bitfld.long 0x00 2. "RXIC,Clear receive FIFO interrupt" "0,1"
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|
newline
|
|
bitfld.long 0x00 1. "RTIC,Clear receive FIFO overrun interrupt" "0,1"
|
|
bitfld.long 0x00 0. "RORIC,Clear receive FIFO overrun interrupt" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "sqi_dmacr,SQI DMA control register Only normal transfer requests will be generated by this module (i.e. no last requests will be issued)"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "tx_dma_en,Enable DMA for SQI-transmit data A request will be generated if TX-FIFO is not full and sqi_cr1.sqi_en (module enable) is set" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "rx_dma_en,Enable DMA for SQI-receive data A request will be generated if RX-FIFO is not empty and sqi_cr1.sqi_en (module enable) is set" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "sqi_pio_out,SQI PIO output level control register IO PIO mode is controlable by 'sqi_cr0' register bits 'sio_cfg'"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "sio3,SIO3 output state" "0,1"
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|
newline
|
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bitfld.long 0x00 6. "sio2,SIO2 output state" "0,1"
|
|
bitfld.long 0x00 5. "miso,MISO/SIO1 output state" "0,1"
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|
newline
|
|
bitfld.long 0x00 4. "mosi,MOSI/SIO0 output state" "0,1"
|
|
bitfld.long 0x00 1.--3. "csn,Chip-select/FSS output state {CS2 CS1 CS0}" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "sclk,Serial SPI clock output state" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "sqi_pio_oe,SQI PIO output enable control register IO PIO mode is controlable by 'sqi_cr0' register bits 'sio_cfg'"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "sio3,SIO3 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "sio2,SIO2 output enable" "0,1"
|
|
bitfld.long 0x00 5. "miso,MISO/SIO1 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "mosi,MOSI/SIO0 output enable" "0,1"
|
|
bitfld.long 0x00 1.--3. "csn,Chip-select/FSS output enable {CS2 CS1 CS0}" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "sclk,Serial SPI clock output enable" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "sqi_pio_in,SQI PIO input status register IO PIO mode is controllable by 'sqi_cr0' register bits 'sio_cfg'"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "sio3,SIO3 input state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "sio2,SIO2 input state" "0,1"
|
|
bitfld.long 0x00 5. "miso,MISO/SIO1 input state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "mosi,MOSI/SIO0 input state" "0,1"
|
|
bitfld.long 0x00 1.--3. "csn,Chip-select/FSS input state {CS2 CS1 CS0}" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "sclk,Serial SPI clock input state" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "sqi_sqirom_cfg,SQIROM mode configuration Configuration register for the SQIROM mode"
|
|
hexmask.long.byte 0x00 24.--31. 1. "clk_div_val,Internal 1 GHz clock will be divided by (clk_div_val+1) for sqirom_clk generation Default setting '12' is 76.9 MHz"
|
|
bitfld.long 0x00 22.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "t_csh,Minimum SQI chips-select-high (idle) time: (t_csh+1) * t_sck (according to clk_div_val)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "dummy_cycles,Selects the number of dummy cycles before data will be sampled from the SQI chip" "0: 0 cycles,1: 1 cycle,2: 2 cycles (default),?,?,?,?,?,?,?,?,?,?,?,?,15: 15 cycles"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "cmd_byte,This byte is transferred to the SQI chip as the command sequence"
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "addr_bits,Number of address bits used to generate the address for the SQI chip" "0: 20 bits (1MByte/8MBit device) (default),1: 21 bits (2MByte/16MBit device),2: 22 bits (4MByte/32MBit device),3: 23 bits (8MByte/64MBit device),4: 24 bits (16MByte/128MBit device),5: 25 bits (32MByte/256MBit device),6: 26 bits (64MByte/512MBit device),7: reserved"
|
|
bitfld.long 0x00 2.--3. "addr_nibbles,Number of nibbles to transfer as the address to the SQI chip" "0: 5 nibbles,1: 6 nibbles (default),2: 7 nibbles,3: 8 nibbles"
|
|
newline
|
|
bitfld.long 0x00 1. "addr_before_cmd,When set to '1' the address nibbles will be transferred before the command byte" "0,1"
|
|
bitfld.long 0x00 0. "enable,Enables the SQIROM mode of the SQI module" "0,1"
|
|
tree.end
|
|
tree "SIGMA_DELTA"
|
|
base ad:0xF801D500
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CTRL_UVW,control register for UVW"
|
|
bitfld.long 0x00 28.--31. "BITSHIFT_2,number of bits left shift of path 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "WORD_2_GEN,select divider for word generator path 2 encoding:(01=8 ... 07=256)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22.--23. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "SINC_2_SEL,select sinc1 sinc2 sinc3 for filter path 2 encoding:(01=sinc1 02=sinc2 03=sinc3)" "?,?,2: sinc2,3: sinc3)"
|
|
bitfld.long 0x00 16.--19. "BITSHIFT_1,number of bits left shift of path 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 15. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 12.--14. "WORD_1_GEN,select divider for word generator path 1 encoding:(01=8 ... 07=256)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "SINC_1_SEL,select sinc1 sinc2 sinc3 for filter path 1 encoding:(01=sinc1 02=sinc2 03=sinc3)" "?,?,2: sinc2,3: sinc3)"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "MCLK_DIV,select MCLK divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "MCLKSRC,MCLK source" "0: internal,1: external"
|
|
bitfld.long 0x00 0. "ENABLE,enable channel UVW" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SIGMA_DELTA_STATUS_UVW,STATUS of UVW"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "IRQ_UVW_IGND,current to ground interrupt UVW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 6. "IRQ_W_SC,short circuit detected interrupt W" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IRQ_V_SC,short circuit detected interrupt V" "0,1"
|
|
bitfld.long 0x00 4. "IRQ_U_SC,short circuit detected interrupt U" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 2. "IRQ_W_I,current exceed interrupt W" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "IRQ_V_I,current exceed interrupt V" "0,1"
|
|
bitfld.long 0x00 0. "IRQ_U_I,current exceed interrupt U" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CMP_UVW_I_under,current compare value underflow"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,CMP_UVW_I_under"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CMP_UVW_I_over,current compare value overflow"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,CMP_UVW_I_over bit0"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CMP_UVW_SC_under,short circuit compare value underflow"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--12. 1. "data,CMP_UVW_SC_under"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CMP_UVW_SC_over,short circuit compare value overflow"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--12. 1. "data,CMP_UVW_SC_over bit0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CMP_UVW_IGND_under,current to GND compare value underflow"
|
|
hexmask.long.word 0x00 18.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "data,CMP_UVW_IGND_under bit0"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CMP_UVW_IGND_over,current to GND compare value overflow"
|
|
hexmask.long.word 0x00 18.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "data,N/A"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_U1,SINCx-filter value from word_clk path 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_U1 bit0"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_U1_CREST,SINCx-filter value from word_clk path 1 captured with event CREST"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_U1_CREAST bit0"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_U1_VALLEY,SINCx-filter value from word_clk path 1 captured with event VALLEY"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_U1_VALLEY bit0"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_U2,SINCx-filter value from word_clk path 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_U2 bit0"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_V1,SINCx-filter value from word_clk path 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_V1 bit0"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_V1_CREST,SINCx-filter value from word_clk path 1 captured with event CREST"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_V1_CREAST bit0"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_V1_VALLEY,SINCx-filter value from word_clk path 1 captured with event VALLEY"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_V1_VALLEY bit0"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_V2,SINCx-filter value from word_clk path 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_V2 bit0"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_W1,SINCx-filter value from word_clk path 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_W1 bit0"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_W1_CREST,SINCx-filter value from word_clk path 1 captured with event CREST"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_W1_CREAST bit0"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_W1_VALLEY,SINCx-filter value from word_clk path 1 captured with event VALLEY"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_W1_VALLEY bit0"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_W2,SINCx-filter value from word_clk path 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_W2 bit0"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CTRL_XYZ,control register for XYZ"
|
|
bitfld.long 0x00 28.--31. "BITSHIFT_2,number of bits left shift path 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "WORD_2_GEN,select divider for word generator path 2 encoding:(01=8 ... 07=256)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22.--23. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "SINC_2_SEL,select sinc1 sinc2 sinc3 for filter path 2 encoding:(01=sinc1 02=sinc2 03=sinc3)" "?,?,2: sinc2,3: sinc3)"
|
|
bitfld.long 0x00 16.--19. "BITSHIFT_1,number of bits left shift path 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 15. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 12.--14. "WORD_1_GEN,select divider for word generator path 1 encoding:(01=8 ... 07=256)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "SINC_1_SEL,select sinc1 sinc2 sinc3 for filter path 1 encoding:(01=sinc1 02=sinc2 03=sinc3)" "?,?,2: sinc2,3: sinc3)"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "MCLK_DIV,select MCLK divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "MCLKSRC,MCLK source" "0: internal,1: external"
|
|
bitfld.long 0x00 0. "ENABLE,enable channel UVW" "0,1"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "SIGMA_DELTA_STATUS_XYZ,STATUS of XYZ"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "IRQ_XYZ_IGND,current to ground interrupt XYZ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 6. "IRQ_Z_SC,short circuit detected interrupt Z" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IRQ_Y_SC,short circuit detected interrupt Y" "0,1"
|
|
bitfld.long 0x00 4. "IRQ_X_SC,short circuit detected interrupt X" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 2. "IRQ_Z_I,current exceed interrupt Z" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "IRQ_Y_I,current exceed interrupt Y" "0,1"
|
|
bitfld.long 0x00 0. "IRQ_X_I,current exceed interrupt X" "0,1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CMP_XYZ_I_under,current compare value underflow"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,CMP_XYZ_I_under bit0"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CMP_XYZ_I_over,current compare value overflow"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,CMP_XYZ_I_over bit0"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CMP_XYZ_SC_under,short circuit compare value underflow"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--12. 1. "data,CMP_XYZ_SC_under bit0"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CMP_XYZ_SC_over,short circuit compare value overflow"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--12. 1. "data,CMP_XYZ_SC_over bit0"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CMP_XYZ_IGND_under,current to GND compare value underflow"
|
|
hexmask.long.word 0x00 18.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "data,CMP_XYZ_IGND_under bit0"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "SIGMA_DELTA_CMP_XYZ_IGND_over,current to GND compare value overflow"
|
|
hexmask.long.word 0x00 18.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "data,CMP_XYZ_IGND_over bit0"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_X1,SINCx-filter value from word_clk path 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_X1 bit0"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_X1_CREST,SINCx-filter value from word_clk path 1 captured with event CREST"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_X1_CREAST bit0"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_X1_VALLEY,SINCx-filter value from word_clk path 1 captured with event VALLEY"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_X1_VALLEY bit0"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_X2,SINCx-filter value from word_clk path 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_X2 bit0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_Y1,SINCx-filter value from word_clk path 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_Y1 bit0"
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_Y1_CREST,SINCx-filter value from word_clk path 1 captured with event CREST"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_Y1_CREAST bit0"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_Y1_VALLEY,SINCx-filter value from word_clk path 1 captured with event VALLEY"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_Y1_VALLEY bit0"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_Y2,SINCx-filter value from word_clk path 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_Y2 bit0"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_Z1,SINCx-filter value from word_clk path 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_Z1 bit0"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_Z1_CREST,SINCx-filter value from word_clk path 1 captured with event CREST"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_Z1_CREAST bit0"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_Z1_VALLEY,SINCx-filter value from word_clk path 1 captured with event VALLEY"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_Z1_VALLEY bit0"
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "SIGMA_DELTA_DATA_Z2,SINCx-filter value from word_clk path 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "data,DATA_Z2 bit0"
|
|
tree.end
|
|
tree "RAP_GPIO"
|
|
repeat 5. (list 0. 1. 2. 3. 4.) (list ad:0xF801F000 ad:0xF801F100 ad:0xF801F200 ad:0xF801F300 ad:0xF801F400)
|
|
tree "RAP_GPIO$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RAP_GPIO_IN,External input port ANDed with GPIO_INmask"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RAP_GPIO_INmask,Input mask register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RAP_GPIO_OUT,External output port"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "RAP_GPIO_mask,Extra functionality for output port: mask A read from this register provides the value of the GPIO_out register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "RAP_GPIO_toggle,Extra functionality for output port: toggle A read from this register provides the value of the GPIO_out register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RAP_GPIO_OUTmask,Output mask register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RAP_GPIO_OE,External enable port"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RAP_GPIO_IRQsource,1 shows that corresponding input port change the value / clear register to clear IRQ request"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RAP_GPIO_IRQposedge,"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RAP_GPIO_IRQnegedge,"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "RAP_GPIO_out_set,Extra functionality for output port: set A read from this register provides the value of the GPIO_out register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "RAP_GPIO_out_clr,Extra functionality for output port: clr A read from this register provides the value of the GPIO_out register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "RAP_GPIO_oe_set,Extra functionality for output port: set A read from this register provides the value of the GPIO_oe register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "RAP_GPIO_oe_clr,Extra functionality for output port: clr A read from this register provides the value of the GPIO_oe register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "RSCAN"
|
|
base ad:0xF8030000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RSCAN_C0CFG,Channel 0 Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RSCAN_C0CTR,Channel 0 Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RSCAN_C0STS,Channel 0 Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RSCAN_C0ERFL,Channel 0 Error Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RSCAN_C1CFG,Channel 1 Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RSCAN_C1CTR,Channel 1 Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RSCAN_C1STS,Channel 1 Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RSCAN_C1ERFL,Channel 1 Error Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RSCAN_C2CFG,Channel 2 Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RSCAN_C2CTR,Channel 2 Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "RSCAN_C2STS,Channel 2 Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RSCAN_C2ERFL,Channel 2 Error Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RSCAN_C3CFG,Channel 3 Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "RSCAN_C3CTR,Channel 3 Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "RSCAN_C3STS,Channel 3 Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "RSCAN_C3ERFL,Channel 3 Error Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RSCAN_C4CFG,Channel 4 Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "RSCAN_C4CTR,Channel 4 Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "RSCAN_C4STS,Channel 4 Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "RSCAN_C4ERFL,Channel 4 Error Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "RSCAN_GIPV,Global IP Version Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RSCAN_GCFG,Global Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RSCAN_GCTR,Global Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "RSCAN_GSTS,Global Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "RSCAN_GERFL,Global Error Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "RSCAN_GTSC,Global Timestamp Counter Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "RSCAN_GAFLECTR,Global Acceptance Filter List Entry Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x9C)++0x03
|
|
line.long 0x00 "RSCAN_GAFLCFG$1,Global Acceptance Filter List Configuration Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RSCAN_RMNB,RX Message Buffer Number Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0xA8)++0x03
|
|
line.long 0x00 "RSCAN_RMND$1,RX Message Buffer NewData Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0xB8)++0x03
|
|
line.long 0x00 "RSCAN_RFCC_$1,RX FIFO Configuration / Control Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
|
|
rgroup.long ($2+0xD8)++0x03
|
|
line.long 0x00 "RSCAN_RFSTS_$1,RX FIFO Status Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
wgroup.long ($2+0xF8)++0x03
|
|
line.long 0x00 "RSCAN_RFPCTR_$1,RX FIFO Pointer Control Register[0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 15. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0x118)++0x03
|
|
line.long 0x00 "RSCAN_CFCC_$1,Common FIFO Configuration / Control Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 15. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
rgroup.long ($2+0x178)++0x03
|
|
line.long 0x00 "RSCAN_CFSTS_$1,Common FIFO Status Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 15. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
wgroup.long ($2+0x1D8)++0x03
|
|
line.long 0x00 "RSCAN_CFPCTR_$1,Common FIFO Pointer Control Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
rgroup.long 0x238++0x03
|
|
line.long 0x00 "RSCAN_FESTS,FIFO Empty Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x23C++0x03
|
|
line.long 0x00 "RSCAN_FFSTS,FIFO Full Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "RSCAN_FMSTS,FIFO MsgLost Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x244++0x03
|
|
line.long 0x00 "RSCAN_RFISTS,RX FIFO Interrupt Flag Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x248++0x03
|
|
line.long 0x00 "RSCAN_CFRISTS,Common FIFO RX Interrupt Flag Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x24C++0x03
|
|
line.long 0x00 "RSCAN_CFTISIS,Common FIFO TX Interrupt Flag Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
group.byte ($2+0x250)++0x00
|
|
line.byte 0x00 "RSCAN_TMC_$1,TX Message Buffer Control Register [0]"
|
|
hexmask.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
group.byte ($2+0x260)++0x00
|
|
line.byte 0x00 "RSCAN_TMC_$1,TX Message Buffer Control Register [16]"
|
|
hexmask.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
group.byte ($2+0x270)++0x00
|
|
line.byte 0x00 "RSCAN_TMC_$1,TX Message Buffer Control Register [32]"
|
|
hexmask.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
group.byte ($2+0x280)++0x00
|
|
line.byte 0x00 "RSCAN_TMC_$1,TX Message Buffer Control Register [48]"
|
|
hexmask.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
group.byte ($2+0x290)++0x00
|
|
line.byte 0x00 "RSCAN_TMC_$1,TX Message Buffer Control Register [64]"
|
|
hexmask.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
rgroup.byte ($2+0x2D0)++0x00
|
|
line.byte 0x00 "RSCAN_TMSTS_$1,TX Message Buffer Status Register [0]"
|
|
hexmask.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
rgroup.byte ($2+0x2E0)++0x00
|
|
line.byte 0x00 "RSCAN_TMSTS_$1,TX Message Buffer Status Register [16]"
|
|
hexmask.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
rgroup.byte ($2+0x2F0)++0x00
|
|
line.byte 0x00 "RSCAN_TMSTS_$1,TX Message Buffer Status Register [32]"
|
|
hexmask.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
rgroup.byte ($2+0x300)++0x00
|
|
line.byte 0x00 "RSCAN_TMSTS_$1,TX Message Buffer Status Register [48]"
|
|
hexmask.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
rgroup.byte ($2+0x310)++0x00
|
|
line.byte 0x00 "RSCAN_TMSTS_$1,TX Message Buffer Status Register [64]"
|
|
hexmask.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x350)++0x03
|
|
line.long 0x00 "RSCAN_TMTRSTS$1,TX Message Buffer Transmission Request Status Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x360)++0x03
|
|
line.long 0x00 "RSCAN_TMTARSTS$1,TX Message Buffer Transmission Abortion Request Status Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x370)++0x03
|
|
line.long 0x00 "RSCAN_TMTCSTS$1,TX Message Buffer Transmission Completion Status Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x380)++0x03
|
|
line.long 0x00 "RSCAN_TMTASTS$1,TX Message Buffer Transmission Abortion Status Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
|
|
group.long ($2+0x390)++0x03
|
|
line.long 0x00 "RSCAN_TMIEC$1,TX Message Buffer Interrupt Enable Configuration Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
group.long ($2+0x3A0)++0x03
|
|
line.long 0x00 "RSCAN_TXQCC$1,TX Queue Configuration / Control Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
rgroup.long ($2+0x3C0)++0x03
|
|
line.long 0x00 "RSCAN_TXQSTS$1,TX Queue Status Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
wgroup.long ($2+0x3E0)++0x03
|
|
line.long 0x00 "RSCAN_TXQPCTR$1,TX Queue Pointer Control Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
group.long ($2+0x400)++0x03
|
|
line.long 0x00 "RSCAN_THLCC$1,TX History List Configuration / Control Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
rgroup.long ($2+0x420)++0x03
|
|
line.long 0x00 "RSCAN_THLSTS$1,TX History List Status Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
wgroup.long ($2+0x440)++0x03
|
|
line.long 0x00 "RSCAN_THLPCTR$1,TX History List Pointer Control Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 2. (strings "0" "1" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x460)++0x03
|
|
line.long 0x00 "RSCAN_GTINTSTS$1,Global TX Interrupt Status Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "RSCAN_GTSTCFG,Global Test Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "RSCAN_GTSTCTR,Global Test Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "RSCAN_GEIMCC,Global Error Insertion Mode Configuration / Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
wgroup.long 0x47C++0x03
|
|
line.long 0x00 "RSCAN_GLOCKK,Global Lock Key Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "RSCAN_GLOTB,Global OTB FIFO Configuration / Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_0,Global Acceptance Filter List ID Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_0,Global Acceptance Filter List Mask Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_0,Global Acceptance Filter List Pointer 0 Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_0,Global Acceptance Filter List Pointer 1 Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_1,Global Acceptance Filter List ID Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_1,Global Acceptance Filter List Mask Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_1,Global Acceptance Filter List Pointer 0 Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_1,Global Acceptance Filter List Pointer 1 Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_2,Global Acceptance Filter List ID Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_2,Global Acceptance Filter List Mask Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_2,Global Acceptance Filter List Pointer 0 Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_2,Global Acceptance Filter List Pointer 1 Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_3,Global Acceptance Filter List ID Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_3,Global Acceptance Filter List Mask Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_3,Global Acceptance Filter List Pointer 0 Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_3,Global Acceptance Filter List Pointer 1 Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_4,Global Acceptance Filter List ID Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_4,Global Acceptance Filter List Mask Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_4,Global Acceptance Filter List Pointer 0 Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_4,Global Acceptance Filter List Pointer 1 Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_5,Global Acceptance Filter List ID Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_5,Global Acceptance Filter List Mask Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_5,Global Acceptance Filter List Pointer 0 Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_5,Global Acceptance Filter List Pointer 1 Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_6,Global Acceptance Filter List ID Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_6,Global Acceptance Filter List Mask Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_6,Global Acceptance Filter List Pointer 0 Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_6,Global Acceptance Filter List Pointer 1 Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_7,Global Acceptance Filter List ID Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_7,Global Acceptance Filter List Mask Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_7,Global Acceptance Filter List Pointer 0 Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_7,Global Acceptance Filter List Pointer 1 Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_8,Global Acceptance Filter List ID Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_8,Global Acceptance Filter List Mask Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_8,Global Acceptance Filter List Pointer 0 Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_8,Global Acceptance Filter List Pointer 1 Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_9,Global Acceptance Filter List ID Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_9,Global Acceptance Filter List Mask Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x598++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_9,Global Acceptance Filter List Pointer 0 Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x59C++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_9,Global Acceptance Filter List Pointer 1 Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_10,Global Acceptance Filter List ID Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_10,Global Acceptance Filter List Mask Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5A8++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_10,Global Acceptance Filter List Pointer 0 Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5AC++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_10,Global Acceptance Filter List Pointer 1 Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_11,Global Acceptance Filter List ID Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_11,Global Acceptance Filter List Mask Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_11,Global Acceptance Filter List Pointer 0 Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_11,Global Acceptance Filter List Pointer 1 Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_12,Global Acceptance Filter List ID Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5C4++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_12,Global Acceptance Filter List Mask Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5C8++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_12,Global Acceptance Filter List Pointer 0 Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5CC++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_12,Global Acceptance Filter List Pointer 1 Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5D0++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_13,Global Acceptance Filter List ID Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5D4++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_13,Global Acceptance Filter List Mask Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5D8++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_13,Global Acceptance Filter List Pointer 0 Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5DC++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_13,Global Acceptance Filter List Pointer 1 Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_14,Global Acceptance Filter List ID Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5E4++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_14,Global Acceptance Filter List Mask Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5E8++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_14,Global Acceptance Filter List Pointer 0 Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5EC++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_14,Global Acceptance Filter List Pointer 1 Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5F0++0x03
|
|
line.long 0x00 "RSCAN_GAFLID_15,Global Acceptance Filter List ID Register [15]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5F4++0x03
|
|
line.long 0x00 "RSCAN_GAFLM_15,Global Acceptance Filter List Mask Register [15]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5F8++0x03
|
|
line.long 0x00 "RSCAN_GAFLP0_15,Global Acceptance Filter List Pointer 0 Register [15]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x5FC++0x03
|
|
line.long 0x00 "RSCAN_GAFLP1_15,Global Acceptance Filter List Pointer 1 Register [15]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x600++0x03
|
|
line.long 0x00 "RSCAN_RMID_0,RX Message Buffer ID Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x604++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_0,RX Message Buffer Pointer Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x608++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_0,RX Message Buffer Data Field 0 Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x60C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_0,RX Message Buffer Data Field 1 Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x610++0x03
|
|
line.long 0x00 "RSCAN_RMID_1,RX Message Buffer ID Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x614++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_1,RX Message Buffer Pointer Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x618++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_1,RX Message Buffer Data Field 0 Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x61C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_1,RX Message Buffer Data Field 1 Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x620++0x03
|
|
line.long 0x00 "RSCAN_RMID_2,RX Message Buffer ID Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x624++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_2,RX Message Buffer Pointer Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x628++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_2,RX Message Buffer Data Field 0 Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x62C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_2,RX Message Buffer Data Field 1 Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x630++0x03
|
|
line.long 0x00 "RSCAN_RMID_3,RX Message Buffer ID Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x634++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_3,RX Message Buffer Pointer Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x638++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_3,RX Message Buffer Data Field 0 Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x63C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_3,RX Message Buffer Data Field 1 Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "RSCAN_RMID_4,RX Message Buffer ID Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x644++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_4,RX Message Buffer Pointer Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x648++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_4,RX Message Buffer Data Field 0 Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x64C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_4,RX Message Buffer Data Field 1 Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x650++0x03
|
|
line.long 0x00 "RSCAN_RMID_5,RX Message Buffer ID Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x654++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_5,RX Message Buffer Pointer Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x658++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_5,RX Message Buffer Data Field 0 Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x65C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_5,RX Message Buffer Data Field 1 Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x660++0x03
|
|
line.long 0x00 "RSCAN_RMID_6,RX Message Buffer ID Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x664++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_6,RX Message Buffer Pointer Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x668++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_6,RX Message Buffer Data Field 0 Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x66C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_6,RX Message Buffer Data Field 1 Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x670++0x03
|
|
line.long 0x00 "RSCAN_RMID_7,RX Message Buffer ID Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x674++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_7,RX Message Buffer Pointer Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x678++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_7,RX Message Buffer Data Field 0 Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x67C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_7,RX Message Buffer Data Field 1 Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x680++0x03
|
|
line.long 0x00 "RSCAN_RMID_8,RX Message Buffer ID Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x684++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_8,RX Message Buffer Pointer Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x688++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_8,RX Message Buffer Data Field 0 Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x68C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_8,RX Message Buffer Data Field 1 Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x690++0x03
|
|
line.long 0x00 "RSCAN_RMID_9,RX Message Buffer ID Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x694++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_9,RX Message Buffer Pointer Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x698++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_9,RX Message Buffer Data Field 0 Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x69C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_9,RX Message Buffer Data Field 1 Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6A0++0x03
|
|
line.long 0x00 "RSCAN_RMID_10,RX Message Buffer ID Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6A4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_10,RX Message Buffer Pointer Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6A8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_10,RX Message Buffer Data Field 0 Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6AC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_10,RX Message Buffer Data Field 1 Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6B0++0x03
|
|
line.long 0x00 "RSCAN_RMID_11,RX Message Buffer ID Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6B4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_11,RX Message Buffer Pointer Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6B8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_11,RX Message Buffer Data Field 0 Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6BC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_11,RX Message Buffer Data Field 1 Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6C0++0x03
|
|
line.long 0x00 "RSCAN_RMID_12,RX Message Buffer ID Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6C4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_12,RX Message Buffer Pointer Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6C8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_12,RX Message Buffer Data Field 0 Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6CC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_12,RX Message Buffer Data Field 1 Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6D0++0x03
|
|
line.long 0x00 "RSCAN_RMID_13,RX Message Buffer ID Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6D4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_13,RX Message Buffer Pointer Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6D8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_13,RX Message Buffer Data Field 0 Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6DC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_13,RX Message Buffer Data Field 1 Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6E0++0x03
|
|
line.long 0x00 "RSCAN_RMID_14,RX Message Buffer ID Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6E4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_14,RX Message Buffer Pointer Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6E8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_14,RX Message Buffer Data Field 0 Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6EC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_14,RX Message Buffer Data Field 1 Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6F0++0x03
|
|
line.long 0x00 "RSCAN_RMID_15,RX Message Buffer ID Register [15]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6F4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_15,RX Message Buffer Pointer Register [15]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6F8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_15,RX Message Buffer Data Field 0 Register [15]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x6FC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_15,RX Message Buffer Data Field 1 Register [15]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x700++0x03
|
|
line.long 0x00 "RSCAN_RMID_16,RX Message Buffer ID Register [16]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x704++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_16,RX Message Buffer Pointer Register [16]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x708++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_16,RX Message Buffer Data Field 0 Register [16]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x70C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_16,RX Message Buffer Data Field 1 Register [16]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x710++0x03
|
|
line.long 0x00 "RSCAN_RMID_17,RX Message Buffer ID Register [17]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x714++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_17,RX Message Buffer Pointer Register [17]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x718++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_17,RX Message Buffer Data Field 0 Register [17]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x71C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_17,RX Message Buffer Data Field 1 Register [17]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x720++0x03
|
|
line.long 0x00 "RSCAN_RMID_18,RX Message Buffer ID Register [18]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x724++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_18,RX Message Buffer Pointer Register [18]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x728++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_18,RX Message Buffer Data Field 0 Register [18]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x72C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_18,RX Message Buffer Data Field 1 Register [18]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x730++0x03
|
|
line.long 0x00 "RSCAN_RMID_19,RX Message Buffer ID Register [19]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x734++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_19,RX Message Buffer Pointer Register [19]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x738++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_19,RX Message Buffer Data Field 0 Register [19]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x73C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_19,RX Message Buffer Data Field 1 Register [19]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x740++0x03
|
|
line.long 0x00 "RSCAN_RMID_20,RX Message Buffer ID Register [20]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x744++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_20,RX Message Buffer Pointer Register [20]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x748++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_20,RX Message Buffer Data Field 0 Register [20]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x74C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_20,RX Message Buffer Data Field 1 Register [20]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x750++0x03
|
|
line.long 0x00 "RSCAN_RMID_21,RX Message Buffer ID Register [21]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x754++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_21,RX Message Buffer Pointer Register [21]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x758++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_21,RX Message Buffer Data Field 0 Register [21]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x75C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_21,RX Message Buffer Data Field 1 Register [21]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x760++0x03
|
|
line.long 0x00 "RSCAN_RMID_22,RX Message Buffer ID Register [22]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x764++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_22,RX Message Buffer Pointer Register [22]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x768++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_22,RX Message Buffer Data Field 0 Register [22]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x76C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_22,RX Message Buffer Data Field 1 Register [22]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x770++0x03
|
|
line.long 0x00 "RSCAN_RMID_23,RX Message Buffer ID Register [23]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x774++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_23,RX Message Buffer Pointer Register [23]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x778++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_23,RX Message Buffer Data Field 0 Register [23]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x77C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_23,RX Message Buffer Data Field 1 Register [23]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x780++0x03
|
|
line.long 0x00 "RSCAN_RMID_24,RX Message Buffer ID Register [24]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x784++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_24,RX Message Buffer Pointer Register [24]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x788++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_24,RX Message Buffer Data Field 0 Register [24]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x78C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_24,RX Message Buffer Data Field 1 Register [24]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x790++0x03
|
|
line.long 0x00 "RSCAN_RMID_25,RX Message Buffer ID Register [25]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x794++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_25,RX Message Buffer Pointer Register [25]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x798++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_25,RX Message Buffer Data Field 0 Register [25]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x79C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_25,RX Message Buffer Data Field 1 Register [25]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7A0++0x03
|
|
line.long 0x00 "RSCAN_RMID_26,RX Message Buffer ID Register [26]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7A4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_26,RX Message Buffer Pointer Register [26]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7A8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_26,RX Message Buffer Data Field 0 Register [26]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7AC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_26,RX Message Buffer Data Field 1 Register [26]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7B0++0x03
|
|
line.long 0x00 "RSCAN_RMID_27,RX Message Buffer ID Register [27]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7B4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_27,RX Message Buffer Pointer Register [27]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7B8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_27,RX Message Buffer Data Field 0 Register [27]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7BC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_27,RX Message Buffer Data Field 1 Register [27]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7C0++0x03
|
|
line.long 0x00 "RSCAN_RMID_28,RX Message Buffer ID Register [28]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7C4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_28,RX Message Buffer Pointer Register [28]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7C8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_28,RX Message Buffer Data Field 0 Register [28]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7CC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_28,RX Message Buffer Data Field 1 Register [28]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7D0++0x03
|
|
line.long 0x00 "RSCAN_RMID_29,RX Message Buffer ID Register [29]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7D4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_29,RX Message Buffer Pointer Register [29]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7D8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_29,RX Message Buffer Data Field 0 Register [29]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7DC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_29,RX Message Buffer Data Field 1 Register [29]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7E0++0x03
|
|
line.long 0x00 "RSCAN_RMID_30,RX Message Buffer ID Register [30]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7E4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_30,RX Message Buffer Pointer Register [30]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7E8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_30,RX Message Buffer Data Field 0 Register [30]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7EC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_30,RX Message Buffer Data Field 1 Register [30]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7F0++0x03
|
|
line.long 0x00 "RSCAN_RMID_31,RX Message Buffer ID Register [31]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7F4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_31,RX Message Buffer Pointer Register [31]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7F8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_31,RX Message Buffer Data Field 0 Register [31]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x7FC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_31,RX Message Buffer Data Field 1 Register [31]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "RSCAN_RMID_32,RX Message Buffer ID Register [32]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x804++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_32,RX Message Buffer Pointer Register [32]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x808++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_32,RX Message Buffer Data Field 0 Register [32]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x80C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_32,RX Message Buffer Data Field 1 Register [32]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x810++0x03
|
|
line.long 0x00 "RSCAN_RMID_33,RX Message Buffer ID Register [33]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x814++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_33,RX Message Buffer Pointer Register [33]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_33,RX Message Buffer Data Field 0 Register [33]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x81C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_33,RX Message Buffer Data Field 1 Register [33]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x820++0x03
|
|
line.long 0x00 "RSCAN_RMID_34,RX Message Buffer ID Register [34]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x824++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_34,RX Message Buffer Pointer Register [34]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x828++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_34,RX Message Buffer Data Field 0 Register [34]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x82C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_34,RX Message Buffer Data Field 1 Register [34]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "RSCAN_RMID_35,RX Message Buffer ID Register [35]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x834++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_35,RX Message Buffer Pointer Register [35]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x838++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_35,RX Message Buffer Data Field 0 Register [35]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x83C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_35,RX Message Buffer Data Field 1 Register [35]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x840++0x03
|
|
line.long 0x00 "RSCAN_RMID_36,RX Message Buffer ID Register [36]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x844++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_36,RX Message Buffer Pointer Register [36]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x848++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_36,RX Message Buffer Data Field 0 Register [36]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x84C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_36,RX Message Buffer Data Field 1 Register [36]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x850++0x03
|
|
line.long 0x00 "RSCAN_RMID_37,RX Message Buffer ID Register [37]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x854++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_37,RX Message Buffer Pointer Register [37]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x858++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_37,RX Message Buffer Data Field 0 Register [37]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x85C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_37,RX Message Buffer Data Field 1 Register [37]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x860++0x03
|
|
line.long 0x00 "RSCAN_RMID_38,RX Message Buffer ID Register [38]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x864++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_38,RX Message Buffer Pointer Register [38]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x868++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_38,RX Message Buffer Data Field 0 Register [38]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x86C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_38,RX Message Buffer Data Field 1 Register [38]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x870++0x03
|
|
line.long 0x00 "RSCAN_RMID_39,RX Message Buffer ID Register [39]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x874++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_39,RX Message Buffer Pointer Register [39]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x878++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_39,RX Message Buffer Data Field 0 Register [39]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x87C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_39,RX Message Buffer Data Field 1 Register [39]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x880++0x03
|
|
line.long 0x00 "RSCAN_RMID_40,RX Message Buffer ID Register [40]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x884++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_40,RX Message Buffer Pointer Register [40]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x888++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_40,RX Message Buffer Data Field 0 Register [40]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x88C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_40,RX Message Buffer Data Field 1 Register [40]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x890++0x03
|
|
line.long 0x00 "RSCAN_RMID_41,RX Message Buffer ID Register [41]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x894++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_41,RX Message Buffer Pointer Register [41]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x898++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_41,RX Message Buffer Data Field 0 Register [41]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x89C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_41,RX Message Buffer Data Field 1 Register [41]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8A0++0x03
|
|
line.long 0x00 "RSCAN_RMID_42,RX Message Buffer ID Register [42]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8A4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_42,RX Message Buffer Pointer Register [42]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8A8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_42,RX Message Buffer Data Field 0 Register [42]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8AC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_42,RX Message Buffer Data Field 1 Register [42]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8B0++0x03
|
|
line.long 0x00 "RSCAN_RMID_43,RX Message Buffer ID Register [43]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8B4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_43,RX Message Buffer Pointer Register [43]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8B8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_43,RX Message Buffer Data Field 0 Register [43]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8BC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_43,RX Message Buffer Data Field 1 Register [43]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8C0++0x03
|
|
line.long 0x00 "RSCAN_RMID_44,RX Message Buffer ID Register [44]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8C4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_44,RX Message Buffer Pointer Register [44]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8C8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_44,RX Message Buffer Data Field 0 Register [44]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8CC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_44,RX Message Buffer Data Field 1 Register [44]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8D0++0x03
|
|
line.long 0x00 "RSCAN_RMID_45,RX Message Buffer ID Register [45]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8D4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_45,RX Message Buffer Pointer Register [45]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8D8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_45,RX Message Buffer Data Field 0 Register [45]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8DC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_45,RX Message Buffer Data Field 1 Register [45]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8E0++0x03
|
|
line.long 0x00 "RSCAN_RMID_46,RX Message Buffer ID Register [46]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8E4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_46,RX Message Buffer Pointer Register [46]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8E8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_46,RX Message Buffer Data Field 0 Register [46]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8EC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_46,RX Message Buffer Data Field 1 Register [46]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8F0++0x03
|
|
line.long 0x00 "RSCAN_RMID_47,RX Message Buffer ID Register [47]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8F4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_47,RX Message Buffer Pointer Register [47]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8F8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_47,RX Message Buffer Data Field 0 Register [47]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x8FC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_47,RX Message Buffer Data Field 1 Register [47]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x900++0x03
|
|
line.long 0x00 "RSCAN_RMID_48,RX Message Buffer ID Register [48]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x904++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_48,RX Message Buffer Pointer Register [48]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x908++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_48,RX Message Buffer Data Field 0 Register [48]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x90C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_48,RX Message Buffer Data Field 1 Register [48]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x910++0x03
|
|
line.long 0x00 "RSCAN_RMID_49,RX Message Buffer ID Register [49]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x914++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_49,RX Message Buffer Pointer Register [49]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x918++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_49,RX Message Buffer Data Field 0 Register [49]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x91C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_49,RX Message Buffer Data Field 1 Register [49]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x920++0x03
|
|
line.long 0x00 "RSCAN_RMID_50,RX Message Buffer ID Register [50]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x924++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_50,RX Message Buffer Pointer Register [50]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x928++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_50,RX Message Buffer Data Field 0 Register [50]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x92C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_50,RX Message Buffer Data Field 1 Register [50]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x930++0x03
|
|
line.long 0x00 "RSCAN_RMID_51,RX Message Buffer ID Register [51]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x934++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_51,RX Message Buffer Pointer Register [51]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x938++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_51,RX Message Buffer Data Field 0 Register [51]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x93C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_51,RX Message Buffer Data Field 1 Register [51]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x940++0x03
|
|
line.long 0x00 "RSCAN_RMID_52,RX Message Buffer ID Register [52]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x944++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_52,RX Message Buffer Pointer Register [52]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x948++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_52,RX Message Buffer Data Field 0 Register [52]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x94C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_52,RX Message Buffer Data Field 1 Register [52]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x950++0x03
|
|
line.long 0x00 "RSCAN_RMID_53,RX Message Buffer ID Register [53]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x954++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_53,RX Message Buffer Pointer Register [53]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x958++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_53,RX Message Buffer Data Field 0 Register [53]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x95C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_53,RX Message Buffer Data Field 1 Register [53]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x960++0x03
|
|
line.long 0x00 "RSCAN_RMID_54,RX Message Buffer ID Register [54]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x964++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_54,RX Message Buffer Pointer Register [54]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x968++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_54,RX Message Buffer Data Field 0 Register [54]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x96C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_54,RX Message Buffer Data Field 1 Register [54]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x970++0x03
|
|
line.long 0x00 "RSCAN_RMID_55,RX Message Buffer ID Register [55]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x974++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_55,RX Message Buffer Pointer Register [55]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x978++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_55,RX Message Buffer Data Field 0 Register [55]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x97C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_55,RX Message Buffer Data Field 1 Register [55]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x980++0x03
|
|
line.long 0x00 "RSCAN_RMID_56,RX Message Buffer ID Register [56]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x984++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_56,RX Message Buffer Pointer Register [56]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x988++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_56,RX Message Buffer Data Field 0 Register [56]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x98C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_56,RX Message Buffer Data Field 1 Register [56]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x990++0x03
|
|
line.long 0x00 "RSCAN_RMID_57,RX Message Buffer ID Register [57]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x994++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_57,RX Message Buffer Pointer Register [57]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x998++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_57,RX Message Buffer Data Field 0 Register [57]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x99C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_57,RX Message Buffer Data Field 1 Register [57]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9A0++0x03
|
|
line.long 0x00 "RSCAN_RMID_58,RX Message Buffer ID Register [58]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9A4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_58,RX Message Buffer Pointer Register [58]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9A8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_58,RX Message Buffer Data Field 0 Register [58]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9AC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_58,RX Message Buffer Data Field 1 Register [58]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9B0++0x03
|
|
line.long 0x00 "RSCAN_RMID_59,RX Message Buffer ID Register [59]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9B4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_59,RX Message Buffer Pointer Register [59]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9B8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_59,RX Message Buffer Data Field 0 Register [59]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9BC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_59,RX Message Buffer Data Field 1 Register [59]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9C0++0x03
|
|
line.long 0x00 "RSCAN_RMID_60,RX Message Buffer ID Register [60]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9C4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_60,RX Message Buffer Pointer Register [60]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9C8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_60,RX Message Buffer Data Field 0 Register [60]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9CC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_60,RX Message Buffer Data Field 1 Register [60]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9D0++0x03
|
|
line.long 0x00 "RSCAN_RMID_61,RX Message Buffer ID Register [61]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9D4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_61,RX Message Buffer Pointer Register [61]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9D8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_61,RX Message Buffer Data Field 0 Register [61]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9DC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_61,RX Message Buffer Data Field 1 Register [61]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9E0++0x03
|
|
line.long 0x00 "RSCAN_RMID_62,RX Message Buffer ID Register [62]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9E4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_62,RX Message Buffer Pointer Register [62]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9E8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_62,RX Message Buffer Data Field 0 Register [62]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9EC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_62,RX Message Buffer Data Field 1 Register [62]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9F0++0x03
|
|
line.long 0x00 "RSCAN_RMID_63,RX Message Buffer ID Register [63]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9F4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_63,RX Message Buffer Pointer Register [63]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9F8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_63,RX Message Buffer Data Field 0 Register [63]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x9FC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_63,RX Message Buffer Data Field 1 Register [63]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA00++0x03
|
|
line.long 0x00 "RSCAN_RMID_64,RX Message Buffer ID Register [64]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA04++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_64,RX Message Buffer Pointer Register [64]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA08++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_64,RX Message Buffer Data Field 0 Register [64]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA0C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_64,RX Message Buffer Data Field 1 Register [64]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA10++0x03
|
|
line.long 0x00 "RSCAN_RMID_65,RX Message Buffer ID Register [65]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA14++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_65,RX Message Buffer Pointer Register [65]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA18++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_65,RX Message Buffer Data Field 0 Register [65]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA1C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_65,RX Message Buffer Data Field 1 Register [65]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA20++0x03
|
|
line.long 0x00 "RSCAN_RMID_66,RX Message Buffer ID Register [66]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA24++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_66,RX Message Buffer Pointer Register [66]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA28++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_66,RX Message Buffer Data Field 0 Register [66]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA2C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_66,RX Message Buffer Data Field 1 Register [66]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA30++0x03
|
|
line.long 0x00 "RSCAN_RMID_67,RX Message Buffer ID Register [67]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA34++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_67,RX Message Buffer Pointer Register [67]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA38++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_67,RX Message Buffer Data Field 0 Register [67]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA3C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_67,RX Message Buffer Data Field 1 Register [67]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA40++0x03
|
|
line.long 0x00 "RSCAN_RMID_68,RX Message Buffer ID Register [68]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA44++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_68,RX Message Buffer Pointer Register [68]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA48++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_68,RX Message Buffer Data Field 0 Register [68]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA4C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_68,RX Message Buffer Data Field 1 Register [68]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA50++0x03
|
|
line.long 0x00 "RSCAN_RMID_69,RX Message Buffer ID Register [69]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA54++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_69,RX Message Buffer Pointer Register [69]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA58++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_69,RX Message Buffer Data Field 0 Register [69]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA5C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_69,RX Message Buffer Data Field 1 Register [69]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA60++0x03
|
|
line.long 0x00 "RSCAN_RMID_70,RX Message Buffer ID Register [70]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA64++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_70,RX Message Buffer Pointer Register [70]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA68++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_70,RX Message Buffer Data Field 0 Register [70]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA6C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_70,RX Message Buffer Data Field 1 Register [70]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA70++0x03
|
|
line.long 0x00 "RSCAN_RMID_71,RX Message Buffer ID Register [71]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA74++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_71,RX Message Buffer Pointer Register [71]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA78++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_71,RX Message Buffer Data Field 0 Register [71]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA7C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_71,RX Message Buffer Data Field 1 Register [71]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA80++0x03
|
|
line.long 0x00 "RSCAN_RMID_72,RX Message Buffer ID Register [72]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA84++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_72,RX Message Buffer Pointer Register [72]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA88++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_72,RX Message Buffer Data Field 0 Register [72]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA8C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_72,RX Message Buffer Data Field 1 Register [72]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA90++0x03
|
|
line.long 0x00 "RSCAN_RMID_73,RX Message Buffer ID Register [73]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA94++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_73,RX Message Buffer Pointer Register [73]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA98++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_73,RX Message Buffer Data Field 0 Register [73]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA9C++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_73,RX Message Buffer Data Field 1 Register [73]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAA0++0x03
|
|
line.long 0x00 "RSCAN_RMID_74,RX Message Buffer ID Register [74]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAA4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_74,RX Message Buffer Pointer Register [74]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAA8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_74,RX Message Buffer Data Field 0 Register [74]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAAC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_74,RX Message Buffer Data Field 1 Register [74]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAB0++0x03
|
|
line.long 0x00 "RSCAN_RMID_75,RX Message Buffer ID Register [75]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAB4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_75,RX Message Buffer Pointer Register [75]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAB8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_75,RX Message Buffer Data Field 0 Register [75]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xABC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_75,RX Message Buffer Data Field 1 Register [75]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAC0++0x03
|
|
line.long 0x00 "RSCAN_RMID_76,RX Message Buffer ID Register [76]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAC4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_76,RX Message Buffer Pointer Register [76]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAC8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_76,RX Message Buffer Data Field 0 Register [76]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xACC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_76,RX Message Buffer Data Field 1 Register [76]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAD0++0x03
|
|
line.long 0x00 "RSCAN_RMID_77,RX Message Buffer ID Register [77]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAD4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_77,RX Message Buffer Pointer Register [77]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAD8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_77,RX Message Buffer Data Field 0 Register [77]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xADC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_77,RX Message Buffer Data Field 1 Register [77]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAE0++0x03
|
|
line.long 0x00 "RSCAN_RMID_78,RX Message Buffer ID Register [78]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAE4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_78,RX Message Buffer Pointer Register [78]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAE8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_78,RX Message Buffer Data Field 0 Register [78]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAEC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_78,RX Message Buffer Data Field 1 Register [78]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAF0++0x03
|
|
line.long 0x00 "RSCAN_RMID_79,RX Message Buffer ID Register [79]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAF4++0x03
|
|
line.long 0x00 "RSCAN_RMPTR_79,RX Message Buffer Pointer Register [79]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAF8++0x03
|
|
line.long 0x00 "RSCAN_RMDF0_79,RX Message Buffer Data Field 0 Register [79]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xAFC++0x03
|
|
line.long 0x00 "RSCAN_RMDF1_79,RX Message Buffer Data Field 1 Register [79]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "RSCAN_RFID_0,RX FIFO Access ID Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE04++0x03
|
|
line.long 0x00 "RSCAN_RFPTR_0,RX FIFO Access Pointer Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE08++0x03
|
|
line.long 0x00 "RSCAN_RFDF0_0,RX FIFO Access Data Field 0 Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE0C++0x03
|
|
line.long 0x00 "RSCAN_RFDF1_0,RX FIFO Access Data Field 1 Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE10++0x03
|
|
line.long 0x00 "RSCAN_RFID_1,RX FIFO Access ID Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE14++0x03
|
|
line.long 0x00 "RSCAN_RFPTR_1,RX FIFO Access Pointer Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE18++0x03
|
|
line.long 0x00 "RSCAN_RFDF0_1,RX FIFO Access Data Field 0 Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE1C++0x03
|
|
line.long 0x00 "RSCAN_RFDF1_1,RX FIFO Access Data Field 1 Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE20++0x03
|
|
line.long 0x00 "RSCAN_RFID_2,RX FIFO Access ID Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE24++0x03
|
|
line.long 0x00 "RSCAN_RFPTR_2,RX FIFO Access Pointer Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE28++0x03
|
|
line.long 0x00 "RSCAN_RFDF0_2,RX FIFO Access Data Field 0 Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE2C++0x03
|
|
line.long 0x00 "RSCAN_RFDF1_2,RX FIFO Access Data Field 1 Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE30++0x03
|
|
line.long 0x00 "RSCAN_RFID_3,RX FIFO Access ID Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE34++0x03
|
|
line.long 0x00 "RSCAN_RFPTR_3,RX FIFO Access Pointer Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE38++0x03
|
|
line.long 0x00 "RSCAN_RFDF0_3,RX FIFO Access Data Field 0 Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE3C++0x03
|
|
line.long 0x00 "RSCAN_RFDF1_3,RX FIFO Access Data Field 1 Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE40++0x03
|
|
line.long 0x00 "RSCAN_RFID_4,RX FIFO Access ID Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE44++0x03
|
|
line.long 0x00 "RSCAN_RFPTR_4,RX FIFO Access Pointer Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE48++0x03
|
|
line.long 0x00 "RSCAN_RFDF0_4,RX FIFO Access Data Field 0 Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE4C++0x03
|
|
line.long 0x00 "RSCAN_RFDF1_4,RX FIFO Access Data Field 1 Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE50++0x03
|
|
line.long 0x00 "RSCAN_RFID_5,RX FIFO Access ID Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE54++0x03
|
|
line.long 0x00 "RSCAN_RFPTR_5,RX FIFO Access Pointer Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE58++0x03
|
|
line.long 0x00 "RSCAN_RFDF0_5,RX FIFO Access Data Field 0 Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE5C++0x03
|
|
line.long 0x00 "RSCAN_RFDF1_5,RX FIFO Access Data Field 1 Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE60++0x03
|
|
line.long 0x00 "RSCAN_RFID_6,RX FIFO Access ID Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE64++0x03
|
|
line.long 0x00 "RSCAN_RFPTR_6,RX FIFO Access Pointer Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE68++0x03
|
|
line.long 0x00 "RSCAN_RFDF0_6,RX FIFO Access Data Field 0 Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE6C++0x03
|
|
line.long 0x00 "RSCAN_RFDF1_6,RX FIFO Access Data Field 1 Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE70++0x03
|
|
line.long 0x00 "RSCAN_RFID_7,RX FIFO Access ID Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE74++0x03
|
|
line.long 0x00 "RSCAN_RFPTR_7,RX FIFO Access Pointer Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE78++0x03
|
|
line.long 0x00 "RSCAN_RFDF0_7,RX FIFO Access Data Field 0 Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xE7C++0x03
|
|
line.long 0x00 "RSCAN_RFDF1_7,RX FIFO Access Data Field 1 Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "RSCAN_CFID_0,Common FIFO Access ID Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xE84++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_0,Common FIFO Access Pointer Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xE88++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_0,Common FIFO Access Data Field 0 Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xE8C++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_0,Common FIFO Access Data Field 1 Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xE90++0x03
|
|
line.long 0x00 "RSCAN_CFID_1,Common FIFO Access ID Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xE94++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_1,Common FIFO Access Pointer Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xE98++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_1,Common FIFO Access Data Field 0 Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xE9C++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_1,Common FIFO Access Data Field 1 Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEA0++0x03
|
|
line.long 0x00 "RSCAN_CFID_2,Common FIFO Access ID Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEA4++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_2,Common FIFO Access Pointer Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEA8++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_2,Common FIFO Access Data Field 0 Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEAC++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_2,Common FIFO Access Data Field 1 Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEB0++0x03
|
|
line.long 0x00 "RSCAN_CFID_3,Common FIFO Access ID Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEB4++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_3,Common FIFO Access Pointer Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEB8++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_3,Common FIFO Access Data Field 0 Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEBC++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_3,Common FIFO Access Data Field 1 Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEC0++0x03
|
|
line.long 0x00 "RSCAN_CFID_4,Common FIFO Access ID Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEC4++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_4,Common FIFO Access Pointer Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEC8++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_4,Common FIFO Access Data Field 0 Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xECC++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_4,Common FIFO Access Data Field 1 Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xED0++0x03
|
|
line.long 0x00 "RSCAN_CFID_5,Common FIFO Access ID Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xED4++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_5,Common FIFO Access Pointer Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xED8++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_5,Common FIFO Access Data Field 0 Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEDC++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_5,Common FIFO Access Data Field 1 Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEE0++0x03
|
|
line.long 0x00 "RSCAN_CFID_6,Common FIFO Access ID Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEE4++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_6,Common FIFO Access Pointer Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEE8++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_6,Common FIFO Access Data Field 0 Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEEC++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_6,Common FIFO Access Data Field 1 Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEF0++0x03
|
|
line.long 0x00 "RSCAN_CFID_7,Common FIFO Access ID Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEF4++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_7,Common FIFO Access Pointer Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEF8++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_7,Common FIFO Access Data Field 0 Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xEFC++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_7,Common FIFO Access Data Field 1 Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "RSCAN_CFID_8,Common FIFO Access ID Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF04++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_8,Common FIFO Access Pointer Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF08++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_8,Common FIFO Access Data Field 0 Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF0C++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_8,Common FIFO Access Data Field 1 Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF10++0x03
|
|
line.long 0x00 "RSCAN_CFID_9,Common FIFO Access ID Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF14++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_9,Common FIFO Access Pointer Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF18++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_9,Common FIFO Access Data Field 0 Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF1C++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_9,Common FIFO Access Data Field 1 Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF20++0x03
|
|
line.long 0x00 "RSCAN_CFID_10,Common FIFO Access ID Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF24++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_10,Common FIFO Access Pointer Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF28++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_10,Common FIFO Access Data Field 0 Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF2C++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_10,Common FIFO Access Data Field 1 Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF30++0x03
|
|
line.long 0x00 "RSCAN_CFID_11,Common FIFO Access ID Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF34++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_11,Common FIFO Access Pointer Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF38++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_11,Common FIFO Access Data Field 0 Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF3C++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_11,Common FIFO Access Data Field 1 Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF40++0x03
|
|
line.long 0x00 "RSCAN_CFID_12,Common FIFO Access ID Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF44++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_12,Common FIFO Access Pointer Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF48++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_12,Common FIFO Access Data Field 0 Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF4C++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_12,Common FIFO Access Data Field 1 Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF50++0x03
|
|
line.long 0x00 "RSCAN_CFID_13,Common FIFO Access ID Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF54++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_13,Common FIFO Access Pointer Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF58++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_13,Common FIFO Access Data Field 0 Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF5C++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_13,Common FIFO Access Data Field 1 Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF60++0x03
|
|
line.long 0x00 "RSCAN_CFID_14,Common FIFO Access ID Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF64++0x03
|
|
line.long 0x00 "RSCAN_CFPTR_14,Common FIFO Access Pointer Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF68++0x03
|
|
line.long 0x00 "RSCAN_CFDF0_14,Common FIFO Access Data Field 0 Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xF6C++0x03
|
|
line.long 0x00 "RSCAN_CFDF1_14,Common FIFO Access Data Field 1 Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "RSCAN_TMID_0,TX Message Buffer ID Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1004++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_0,TX Message Buffer Pointer Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_0,TX Message Buffer Data Field 0 Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x100C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_0,TX Message Buffer Data Field 1 Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1010++0x03
|
|
line.long 0x00 "RSCAN_TMID_1,TX Message Buffer ID Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1014++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_1,TX Message Buffer Pointer Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_1,TX Message Buffer Data Field 0 Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x101C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_1,TX Message Buffer Data Field 1 Register [1]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1020++0x03
|
|
line.long 0x00 "RSCAN_TMID_2,TX Message Buffer ID Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1024++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_2,TX Message Buffer Pointer Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_2,TX Message Buffer Data Field 0 Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x102C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_2,TX Message Buffer Data Field 1 Register [2]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1030++0x03
|
|
line.long 0x00 "RSCAN_TMID_3,TX Message Buffer ID Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1034++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_3,TX Message Buffer Pointer Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1038++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_3,TX Message Buffer Data Field 0 Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x103C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_3,TX Message Buffer Data Field 1 Register [3]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "RSCAN_TMID_4,TX Message Buffer ID Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1044++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_4,TX Message Buffer Pointer Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_4,TX Message Buffer Data Field 0 Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x104C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_4,TX Message Buffer Data Field 1 Register [4]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1050++0x03
|
|
line.long 0x00 "RSCAN_TMID_5,TX Message Buffer ID Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1054++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_5,TX Message Buffer Pointer Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1058++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_5,TX Message Buffer Data Field 0 Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x105C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_5,TX Message Buffer Data Field 1 Register [5]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1060++0x03
|
|
line.long 0x00 "RSCAN_TMID_6,TX Message Buffer ID Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1064++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_6,TX Message Buffer Pointer Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_6,TX Message Buffer Data Field 0 Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x106C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_6,TX Message Buffer Data Field 1 Register [6]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1070++0x03
|
|
line.long 0x00 "RSCAN_TMID_7,TX Message Buffer ID Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1074++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_7,TX Message Buffer Pointer Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1078++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_7,TX Message Buffer Data Field 0 Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x107C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_7,TX Message Buffer Data Field 1 Register [7]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "RSCAN_TMID_8,TX Message Buffer ID Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1084++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_8,TX Message Buffer Pointer Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_8,TX Message Buffer Data Field 0 Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x108C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_8,TX Message Buffer Data Field 1 Register [8]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1090++0x03
|
|
line.long 0x00 "RSCAN_TMID_9,TX Message Buffer ID Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1094++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_9,TX Message Buffer Pointer Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1098++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_9,TX Message Buffer Data Field 0 Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x109C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_9,TX Message Buffer Data Field 1 Register [9]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "RSCAN_TMID_10,TX Message Buffer ID Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10A4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_10,TX Message Buffer Pointer Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_10,TX Message Buffer Data Field 0 Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10AC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_10,TX Message Buffer Data Field 1 Register [10]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10B0++0x03
|
|
line.long 0x00 "RSCAN_TMID_11,TX Message Buffer ID Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10B4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_11,TX Message Buffer Pointer Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10B8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_11,TX Message Buffer Data Field 0 Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10BC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_11,TX Message Buffer Data Field 1 Register [11]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "RSCAN_TMID_12,TX Message Buffer ID Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10C4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_12,TX Message Buffer Pointer Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_12,TX Message Buffer Data Field 0 Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10CC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_12,TX Message Buffer Data Field 1 Register [12]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10D0++0x03
|
|
line.long 0x00 "RSCAN_TMID_13,TX Message Buffer ID Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10D4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_13,TX Message Buffer Pointer Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10D8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_13,TX Message Buffer Data Field 0 Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10DC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_13,TX Message Buffer Data Field 1 Register [13]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10E0++0x03
|
|
line.long 0x00 "RSCAN_TMID_14,TX Message Buffer ID Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10E4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_14,TX Message Buffer Pointer Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_14,TX Message Buffer Data Field 0 Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10EC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_14,TX Message Buffer Data Field 1 Register [14]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10F0++0x03
|
|
line.long 0x00 "RSCAN_TMID_15,TX Message Buffer ID Register [15]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10F4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_15,TX Message Buffer Pointer Register [15]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10F8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_15,TX Message Buffer Data Field 0 Register [15]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10FC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_15,TX Message Buffer Data Field 1 Register [15]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "RSCAN_TMID_16,TX Message Buffer ID Register [16]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1104++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_16,TX Message Buffer Pointer Register [16]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_16,TX Message Buffer Data Field 0 Register [16]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x110C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_16,TX Message Buffer Data Field 1 Register [16]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1110++0x03
|
|
line.long 0x00 "RSCAN_TMID_17,TX Message Buffer ID Register [17]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1114++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_17,TX Message Buffer Pointer Register [17]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1118++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_17,TX Message Buffer Data Field 0 Register [17]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x111C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_17,TX Message Buffer Data Field 1 Register [17]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1120++0x03
|
|
line.long 0x00 "RSCAN_TMID_18,TX Message Buffer ID Register [18]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1124++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_18,TX Message Buffer Pointer Register [18]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_18,TX Message Buffer Data Field 0 Register [18]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x112C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_18,TX Message Buffer Data Field 1 Register [18]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1130++0x03
|
|
line.long 0x00 "RSCAN_TMID_19,TX Message Buffer ID Register [19]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1134++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_19,TX Message Buffer Pointer Register [19]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1138++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_19,TX Message Buffer Data Field 0 Register [19]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x113C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_19,TX Message Buffer Data Field 1 Register [19]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1140++0x03
|
|
line.long 0x00 "RSCAN_TMID_20,TX Message Buffer ID Register [20]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1144++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_20,TX Message Buffer Pointer Register [20]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_20,TX Message Buffer Data Field 0 Register [20]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x114C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_20,TX Message Buffer Data Field 1 Register [20]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1150++0x03
|
|
line.long 0x00 "RSCAN_TMID_21,TX Message Buffer ID Register [21]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1154++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_21,TX Message Buffer Pointer Register [21]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1158++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_21,TX Message Buffer Data Field 0 Register [21]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x115C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_21,TX Message Buffer Data Field 1 Register [21]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1160++0x03
|
|
line.long 0x00 "RSCAN_TMID_22,TX Message Buffer ID Register [22]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1164++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_22,TX Message Buffer Pointer Register [22]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_22,TX Message Buffer Data Field 0 Register [22]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x116C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_22,TX Message Buffer Data Field 1 Register [22]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1170++0x03
|
|
line.long 0x00 "RSCAN_TMID_23,TX Message Buffer ID Register [23]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1174++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_23,TX Message Buffer Pointer Register [23]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1178++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_23,TX Message Buffer Data Field 0 Register [23]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x117C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_23,TX Message Buffer Data Field 1 Register [23]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1180++0x03
|
|
line.long 0x00 "RSCAN_TMID_24,TX Message Buffer ID Register [24]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1184++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_24,TX Message Buffer Pointer Register [24]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_24,TX Message Buffer Data Field 0 Register [24]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x118C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_24,TX Message Buffer Data Field 1 Register [24]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1190++0x03
|
|
line.long 0x00 "RSCAN_TMID_25,TX Message Buffer ID Register [25]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1194++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_25,TX Message Buffer Pointer Register [25]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1198++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_25,TX Message Buffer Data Field 0 Register [25]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x119C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_25,TX Message Buffer Data Field 1 Register [25]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11A0++0x03
|
|
line.long 0x00 "RSCAN_TMID_26,TX Message Buffer ID Register [26]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11A4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_26,TX Message Buffer Pointer Register [26]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_26,TX Message Buffer Data Field 0 Register [26]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11AC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_26,TX Message Buffer Data Field 1 Register [26]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11B0++0x03
|
|
line.long 0x00 "RSCAN_TMID_27,TX Message Buffer ID Register [27]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11B4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_27,TX Message Buffer Pointer Register [27]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11B8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_27,TX Message Buffer Data Field 0 Register [27]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11BC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_27,TX Message Buffer Data Field 1 Register [27]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11C0++0x03
|
|
line.long 0x00 "RSCAN_TMID_28,TX Message Buffer ID Register [28]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11C4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_28,TX Message Buffer Pointer Register [28]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_28,TX Message Buffer Data Field 0 Register [28]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11CC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_28,TX Message Buffer Data Field 1 Register [28]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11D0++0x03
|
|
line.long 0x00 "RSCAN_TMID_29,TX Message Buffer ID Register [29]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11D4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_29,TX Message Buffer Pointer Register [29]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11D8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_29,TX Message Buffer Data Field 0 Register [29]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11DC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_29,TX Message Buffer Data Field 1 Register [29]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11E0++0x03
|
|
line.long 0x00 "RSCAN_TMID_30,TX Message Buffer ID Register [30]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11E4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_30,TX Message Buffer Pointer Register [30]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_30,TX Message Buffer Data Field 0 Register [30]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11EC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_30,TX Message Buffer Data Field 1 Register [30]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11F0++0x03
|
|
line.long 0x00 "RSCAN_TMID_31,TX Message Buffer ID Register [31]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11F4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_31,TX Message Buffer Pointer Register [31]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11F8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_31,TX Message Buffer Data Field 0 Register [31]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x11FC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_31,TX Message Buffer Data Field 1 Register [31]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1200++0x03
|
|
line.long 0x00 "RSCAN_TMID_32,TX Message Buffer ID Register [32]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1204++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_32,TX Message Buffer Pointer Register [32]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1208++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_32,TX Message Buffer Data Field 0 Register [32]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x120C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_32,TX Message Buffer Data Field 1 Register [32]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1210++0x03
|
|
line.long 0x00 "RSCAN_TMID_33,TX Message Buffer ID Register [33]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1214++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_33,TX Message Buffer Pointer Register [33]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1218++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_33,TX Message Buffer Data Field 0 Register [33]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x121C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_33,TX Message Buffer Data Field 1 Register [33]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1220++0x03
|
|
line.long 0x00 "RSCAN_TMID_34,TX Message Buffer ID Register [34]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1224++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_34,TX Message Buffer Pointer Register [34]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1228++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_34,TX Message Buffer Data Field 0 Register [34]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x122C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_34,TX Message Buffer Data Field 1 Register [34]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1230++0x03
|
|
line.long 0x00 "RSCAN_TMID_35,TX Message Buffer ID Register [35]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1234++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_35,TX Message Buffer Pointer Register [35]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1238++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_35,TX Message Buffer Data Field 0 Register [35]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x123C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_35,TX Message Buffer Data Field 1 Register [35]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1240++0x03
|
|
line.long 0x00 "RSCAN_TMID_36,TX Message Buffer ID Register [36]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1244++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_36,TX Message Buffer Pointer Register [36]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1248++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_36,TX Message Buffer Data Field 0 Register [36]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x124C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_36,TX Message Buffer Data Field 1 Register [36]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1250++0x03
|
|
line.long 0x00 "RSCAN_TMID_37,TX Message Buffer ID Register [37]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1254++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_37,TX Message Buffer Pointer Register [37]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1258++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_37,TX Message Buffer Data Field 0 Register [37]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x125C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_37,TX Message Buffer Data Field 1 Register [37]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1260++0x03
|
|
line.long 0x00 "RSCAN_TMID_38,TX Message Buffer ID Register [38]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1264++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_38,TX Message Buffer Pointer Register [38]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1268++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_38,TX Message Buffer Data Field 0 Register [38]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x126C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_38,TX Message Buffer Data Field 1 Register [38]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1270++0x03
|
|
line.long 0x00 "RSCAN_TMID_39,TX Message Buffer ID Register [39]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1274++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_39,TX Message Buffer Pointer Register [39]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1278++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_39,TX Message Buffer Data Field 0 Register [39]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x127C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_39,TX Message Buffer Data Field 1 Register [39]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1280++0x03
|
|
line.long 0x00 "RSCAN_TMID_40,TX Message Buffer ID Register [40]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1284++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_40,TX Message Buffer Pointer Register [40]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1288++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_40,TX Message Buffer Data Field 0 Register [40]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x128C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_40,TX Message Buffer Data Field 1 Register [40]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1290++0x03
|
|
line.long 0x00 "RSCAN_TMID_41,TX Message Buffer ID Register [41]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1294++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_41,TX Message Buffer Pointer Register [41]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1298++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_41,TX Message Buffer Data Field 0 Register [41]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x129C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_41,TX Message Buffer Data Field 1 Register [41]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12A0++0x03
|
|
line.long 0x00 "RSCAN_TMID_42,TX Message Buffer ID Register [42]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12A4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_42,TX Message Buffer Pointer Register [42]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12A8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_42,TX Message Buffer Data Field 0 Register [42]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12AC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_42,TX Message Buffer Data Field 1 Register [42]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12B0++0x03
|
|
line.long 0x00 "RSCAN_TMID_43,TX Message Buffer ID Register [43]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12B4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_43,TX Message Buffer Pointer Register [43]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12B8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_43,TX Message Buffer Data Field 0 Register [43]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12BC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_43,TX Message Buffer Data Field 1 Register [43]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12C0++0x03
|
|
line.long 0x00 "RSCAN_TMID_44,TX Message Buffer ID Register [44]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12C4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_44,TX Message Buffer Pointer Register [44]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12C8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_44,TX Message Buffer Data Field 0 Register [44]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12CC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_44,TX Message Buffer Data Field 1 Register [44]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12D0++0x03
|
|
line.long 0x00 "RSCAN_TMID_45,TX Message Buffer ID Register [45]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12D4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_45,TX Message Buffer Pointer Register [45]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12D8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_45,TX Message Buffer Data Field 0 Register [45]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12DC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_45,TX Message Buffer Data Field 1 Register [45]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12E0++0x03
|
|
line.long 0x00 "RSCAN_TMID_46,TX Message Buffer ID Register [46]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12E4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_46,TX Message Buffer Pointer Register [46]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12E8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_46,TX Message Buffer Data Field 0 Register [46]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12EC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_46,TX Message Buffer Data Field 1 Register [46]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12F0++0x03
|
|
line.long 0x00 "RSCAN_TMID_47,TX Message Buffer ID Register [47]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12F4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_47,TX Message Buffer Pointer Register [47]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12F8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_47,TX Message Buffer Data Field 0 Register [47]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12FC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_47,TX Message Buffer Data Field 1 Register [47]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1300++0x03
|
|
line.long 0x00 "RSCAN_TMID_48,TX Message Buffer ID Register [48]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1304++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_48,TX Message Buffer Pointer Register [48]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1308++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_48,TX Message Buffer Data Field 0 Register [48]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x130C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_48,TX Message Buffer Data Field 1 Register [48]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1310++0x03
|
|
line.long 0x00 "RSCAN_TMID_49,TX Message Buffer ID Register [49]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1314++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_49,TX Message Buffer Pointer Register [49]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1318++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_49,TX Message Buffer Data Field 0 Register [49]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x131C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_49,TX Message Buffer Data Field 1 Register [49]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1320++0x03
|
|
line.long 0x00 "RSCAN_TMID_50,TX Message Buffer ID Register [50]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1324++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_50,TX Message Buffer Pointer Register [50]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1328++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_50,TX Message Buffer Data Field 0 Register [50]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x132C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_50,TX Message Buffer Data Field 1 Register [50]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1330++0x03
|
|
line.long 0x00 "RSCAN_TMID_51,TX Message Buffer ID Register [51]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1334++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_51,TX Message Buffer Pointer Register [51]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1338++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_51,TX Message Buffer Data Field 0 Register [51]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x133C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_51,TX Message Buffer Data Field 1 Register [51]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1340++0x03
|
|
line.long 0x00 "RSCAN_TMID_52,TX Message Buffer ID Register [52]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1344++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_52,TX Message Buffer Pointer Register [52]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1348++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_52,TX Message Buffer Data Field 0 Register [52]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x134C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_52,TX Message Buffer Data Field 1 Register [52]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1350++0x03
|
|
line.long 0x00 "RSCAN_TMID_53,TX Message Buffer ID Register [53]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1354++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_53,TX Message Buffer Pointer Register [53]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1358++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_53,TX Message Buffer Data Field 0 Register [53]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x135C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_53,TX Message Buffer Data Field 1 Register [53]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1360++0x03
|
|
line.long 0x00 "RSCAN_TMID_54,TX Message Buffer ID Register [54]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1364++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_54,TX Message Buffer Pointer Register [54]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1368++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_54,TX Message Buffer Data Field 0 Register [54]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x136C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_54,TX Message Buffer Data Field 1 Register [54]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1370++0x03
|
|
line.long 0x00 "RSCAN_TMID_55,TX Message Buffer ID Register [55]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1374++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_55,TX Message Buffer Pointer Register [55]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1378++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_55,TX Message Buffer Data Field 0 Register [55]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x137C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_55,TX Message Buffer Data Field 1 Register [55]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1380++0x03
|
|
line.long 0x00 "RSCAN_TMID_56,TX Message Buffer ID Register [56]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1384++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_56,TX Message Buffer Pointer Register [56]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1388++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_56,TX Message Buffer Data Field 0 Register [56]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x138C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_56,TX Message Buffer Data Field 1 Register [56]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1390++0x03
|
|
line.long 0x00 "RSCAN_TMID_57,TX Message Buffer ID Register [57]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1394++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_57,TX Message Buffer Pointer Register [57]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1398++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_57,TX Message Buffer Data Field 0 Register [57]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x139C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_57,TX Message Buffer Data Field 1 Register [57]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13A0++0x03
|
|
line.long 0x00 "RSCAN_TMID_58,TX Message Buffer ID Register [58]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13A4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_58,TX Message Buffer Pointer Register [58]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13A8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_58,TX Message Buffer Data Field 0 Register [58]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13AC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_58,TX Message Buffer Data Field 1 Register [58]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13B0++0x03
|
|
line.long 0x00 "RSCAN_TMID_59,TX Message Buffer ID Register [59]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13B4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_59,TX Message Buffer Pointer Register [59]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13B8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_59,TX Message Buffer Data Field 0 Register [59]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13BC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_59,TX Message Buffer Data Field 1 Register [59]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13C0++0x03
|
|
line.long 0x00 "RSCAN_TMID_60,TX Message Buffer ID Register [60]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13C4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_60,TX Message Buffer Pointer Register [60]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13C8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_60,TX Message Buffer Data Field 0 Register [60]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13CC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_60,TX Message Buffer Data Field 1 Register [60]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13D0++0x03
|
|
line.long 0x00 "RSCAN_TMID_61,TX Message Buffer ID Register [61]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13D4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_61,TX Message Buffer Pointer Register [61]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13D8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_61,TX Message Buffer Data Field 0 Register [61]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13DC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_61,TX Message Buffer Data Field 1 Register [61]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13E0++0x03
|
|
line.long 0x00 "RSCAN_TMID_62,TX Message Buffer ID Register [62]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13E4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_62,TX Message Buffer Pointer Register [62]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13E8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_62,TX Message Buffer Data Field 0 Register [62]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13EC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_62,TX Message Buffer Data Field 1 Register [62]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13F0++0x03
|
|
line.long 0x00 "RSCAN_TMID_63,TX Message Buffer ID Register [63]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13F4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_63,TX Message Buffer Pointer Register [63]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13F8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_63,TX Message Buffer Data Field 0 Register [63]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x13FC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_63,TX Message Buffer Data Field 1 Register [63]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1400++0x03
|
|
line.long 0x00 "RSCAN_TMID_64,TX Message Buffer ID Register [64]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1404++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_64,TX Message Buffer Pointer Register [64]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1408++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_64,TX Message Buffer Data Field 0 Register [64]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x140C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_64,TX Message Buffer Data Field 1 Register [64]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1410++0x03
|
|
line.long 0x00 "RSCAN_TMID_65,TX Message Buffer ID Register [65]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1414++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_65,TX Message Buffer Pointer Register [65]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1418++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_65,TX Message Buffer Data Field 0 Register [65]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x141C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_65,TX Message Buffer Data Field 1 Register [65]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1420++0x03
|
|
line.long 0x00 "RSCAN_TMID_66,TX Message Buffer ID Register [66]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1424++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_66,TX Message Buffer Pointer Register [66]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1428++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_66,TX Message Buffer Data Field 0 Register [66]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x142C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_66,TX Message Buffer Data Field 1 Register [66]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1430++0x03
|
|
line.long 0x00 "RSCAN_TMID_67,TX Message Buffer ID Register [67]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1434++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_67,TX Message Buffer Pointer Register [67]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1438++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_67,TX Message Buffer Data Field 0 Register [67]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x143C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_67,TX Message Buffer Data Field 1 Register [67]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1440++0x03
|
|
line.long 0x00 "RSCAN_TMID_68,TX Message Buffer ID Register [68]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1444++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_68,TX Message Buffer Pointer Register [68]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1448++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_68,TX Message Buffer Data Field 0 Register [68]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x144C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_68,TX Message Buffer Data Field 1 Register [68]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1450++0x03
|
|
line.long 0x00 "RSCAN_TMID_69,TX Message Buffer ID Register [69]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1454++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_69,TX Message Buffer Pointer Register [69]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1458++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_69,TX Message Buffer Data Field 0 Register [69]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x145C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_69,TX Message Buffer Data Field 1 Register [69]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1460++0x03
|
|
line.long 0x00 "RSCAN_TMID_70,TX Message Buffer ID Register [70]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1464++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_70,TX Message Buffer Pointer Register [70]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1468++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_70,TX Message Buffer Data Field 0 Register [70]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x146C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_70,TX Message Buffer Data Field 1 Register [70]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1470++0x03
|
|
line.long 0x00 "RSCAN_TMID_71,TX Message Buffer ID Register [71]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1474++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_71,TX Message Buffer Pointer Register [71]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1478++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_71,TX Message Buffer Data Field 0 Register [71]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x147C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_71,TX Message Buffer Data Field 1 Register [71]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1480++0x03
|
|
line.long 0x00 "RSCAN_TMID_72,TX Message Buffer ID Register [72]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1484++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_72,TX Message Buffer Pointer Register [72]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1488++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_72,TX Message Buffer Data Field 0 Register [72]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x148C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_72,TX Message Buffer Data Field 1 Register [72]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1490++0x03
|
|
line.long 0x00 "RSCAN_TMID_73,TX Message Buffer ID Register [73]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1494++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_73,TX Message Buffer Pointer Register [73]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x1498++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_73,TX Message Buffer Data Field 0 Register [73]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x149C++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_73,TX Message Buffer Data Field 1 Register [73]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14A0++0x03
|
|
line.long 0x00 "RSCAN_TMID_74,TX Message Buffer ID Register [74]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14A4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_74,TX Message Buffer Pointer Register [74]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14A8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_74,TX Message Buffer Data Field 0 Register [74]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14AC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_74,TX Message Buffer Data Field 1 Register [74]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14B0++0x03
|
|
line.long 0x00 "RSCAN_TMID_75,TX Message Buffer ID Register [75]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14B4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_75,TX Message Buffer Pointer Register [75]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14B8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_75,TX Message Buffer Data Field 0 Register [75]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14BC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_75,TX Message Buffer Data Field 1 Register [75]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14C0++0x03
|
|
line.long 0x00 "RSCAN_TMID_76,TX Message Buffer ID Register [76]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14C4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_76,TX Message Buffer Pointer Register [76]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14C8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_76,TX Message Buffer Data Field 0 Register [76]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14CC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_76,TX Message Buffer Data Field 1 Register [76]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14D0++0x03
|
|
line.long 0x00 "RSCAN_TMID_77,TX Message Buffer ID Register [77]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14D4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_77,TX Message Buffer Pointer Register [77]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14D8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_77,TX Message Buffer Data Field 0 Register [77]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14DC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_77,TX Message Buffer Data Field 1 Register [77]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14E0++0x03
|
|
line.long 0x00 "RSCAN_TMID_78,TX Message Buffer ID Register [78]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14E4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_78,TX Message Buffer Pointer Register [78]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14E8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_78,TX Message Buffer Data Field 0 Register [78]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14EC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_78,TX Message Buffer Data Field 1 Register [78]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14F0++0x03
|
|
line.long 0x00 "RSCAN_TMID_79,TX Message Buffer ID Register [79]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14F4++0x03
|
|
line.long 0x00 "RSCAN_TMPTR_79,TX Message Buffer Pointer Register [79]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14F8++0x03
|
|
line.long 0x00 "RSCAN_TMDF0_79,TX Message Buffer Data Field 0 Register [79]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x14FC++0x03
|
|
line.long 0x00 "RSCAN_TMDF1_79,TX Message Buffer Data Field 1 Register [79]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
rgroup.long ($2+0x1800)++0x03
|
|
line.long 0x00 "RSCAN_THLACC$1,TX History List Access Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1900)++0x03
|
|
line.long 0x00 "RSCAN_RPGACC_$1,RAM Test Page Access Register [0]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1940)++0x03
|
|
line.long 0x00 "RSCAN_RPGACC_$1,RAM Test Page Access Register [16]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1980)++0x03
|
|
line.long 0x00 "RSCAN_RPGACC_$1,RAM Test Page Access Register [32]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x19C0)++0x03
|
|
line.long 0x00 "RSCAN_RPGACC_$1,RAM Test Page Access Register [48]"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
tree.end
|
|
tree "SSP"
|
|
repeat 2. (list 0. 1.) (list ad:0xF8034000 ad:0xF8035000)
|
|
tree "SSP$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSP_SSPCR0,SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimCell SSP"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SCR,The value SCR is used to generate the transmit and receive bit rate of the PrimCell SSP"
|
|
newline
|
|
bitfld.long 0x00 7. "SPH,SSPCLKOUT phase (applicable to Motorola SPI frame format only)" "0,1"
|
|
bitfld.long 0x00 6. "SPO,SSPCLKOUT polarity (applicable to Motorola SPI frame format only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "FRF,Frame format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "DSS,Data size select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP_SSPCR1,SSPCR1 is the control register 1 and contains four different bit fields which control various functions within the PrimCell SSP"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 4.--15. 1. "Reserved,Reserved read unpredictable should be written as 0"
|
|
newline
|
|
bitfld.long 0x00 3. "SOD,Slave-mode output disable" "0,1"
|
|
bitfld.long 0x00 2. "MS,Master or Slave mode select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SSE,Synchronous serial port enable" "0,1"
|
|
bitfld.long 0x00 0. "LBM,Loop back mode" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSP_SSPDR,When SSPDR is read the entry in the receive FIFO (pointed to by the current FIFO read pointer) is accessed"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "DATA,Transmir/Receive FIFO: Read=Receive FIFO Write=Transmit FIFO"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSP_SSPSR,SSPSR is status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 5.--15. 1. "Reserved,Reserved read unpredictable should be written as 0"
|
|
newline
|
|
bitfld.long 0x00 4. "BSY,PrimeCell SSP busy flag" "0,1"
|
|
bitfld.long 0x00 3. "RFF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RNE,Receive FIFO not empty" "0,1"
|
|
bitfld.long 0x00 1. "TNF,Transmit FIFO not full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TFE,Transmit FIFO empty" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SSP_SSPCPSR,SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally before further use"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read unpredictable must be written as 0"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CPDSDVSR,Clock prescale divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SSP_SSPIMSC,The SSPIMSC register is the interrupt mask set or clear register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 4.--15. 1. "Reserved,Reserved read as zero do not modify"
|
|
newline
|
|
bitfld.long 0x00 3. "TXIM,Transmit FIFO interrupt mask" "0,1"
|
|
bitfld.long 0x00 2. "RXIM,Receive FIFO interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RTIM,Receive timeout interrupt mask" "0,1"
|
|
bitfld.long 0x00 0. "RORIM,Receive overrun interrupt mask" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SSP_SSPRIS,The SSPRIS register is the raw interrupt status register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 4.--15. 1. "Reserved,Reserced read as zero do not modify"
|
|
newline
|
|
bitfld.long 0x00 3. "TXRIS,Gives the raw interrupt state (prior to masking) of the SSPTXINTR interrupt" "0,1"
|
|
bitfld.long 0x00 2. "RXRIS,Gives the raw interrupt state (prior to masking) of the SSPRXINTR interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RTRIS,Gives the raw interrupt state (prior to masking) of the SSPRTINTR interrupt" "0,1"
|
|
bitfld.long 0x00 0. "RORRIS,Gives the raw interrupt state (prior to masking) of the SSPRORINTR interrupt" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SSP_SSPMIS,The SSPMIS register is the masked interrupt status register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 4.--15. 1. "Reserved,Reserced read as zero do not modify"
|
|
newline
|
|
bitfld.long 0x00 3. "TXMIS,Gives the transmit FIFO masked interrupt state (after masking) of the SSPTXINTR interrupt" "0,1"
|
|
bitfld.long 0x00 2. "RXMIS,Gives the transmit FIFO masked interrupt state (after masking) of the SSPRXINTR interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RTMIS,Gives the transmit FIFO masked interrupt state (after masking) of the SSPRTINTR interrupt" "0,1"
|
|
bitfld.long 0x00 0. "RORMIS,Gives the transmit FIFO masked interrupt state (after masking) of the SSPRORINTR interrupt" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSP_SSPICR,The SSPICR register is the interrupt clear register and is write-only"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 2.--15. 1. "Reserved,Reserved read as zero do not modify"
|
|
newline
|
|
bitfld.long 0x00 1. "RTIC,Clears the SSPRTINTR interrupt" "0,1"
|
|
bitfld.long 0x00 0. "RORIC,Clears the SSPRORINTR interrupt" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SSP_SSPDMACR,The SSPDMACR register is the DMA control register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 2.--15. 1. "Reserved,Reserved read aszero do not modify"
|
|
newline
|
|
bitfld.long 0x00 1. "TXDMAE,Transmit DMA Enable" "0,1"
|
|
bitfld.long 0x00 0. "RXDMAE,Receive DMA Enable" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SSP_SSPTCR,SSPTCR is the test control register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 2.--15. 1. "Reserved,Reserved unpredictable when"
|
|
newline
|
|
bitfld.long 0x00 1. "TESTFIFO,Test FIFO enable" "0,1"
|
|
bitfld.long 0x00 0. "ITEN,Integration test enable" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "SSP_SSPITIP,In integration test mode it allows inputs to be both written to and read from"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 5.--15. 1. "Reserved,Reserved unpredictable when"
|
|
newline
|
|
bitfld.long 0x00 4. "SSPTXDMACLR,Writes to this bit specify the value to be driven on the intra-chip input SSPTXDMACLR in the integration test mode" "0,1"
|
|
bitfld.long 0x00 3. "SSPRXDMACLR,Writes to this bit specify the value to be driven on the intra-chip input SSPRXDMACLR in the integration test mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SSPCLKIN,Reads return the value of the SSPCLKIN primary input" "0,1"
|
|
bitfld.long 0x00 1. "SSPFSSIN,Reads return the value of the SSPFSSIN primary input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SSPRXD,Reads return the value of the SSPRXD primary input" "0,1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "SSP_SSPITOP,The primary outputs are hard-coded and the intra-chip outputs are read/"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 13. "SSPTXDMASREQ,Intra-chip output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "SSPTXDMABREQ,Intra-chip output" "0,1"
|
|
bitfld.long 0x00 11. "SSPRXDMASREQ,Intra-chip output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "SSPRXDMABREQ,Intra-chip output" "0,1"
|
|
bitfld.long 0x00 9. "SSPINTR,Intra-chip output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "SSPTXINTR,Intra-chip output" "0,1"
|
|
bitfld.long 0x00 7. "SSPRXINTR,Intra-chip output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SSPRTINTR,Intra-chip output" "0,1"
|
|
bitfld.long 0x00 5. "SSPRORINTR,Intra-chip output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "nSSPCTLOE,Primary output" "0,1"
|
|
bitfld.long 0x00 3. "nSSPOE,Primary output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SSPCLKOUT,Primary output" "0,1"
|
|
bitfld.long 0x00 1. "SSPFSSOUT,Primary output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SSPTXD,Primary output" "0,1"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SSP_SSPTDR,It allows data to be written into the receive FIFO and read out from the transmit FIFO for test purposes"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "DATA,When the TESTFIFO signal is asserted data is written into the receive FIFO and out of the transmit FIFO"
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "SSP_SSPPeriphID0,The SSPPeriphID0 register is hard-coded and the fields within the register determine the reset value"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zero"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "PartNumber0,This is used to identify the peripheral"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "SSP_SSPPeriphID1,The SSPPeriphID1 register is hard-coded and the fields within the register determine the reset value"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zero"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "Designer0,This is the identification of the designer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PartNumber1,This is used to identify the peripheral" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "SSP_SSPPeriphID2,The SSPPeriphID2 register is hard-coded and the fields within the register determine the reset value"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zero"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "Revision,This is the revision number of the peripherial" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "Designer1,This is the identification of the designer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "SSP_SSPPeriphID3,The SSPPeriphID3 register is hard-coded and the fields within the register determine the reset value"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zero"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "Configuration,This is the configuration option of the peripherial"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "SSP_SSPPCellID0,The SSPPCellID0 register is hard-coded and the fields within the register determine the reset value"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zero"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "SSPPCellID0,These bits read back as 0x0D"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "SSP_SSPPCellID1,The SSPPCellID1 register is hard-coded and the fields within the register determine the reset value"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zero"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "SSPPCellID1,These bits read back as 0xF0"
|
|
rgroup.long 0xFF8++0x03
|
|
line.long 0x00 "SSP_SSPPCellID2,The SSPPCellID2 register is hard-coded and the fields within the register determine the reset value"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zero"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "SSPPCellID2,These bits read back as 0x05"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "SSP_SSPPCellID3,The SSPPCellID3 register is hard-coded and the fields within the register determine the reset value"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zero"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "SSPPCellID3,These bits read back as 0xB1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "RAP_UART"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0xF8036000 ad:0xF8037000 ad:0xF8038000 ad:0xF8039000)
|
|
tree "RAP_UART$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RAP_UART_UARTDR,Data read or written from the interface"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 11. "OE,Overrun error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "BE,Break error" "0,1"
|
|
bitfld.long 0x00 9. "PE,Parity error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "FE,Framing error" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive (read) data character"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RAP_UART_UARTRSR,Receive Status Register UARTRSR (Read) / Error Clear Register UARTECR (Write)"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 4.--15. 1. "Reserved,Reserved unpredictable when"
|
|
newline
|
|
bitfld.long 0x00 3. "OE,Overrun error" "0,1"
|
|
bitfld.long 0x00 2. "BE,Break error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Parity error" "0,1"
|
|
bitfld.long 0x00 0. "FE,Framing error" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RAP_UART_UARTFR,Flag register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 9.--15. 1. "Reserved,Reserved read as zero do not modify"
|
|
newline
|
|
bitfld.long 0x00 8. "RI,Ring indicator" "0,1"
|
|
bitfld.long 0x00 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RXFF,Receive FIFO full" "0,1"
|
|
bitfld.long 0x00 5. "TXFF,Transmit FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RXFE,Receive FIFO empty" "0,1"
|
|
bitfld.long 0x00 3. "BUSY,UART busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCD,Data carrier detect" "0,1"
|
|
bitfld.long 0x00 1. "DSR,Data set ready" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CTS,Clear to send" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RAP_UART_UARTILPR,IrDA low power counter register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read as zero do not modify"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "ILPDVSR,8-bit low-power divisor value"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RAP_UART_UARTIBRD,Integer baud rate divisor register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "BAUDDIVINT,The integer baud rate divisor"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RAP_UART_UARTFBRD,Fractional baud rate divisor register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 6.--15. 1. "Reserved,Reserved read as zero do not modify"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "BAUDDIVFRAC,The fractional baud rate divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RAP_UART_UARTLCR_H,Line control register HIGH byte"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read as zero do not modify"
|
|
newline
|
|
bitfld.long 0x00 7. "SPS,Stick parity select" "0: stick parity is disabled,1: if the EPS bit is 1 then the parity bit is"
|
|
bitfld.long 0x00 5.--6. "WLEN,Word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
|
|
newline
|
|
bitfld.long 0x00 4. "FEN,Enable FIFOs" "0: FIFOs are disabled (character mode) that is the,1: transmit and receive FIFO buffers are enabled"
|
|
bitfld.long 0x00 3. "STP2,Two stop bits select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "EPS,Even parity select" "0: odd parity,1: even parity"
|
|
bitfld.long 0x00 1. "PEN,Parity enable" "0: parity is disabled and no parity bit added to,1: parity checking and generation is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "BRK,Send break" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RAP_UART_UARTCR,Control register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "CTSEn,CTS hardware flow control enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "RTSEn,RTS hardware flow control enable" "0,1"
|
|
bitfld.long 0x00 13. "Out2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "Out1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output" "0,1"
|
|
bitfld.long 0x00 11. "RTS,Request to send" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "DTR,Data transmit ready" "0,1"
|
|
bitfld.long 0x00 9. "RXE,Receive enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "TXE,Transmit enable" "0,1"
|
|
bitfld.long 0x00 7. "LBE,Loopback enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--6. "Reserved,Reserved read as zero do not modify" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2. "SIRLP,SIR low-power IrDA mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SIREN,SIR enable" "0: IrDA SIR ENDEC is disabled,1: IrDA SIR ENDEC is enabled"
|
|
bitfld.long 0x00 0. "UARTEN,UART enable" "0: UART is disabled,1: the UART is enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "RAP_UART_UARTIFLS,Interrupt FIFO level select register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 6.--15. 1. "Reserved,Reserved read as zero do not modify"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "RXIFLSEL,Receive interrupt FIFO level select" "0: Receive FIFO becomes,1: Receive FIFO becomes,2: Receive FIFO becomes,3: Receive FIFO becomes,4: Receive FIFO becomes,?..."
|
|
bitfld.long 0x00 0.--2. "TXIFLSEL,Transmit interrupt FIFO level select" "0: Transmit FIFO becomes,1: Transmit FIFO becomes,2: Transmit FIFO becomes,3: Transmit FIFO becomes,4: Transmit FIFO becomes,?..."
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "RAP_UART_UARTIMSC,Interrupt mask set/clear"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 11.--15. "Reserved,Reserved read as zero do not modify" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "OEIM,Overrun error interrupt mask" "0,1"
|
|
bitfld.long 0x00 9. "BEIM,Break error interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PEIM,Parity error interrupt mask" "0,1"
|
|
bitfld.long 0x00 7. "FEIM,Framing error interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTIM,Receive timeout interrupt mask" "0,1"
|
|
bitfld.long 0x00 5. "TXIM,Transmit interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RXIM,Receive interrupt mask" "0,1"
|
|
bitfld.long 0x00 3. "DSRMIM,nUARTDSR modem interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDMIM,nUARTDCD modem interrupt mask" "0,1"
|
|
bitfld.long 0x00 1. "CTSMIM,nUARTCTS modem interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RIMIN,nUARTRI modem interrupt mask" "0,1"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "RAP_UART_UARTRIS,Raw interrupt status"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 11.--15. "Reserved,Reserved read as zero do not modify" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "OERIS,Overrun error interrupt status" "0,1"
|
|
bitfld.long 0x00 9. "BERIS,Break error interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PERIS,Parity error interrupt status" "0,1"
|
|
bitfld.long 0x00 7. "FERIS,Framing error interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTRIS,Receive timeout interrupt status" "0,1"
|
|
bitfld.long 0x00 5. "TXRIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RXRIS,Receive interrupt status" "0,1"
|
|
bitfld.long 0x00 3. "DSRRMIS,nUARTDSR modem interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDRMIS,nUARTDCD modem interrupt status" "0,1"
|
|
bitfld.long 0x00 1. "CTSRMIS,nUARTCTS modem interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RIRMIS,nUARTRI modem interrupt status" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "RAP_UART_UARTMIS,Masked interrupt status"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 11.--15. "Reserved,Reserved read as zero do not modify" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "OEMIS,Overrun error masked interrupt status" "0,1"
|
|
bitfld.long 0x00 9. "BEMIS,Break error masked interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PEMIS,Parity error masked interrupt status" "0,1"
|
|
bitfld.long 0x00 7. "FEMIS,Framing error masked interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTMIS,Receive timeout masked interrupt status" "0,1"
|
|
bitfld.long 0x00 5. "TXMIS,Transmit masked interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RXMIS,Receive masked interrupt status" "0,1"
|
|
bitfld.long 0x00 3. "DSRMMIS,nUARTDSR modem masked interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDMMIS,nUARTDCD modem masked interrupt status" "0,1"
|
|
bitfld.long 0x00 1. "CTSMMIS,nUARTCTS modem masked interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RIMMIS,nUARTRI modem masked interrupt status" "0,1"
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "RAP_UART_UARTICR,Interrupt clear register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 11.--15. "Reserved,Reserved read as zero do not modify" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "OEIC,Overrun error interrupt clear" "0,1"
|
|
bitfld.long 0x00 9. "BEIC,Break error interrupt clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PEIC,Parity error interrupt clear" "0,1"
|
|
bitfld.long 0x00 7. "FEIC,Framing error interrupt clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTIC,Receive timeout interrupt clear" "0,1"
|
|
bitfld.long 0x00 5. "TXIC,Transmit interrupt clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RXIC,Receive interrupt clear" "0,1"
|
|
bitfld.long 0x00 3. "DSRMIC,nUARTDSR modem interrupt clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDMIC,nUARTDCD modem interrupt clear" "0,1"
|
|
bitfld.long 0x00 1. "CTSMIC,nUARTCTS modem interrupt clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RIMIC,nUARTRI modem interrupt clear" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RAP_UART_UARTDMACR,DMA control register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 3.--15. 1. "Reserved,Reserved read as zero do not modify"
|
|
newline
|
|
bitfld.long 0x00 2. "DMAONERR,DMA on error" "0,1"
|
|
bitfld.long 0x00 1. "TXDMAE,Transmit DMA enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RXDMAE,Receive DMA enable" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RAP_UART_UARTTCR,Test Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 3.--15. 1. "Reserved,Reserved unpredictable when"
|
|
newline
|
|
bitfld.long 0x00 2. "SIRTEST,SIR test enable" "0,1"
|
|
bitfld.long 0x00 1. "TESTFIFO,Test FIFO enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ITEN,Integration test enable" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RAP_UART_UARTITIP,Integration test input read/set register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved unpredictable when"
|
|
newline
|
|
bitfld.long 0x00 7. "UARTTXDMACLR,Writes to this bit specify the value to be driven on the intra-chip input UARTTXDMACLR in the integration test mode" "0,1"
|
|
bitfld.long 0x00 6. "UARTRXDMACLR,Writes to this bit specify the value to be driven on the intra-chip input UARTRXDMACLR in the integration test mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "nUARTRI,Reads return the value of the nUARTRI primary input" "0,1"
|
|
bitfld.long 0x00 4. "nUARTDCD,Reads return the value of the nUARTDCD primary input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "nUARTCTS,Reads return the value of the nUARTCTS primary input" "0,1"
|
|
bitfld.long 0x00 2. "nUARTDSR,Reads return the value of the nUARTDSR primary input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SIRIN,Reads return the value of the SIRIN primary input" "0,1"
|
|
bitfld.long 0x00 0. "UARTRXD,Reads return the value of the UARTRXD primary input" "0,1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RAP_UART_UARTITOP,Integration test output read/set register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "UARTTXDMASREQ,Intra-chip output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "UARTTXDMABREQ,Intra-chip output" "0,1"
|
|
bitfld.long 0x00 13. "UARTRXDMASREQ,Intra-chip output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "UARTDMABREQ,Intra-chip output" "0,1"
|
|
bitfld.long 0x00 11. "UARTMSINTR,Intra-chip output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "UARTRXINTR,Intra-chip output" "0,1"
|
|
bitfld.long 0x00 9. "UARTTXINTR,Intra-chip output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "UARTRTINTR,Intra-chip output" "0,1"
|
|
bitfld.long 0x00 7. "UARTEINTR,Intra-chip output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "UARTINTR,Intra-chip output" "0,1"
|
|
bitfld.long 0x00 5. "nUARTOut2,Primary output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "nUARTOut1,Primary output" "0,1"
|
|
bitfld.long 0x00 3. "nUARTRTS,Primary output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "nUARTDTR,Primary output" "0,1"
|
|
bitfld.long 0x00 1. "nSIROUT,Primary output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UARTTXD,Primary output" "0,1"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "RAP_UART_UARTTDR,Test data register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 11.--15. "Reserved,Reserved unpredictable when" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "DATA,When the TESTFIFO bit is set to 1 data is written into the receive FIFO and read out of the transmit FIFO"
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "RAP_UART_UARTPeriphID0,Peripheral Identification register bits 7:0"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zeros"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "PartNumber0,These bits read back as 0x11"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "RAP_UART_UARTPeriphID1,Peripheral Identification register bits 15:8"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zeros"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "Designer0,These bits read back as 0x1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PartNumber1,These bits read back as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "RAP_UART_UARTPeriphID2,Peripheral Identification register bits 23:16"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zeros"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "Revision,This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "Designer1,These bits read back as 0x4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "RAP_UART_UARTPeriphID3,Peripheral Identification register bits 31:24"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zeros"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "Configuration,These bits read back as 0x00"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "RAP_UART_UARTPcellID0,PrimeCell identification register bits 7:0"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zeros"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "UARTPCellID0,These bits read back as 0x0D"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "RAP_UART_UARTPcellID1,PrimeCell identification register bits 15:8"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zeros"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "UARTPcellID1,These bits read back as 0xF0"
|
|
rgroup.long 0xFF8++0x03
|
|
line.long 0x00 "RAP_UART_UARTPcellID2,PrimeCell identification register bits 23:16"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zeros"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "UARTPcellID2,These bits read back as 0x05"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "RAP_UART_UARTPcellID3,PrimeCell identification register bits 31:24"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved,Reserved read undefined must read as zeros"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "UARTPcellID3,These bits read back as 0xB1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SDIO"
|
|
base ad:0xF803A000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SDIO_SD_CMD,Command type regsiter"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 14.--15. "MD_MLT_BLK,Bit" "0: MD6 bit Bit,1: Multiple block transfer,?..."
|
|
newline
|
|
bitfld.long 0x00 13. "MD5,MD5 bit" "0,1"
|
|
bitfld.long 0x00 12. "MD4,MD4 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "MD3,MD3 bit" "0,1"
|
|
bitfld.long 0x00 8.--10. "MD_RSP,Bit" "0: MD0 bit Bit,1: MD1 bit Bit,2: MD1 bit,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "C,Bit" "0: C bit0 Bit,1: C1 bit,?..."
|
|
bitfld.long 0x00 0.--5. "CF,Bit" "0: CF40 bit Bit,1: CF41 bit Bit,2: CF42 bit Bit,3: CF43 bit Bit,4: CF44 bit Bit,5: CF45 bit,?..."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SDIO_SD_PORTSEL,SD port select regsiter"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 9. "NP1,Number of Ports" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "NP0,Port Sel 0 bit" "0,1"
|
|
bitfld.long 0x00 2.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 1. "SD_PORTSEL1,SD_PORTSEL bit1" "0,1"
|
|
bitfld.long 0x00 0. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SDIO_SD_ARG0,SD command argument register"
|
|
hexmask.long 0x00 0.--31. 1. "CF,Set command format[39:8]"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SDIO_SD_ARG1,SD command argument register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "CF,Set command format[39:24]"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SDIO_SD_STOP,Data stop register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "SEC,Stop Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "STP,SD_STOP bit0" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SDIO_SD_SECCNT,Block count register"
|
|
abitfld.long 0x00 0.--31. "CNT,Bit" "0x00000000=0: Count 0 Bit,0x00000001=1: CNT1 Bit,0x00000002=2: CNT2 Bit,0x00000003=3: CNT3 Bit,0x00000004=4: CNT4 Bit,0x00000005=5: CNT5 Bit,0x00000006=6: CNT6 Bit,0x00000007=7: CNT7 Bit,0x00000008=8: CNT8 Bit,0x00000009=9: CNT9 Bit,0x0000000A=10: Count 10 Bit,0x0000000B=11: CNT11 Bit,0x0000000C=12: CNT12 Bit,0x0000000D=13: CNT13 Bit,0x0000000E=14: CNT14 Bit,0x0000000F=15: CNT15 Bit,0x00000010=16: CNT16 Bit,0x00000011=17: CNT17 Bit,0x00000012=18: CNT18 Bit,0x00000013=19: CNT19 Bit,0x00000014=20: Count20 Bit,0x00000015=21: CNT21 Bit,0x00000016=22: CNT22 Bit,0x00000017=23: CNT23 Bit,0x00000018=24: CNT24 Bit,0x00000019=25: CNT25 Bit,0x0000001A=26: CNT26 Bit,0x0000001B=27: CNT27 Bit,0x0000001C=28: CNT28 Bit,0x0000001D=29: CNT29 Bit,0x0000001E=30: CNT30 Bit,0x0000001F=31: CNT31"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SDIO_SD_RSP10,SD card response register"
|
|
hexmask.long 0x00 0.--31. 1. "SD_RSP,Response from SD card [R39 to R8]"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SDIO_SD_RSP1,SD card response register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "SD_RSP,Response from SD card [R39 to R24]"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SDIO_SD_RSP32,SD card response register"
|
|
hexmask.long 0x00 0.--31. 1. "SD_RSP,Response from SD card [R71 to R40]"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SDIO_SD_RSP3,SD card response register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "SD_RSP,Response from SD card [R71 to R56]"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SDIO_SD_RSP54,SD card response register"
|
|
hexmask.long 0x00 0.--31. 1. "SD_RSP,Response from SD card [R103 to R72]"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SDIO_SD_RSP5,SD card response register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "SD_RSP,Response from SD card [R103 to R88]"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SDIO_SD_RSP76,SD card response register"
|
|
hexmask.long 0x00 0.--31. 1. "SD_RSP,Response from SD card [R127 to R104]"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SDIO_SD_RSP7,SD card response register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "SD_RSP,Response from SD card [R127 to R120]"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SDIO_SD_INFO1,SD card interrupt flag register 1"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 10. "INFO10,Indicates the SD0DAT3 state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "INFO9,SD0DAT3 Card Insertion" "0,1"
|
|
bitfld.long 0x00 8. "INFO8,SD0DAT3 Card Removal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "INFO7,Write Protect Port 0" "0,1"
|
|
bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INFO5,ISD0CD state" "0,1"
|
|
bitfld.long 0x00 4. "INFO4,ISD0CD Card Removal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INFO3,ISD0CD Card Insertion" "0,1"
|
|
bitfld.long 0x00 2. "INFO2,Access End" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 0. "INFO0,Response End" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SDIO_SD_INFO2,SD card interrupt flag register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "ILA,Illegal Write Access" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CBSY,CMD Type Register Busy" "0,1"
|
|
bitfld.long 0x00 13. "SCLKDIVEN,Command Setting Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 10. "BSYNC2,C2 busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "BWE,SD_BUF Write Enable" "0,1"
|
|
bitfld.long 0x00 8. "BRE,SD_BUF Read Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "DAT0,SDDAT0" "0,1"
|
|
bitfld.long 0x00 6. "ERR6,Response Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ERR5,SD_BUF Illegal RD Access" "0,1"
|
|
bitfld.long 0x00 4. "ERR4,SD BUF illegalel WR access" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ERR3,Data Timeout" "0,1"
|
|
bitfld.long 0x00 2. "ERR2,End Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ERR1,CRC Error" "0,1"
|
|
bitfld.long 0x00 0. "ERR0,CMD Error" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SDIO_SD_INFO1_MASK,SD_INFO1_interrupt mask register"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 9. "MASK9,INFO9 interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "MASK8,INFO8 interrupt mask" "0,1"
|
|
bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4. "MASK4,INFO4 interrupt mask" "0,1"
|
|
bitfld.long 0x00 3. "MASK3,INFO3 interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "MASK2,INFO2 interrupt mask" "0,1"
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MASK0,INFO0 interrupt mask" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SDIO_SD_INFO2_MASK,SD_INFO2 interrupt mask register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "IMASK,ILA interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "Reserved3,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 9. "BMASK1,BRW interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "BMASK0,BRE interrupt mask" "0,1"
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "EMASK6,ERR6 interrupt mask" "0,1"
|
|
bitfld.long 0x00 5. "EMASK5,ERR5 interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "EMASK4,ERR4 interrupt mask" "0,1"
|
|
bitfld.long 0x00 3. "EMASK3,ERR3 interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "EMASK2,ERR2 interrupt mask" "0,1"
|
|
bitfld.long 0x00 1. "EMASK1,ERR1 interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "EMASK0,ERR0 interrupt mask" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SDIO_SD_CLK_CTRL,SD clock control register"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 10. "SD_CLK_SEL,OSDCLKSEL Port Control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SD_CLK_OFFEN,SD_CLK Automatic control enable" "0,1"
|
|
bitfld.long 0x00 8. "SD_CLK_EN,SD_CLK output control enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV,SD clock divider"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SDIO_SD_SIZE,Transfer data length register"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--9. 1. "LEN,Transfer Data Size"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SDIO_SD_OPTION,SD card access control option register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "WIDTH,Bus Width" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Reserved1,Reserved" "0,1"
|
|
bitfld.long 0x00 8.--13. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "TOP,Timout Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CTOP,Card Detect timing counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "SDIO_SD_ERR_STS1,SD error status register 1"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 12.--14. "CRCSTS,CRC status" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "ERRSTS11,CRC status error" "0,1"
|
|
bitfld.long 0x00 10. "ERRSTS10,CRC error in read data" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ERRSTS9,CRC error in response" "0,1"
|
|
bitfld.long 0x00 8. "ERRSTS8,CRC status error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 5. "ERRSTS5,CRC status error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERRSTS4,RD data length error" "0,1"
|
|
bitfld.long 0x00 3. "ERRSTS3,Response Length error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERRSTS2,Response Length error" "0,1"
|
|
bitfld.long 0x00 1. "ERRSTS1,Command index error in the response" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ERRSTS0,Command index error in the response" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "SDIO_SD_ERR_STS2,SD error status register 2"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 6. "ERRSTS6,Too long busy ofter CRC status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ERRSTS5,No CRC status" "0,1"
|
|
bitfld.long 0x00 4. "ERRSTS4,No read data" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ERRSTS3,Too long busy" "0,1"
|
|
bitfld.long 0x00 2. "ERRSTS2,Too long busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ERRSTS1,No response for the command" "0,1"
|
|
bitfld.long 0x00 0. "ERRSTS0,No response for the command" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SDIO_SD_BUF0,SD buffer read/write register"
|
|
hexmask.long 0x00 0.--31. 1. "SD_BUF0,SD_BUF0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SDIO_SDIO_MODE,SDIO Mode Control Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 9. "C52PUB,SDIO non abort" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "IOABT,SDIO abort" "0,1"
|
|
bitfld.long 0x00 3.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2. "RWREQ,Read wait request" "0,1"
|
|
bitfld.long 0x00 1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IOMOD,SDIO mode" "0,1"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "SDIO_SDIO_INFO1,SDIO interrupt flag register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "EXWT,Settings Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "EXPUB52,Setting Condition" "0,1"
|
|
hexmask.long.word 0x00 1.--13. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "IOIRQ,SDIO Interrupt" "0,1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "SDIO_SDIO_INFO1_MASK,SDIO Interrupt Mask Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "SDIO_INFO1_MASK1,EXWT Interrupt masked" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "MEXPUB52,EXPUB52 interrupt mask" "0,1"
|
|
hexmask.long.word 0x00 3.--13. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "Reserved1,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0. "IOMASK,IOIRQ interrupt mask" "0,1"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "SDIO_CC_EXT_MODE,DMA Mode Enable Register"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "DMASDRW,Enable SD_BUF RD/WR DMA transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "SDIO_SOFT_RST,Software reset register"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1.--2. "Reserved1,Fixed 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "SDRST,Software reset of SD I/F unit" "0,1"
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "SDIO_Version,Version register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "UR7,CPRM preset/absent" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "UR6,SDCLK:ICMLK Capability" "0,1"
|
|
bitfld.long 0x00 12.--13. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "UR,Version of renesas IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IP,Version of adopted IP"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "SDIO_HOST_MODE,Host interface mode register"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "WMODE,Access size of the SD_BUF" "0,1"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "SDIO_SDIF_MODE,SD Interface mode register set"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "DDR,DDR mode selection" "0,1"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDIO_EXT_SWAP,Swap control register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "SDBRSWAP,SD_BUF0 Swap" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SDBWSWAP,SD_BUF Swap" "0,1"
|
|
bitfld.long 0x00 0.--5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "SDIO_SD_STATUS,SD Status register"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8.--10. "OSTATUS22_20,Contol port OSSTATUS" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSTATUS11_10,Contol port OSSTATUS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PWR,Contol port OPOWR[1:0]" "0,1,2,3"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "SDIO_EXT_SDIO,Extended port SDIO Interrupt register"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 9.--10. "Reserved5,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8. "IOMSK1,IOIRQ1 interrupt mask" "0,1"
|
|
bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4. "IOMODE1,Port 1 SD IO mode" "0,1"
|
|
bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "IOIRQ1,SDIO interrupt received from card" "0,1"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "SDIO_EXT_WP,Extended port write protect register"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "PORT1,Indicates the ISD1WP state" "0,1"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "SDIO_EXT_CD,Extended port card detect (ISDCD) register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 6.--7. "Reserved2,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 3.--4. "Reserved1,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2. "P1CD,Indicates the ISD1CD state" "0,1"
|
|
bitfld.long 0x00 1. "P1INS,Indicates the ISD1Card Insertion" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "P1REM,Indicates the ISD1 card removal" "0,1"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "SDIO_EXT_CD_DAT3,Extended port card detect register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 6.--7. "Reserved2,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 3.--4. "Reserved1,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2. "P1DCD,Indicates the SD1DAT3 state" "0,1"
|
|
bitfld.long 0x00 1. "P1DINS,SD1DAT3 card insertion" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "P1DREM,SD1DAT3 removal" "0,1"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "SDIO_EXT_CD_MASK,EXT_CD interrupt mask register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 6.--7. "Reserved4,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "Reserved3,Fixed 1" "0,1"
|
|
bitfld.long 0x00 3.--4. "Reserved2,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2. "Reserved1,Fixed 1" "0,1"
|
|
bitfld.long 0x00 1. "MP1INS,P1INS interrupt masked" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MP1REM,P1INS interrupt masked" "0,1"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "SDIO_EXT_CD_DAT3_MASK,EXT_CD_DAT3 interrupt mask register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 6.--7. "Reserved4,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "Reserved3,Fixed 1" "0,1"
|
|
bitfld.long 0x00 3.--4. "Reserved2,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2. "Reserved1,Fixed 1" "0,1"
|
|
bitfld.long 0x00 1. "MP1DINS,P1DINS interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MP1DREM,P1DREM interrupt mask" "0,1"
|
|
tree.end
|
|
tree "PVO"
|
|
base ad:0xF803C000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PVO_REV,HW Version"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "REVMAJ,Major version"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "REVMIN,Minor version"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REV,Revision"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PVO_LNUM,Layer Count"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LNUMLNUM,Number of layers"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PVO_SIZE,Sync Size"
|
|
bitfld.long 0x00 28.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--27. 1. "SIZEHSIZE,H Sync width-1 (pixels)"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "SIZEVSIZE,V Sync height-1 (lines)"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PVO_BPO,Back Porch (accumulated)"
|
|
bitfld.long 0x00 28.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--27. 1. "BPOWBPO,Accumulated width including sync and back porch -1 (pixels)"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "BPOHBPO,Accumulated height including sync and back porch -1 (lines)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PVO_AWD,Active Width (accumulated)"
|
|
bitfld.long 0x00 28.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--27. 1. "AWDWAWD,Accumulated width including sync back porch and active width -1 (pixels)"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "AWDHAWD,Accumulated height including sync back porch and active height -1 (lines)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PVO_TWD,Total Width"
|
|
bitfld.long 0x00 28.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--27. 1. "TWDWTWD,Total width including sync back porch active width and front porch -1 (pixels)"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "TWDHTWD,Total height including sync back porch active height and front porch -1 (lines)"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PVO_GCNT,Global Control"
|
|
bitfld.long 0x00 31. "GCNTHSP,HSync polarity" "0,1"
|
|
bitfld.long 0x00 30. "GCNTVSP,VSync polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "GCNTBLP,Blank polarity" "0,1"
|
|
hexmask.long.word 0x00 19.--28. 1. "bf_align5,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 18. "GCNTSTEN,Slave timing mode on" "0,1"
|
|
bitfld.long 0x00 17. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "GCNTDEN,Dithering on" "0,1"
|
|
bitfld.long 0x00 15. "bf_align3,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "GCNTDBR,Dither bits red (0-4)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "GCNTDBG,Dither bits green (0-4)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "GCNTDBB,Dither bits blue (0-4)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "GCNTGEN,Global enable" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "PVO_CFG1,Global Configuration 1"
|
|
bitfld.long 0x00 31. "CFG1BMEN,Blind Mode enabled" "0,1"
|
|
bitfld.long 0x00 30. "CFG1CRME,Configuration Reading Mode enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "CFG1SREN,Status registers enabled" "0,1"
|
|
bitfld.long 0x00 28. "CFG1DWP,Dither width programmable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "CFG1SPP,Sync polarity programmable" "0,1"
|
|
bitfld.long 0x00 26. "CFG1IPP,IRQ polarity programmable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "CFG1TIP,Timing programmable" "0,1"
|
|
bitfld.long 0x00 24. "CFG1LIPP,Line IRQ position programmable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "CFG1BBE,Background blending enabled" "0,1"
|
|
bitfld.long 0x00 22. "CFG1BCP,Background color programmable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "CFG1SRE,Shadow registers enabled" "0,1"
|
|
bitfld.long 0x00 20. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "CFG1GMCT,Gamma correction technique" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "CFG1DIT,Dithering technique" "0,1,2,3"
|
|
bitfld.long 0x00 13. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "CFG1PBE,Precise blending enabled" "0,1"
|
|
bitfld.long 0x00 8.--11. "CFG1OWR,Output width red" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CFG1OWG,Output width green" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CFG1OWB,Output width blue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PVO_CFG2,Global Configuration 2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 7. "CFG2EDAE,External display control ability enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "CFG2BWT,Bus width (log2 of number of bytes)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CFG2DPE,Dual-port ability enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CFG2DWE,Dual-view ability enabled" "0,1"
|
|
bitfld.long 0x00 1. "CFG2STSAE,Slave timing synchronization ability enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CFG2BLAE,Background layer ability enabled" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PVO_SRC,Shadow Reload Control"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 1. "SRCVBR,Vertical blanking reload (self clearing after reload can not be reset once set)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SRCIMR,Immediate reload (self clearing at once)" "0,1"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "PVO_GCR,Gamma Correction"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PVO_BCL,Background Color"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "BCLBAC,Background color (RGB)"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "PVO_IRP,IRQ Polarity"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PVO_IER,IRQ Enable"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 5. "IERSTNISIE,Slave timing not in sync IRQ on" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "IERSTNSIE,Slave timing no signal IRQ on" "0,1"
|
|
bitfld.long 0x00 3. "IERRRIE,Register reload IRQ on" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "IERBEIE,Bus error IRQ on" "0,1"
|
|
bitfld.long 0x00 1. "IERFUIE,FIFO Underrun IRQ on" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IERLIE,Line IRQ on" "0,1"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "PVO_ISR,IRQ Status"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 5. "ISRSTNISIS,Slave timing not in sync IRQ status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ISRSTNSIS,Slave timing no signal IRQ status" "0,1"
|
|
bitfld.long 0x00 3. "ISRRRIS,Register reload IRQ status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ISRBEIS,Bus error IRQ status" "0,1"
|
|
bitfld.long 0x00 1. "ISRFUIS,FIFO Underrun IRQ status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ISRLIS,Line IRQ status" "0,1"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "PVO_ICR,IRQ Clear"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 5. "ICRSTNISIC,Clear slave timing not in sync IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ICRSTNSIC,Clear slave timing no signal IRQ" "0,1"
|
|
bitfld.long 0x00 3. "ICRRRIC,Clear register reload IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ICRBEIC,Clear bus error IRQ" "0,1"
|
|
bitfld.long 0x00 1. "ICRFUIC,Clear FIFO underrun IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ICRLIC,Clear line IRQ" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PVO_LIPC,Line IRQ Position Control"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "LIPCLIP,Line IRQ position"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "PVO_PST,Position Status"
|
|
hexmask.long.word 0x00 16.--31. 1. "PSTCXP,Current X position"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSTCYP,Current Y position"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "PVO_SBS,Sync/Blank Status"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 3. "SBSHSS,HSync Status (active high)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SBSVSS,VSync Status (active high)" "0,1"
|
|
bitfld.long 0x00 1. "SBSHBS,HBlank Status (active high)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SBSVBS,VBlank Status (active high)" "0,1"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "PVO_BLB,Background Layer Base"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "PVO_BLI,Background Layer Increments"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "PVO_BLA,Background Layer RAM Address"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
wgroup.long 0x58++0x03
|
|
line.long 0x00 "PVO_BLD,Background Layer Data"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "PVO_STS,Slave Timing Mode Status"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "STSLFMA,Low frequency mode active" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "STSEVEL,External vsync event line"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "PVO_L0LCFG,Layer 0 Layer Configuration"
|
|
hexmask.long.byte 0x00 24.--31. 1. "L0LCFGSPF,Supported pixel formats (bit mask custom)"
|
|
abitfld.long 0x00 16.--23. "L0LCFGSBF1,Bit" "0x00=0: Supported blending factors for f1,0x01=1: Supported blending factors for f1,0x02=2: Supported blending factors for f1,0x03=3: Supported blending factors for f1,0x04=4: Supported blending factors for f1,0x05=5: Supported blending factors for f1,0x06=6: Supported blending factors for f1,0x07=7: Supported blending factors for f1"
|
|
newline
|
|
abitfld.long 0x00 8.--15. "L0LCFGSBF2,Bit" "0x00=0: Supported blending factors for f2,0x01=1: Supported blending factors for f2,0x02=2: Supported blending factors for f2,0x03=3: Supported blending factors for f2,0x04=4: Supported blending factors for f2,0x05=5: Supported blending factors for f2,0x06=6: Supported blending factors for f2,0x07=7: Supported blending factors for f2"
|
|
bitfld.long 0x00 7. "L0LCFGCKRE,Color key replace ability enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "L0LCFGCAE,CLUT ability enabled" "0,1"
|
|
bitfld.long 0x00 5. "L0LCFGWAE,Windowing ability enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "L0LCFGDCP,Default color programmable" "0,1"
|
|
bitfld.long 0x00 3. "L0LCFGAFE,Alpha FB ability enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "L0LCFGCFLE,Color FB line gap ability enabled" "0,1"
|
|
bitfld.long 0x00 1. "L0LCFGCFDE,Color FB duplication ability enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "L0LCFGCKE,Color key ability enabled" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PVO_L0CNT,Layer 0 Control"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 5. "L0CNTCKRE,Color key replace on" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "L0CNTCLE,CLUT lookup on" "0,1"
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "L0CNTCKE,Color key feature on" "0,1"
|
|
bitfld.long 0x00 0. "L0CNTLAE,Layer on" "0,1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PVO_L0WHP,Layer 0 Window Horizontal Position"
|
|
bitfld.long 0x00 28.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--27. 1. "L0WHPHSTOP,Horizontal Stop Position"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "L0WHPHSTAP,Horizontal Start Position"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PVO_L0WVP,Layer 0 Window Vertical Position"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "L0WVPVSTOP,Vertical Stop Position"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "L0WVPVSTAP,Vertical Start Position"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PVO_L0CKR,Layer 0 Color Key"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "L0CKRTRC,Transparency color"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PVO_L0PFR,Layer 0 Pixel Format"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--2. "L0PFRPIF,Pixel format" "0,1,2,3,4,5,6,7"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PVO_L0CAR,Layer 0 Constant Alpha"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "L0CARCOA,Constant alpha"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "PVO_L0DCR,Layer 0 Default Color"
|
|
hexmask.long 0x00 0.--31. 1. "L0DCRDEC,Default color (ARGB)"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PVO_L0BFR,Layer 0 Blending Factors"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8.--10. "L0BFRSELF1,Selection of factor f1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. "L0BFRSELF2,Selection of factor f2" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "PVO_L0AFCF,Layer 0 Alpha FB Configuration"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "PVO_L0AFCT,Layer 0 Alpha FB Configuration"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "PVO_L0CFA,Layer 0 Color FB Address"
|
|
hexmask.long 0x00 0.--31. 1. "L0CFAADD,Color FB start address"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PVO_L0CFL,Layer 0 Color FB Length"
|
|
bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--28. 1. "L0CFLPC,Pitch of color FB in bytes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--12. 1. "L0CFLLCF,Line length of color FB in bytes (+7)"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "PVO_L0CFG,Layer 0 Color FB Gap"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "L0CFGLGCF,Line gap of color FB in pixels"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "PVO_L0AFA,Layer 0 Alpha FB Address"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "PVO_L0AFL,Layer 0 Alpha FB Length"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "PVO_L0AFG,Layer 0 Alpha FB Gap"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
wgroup.long 0xC4++0x03
|
|
line.long 0x00 "PVO_L0CWA,Layer 0 CLUT Write Access"
|
|
hexmask.long.byte 0x00 24.--31. 1. "L0CWAADD,Address of CLUT entry"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "L0CWADATA,RGB888 value to be written"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "PVO_L1LCFG,Layer 1 Layer Configuration"
|
|
hexmask.long.byte 0x00 24.--31. 1. "L1LCFGSPF,Supported pixel formats (bit mask custom)"
|
|
abitfld.long 0x00 16.--23. "L1LCFGSBF1,Bit" "0x00=0: Supported blending factors for f1,0x01=1: Supported blending factors for f1,0x02=2: Supported blending factors for f1,0x03=3: Supported blending factors for f1,0x04=4: Supported blending factors for f1,0x05=5: Supported blending factors for f1,0x06=6: Supported blending factors for f1,0x07=7: Supported blending factors for f1"
|
|
newline
|
|
abitfld.long 0x00 8.--15. "L1LCFGSBF2,Bit" "0x00=0: Supported blending factors for f2,0x01=1: Supported blending factors for f2,0x02=2: Supported blending factors for f2,0x03=3: Supported blending factors for f2,0x04=4: Supported blending factors for f2,0x05=5: Supported blending factors for f2,0x06=6: Supported blending factors for f2,0x07=7: Supported blending factors for f2"
|
|
bitfld.long 0x00 7. "L1LCFGCKRE,Color key replace ability enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "L1LCFGCAE,CLUT ability enabled" "0,1"
|
|
bitfld.long 0x00 5. "L1LCFGWAE,Windowing ability enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "L1LCFGDCP,Default color programmable" "0,1"
|
|
bitfld.long 0x00 3. "L1LCFGAFE,Alpha FB ability enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "L1LCFGCFLE,Color FB line gap ability enabled" "0,1"
|
|
bitfld.long 0x00 1. "L1LCFGCFDE,Color FB duplication ability enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "L1LCFGCKE,Color key ability enabled" "0,1"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "PVO_L1CNT,Layer 1 Control"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 5. "L1CNTCKRE,Color key replace on" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "L1CNTCLE,CLUT lookup on" "0,1"
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "L1CNTCKE,Color key feature on" "0,1"
|
|
bitfld.long 0x00 0. "L1CNTLAE,Layer on" "0,1"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "PVO_L1WHP,Layer 1 Window Horizontal Position"
|
|
bitfld.long 0x00 28.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--27. 1. "L1WHPHSTOP,Horizontal Stop Position"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "L1WHPHSTAP,Horizontal Start Position"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "PVO_L1WVP,Layer 1 Window Vertical Position"
|
|
bitfld.long 0x00 27.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--26. 1. "L1WVPVSTOP,Vertical Stop Position"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--10. 1. "L1WVPVSTAP,Vertical Start Position"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PVO_L1CKR,Layer 1 Color Key"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "L1CKRTRC,Transparency color"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "PVO_L1PFR,Layer 1 Pixel Format"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--2. "L1PFRPIF,Pixel format" "0,1,2,3,4,5,6,7"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PVO_L1CAR,Layer 1 Constant Alpha"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "L1CARCOA,Constant alpha"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "PVO_L1DCR,Layer 1 Default Color"
|
|
hexmask.long 0x00 0.--31. 1. "L1DCRDEC,Default color (ARGB)"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PVO_L1BFR,Layer 1 Blending Factors"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8.--10. "L1BFRSELF1,Selection of factor f1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. "L1BFRSELF2,Selection of factor f2" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "PVO_L1AFCF,Layer 1 Alpha FB Configuration"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "PVO_L1AFCT,Layer 1 Alpha FB Configuration"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "PVO_L1CFA,Layer 1 Color FB Address"
|
|
hexmask.long 0x00 0.--31. 1. "L1CFAADD,Color FB start address"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PVO_L1CFL,Layer 1 Color FB Length"
|
|
bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--28. 1. "L1CFLPC,Pitch of color FB in bytes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--12. 1. "L1CFLLCF,Line length of color FB in bytes (+7)"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "PVO_L1CFG,Layer 1 Color FB Gap"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--10. 1. "L1CFGLGCF,Line gap of color FB in pixels"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "PVO_L1AFA,Layer 1 Alpha FB Address"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "PVO_L1AFL,Layer 1 Alpha FB Length"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "PVO_L1AFG,Layer 1 Alpha FB Gap"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
wgroup.long 0x144++0x03
|
|
line.long 0x00 "PVO_L1CWA,Layer 1 CLUT Write Access"
|
|
hexmask.long.byte 0x00 24.--31. 1. "L1CWAADD,Address of CLUT entry"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "L1CWADATA,RGB888 value to be written"
|
|
tree.end
|
|
tree "DAVEHD"
|
|
base ad:0xF803D000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DAVEHD_STC_VERSION,STC version"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Constant,Constant 0xD4"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HW_Version_Major,HW version major"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "HW_Version_Minor,HW version minor"
|
|
hexmask.long.byte 0x00 0.--7. 1. "HW_Revision,HW revision (for bug fixes etc)"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "DAVEHD_STC_CONFIG1,STC configuration 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Max_Color_Passes,C_MAX_COLOR_PASSES"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Max_Texture_Units,C_MAX_TEXTURE_UNITS"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "STR_Num_Lines,log2 of C_STR_NUM_LINES" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "STR_Line_Length,log2 of C_STR_LINE_LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MBI_Num_Bytes,log2 of C_MBI_NUM_BYTES" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "DAVEHD_STC_CONFIG2,STC configuration 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Num_Perf_Counters,C_NUM_PERF_COUNTERS"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Num_Limiters,C_NUM_LIMITERS"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Num_Pixel_Pipes,C_NUM_PIXEL_PIPES"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Num_Const_Colors,C_NUM_CONST_COLORS"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "DAVEHD_STC_CONFIG3,STC configuration 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "STC_Call_Stack_Depth,C_STC_CALL_STACK_DEPTH"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "Tex_Clut_Depth,log2 of C_TEX_CLUT_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "Tex_Clut_Has_Alpha,C_TEX_CLUT_HAS_ALPHA" "0,1"
|
|
bitfld.long 0x00 0. "Tex_Clut_Available,C_TEX_CLUT_AVAILABLE" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "DAVEHD_STC_BUSY,Modules busy bits"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--9. 1. "Busy_Status,Modules busy bits"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DAVEHD_STC_CTRL1,STC control"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 14. "Limit_Prefetch_In_Ring,Limit prefetch in ring (stack level 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "Stream_Halt_Request,Stream halt request (automatically reset on successful stream halt see Halting)" "0,1"
|
|
bitfld.long 0x00 12. "Stall_Request,Stall request (see Core Stalling)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 10. "Checksum_Protection_Mode,Checksum protection mode (see Checksum Protection)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 8. "Permanent_Enable_Clock,Permanent clock enable (see Clock gating)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "Sync_Irq_Enable,Sync IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "MBI_Error_Irq_Enable,MBI error IRQ enable" "0,1"
|
|
bitfld.long 0x00 2. "Stall_Irq_Enable,Stall IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "Pause_Irq_Enable,Pause IRQ enable (see Ring-Buffer mode)" "0,1"
|
|
bitfld.long 0x00 0. "Stop_Irq_Enable,Stop IRQ enable (see Interrupts/Errors)" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DAVEHD_STC_CTRL2,STC control"
|
|
hexmask.long.word 0x00 23.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 21.--22. "MBI_Write_Error_Source,MBI write error source" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20. "MBI_Write_Error,See Bus error handling on the meaning of this error status bits" "0,1"
|
|
bitfld.long 0x00 17.--19. "MBI_Read_Error_Source,MBI read error source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "MBI_Read_Error,See Bus error handling on the meaning of this error status bits" "0,1"
|
|
bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "Stop_Irq_Code,Stop IRQ code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4. "Sync_Irq_Triggered,Sync IRQ triggered" "0,1"
|
|
bitfld.long 0x00 3. "MBI_Error_Irq_Triggered,MBI error IRQ triggered" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "Stall_Irq_Triggered,Stall IRQ triggered (see Core Stalling)" "0,1"
|
|
bitfld.long 0x00 1. "Pause_Irq_Triggered,Pause IRQ enable (see Ring-Buffer mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "Stop_Irq_Triggered,Stop IRQ triggered" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DAVEHD_STC_STRSTAADR,Stream start address"
|
|
hexmask.long 0x00 2.--31. 1. "Stream_Address,Stream start address"
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DAVEHD_STC_STRPAUADR,Stream ring pause address"
|
|
hexmask.long 0x00 2.--31. 1. "Ring_Pause_Address,Ring-buffer pause address"
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DAVEHD_STC_STRRNGADR,Stream current ring address"
|
|
hexmask.long 0x00 2.--31. 1. "Current_Ring_Address,Current stream address inside ring-buffer i.e"
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DAVEHD_STC_STRCURADR,Stream current address"
|
|
hexmask.long 0x00 2.--31. 1. "Current_Stream_Address,Current stream address (possibly inside sub-stream)"
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DAVEHD_STC_CHECKSUM,Checksum"
|
|
hexmask.long 0x00 0.--31. 1. "Current_Reference_Checksum,Checksum"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DAVEHD_STC_SYNC0,Synchronization_ID 0"
|
|
hexmask.long 0x00 0.--31. 1. "Synchronization_ID_0,Synchronization ID for driver usage"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAVEHD_STC_SYNC1,Synchronization_ID 1"
|
|
hexmask.long 0x00 0.--31. 1. "Synchronization_ID_1,Synchronization ID for driver usage"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DAVEHD_STC_SYNC2,Synchronization_ID 2"
|
|
hexmask.long 0x00 0.--31. 1. "Synchronization_ID_2,Synchronization ID for driver usage"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "DAVEHD_STC_STACKPTR,Call Stack Pointer"
|
|
hexmask.long 0x00 2.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--1. "Call_Stack_Pointer,Call stack pointer" "0,1,2,3"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DAVEHD_STC_STACKENT0,Call Stack Entry 0"
|
|
hexmask.long 0x00 2.--31. 1. "Call_Stack_Entry_0,Addresses on call stack 16 successive registers maximum depending on C_STC_CALL_STACK_DEPTH"
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DAVEHD_STC_STACKENT1,Call Stack Entry 1"
|
|
hexmask.long 0x00 2.--31. 1. "Call_Stack_Entry_1,Addresses on call stack 16 successive registers maximum depending on C_STC_CALL_STACK_DEPTH"
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DAVEHD_STC_STACKENT2,Call Stack Entry 2"
|
|
hexmask.long 0x00 2.--31. 1. "Call_Stack_Entry_2,Addresses on call stack 16 successive registers maximum depending on C_STC_CALL_STACK_DEPTH"
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DAVEHD_STC_STACKENT3,Call Stack Entry 3"
|
|
hexmask.long 0x00 2.--31. 1. "Call_Stack_Entry_3,Addresses on call stack 16 successive registers maximum depending on C_STC_CALL_STACK_DEPTH"
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DAVEHD_STC_STACKENT4,Call Stack Entry 4"
|
|
hexmask.long 0x00 2.--31. 1. "Call_Stack_Entry_4,Addresses on call stack 16 successive registers maximum depending on C_STC_CALL_STACK_DEPTH"
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DAVEHD_STC_STACKENT5,Call Stack Entry 5"
|
|
hexmask.long 0x00 2.--31. 1. "Call_Stack_Entry_5,Addresses on call stack 16 successive registers maximum depending on C_STC_CALL_STACK_DEPTH"
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DAVEHD_STC_STACKENT6,Call Stack Entry 6"
|
|
hexmask.long 0x00 2.--31. 1. "Call_Stack_Entry_6,Addresses on call stack 16 successive registers maximum depending on C_STC_CALL_STACK_DEPTH"
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "DAVEHD_STC_STACKENT7,Call Stack Entry 7"
|
|
hexmask.long 0x00 2.--31. 1. "Call_Stack_Entry_7,Addresses on call stack 16 successive registers maximum depending on C_STC_CALL_STACK_DEPTH"
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "DAVEHD_STC_PERFCNT0,Performance Counter Values 0"
|
|
hexmask.long 0x00 0.--31. 1. "Performance_Counter_Values_0,Up to 32 performance counter actual values"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DAVEHD_STC_PERFCNT1,Performance Counter Values 1"
|
|
hexmask.long 0x00 0.--31. 1. "Performance_Counter_Values_1,Up to 32 performance counter actual values"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "DAVEHD_STC_PERFCNT2,Performance Counter Values 2"
|
|
hexmask.long 0x00 0.--31. 1. "Performance_Counter_Values_2,Up to 32 performance counter actual values"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "DAVEHD_STC_PERFCNT3,Performance Counter Values 3"
|
|
hexmask.long 0x00 0.--31. 1. "Performance_Counter_Values_3,Up to 32 performance counter actual values"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DAVEHD_PSU_BBOXULC,Bounding box upper left corner"
|
|
bitfld.long 0x00 28.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--27. 1. "Lim_Bbox_Ymin,Bounding box upper border"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "Lim_Bbox_Xmin,Bounding box left border"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "DAVEHD_PSU_BBOXLRC,Bounding box lower right corner"
|
|
bitfld.long 0x00 28.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--27. 1. "Lim_Bbox_Ymax,Bounding box lower border"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "Lim_Bbox_Xmax,Bounding box right border"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "DAVEHD_PSU_STARTPOS,Start position for enumeration"
|
|
bitfld.long 0x00 28.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--27. 1. "Lim_Start_Y,Y start position for enumeration (X start position is at left border of Bbox)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "DAVEHD_PSU_PIXCTRL,Pixel selection unit Limiter control registers"
|
|
bitfld.long 0x00 30.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "Bez_Ctrl,Control structure for Bezier function" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "Lim_Ctrl_5,Control structure for Limiter n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "Lim_Ctrl_4,Control structure for Limiter n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "Lim_Ctrl_3,Control structure for Limiter n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "Lim_Ctrl_2,Control structure for Limiter n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "Lim_Ctrl_1,Control structure for Limiter n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "Lim_Ctrl_0,Control structure for Limiter n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "DAVEHD_PSU_STRIPE,Enumeration stripes width and offset"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Lim_Stripe_Offset,Offset for first width of stripe"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Lim_Stripe_Width,Width of stripes for stripe-wise enumeration (0 = full span no stripe-wise enumeration)"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DAVEHD_PSU_BEZCTRL,Bezier control"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--5. "Bez_Lim_Scale,Scaling factor for bezier limiter values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "DAVEHD_PSU_BEZOFFSET0,Offset to Limiter value for Bezier function (14.18 signed fixed point)"
|
|
hexmask.long 0x00 0.--31. 1. "Bez_Voff_0,Offset to Limiter value for Bezier function (14.18 signed fixed point)"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "DAVEHD_PSU_BEZOFFSET1,Offset to Limiter value for Bezier function (14.18 signed fixed point)"
|
|
hexmask.long 0x00 0.--31. 1. "Bez_Voff_1,Offset to Limiter value for Bezier function (14.18 signed fixed point)"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "DAVEHD_PSU_BEZAACTRL,Bezier antialiasing and width control"
|
|
bitfld.long 0x00 26.--31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "Bez_Aa,Anti-aliasing width of Bezier element"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Bez_Aa_Offset,Anti-aliasing offset to shift anti-aliasing region from inside to outside of curve"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Bez_Width,"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMVSTART0,Initial Limiter value of enumeration start position (14.18 signed fixed point)"
|
|
hexmask.long 0x00 0.--31. 1. "Lim_Vstart_0,Initial Limiter value of enumeration start position (14.18 signed fixed point)"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMDX0,IFractional part of Limiter x step (2.18 signed fixed point)"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "Lim_dx_0,Fractional part of Limiter x step (2.18 signed fixed point)"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMDY0,IFractional part of Limiter y step (2.18 signed fixed point)"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "Lim_dy_0,Fractional part of Limiter y step (2.18 signed fixed point)"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMVSTART1,Initial Limiter value of enumeration start position (14.18 signed fixed point)"
|
|
hexmask.long 0x00 0.--31. 1. "Lim_Vstart_1,Initial Limiter value of enumeration start position (14.18 signed fixed point)"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMDX1,IFractional part of Limiter x step (2.18 signed fixed point)"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "Lim_dx_1,Fractional part of Limiter x step (2.18 signed fixed point)"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMDY1,IFractional part of Limiter y step (2.18 signed fixed point)"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "Lim_dy_1,Fractional part of Limiter y step (2.18 signed fixed point)"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMVSTART2,Initial Limiter value of enumeration start position (14.18 signed fixed point)"
|
|
hexmask.long 0x00 0.--31. 1. "Lim_Vstart_2,Initial Limiter value of enumeration start position (14.18 signed fixed point)"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMDX2,IFractional part of Limiter x step (2.18 signed fixed point)"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "Lim_dx_2,Fractional part of Limiter x step (2.18 signed fixed point)"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMDY2,IFractional part of Limiter y step (2.18 signed fixed point)"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "Lim_dy_2,Fractional part of Limiter y step (2.18 signed fixed point)"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMVSTART3,Initial Limiter value of enumeration start position (14.18 signed fixed point)"
|
|
hexmask.long 0x00 0.--31. 1. "Lim_Vstart_3,Initial Limiter value of enumeration start position (14.18 signed fixed point)"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMDX3,IFractional part of Limiter x step (2.18 signed fixed point)"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "Lim_dx_3,Fractional part of Limiter x step (2.18 signed fixed point)"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMDY3,IFractional part of Limiter y step (2.18 signed fixed point)"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "Lim_dy_3,Fractional part of Limiter y step (2.18 signed fixed point)"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMVSTART4,Initial Limiter value of enumeration start position (14.18 signed fixed point)"
|
|
hexmask.long 0x00 0.--31. 1. "Lim_Vstart_4,Initial Limiter value of enumeration start position (14.18 signed fixed point)"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMDX4,IFractional part of Limiter x step (2.18 signed fixed point)"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "Lim_dx_4,Fractional part of Limiter x step (2.18 signed fixed point)"
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMDY4,IFractional part of Limiter y step (2.18 signed fixed point)"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "Lim_dy_4,Fractional part of Limiter y step (2.18 signed fixed point)"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMVSTART5,Initial Limiter value of enumeration start position (14.18 signed fixed point)"
|
|
hexmask.long 0x00 0.--31. 1. "Lim_Vstart_5,Initial Limiter value of enumeration start position (14.18 signed fixed point)"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMDX5,IFractional part of Limiter x step (2.18 signed fixed point)"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "Lim_dx_5,Fractional part of Limiter x step (2.18 signed fixed point)"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "DAVEHD_PSU_LIMDY5,IFractional part of Limiter y step (2.18 signed fixed point)"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "Lim_dy_5,Fractional part of Limiter y step (2.18 signed fixed point)"
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "DAVEHD_PSU_DBGCTRL,Debug control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4.--7. "Lim_Debug,Limiter debug control bits (tbd.)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "Bez_Debug,Dezier debug control bits (tbd.)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "DAVEHD_PSU_MAXPOS,Maximum coordinates generated by PSU clipping limits for bounding box"
|
|
bitfld.long 0x00 28.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--27. 1. "Lim_Ymax,Maximum Y coordinate"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "Lim_Xmax,Maximum X coordinate"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXAOFFSETU0,Start value for texture U coordinate"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_U_Offset_0,Start value for texture U coordinate"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXAOFFSETV0,Start value for texture V coordinate"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_V_Offset_0,Start value for texture V coordinate"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADUX0,Increment of texture U coordinate for a pixel step in X direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dUX_0,Increment of texture U coordinate for a pixel step in X direction"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADUY0,Increment of texture U coordinate for a pixel step in Y direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dUY_0,Increment of texture U coordinate for a pixel step in Y direction"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADVX0,Increment of texture V coordinate for a pixel step in X direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dVX_0,Increment of texture V coordinate for a pixel step in X direction"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADVY0,Increment of texture V coordinate for a pixel step in Y direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dVY_0,Increment of texture V coordinate for a pixel step in Y direction"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXAOFFSETU1,Start value for texture U coordinate"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_U_Offset_1,Start value for texture U coordinate"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXAOFFSETV1,Start value for texture V coordinate"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_V_Offset_1,Start value for texture V coordinate"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADUX1,Increment of texture U coordinate for a pixel step in X direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dUX_1,Increment of texture U coordinate for a pixel step in X direction"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADUY1,Increment of texture U coordinate for a pixel step in Y direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dUY_1,Increment of texture U coordinate for a pixel step in Y direction"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADVX1,Increment of texture V coordinate for a pixel step in X direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dVX_1,Increment of texture V coordinate for a pixel step in X direction"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADVY1,Increment of texture V coordinate for a pixel step in Y direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dVY_1,Increment of texture V coordinate for a pixel step in Y direction"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "DAVEHD_ZSS_PITCH,ZSA cache scheduler pitch"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--12. 1. "Zss_Pitch,ZSA buffer pitch"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "DAVEHD_ZSS_SPANCONF,ZSA cache scheduler span config"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Zss_Span_Length_Limit,Maximum length of a span for the ZSA buffer cache in pixels-1"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXAZOFFSET,Start value for Z coordinate"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_Z_Offset,Start value for Z coordinate"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADZX,Increment of Z coordinate for a pixel step in X direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dZX,Increment of Z coordinate for a pixel step in X direction"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADZY,Increment of Z coordinate for a pixel step in Y direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dZY,Increment of Z coordinate for a pixel step in Y direction"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXAZOFFRHW,Start value for RHW attribute (1/w) of Z"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_Z_RHW_Offset,Start value for RHW attribute (1/w) of Z"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXAZDRHWX,Increment of RHW attribute of Z for a pixel step in X direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_Z_dRHWX,Increment of RHW attribute of Z for a pixel step in X direction"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXAZDRHWY,Increment of RHW attribute of Z for a pixel step in Y direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_Z_dRHWY,Increment of RHW attribute of Z for a pixel step in Y direction"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXAOFFRHW0,Start value for RHW attribute (1/w)"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_RHW_Offset_0,Start value for RHW attribute (1/w)"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADRHWX0,Increment of RHW attribute for a pixel step in X direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dRHWX_0,Increment of RHW attribute for a pixel step in X direction"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADRHWY0,Increment of RHW attribute for a pixel step in Y direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dRHWY_0,Increment of RHW attribute for a pixel step in Y direction"
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXAOFFRHW1,Start value for RHW attribute (1/w)"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_RHW_Offset_1,Start value for RHW attribute (1/w)"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADRHWX1,Increment of RHW attribute for a pixel step in X direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dRHWX_1,Increment of RHW attribute for a pixel step in X direction"
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "DAVEHD_TXI_TXADRHWY1,Increment of RHW attribute for a pixel step in Y direction"
|
|
hexmask.long 0x00 0.--31. 1. "Txa_dRHWY_1,Increment of RHW attribute for a pixel step in Y direction"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "DAVEHD_ZSA_CTRL,ZSA control registers"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "Zsc_Discard_Noncovered,Enable discarding of pixels which have a coverage of 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "Zsc_Read_Enable,Enable read of ZSA buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 0.--2. "Zsa_Buffer_Org,ZSA buffer data organization" "0,1,2,3,4,5,6,7"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "DAVEHD_ZSA_START,ZSA buffer start address"
|
|
hexmask.long 0x00 0.--31. 1. "Zsc_Start_Address,ZSA buffer start address"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "DAVEHD_ZSA_UNITCTRL1,ZSA Unit Control register 1"
|
|
bitfld.long 0x00 27.--31. "bf_align5,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "Zsu_Stencil_Test_Failed_Op,Stencil operation on and failed stencil test" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 20.--22. "Zsu_Stencil_Depth_Test_Passed_Op,Stencil operation on passed stencil test and passed depth test" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. "bf_align3,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 16.--18. "Zsu_Stencil_Depth_Test_Failed_Op,Stencil operation on passed stencil test and failed depth test" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 12.--14. "Zsu_Stencil_Func,Stencil buffer test function" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. "Zsu_Depth_Write,Depth write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 4.--6. "Zsu_Depth_Func,Depth test function" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "Zsu_Alpha_Mask_Clear_Enable,Alpha_Mask_Clear_Enable" "0,1"
|
|
bitfld.long 0x00 2. "Zsu_Alpha_Mask_Maximize_Enable,Alpha_Mask_Maximize_Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "Zsu_Alpha_Mask_Mode,Global alpha mask mode" "0,1"
|
|
bitfld.long 0x00 0. "Zsu_Alpha_Mask_Enable,Enable global alpha mask" "0,1"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "DAVEHD_ZSA_UNITCTRL2,ZSA Unit Control register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Zsu_Stencil_Write_Mask,Stencil comparison write mask"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Zsu_Stencil_Ref,Stencil comparison reference value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Zsu_Stencil_Mask,Stencil comparison mask"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "DAVEHD_TXA_TEXSIZE0,Texture size"
|
|
bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--28. 1. "Txa_Height_0,Height of the texture in texels"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--12. 1. "Txa_Width_0,Width of the texture in texels"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "DAVEHD_TXA_FILTER0,Filter shape size and texture pitch"
|
|
bitfld.long 0x00 30.--31. "Txa_Filter_Sample_Shape_0,Shape of a texture filter sample" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "Txa_Filter_Kernel_Width_0,Size of filter kernel in sub-samples (texels) in U direction-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "Txa_Filter_Kernel_Height_0,Size of filter kernel in sub-samples (texels) in V direction-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 13.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "Txa_Pitch_0,Unsigned pitch of the texture in texels"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "DAVEHD_TXA_TEXSIZE1,Texture size"
|
|
bitfld.long 0x00 29.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--28. 1. "Txa_Height_1,Height of the texture in texels"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--12. 1. "Txa_Width_1,Width of the texture in texels"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "DAVEHD_TXA_FILTER1,Filter shape size and texture pitch"
|
|
bitfld.long 0x00 30.--31. "Txa_Filter_Sample_Shape_1,Shape of a texture filter sample" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "Txa_Filter_Kernel_Width_1,Size of filter kernel in sub-samples (texels) in U direction-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "Txa_Filter_Kernel_Height_1,Size of filter kernel in sub-samples (texels) in V direction-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 13.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "Txa_Pitch_1,Unsigned pitch of the texture in texels"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "DAVEHD_CMM_TEXUNIT,Global texture unit register"
|
|
bitfld.long 0x00 30.--31. "Txc_Debug_Mode,Texture cache debug mode" "0,1,2,3"
|
|
hexmask.long.word 0x00 14.--29. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "Rld_Pixel_Width,Number of bytes per pixel (0=1byte 1=2bytes 2=3bytes 3=4bytes)" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--11. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "Tex_Depth_Enable,Activate interpolation of depth as additional pair of U/V coordinates" "0,1"
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "Tex_Num_Units,Number of active texture units" "0,1,2,3"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "DAVEHD_COL_COLUNIT,Global color unit registers"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--2. "Col_Num_Passes,Number of active color unit passes" "0,1,2,3,4,5,6,7"
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "DAVEHD_FBD_RDDEC,Framebuffer read decision registers"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Fbd_Alpha_Test_Ref,Alpha test comparison reference value"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 4.--6. "Fbd_Read_Decision_Flags,Framebuffer read decision flags" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 0.--2. "Fbd_Alpha_Test_Op,Alpha test operation: Decides whether the source pixel is passed on or dropped" "0,1,2,3,4,5,6,7"
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "DAVEHD_FBD_DBGCTRL,Framebuffer cache scheduler pitch and debug control"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "Fbs_Debug_Enable,Enable framebuffer cache scheduler debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--12. 1. "Fbs_Pitch,Framebuffer pitch"
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "DAVEHD_FBD_SPANCONF,Framebuffer cache scheduler span config"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Fbs_Read_Gap_Length_Limit,Maximum length of a read gap inside a span for the framebuffer cache in pixels"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Fbs_Span_Length_Limit,Maximum length of a span for the framebuffer cache in pixels-1"
|
|
group.long 0x814++0x03
|
|
line.long 0x00 "DAVEHD_RLD_START,Start address of RLE code of the texture in memory"
|
|
hexmask.long 0x00 0.--31. 1. "Rld_Start_Address,Start address of RLE code of the texture in memory"
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "DAVEHD_COL_CONSTCOL0,constant color registers"
|
|
hexmask.long 0x00 0.--31. 1. "Col_Const_Color_0,constant color register"
|
|
group.long 0x81C++0x03
|
|
line.long 0x00 "DAVEHD_COL_CONSTCOL1,constant color registers"
|
|
hexmask.long 0x00 0.--31. 1. "Col_Const_Color_1,constant color register"
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "DAVEHD_COL_CONSTCOL2,constant color registers"
|
|
hexmask.long 0x00 0.--31. 1. "Col_Const_Color_2,constant color register"
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "DAVEHD_COL_CONSTCOL3,constant color registers"
|
|
hexmask.long 0x00 0.--31. 1. "Col_Const_Color_3,constant color register"
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "DAVEHD_TXA_TEXMODE0,Texture mode"
|
|
bitfld.long 0x00 29.--31. "bf_align5,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "Txp_Discard_Alpha,Boolean value: Set alpha to 1.0 instead of using value read from texture" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23.--27. "bf_align4,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20.--22. "Tex_Virtual_Tiling_Mode_0,Virtual tiling mode of texture" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. "bf_align3,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 16.--18. "Txa_Swizzle_Mode_0,Swizzle mode of texture" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "Tex_Org_0,Texel organization/format of texture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "Tex_Filter_V,Filter enable in V direction" "0,1"
|
|
bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "Txa_Wrap_Mode_V_0,Wrap mode in V direction" "0,1,2,3"
|
|
bitfld.long 0x00 3. "Tex_Filter_U,Filter enable in U direction" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 0.--1. "Txa_Wrap_Mode_U_0,Wrap mode in U direction" "0,1,2,3"
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "DAVEHD_TXA_START0,Start address of top-left texel of the texture in memory"
|
|
hexmask.long 0x00 0.--31. 1. "Txc_Start_Address_0,Start address of top-left texel of the texture in memory"
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "DAVEHD_TXP_CTRL0,TXP control"
|
|
bitfld.long 0x00 31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "Txc_Burst_Pitch_0,Pitch in bytes between two bursts if texture cache operates in virtual tiling mode"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "Txc_Use_Rld,Texture is run length encoded (RLE) use RLD for decoding (since there is only one RLD unit max one of the texture units can set this bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "Txp_Color_Key_Enable,Boolean value: Replace alpha and RGB of pixel by all 0 when color key matches" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 0.--2. "Txp_CLUT_Mode_0,Configure usage of CLUT in texel processing" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "DAVEHD_TXP_CLUTOFFSET0,Offset for all CLUT lookups of the texture unit"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--8. 1. "Txp_CLUT_Offset_0,Offset for all CLUT lookups of the texture unit"
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "DAVEHD_TXP_COLORKEY0,Color key comparison value"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "Txp_Color_Key_0,Color key comparison value"
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "DAVEHD_TXP_FILLCOLOR0,Texel fill color for wrap mode FILL"
|
|
hexmask.long 0x00 0.--31. 1. "Txp_Fill_Color_0,Texel fill color for wrap mode FILL"
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "DAVEHD_TXP_FILTER0,Scale and bias for filter in TXP"
|
|
bitfld.long 0x00 29.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 20.--28. 1. "Txp_Filter_Bias_0,Bias for filtering in TXP unit"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 12.--17. "Txp_Filter_Shift_0,Shift of scale for filtering in TXP unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--9. 1. "Txp_Filter_Scale_0,Scale for filtering in TXP unit"
|
|
group.long 0xA1C++0x03
|
|
line.long 0x00 "DAVEHD_TXA_TEXMODE1,Texture mode"
|
|
bitfld.long 0x00 29.--31. "bf_align5,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "Txp_Discard_Alpha,Boolean value: Set alpha to 1.0 instead of using value read from texture" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23.--27. "bf_align4,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20.--22. "Tex_Virtual_Tiling_Mode_1,Virtual tiling mode of texture" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. "bf_align3,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 16.--18. "Txa_Swizzle_Mode_1,Swizzle mode of texture" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "Tex_Org_1,Texel organization/format of texture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "Tex_Filter_V,Filter enable in V direction" "0,1"
|
|
bitfld.long 0x00 6. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "Txa_Wrap_Mode_V_1,Wrap mode in V direction" "0,1,2,3"
|
|
bitfld.long 0x00 3. "Tex_Filter_U,Filter enable in U direction" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 0.--1. "Txa_Wrap_Mode_U_1,Wrap mode in U direction" "0,1,2,3"
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "DAVEHD_TXA_START1,Start address of top-left texel of the texture in memory"
|
|
hexmask.long 0x00 0.--31. 1. "Txc_Start_Address_1,Start address of top-left texel of the texture in memory"
|
|
group.long 0xA24++0x03
|
|
line.long 0x00 "DAVEHD_TXP_CTRL1,TXP control"
|
|
bitfld.long 0x00 31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "Txc_Burst_Pitch_1,Pitch in bytes between two bursts if texture cache operates in virtual tiling mode"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 8. "Txc_Use_Rld,Texture is run length encoded (RLE) use RLD for decoding (since there is only one RLD unit max one of the texture units can set this bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "Txp_Color_Key_Enable,Boolean value: Replace alpha and RGB of pixel by all 0 when color key matches" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 0.--2. "Txp_CLUT_Mode_1,Configure usage of CLUT in texel processing" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "DAVEHD_TXP_CLUTOFFSET1,Offset for all CLUT lookups of the texture unit"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--8. 1. "Txp_CLUT_Offset_1,Offset for all CLUT lookups of the texture unit"
|
|
group.long 0xA2C++0x03
|
|
line.long 0x00 "DAVEHD_TXP_COLORKEY1,Color key comparison value"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "Txp_Color_Key_1,Color key comparison value"
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "DAVEHD_TXP_FILLCOLOR1,Texel fill color for wrap mode FILL"
|
|
hexmask.long 0x00 0.--31. 1. "Txp_Fill_Color_1,Texel fill color for wrap mode FILL"
|
|
group.long 0xA34++0x03
|
|
line.long 0x00 "DAVEHD_TXP_FILTER1,Scale and bias for filter in TXP"
|
|
bitfld.long 0x00 29.--31. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 20.--28. 1. "Txp_Filter_Bias_1,Bias for filtering in TXP unit"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 12.--17. "Txp_Filter_Shift_1,Shift of scale for filtering in TXP unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--9. 1. "Txp_Filter_Scale_1,Scale for filtering in TXP unit"
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP1ACTRL0,Control structure for Op1a (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op1a_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op1a_Invert_Mode_0,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op1a_Argb_Select_0,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op1a_Input_Select_0,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op1a_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op1a_Invert_Mode_0,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op1a_Argb_Select_0,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op1a_Argb_Select_0,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op1a_Argb_Select_0,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op1a_Input_Select_0,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP1BCTRL0,Control structure for Op1b (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "Col_Alpha_Carry1,Enable carry in for first adder in color unit" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op1b_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op1b_Invert_Mode_0,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op1b_Argb_Select_0,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op1b_Input_Select_0,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "Col_Rgb_Carry1,Enable carry in for first adder in color unit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op1b_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op1b_Invert_Mode_0,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op1b_Argb_Select_0,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op1b_Argb_Select_0,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op1b_Argb_Select_0,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op1b_Input_Select_0,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP2ACTRL0,Control structure for Op2a (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op2a_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op2a_Invert_Mode_0,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op2a_Argb_Select_0,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op2a_Input_Select_0,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op2a_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op2a_Invert_Mode_0,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op2a_Argb_Select_0,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op2a_Argb_Select_0,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op2a_Argb_Select_0,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op2a_Input_Select_0,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB0C++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP2BCTRL0,Control structure for Op2b (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "Col_Alpha_Carry2,Enable carry in for first adder in color unit" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op2b_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op2b_Invert_Mode_0,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op2b_Argb_Select_0,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op2b_Input_Select_0,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "Col_Rgb_Carry2,Enable carry in for first adder in color unit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op2b_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op2b_Invert_Mode_0,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op2b_Argb_Select_0,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op2b_Argb_Select_0,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op2b_Argb_Select_0,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op2b_Input_Select_0,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP3CTRL0,Control structure for Op3 (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op3_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op3_Invert_Mode_0,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op3_Argb_Select_0,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op3_Input_Select_0,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op3_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op3_Invert_Mode_0,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op3_Argb_Select_0,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op3_Argb_Select_0,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op3_Argb_Select_0,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op1a_Input_Select_0,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "DAVEHD_COL_CORECTRL0,Control structure for core output (Alpha and RGB path)"
|
|
bitfld.long 0x00 29.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "Col_Alpha_Clamp_Out,Enable clamping of output value to range 0..255 (-256 to 255 otherwise)" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 18.--27. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16.--17. "Col_Alpha_Scale_Out_0,Select scale mode for output value" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "Col_Rgb_Clamp_Out,Enable clamping of output value to range 0..255 (-256 to 255 otherwise)" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 2.--11. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--1. "Col_Rgb_Scale_Out_0,Select scale mode for output value" "0,1,2,3"
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP1ACTRL1,Control structure for Op1a (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op1a_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op1a_Invert_Mode_1,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op1a_Argb_Select_1,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op1a_Input_Select_1,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op1a_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op1a_Invert_Mode_1,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op1a_Argb_Select_1,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op1a_Argb_Select_1,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op1a_Argb_Select_1,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op1a_Input_Select_1,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP1BCTRL1,Control structure for Op1b (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "Col_Alpha_Carry1,Enable carry in for first adder in color unit" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op1b_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op1b_Invert_Mode_1,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op1b_Argb_Select_1,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op1b_Input_Select_1,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "Col_Rgb_Carry1,Enable carry in for first adder in color unit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op1b_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op1b_Invert_Mode_1,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op1b_Argb_Select_1,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op1b_Argb_Select_1,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op1b_Argb_Select_1,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op1b_Input_Select_1,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP2ACTRL1,Control structure for Op2a (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op2a_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op2a_Invert_Mode_1,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op2a_Argb_Select_1,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op2a_Input_Select_1,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op2a_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op2a_Invert_Mode_1,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op2a_Argb_Select_1,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op2a_Argb_Select_1,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op2a_Argb_Select_1,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op2a_Input_Select_1,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB24++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP2BCTRL1,Control structure for Op2b (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "Col_Alpha_Carry2,Enable carry in for first adder in color unit" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op2b_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op2b_Invert_Mode_1,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op2b_Argb_Select_1,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op2b_Input_Select_1,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "Col_Rgb_Carry2,Enable carry in for first adder in color unit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op2b_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op2b_Invert_Mode_1,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op2b_Argb_Select_1,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op2b_Argb_Select_1,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op2b_Argb_Select_1,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op2b_Input_Select_1,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP3CTRL1,Control structure for Op3 (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op3_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op3_Invert_Mode_1,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op3_Argb_Select_1,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op3_Input_Select_1,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op3_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op3_Invert_Mode_1,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op3_Argb_Select_1,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op3_Argb_Select_1,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op3_Argb_Select_1,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op3_Input_Select_1,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB2C++0x03
|
|
line.long 0x00 "DAVEHD_COL_CORECTRL1,Control structure for core output (Alpha and RGB path)"
|
|
bitfld.long 0x00 29.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "Col_Alpha_Clamp_Out,Enable clamping of output value to range 0..255 (-256 to 255 otherwise)" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 18.--27. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16.--17. "Col_Alpha_Scale_Out_1,Select scale mode for output value" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "Col_Rgb_Clamp_Out,Enable clamping of output value to range 0..255 (-256 to 255 otherwise)" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 2.--11. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--1. "Col_Rgb_Scale_Out_1,Select scale mode for output value" "0,1,2,3"
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP1ACTRL2,Control structure for Op1a (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op1a_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op1a_Invert_Mode_2,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op1a_Argb_Select_2,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op1a_Input_Select_2,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op1a_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op1a_Invert_Mode_2,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op1a_Argb_Select_2,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op1a_Argb_Select_2,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op1a_Argb_Select_2,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op1a_Input_Select_2,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB34++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP1BCTRL2,Control structure for Op1b (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "Col_Alpha_Carry1,Enable carry in for first adder in color unit" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op1b_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op1b_Invert_Mode_2,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op1b_Argb_Select_2,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op1b_Input_Select_2,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "Col_Rgb_Carry1,Enable carry in for first adder in color unit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op1b_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op1b_Invert_Mode_2,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op1b_Argb_Select_2,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op1b_Argb_Select_2,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op1b_Argb_Select_2,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op1b_Input_Select_2,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP2ACTRL2,Control structure for Op2a (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op2a_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op2a_Invert_Mode_2,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op2a_Argb_Select_2,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op2a_Input_Select_2,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op2a_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op2a_Invert_Mode_2,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op2a_Argb_Select_2,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op2a_Argb_Select_2,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op2a_Argb_Select_2,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op2a_Input_Select_2,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB3C++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP2BCTRL2,Control structure for Op2b (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "Col_Alpha_Carry2,Enable carry in for first adder in color unit" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op2b_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op2b_Invert_Mode_2,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op2b_Argb_Select_2,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op2b_Input_Select_2,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "Col_Rgb_Carry2,Enable carry in for first adder in color unit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op2b_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op2b_Invert_Mode_2,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op2b_Argb_Select_2,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op2b_Argb_Select_2,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op2b_Argb_Select_2,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op2b_Input_Select_2,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "DAVEHD_COL_OP3CTRL2,Control structure for Op3 (Alpha and RGB path)"
|
|
bitfld.long 0x00 31. "bf_align4,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 30. "Col_Alpha_Op3_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "Col_Alpha_Op3_Invert_Mode_2,Select inversion mode for Op" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "Col_Alpha_Op3_Argb_Select_2,Select A R G or B for Op" "0,1,2,3"
|
|
bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "Col_Alpha_Op3_Input_Select_2,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "Col_Rgb_Op3_Mul2,Enable shift left by 1 for Op" "0,1"
|
|
bitfld.long 0x00 12.--13. "Col_Rgb_Op3_Invert_Mode_2,Select inversion mode for Op" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "Col_Red_Op3_Argb_Select_2,Select A R G or B for Op (red path)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "Col_Green_Op3_Argb_Select_2,Select A R G or B for Op (green path)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "Col_Blue_Op3_Argb_Select_2,Select A R G or B for Op (blue path)" "0,1,2,3"
|
|
bitfld.long 0x00 5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "Col_Rgb_Op3_Input_Select_2,Select input for Op" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB44++0x03
|
|
line.long 0x00 "DAVEHD_COL_CORECTRL2,Control structure for core output (Alpha and RGB path)"
|
|
bitfld.long 0x00 29.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "Col_Alpha_Clamp_Out,Enable clamping of output value to range 0..255 (-256 to 255 otherwise)" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 18.--27. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16.--17. "Col_Alpha_Scale_Out_2,Select scale mode for output value" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "Col_Rgb_Clamp_Out,Enable clamping of output value to range 0..255 (-256 to 255 otherwise)" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 2.--11. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--1. "Col_Rgb_Scale_Out_2,Select scale mode for output value" "0,1,2,3"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "DAVEHD_BLU_FRBPIXORG,Framebuffer pixel organization/format"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--3. "Fb_Pixel_Org,Framebuffer pixel organization/format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "DAVEHD_FBC_START,Framebuffer start address"
|
|
hexmask.long 0x00 0.--31. 1. "Fbc_Start_Address,Framebuffer start address"
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "DAVEHD_BLU_MODE,Blend unit factor and mode"
|
|
bitfld.long 0x00 31. "Blu_Fb_Postdivide_Enable,Divide color channels by alpha channel after blending (before coverage blending) when enabled" "0,1"
|
|
bitfld.long 0x00 30. "Blu_Fb_Premultiply_Enable,Multiply destination colors by destination alpha before blending when enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "bf_align6,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 28. "Blu_Alpha_Blend_Mode,Alpha channel blending blend mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "bf_align5,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "Blu_Alpha_Src_Blend_Factor_Invert,Destination blend factor inversion for alpha channel blending" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "bf_align4,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "Blu_Alpha_Dst_Blend_Factor_Select,Destination blend factor for alpha channel blending" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "Blu_Alpha_Src_Blend_Factor_Select,Source blend factor for alpha channel blending" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 15. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 12.--14. "Blu_Color_Blend_Mode,Color channel blending blend mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "Blu_Color_Dst_Blend_Factor_Use_Alpha,Destination blend factor A / RGB selection for color channel blending" "0,1"
|
|
bitfld.long 0x00 10. "Blu_Color_Src_Blend_Factor_Use_Alpha,Source blend factor A / RGB selection for color channel blending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "Blu_Color_Dst_Blend_Factor_Invert,Destination blend factor inversion for color channel blending" "0,1"
|
|
bitfld.long 0x00 8. "Blu_Color_Src_Blend_Factor_Invert,Source blend factor inversion for color channel blending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "Blu_Color_Dst_Blend_Factor_Select,Destination blend factor for color channel blending" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "Blu_Color_Src_Blend_Factor_Select,Source blend factor for color channel blending" "0,1,2,3"
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "DAVEHD_BLU_DITHCTRL,Blend unit dither control"
|
|
bitfld.long 0x00 26.--31. "bf_align4,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 24.--25. "Blu_Dither_Shift_Blue,Right shift for the dither value for the blue channel" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "Blu_Dither_Shift_Green,Right shift for the dither value for the green channel" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "Blu_Dither_Shift_Red,Right shift for the dither value for the red channel" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4.--7. "Blu_Dither_Base,X/Y shift of the dither matrix relative to the dither offset of the pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "Blu_Dither_Enable,Enable dithering after blending" "0,1"
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "DAVEHD_BLU_WRCTRL,Blend unit write control"
|
|
hexmask.long.word 0x00 18.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 17. "Blu_Coverage_Debug_Enable,Enable coverage debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "Blu_Coverage_Blending_Enable,Enable coverage blending" "0,1"
|
|
hexmask.long.word 0x00 4.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 3. "Blu_Write_Alpha,Enable writing of the alpha channel" "0,1"
|
|
bitfld.long 0x00 2. "Blu_Write_Red,Enable writing of the red channel" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "Blu_Write_Green,Enable writing of the green channel" "0,1"
|
|
bitfld.long 0x00 0. "Blu_Write_Blue,Enable writing of the blue channel" "0,1"
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "DAVEHD_PFC_ENABLE,Performance counter enable"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--3. "Pfc_Enable,Enable for Performance counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE04++0x03
|
|
line.long 0x00 "DAVEHD_PFC_CLEAR,Performance counter clear"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--3. "Pfc_Clear,Clear for Performance counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE08++0x03
|
|
line.long 0x00 "DAVEHD_PFC_EVENTSEL0,Performance counter event selection"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "Pfc_Event_Select_0,Performance counter event selection"
|
|
group.long 0xE0C++0x03
|
|
line.long 0x00 "DAVEHD_PFC_EVENTSEL1,Performance counter event selection"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "Pfc_Event_Select_1,Performance counter event selection"
|
|
group.long 0xE10++0x03
|
|
line.long 0x00 "DAVEHD_PFC_EVENTSEL2,Performance counter event selection"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "Pfc_Event_Select_2,Performance counter event selection"
|
|
group.long 0xE14++0x03
|
|
line.long 0x00 "DAVEHD_PFC_EVENTSEL3,Performance counter event selection"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 0.--6. 1. "Pfc_Event_Select_3,Performance counter event selection"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "DAVEHD_CLR_VALUE,Clear unit color value"
|
|
hexmask.long 0x00 0.--31. 1. "Clr_Value,Clear unit color value"
|
|
group.long 0xF04++0x03
|
|
line.long 0x00 "DAVEHD_CLR_CONFIG,Clear unit line config"
|
|
bitfld.long 0x00 31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "Clr_Pitch,Clear unit pitch in bytes"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. "Clr_Line_Length,Clear unit line length in bytes-1"
|
|
group.long 0xF08++0x03
|
|
line.long 0x00 "DAVEHD_CLR_LINES,Clear unit number of lines"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16.--19. "Clr_Mask,Clear unit write byte mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "Clr_Num_Lines,Clear unit number of lines-1 (height-1)"
|
|
group.long 0xF0C++0x03
|
|
line.long 0x00 "DAVEHD_CLR_FRBADDR,Framebuffer start address for clear unit"
|
|
hexmask.long 0x00 0.--31. 1. "Clr_Start_Address,Framebuffer start address for clear unit"
|
|
tree.end
|
|
tree "SWITCH_3P"
|
|
base ad:0xF8040000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_REVISION,Revision Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "CUSTOMER_REVISION,Customer revision"
|
|
hexmask.long.word 0x00 0.--15. 1. "CORE_REVISION,Core revision"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_SCRATCH,Scratch Register"
|
|
hexmask.long 0x00 0.--31. 1. "SCRATCH,The Scratch Register provides a memory location to test the register access"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_PORT_ENA,Port Enable"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--2. "PORT_ENA,Port enable bits" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_UCAST_DEFAULT_MASK,Default unicast resolution"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--2. "UCAST_DEFAULT_MASK,Default unicast flooding mask bits" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_VLAN_VERIFY,Verify VLAN domain / Discard unknown"
|
|
hexmask.long.word 0x00 19.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16.--18. "DISCARD_UNKNOWN,When set and a frame is received with a VLAN ID that is unknown or has no VLAN tag the frame is discarded and not forwarded" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 3.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--2. "VLAN_VERIFY,Verify VLAN domain for incoming frame at port" "0,1,2,3,4,5,6,7"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_BCAST_DEFAULT_MASK,Default broadcast resolution"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--2. "BCAST_DEFAULT_MASK,Default broadcast resolution" "0,1,2,3,4,5,6,7"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_MCAST_DEFAULT_MASK,Default multicast resolution"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--2. "MCAST_DEFAULT_MASK,Default multicast resolution" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_INPUT_LEARN_BLOCK,Define port in blocking state and enable or disable learning"
|
|
hexmask.long.word 0x00 19.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16.--18. "DISABLE_LEARNING,When learning is disabled for a port (Bit=1) only Bridge Protocol Data Unit frames will be learned" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 3.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--2. "ENABLE_BLOCKING,When blocking is enabled for a port (Bit=1) only Bridge Protocol data units are accepted on that input all other frames are discarded" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_MGMT_CONFIG,Bridge Management Port Configuration"
|
|
hexmask.long.word 0x00 19.--31. 1. "RESERVED2,Portmask for transmission of management frames"
|
|
bitfld.long 0x00 16.--18. "PORTMASK,Portmask for transmission of management frames" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "PRIORITY,Priority to use for transmitted management frames" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 7. "DISCARD,If set Bridge Protocol Frames are discarded always" "0,1"
|
|
bitfld.long 0x00 6. "ENABLE,If set all Bridge Protocol Frames are forwarded exclusively to the management port specified in bits 3:0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "MESSAGE_TRANSMITTED,Set (latched) when a message was transmitted from the management port to any output port" "0,1"
|
|
bitfld.long 0x00 4. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "PORT,The Port number of the port that should act as a management port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_MODE_CONFIG,Defines several global configuration settings"
|
|
bitfld.long 0x00 31. "STATS_RESET,Self clearing switch statistics reset bit" "0,1"
|
|
hexmask.long 0x00 0.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_VLAN_TAG_ID,The VLAN type field value to expect to identify a VLAN tagged frame"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "VLAN_TAG_ID,VLAN_TAG_ID"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_OQMGR_STATUS,Memory Manager Status"
|
|
hexmask.long 0x00 7.--31. 1. "CELLS_AVAILABLE,Real-time indication of currently available cells in memory"
|
|
bitfld.long 0x00 6. "DEQUEUE_GRANT,Indication of if currently inputs are de-queued" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 3. "MEM_FULL_LATCH,Latched version of mem_full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "MEM_FULL,Current memory full indication" "0,1"
|
|
bitfld.long 0x00 1. "NO_CELL_LATCH,Set when memory has exceeded the maximum available number of cells" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BUSY_INITIALIZING,When set (1) Memory controller is still initializing the memory" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_QMGR_MINCELLS,Low Memory Threshold"
|
|
hexmask.long 0x00 0.--31. 1. "MINCELLS,Low Memory threshold"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_QMGR_ST_MINCELLS,Lowest number of free cells reached"
|
|
hexmask.long 0x00 0.--31. 1. "ST_MINCELLS,Statistic providing the lowest number of free cells reached in memory during operation since this statistics was last cleared"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_QMGR_CGS_STAT,Port Congestion status"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--2. "CONGEST_STAT,Congestion Status" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_QMGR_IFACE_STAT,Switch input and output interface status"
|
|
hexmask.long.word 0x00 19.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16.--18. "RX_FIFO_DATA_AVAILABLE,QMGR_IFACE_STAT bit3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 3.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--2. "TX_FIFO_STAT_RDY,Per port tx fifo status ready indication" "0,1,2,3,4,5,6,7"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_QMGR_WEIGHTS,5-bit Queue weights for each queue"
|
|
bitfld.long 0x00 29.--31. "bf_align3,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. "QUEUE_WEIGHT_3,Weight for Queue 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 21.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. "QUEUE_WEIGHT_2,Weight for Queue 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. "QUEUE_WEIGHT_1,Weight for Queue 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "QUEUE_WEIGHT_0,Weight for Queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_VLAN_PRIORITY$1,VLAN priority resolution"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 21.--23. "INPUT_PRIORITY7,Priority for input 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 18.--20. "INPUT_PRIORITY6,Priority for input 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "INPUT_PRIORITY5,Priority for input 5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INPUT_PRIORITY4,Priority for input 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. "INPUT_PRIORITY3,Priority for input 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "INPUT_PRIORITY2,Priority for input 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--5. "INPUT_PRIORITY1,Priority for input 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "INPUT_PRIORITY0,Priority for input 0" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
|
|
group.long ($2+0x140)++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_IP_PRIORITY$1,IPv4 and IPv6 priority resolution table programming"
|
|
bitfld.long 0x00 31. "READ,Must be cleared to write values in the tables" "0,1"
|
|
hexmask.long.tbyte 0x00 11.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "PRIORITY,The priority information to write into the addressed table entry" "0,1,2,3"
|
|
bitfld.long 0x00 8. "IPV6_SELECT,If set during a write the IPv6 table is accessed" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "ADDRESS,The address of the priority entry to read or write for a frame received on port n"
|
|
repeat.end
|
|
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_PRIORITY_CFG$1,Priority resolution configuration"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 4.--6. "DEFAULT_PRIORITY,The default priority of a frame received on port n if none of the priority resolutions could define a priority of the frame" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 1. "IP_EN,Enable IP priority resolution for frame received on port n" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "VLAN_EN,Enable VLAN priority resolution for frame received on port n" "0,1"
|
|
repeat.end
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_CONTROL,Hub Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED0,HUB_CONTROL bit1"
|
|
bitfld.long 0x00 4.--7. "INTER_PKT_GAP,Inter Packet Gap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "BCAST_FILT_EN,Enable broadcast filter" "0,1"
|
|
bitfld.long 0x00 2. "DIRECT_P1_P0_EN,Enable hub direction from Port 0 to Port 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DIRECT_P0_P1_EN,Enable hub direction from Port 0 to Port 1" "0,1"
|
|
bitfld.long 0x00 0. "EXT_MODULE_EN,Enable hub extension module" "0,1"
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_STATS,Hub Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "FRM_NUM_P1_P0,Number of frames forwarded through the hub from port 1 to port 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "FRM_NUM_P0_P1,Number of frames forwarded through the hub from port 0 to port 1"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC0_LO,Hub Receive Filtering address lower bytes"
|
|
hexmask.long 0x00 0.--31. 1. "FLT_MAC0_LO,First 4 octets of MAC address 0"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC0_HI,Hub Receive Filtering address upper bytes"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "FORCE_FWD_EN,Force forward enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "COMP_MASK0,8-bit mask for comparing the last byte of the MAC address"
|
|
hexmask.long.word 0x00 0.--15. 1. "FLT_MAC0_HI,Last 2 octets of MAC address 0"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC1_LO,Hub Receive Filtering address lower bytes"
|
|
hexmask.long 0x00 0.--31. 1. "FLT_MAC1_LO,First 4 octets of MAC address 1"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC1_HI,Hub Receive Filtering address upper bytes"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "FORCE_FWD_EN,Force forward enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "COMP_MASK1,8-bit mask for comparing the last byte of the MAC address"
|
|
hexmask.long.word 0x00 0.--15. 1. "FLT_MAC1_HI,Last 2 octets of MAC address 0"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC2_LO,Hub Receive Filtering address lower bytes"
|
|
hexmask.long 0x00 0.--31. 1. "FLT_MAC2_LO,First 4 octets of MAC address 2"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC2_HI,Hub Receive Filtering address upper bytes"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "FORCE_FWD_EN,Force forward enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "COMP_MASK2,8-bit mask for comparing the last byte of the MAC address"
|
|
hexmask.long.word 0x00 0.--15. 1. "FLT_MAC2_HI,Last 2 octets of MAC address 0"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC3_LO,Hub Receive Filtering address lower bytes"
|
|
hexmask.long 0x00 0.--31. 1. "FLT_MAC3_LO,First 4 octets of MAC address 3"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC3_HI,Hub Receive Filtering address upper bytes"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "FORCE_FWD_EN,Force forward enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "COMP_MASK3,8-bit mask for comparing the last byte of the MAC address"
|
|
hexmask.long.word 0x00 0.--15. 1. "FLT_MAC3_HI,Last 2 octets of MAC address 0"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC4_LO,Hub Receive Filtering address lower bytes"
|
|
hexmask.long 0x00 0.--31. 1. "FLT_MAC4_LO,First 4 octets of MAC address 4"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC4_HI,Hub Receive Filtering address upper bytes"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "FORCE_FWD_EN,Force forward enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "COMP_MASK4,8-bit mask for comparing the last byte of the MAC address"
|
|
hexmask.long.word 0x00 0.--15. 1. "FLT_MAC4_HI,Last 2 octets of MAC address 0"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC5_LO,Hub Receive Filtering address lower bytes"
|
|
hexmask.long 0x00 0.--31. 1. "FLT_MAC5_LO,First 4 octets of MAC address 5"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC5_HI,Hub Receive Filtering address upper bytes"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "FORCE_FWD_EN,Force forward enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "COMP_MASK5,8-bit mask for comparing the last byte of the MAC address"
|
|
hexmask.long.word 0x00 0.--15. 1. "FLT_MAC5_HI,Last 2 octets of MAC address 0"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC6_LO,Hub Receive Filtering address lower bytes"
|
|
hexmask.long 0x00 0.--31. 1. "FLT_MAC6_LO,First 4 octets of MAC address 6"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_HUB_FLT_MAC6_HI,Hub Receive Filtering address upper bytes"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "FORCE_FWD_EN,Force forward enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "COMP_MASK6,8-bit mask for comparing the last byte of the MAC address"
|
|
hexmask.long.word 0x00 0.--15. 1. "FLT_MAC6_HI,Last 2 octets of MAC address 0"
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x280)++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_VLAN_RES_TABLE$1,VLAN Resolution Table entry $1"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 3.--14. 1. "VLAN_ID,VLAN ID"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "PORT_MASK,Port mask bits" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x2C0)++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_VLAN_RES_TABLE$1,VLAN Resolution Table entry $1"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 3.--14. 1. "VLAN_ID,VLAN ID"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "PORT_MASK,Port mask bits" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_TOTAL_BYTE_FRM,Sum of bytes of frames counted in TOTAL_FRM"
|
|
hexmask.long 0x00 0.--31. 1. "TOTAL_BYTE_FRM,Sum of bytes of frames counted in TOTAL_FRM"
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_TOTAL_BYT_DISC,Sum of bytes of frames counted in TOTAL_DISC"
|
|
hexmask.long 0x00 0.--31. 1. "TOTAL_BYT_DISC,Sum of bytes of frames counted in TOTAL_DISC"
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_TOTAL_FRM,Total number of incoming frames processed and not discarded"
|
|
hexmask.long 0x00 0.--31. 1. "TOTAL_FRM,Total number of incoming frames processed and not discarded"
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_TOTAL_DISC,Total number of incoming frames processed but discarded"
|
|
hexmask.long 0x00 0.--31. 1. "TOTAL_DISC,Total number of incoming frames processed but discarded in the switch"
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_ODISC0,Port0 Outgoing frames discarded due to output Queue congestion"
|
|
hexmask.long 0x00 0.--31. 1. "ODISC0,Port 0 Outgoing frames discarded due to output Queue congestion"
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_IDISC_BLOCKED0,Port0 Incoming frames discarded due to blocking mode"
|
|
hexmask.long 0x00 0.--31. 1. "IDISC_BLOCKED0,Port 0 incoming frames discarded (after learning) as port is configured in blocking mode"
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_ODISC1,Port1 Outgoing frames discarded due to output Queue congestion"
|
|
hexmask.long 0x00 0.--31. 1. "ODISC1,Port 1 Outgoing frames discarded due to output Queue congestion"
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_IDISC_BLOCKED1,Port1 Incoming frames discarded due to blocking mode"
|
|
hexmask.long 0x00 0.--31. 1. "IDISC_BLOCKED1,Port 1 incoming frames discarded (after learning) as port is configured in blocking mode"
|
|
rgroup.long 0x320++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_ODISC2,Port2 Outgoing frames discarded due to output Queue congestion"
|
|
hexmask.long 0x00 0.--31. 1. "ODISC2,Port 2 Outgoing frames discarded due to output Queue congestion"
|
|
rgroup.long 0x324++0x03
|
|
line.long 0x00 "SWITCH_3P_SWITCH_IDISC_BLOCKED2,Port2 Incoming frames discarded due to blocking mode"
|
|
hexmask.long 0x00 0.--31. 1. "IDISC_BLOCKED2,Port 2 incoming frames discarded (after learning) as port is configured in blocking mode"
|
|
rgroup.long 0x500++0x03
|
|
line.long 0x00 "SWITCH_3P_LRN_REC_A,Learning Record A"
|
|
hexmask.long 0x00 0.--31. 1. "LRN_REC_A,Learning Record A"
|
|
rgroup.long 0x504++0x03
|
|
line.long 0x00 "SWITCH_3P_LRN_REC_B,Learning Record B"
|
|
hexmask.long 0x00 0.--31. 1. "LRN_REC_B,Learning Record B"
|
|
rgroup.long 0x508++0x03
|
|
line.long 0x00 "SWITCH_3P_LRN_STATUS,Learning data available status"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "LRN_STATUS,Learning data available status" "0,1"
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "SWITCH_3P_MDIO0_CFG_STATUS,MDIO Configuration and Status register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 7.--15. 1. "CLK_DIV,Clock divisor"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 5. "DIS_PREAMBLE,Disable Preamble" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--4. "HOLD_TIME,Hold time setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "READ_ERR,Read error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BUSY,Busy" "0,1"
|
|
group.long 0x704++0x03
|
|
line.long 0x00 "SWITCH_3P_MDIO0_COMMAND,MDIO PHY Address and Port"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "WR_RD,If written with 1 a read transaction is initiated" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "RESERVED01,MDIO0_COMMAND bit0" "0,1"
|
|
bitfld.long 0x00 10.--13. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "PHY_ADDR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "REG_ADDR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x708++0x03
|
|
line.long 0x00 "SWITCH_3P_MDIO0_DATA,16 bit data word for read/write transactions"
|
|
bitfld.long 0x00 31. "BUSY,reserved value" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DATA,16 bit data word for read/write transactions"
|
|
group.long 0x710++0x03
|
|
line.long 0x00 "SWITCH_3P_MDIO1_CFG_STATUS,MDIO Configuration and Status register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 7.--15. 1. "CLK_DIV,Clock divisor"
|
|
newline
|
|
bitfld.long 0x00 6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 5. "DIS_PREAMBLE,Disable Preamble" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--4. "HOLD_TIME,Hold time setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "READ_ERR,Read error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BUSY,Busy" "0,1"
|
|
group.long 0x714++0x03
|
|
line.long 0x00 "SWITCH_3P_MDIO1_COMMAND,MDIO PHY Address and Port"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "WR_RD,If written with 1 a read transaction is initiated" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "RESERVED01,MDIO1_COMMAND bit0" "0,1"
|
|
bitfld.long 0x00 10.--13. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "PHY_ADDR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "REG_ADDR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x718++0x03
|
|
line.long 0x00 "SWITCH_3P_MDIO1_DATA,16 bit data word for read/write transactions"
|
|
bitfld.long 0x00 31. "BUSY,reserved value" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DATA,16 bit data word for read/write transactions"
|
|
group.long 0x1800++0x03
|
|
line.long 0x00 "SWITCH_3P_FIFO_CMD_STAT,Command/Status Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 24. "SW_RESET,Self-Clearing Reset Command Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "TX_SECTION_EMPTY,Transmit transaction state-machine is idle" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "TX_IDLE,Transmit transaction state-machine is idle" "0,1"
|
|
bitfld.long 0x00 13.--14. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12. "RX_FRAME_AVAIL,Receive frame available" "0,1"
|
|
hexmask.long.word 0x00 3.--11. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 2. "ENDIAN_CONV,Enable endian conversion" "0,1"
|
|
bitfld.long 0x00 1. "RX_ENABLE,Enable receive" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TX_ENABLE,Enable transmit" "0,1"
|
|
group.long 0x1804++0x03
|
|
line.long 0x00 "SWITCH_3P_FIFO_IRQ_CONTROL,Interrupt Control"
|
|
bitfld.long 0x00 31. "ATOMIC_AND,When set during a register-write the enable bits are AND'ed with the current setting of the register (i.e. clearing bits)" "0,1"
|
|
bitfld.long 0x00 30. "ATOMIC_OR,When set during a register-write the enable bits are OR'ed into the current setting of the register (i.e. setting bits)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "LOW_INT_EN,Enable active low interrupt" "0,1"
|
|
hexmask.long.word 0x00 17.--28. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16. "PORT1_LINK_CHANGE_EVENT_ENA,Enable Link change interrupt event for Port 1" "0,1"
|
|
bitfld.long 0x00 15. "PORT0_LINK_CHANGE_EVENT_ENA,Enable Link change interrupt event for Port 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 13. "TX_TIMESTAMP_CAPTURE_EVENT_PORT1_ENA,Enable interrupt on TX timestamp capture event on port1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "TX_TIMESTAMP_CAPTURE_EVENT_PORT0_ENA,Enable interrupt on TX timestamp capture event on port0" "0,1"
|
|
bitfld.long 0x00 11. "TIMER_PERIODIC_EVENT_ENA,Enable Interrupt on Timer periodic event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--10. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4. "IRQ_MDIO1_DONE_ENA,Enable interrupt when Port 1 MDIO read/write transaction done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IRQ_MDIO0_DONE_ENA,Enable interrupt when Port 0 MDIO read/write transaction done" "0,1"
|
|
bitfld.long 0x00 2. "IRQ_TX_SECTION_ENA,Transmit FIFO section interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "IRQ_TX_IDLE_ENA,Bridge TX FIFO state machine Idle interrupt" "0,1"
|
|
bitfld.long 0x00 0. "IRQ_RX_ENA,Enable receive interrupt" "0,1"
|
|
group.long 0x1808++0x03
|
|
line.long 0x00 "SWITCH_3P_FIFO_IRQ_STAT_ACK,Interrupt Status/Acknowledgement"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 16. "PORT1_LINK_CHNAGE_EVENT_PENDING,Latched link status change event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "PORT0_LINK_CHNAGE_EVENT_PENDING,Latched link status change event" "0,1"
|
|
bitfld.long 0x00 14. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "TX_TIMESTAMP_CAPTURE_EVENT_PORT1_PENDING,Latched Interrupt on TX timestamp capture event on port1" "0,1"
|
|
bitfld.long 0x00 12. "TX_TIMESTAMP_CAPTURE_EVENT_PORT0_PENDING,Latched Interrupt on TX timestamp capture event on port0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "TIMER_PERIODIC_EVENT_PENDING,Latched Interrupt on Timer periodic event" "0,1"
|
|
bitfld.long 0x00 5.--10. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4. "MDIO1_DONE_LATCH,Latched Port 1 MDIO transaction done status" "0,1"
|
|
bitfld.long 0x00 3. "MDIO0_DONE_LATCH,Latched Port 0 MDIO transaction done status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TX_IRQ_SECTION_PENDING,Unmasked transmit section interrupt indication" "0,1"
|
|
bitfld.long 0x00 1. "TX_IRQ_IDLE_PENDING,Unmasked transmit state machine idle interrupt indication" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RX_IRQ_PENDING,Unmasked receive interrupt indication" "0,1"
|
|
group.long 0x180C++0x03
|
|
line.long 0x00 "SWITCH_3P_FIFO_TX_CMD_STAT,Transmit Transaction control and status"
|
|
bitfld.long 0x00 31. "FRAME_COMPLETE,Must be written with '1' before any write occurs to the transmit data FIFO" "0,1"
|
|
hexmask.long.word 0x00 19.--30. 1. "EXTENDED_STATUS_CONTROLL,A 12-bit vector that is available for control of special functions per frame (tx_xstat(11:0))"
|
|
newline
|
|
bitfld.long 0x00 18. "SHIFT,Indicates to the transmit data FIFO that the frame will be written with 2 additional octets before the frame data" "0,1"
|
|
bitfld.long 0x00 17. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "SET_ERROR,If written with '1' at same time as FRAME_COMPLETE the frame will be transmitted with an error indication or discarded" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "FRAME_LENGTH,Length of frame in bytes to transmit"
|
|
group.long 0x1810++0x03
|
|
line.long 0x00 "SWITCH_3P_FIFO_RX_CMD_STAT,Receive Transaction control and status"
|
|
bitfld.long 0x00 31. "VALID,All bits in this register are valid only when the VALID bit is set" "0,1"
|
|
bitfld.long 0x00 28.--30. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. "FDISCARD_CMD,Frame discard command" "0,1"
|
|
bitfld.long 0x00 26. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "SHIFT,If set 1 instructs the MAC to write 2 additional bytes in front of each frame received into the RX FIFO" "0,1"
|
|
bitfld.long 0x00 24. "READ_CMD,Writing this bit with '1' removes the current status from the MAC internal frame status FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 17.--21. "EXTENDED_STATUS,External 5-bit vector that was provided with the frame during end-of-packet (see pin rx_xstat)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16. "ERROR,The frame was received with an error" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "FRAME_LENGTH,Length of frame received"
|
|
rgroup.long 0x1814++0x03
|
|
line.long 0x00 "SWITCH_3P_FIFO_RX_DISCARDED,Number of discarded frames in receive due to bridge internal buffer overflow"
|
|
hexmask.long 0x00 0.--31. 1. "RX_DISCARDED,Counter showing discarded frames in receive due to bridge internal buffer overflow"
|
|
group.long 0x181C++0x03
|
|
line.long 0x00 "SWITCH_3P_FIFO_TX_SECTION_EMPTY,Transmit FIFO threshold"
|
|
hexmask.long 0x00 0.--31. 1. "TX_FIFO_THRESHOLD,Transmit FIFO threshold"
|
|
rgroup.long 0x1820++0x03
|
|
line.long 0x00 "SWITCH_3P_FIFO_RX_FRM_TS,Received timestamp of the frame"
|
|
hexmask.long 0x00 0.--31. 1. "RX_FRM_TS,Received timestamp of the frame"
|
|
group.long 0x1830++0x03
|
|
line.long 0x00 "SWITCH_3P_FIFO_MGMT_TAG_CONFIG,Configure the management port specific frame tagging function"
|
|
hexmask.long.word 0x00 16.--31. 1. "TAGFIELD,The value of the tag that is found in the first type/length field of the frame to identify that the control information is present within a frame"
|
|
hexmask.long.word 0x00 2.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 1. "ALL_FRAMES,Enable Tag insertion for all frames" "0,1"
|
|
bitfld.long 0x00 0. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
rgroup.long 0x8000++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_REV,Design Revision"
|
|
hexmask.long.word 0x00 16.--31. 1. "CUSTOMER_REVISION,Customer specific revision"
|
|
hexmask.long.word 0x00 0.--15. 1. "CORE_REVISION,Core revision"
|
|
group.long 0x8004++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_SCRATCH,Scratch Register"
|
|
hexmask.long 0x00 0.--31. 1. "SCRATCH,Scratch register"
|
|
group.long 0x8008++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_COMMAND_CONFIG,Command Register"
|
|
bitfld.long 0x00 31. "CNT_RESET,Self-Clearing Counter Reset Command" "0,1"
|
|
bitfld.long 0x00 27.--30. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "RX_ERR_DISC,Receive Errored Frame Discard Enable" "0,1"
|
|
bitfld.long 0x00 25. "ENA,10Mbps Interface Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "NO_LGTH_CHECK,Payload Length Check Disable" "0,1"
|
|
bitfld.long 0x00 23. "CNTL_FRM_ENA,MAC Control Frame Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "LOOP_ENA,Enable GMII / MII loopback when set to 1 normal operation when set to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "MHASH_SEL,Multicast Address Resolution Hash Code Option" "0,1"
|
|
bitfld.long 0x00 13. "SW_RESET,Self-Clearing Software Reset Command" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 10. "HD_ENA,Half duplex enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "TX_ADDR_INS,Set MAC address on transmit" "0,1"
|
|
bitfld.long 0x00 8. "PAUSE_IGNORE,Ignore Pause Frame Quanta" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "PAUSE_FWD,Terminate / Forward Pause Frames" "0,1"
|
|
bitfld.long 0x00 6. "CRC_FWD,Terminate / Forward Received CRC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PAD_EN,Enable / Disable Frame Padding" "0,1"
|
|
bitfld.long 0x00 4. "PROMIS_EN,Enable / Disable MAC promiscuous operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ETH_SPEED,Enable Gigabit Ethernet operation (GMII) when set to 1 enable 10/100Mbps Ethernet operation (MII) when set to 0" "0,1"
|
|
bitfld.long 0x00 2. "TX_CRC_FWD,Write 0 always" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RX_ENA,Enable / Disable MAC receive path" "0,1"
|
|
bitfld.long 0x00 0. "TX_ENA,Enable / Disable MAC transmit path" "0,1"
|
|
group.long 0x8014++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_FRM_LENGTH,Maximum Frame Length"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--13. 1. "MAX_FRM_LNGTH,Maximum Frame Length"
|
|
group.long 0x8018++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_PAUSE_QUANT,Receive Pause Quanta"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED0,MAC_0_PAUSE_QUANT bit0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RX_PAUSE_QUANT,Receive Pause Quanta"
|
|
rgroup.long 0x801C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_SECTION_EMPTY,Receive FIFO section empty threshold"
|
|
hexmask.long 0x00 0.--31. 1. "RX_SECTION_EMPTY,Receive FIFO section empty threshold"
|
|
rgroup.long 0x8020++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_SECTION_FULL,Receive FIFO section full threshold"
|
|
hexmask.long 0x00 0.--31. 1. "RX_SECTION_FULL,Receive FIFO section full threshold"
|
|
group.long 0x8024++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_SECTION_EMPTY,Transmit FIFO section empty threshold"
|
|
hexmask.long 0x00 0.--31. 1. "TX_SECTION_EMPTY,Transmit FIFO section empty threshold"
|
|
group.long 0x8028++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_SECTION_FULL,Transmit FIFO section full threshold"
|
|
hexmask.long 0x00 0.--31. 1. "TX_SECTION_FULL,Transmit FIFO section full threshold"
|
|
rgroup.long 0x802C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ALMOST_EMPTY,Receive FIFO almost empty threshold"
|
|
hexmask.long 0x00 0.--31. 1. "RX_ALMOST_EMPTY,Receive FIFO almost empty threshold"
|
|
rgroup.long 0x8030++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ALMOST_FULL,Receive FIFO almost full threshold"
|
|
hexmask.long 0x00 0.--31. 1. "RX_ALMOST_FULL,Receive FIFO almost full threshold"
|
|
rgroup.long 0x8034++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ALMOST_EMPTY,Transmit FIFO almost empty threshold"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ALMOST_EMPTY,Transmit FIFO almost empty threshold"
|
|
rgroup.long 0x8038++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ALMOST_FULL,Transmit FIFO almost full threshold"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ALMOST_FULL,Transmit FIFO almost full threshold"
|
|
rgroup.long 0x8058++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_STATUS,Status information for both MACs"
|
|
hexmask.long.word 0x00 17.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15.--16. "RESERVED2,MAC_0_STATUS bit1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14. "MAC_1_CURR_HD_SET,Current Halfduplex setting" "0,1"
|
|
bitfld.long 0x00 13. "MAC_1_CURR_ENA,Current ena_10" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "MAC_1_CURR_SPD,Current Speed" "0,1"
|
|
bitfld.long 0x00 11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "MAC_0_CURR_HD_SET,Current Halfduplex setting" "0,1"
|
|
bitfld.long 0x00 9. "MAC_0_CURR_ENA,Current ena_10" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "MAC_0_CURR_SPD,Current Speed" "0,1"
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "REG_IF_ERR,Register interface error occured" "0,1"
|
|
group.long 0x805C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_IPG_LENGTH,Programmable Inter-Packet Gap"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--4. "TX_IPG_LENGTH,Programmable Inter-Packet Gap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x8100++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_OCTETS,Total octets good and bad frames"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_OCTETS,Total octets good and bad frames"
|
|
rgroup.long 0x8104++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_OCTETS_OK,Total octets good frames only"
|
|
hexmask.long 0x00 0.--31. 1. "OCTETS_OK,Total octets good frames only"
|
|
rgroup.long 0x8108++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_A_ALIGNMENT_ERRORS,Counts when mii_rx_dv deasserted but no SFD (0xd5) was detected (i.e. missing frame start)"
|
|
hexmask.long 0x00 0.--31. 1. "A_ALIGNMENT_ERRORS,Counts when mii_rx_dv deasserted but no SFD (0xd5) was detected (i.e. missing frame start)"
|
|
rgroup.long 0x810C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_A_PAUSE_MAC_CTRL_FRAMES,Good pause frames received"
|
|
hexmask.long 0x00 0.--31. 1. "A_PAUSE_MAC_CTRL_FRAMES,Good pause frames received"
|
|
rgroup.long 0x8110++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_FRAMES_OK,Good frames received"
|
|
hexmask.long 0x00 0.--31. 1. "FRAMES_OK,Good frames received"
|
|
rgroup.long 0x8114++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_CRC_ERRORS,Wrong CRC but good length (64..MTU)"
|
|
hexmask.long 0x00 0.--31. 1. "CRC_ERRORS,Wrong CRC but good length"
|
|
rgroup.long 0x8118++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_VLAN_OK,Good VLAN tagged"
|
|
hexmask.long 0x00 0.--31. 1. "VLAN_OK,Good VLAN tagged"
|
|
rgroup.long 0x811C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_IFLN_ERRORS,Counts for any receive errors"
|
|
hexmask.long 0x00 0.--31. 1. "IFLN_ERRORS,Counts for any receive errors"
|
|
rgroup.long 0x8120++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_IFLN_UCAST_PKTS,Good Unicast"
|
|
hexmask.long 0x00 0.--31. 1. "IFLN_UCAST_PKTS,Good Unicast"
|
|
rgroup.long 0x8124++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_IFLN_MULTICAST_PKTS,Good Multicast"
|
|
hexmask.long 0x00 0.--31. 1. "IFLN_MULTICAST_PKTS,Good Multicast"
|
|
rgroup.long 0x8128++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_IFLN_BROADCAST_PKTS,Good Broadcast"
|
|
hexmask.long 0x00 0.--31. 1. "IFLN_BROADCAST_PKTS,Good Broadcast"
|
|
rgroup.long 0x812C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_DROP_EVENTS,Increments when frames are dropped due to receive FIFO full at begin of frame"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_DROP_EVENTS,Increments when frames are dropped due to receive FIFO full at begin of frame"
|
|
rgroup.long 0x8130++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_PKTS,Total frames good & bad"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS,Total frames good & bad"
|
|
rgroup.long 0x8134++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_UNDERSIZE_PKTS,Frames with length less 64 bytes and good CRC"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_UNDERSIZE_PKTS,Frames with length less 64 bytes and good CRC"
|
|
rgroup.long 0x8138++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_PKTS_64_OCTETS,Frames with length of 64 bytes"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_64_OCTETS,Frames with length of 64 bytes"
|
|
rgroup.long 0x813C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_PKTS_65_127_OCTETS,Frames with length from 65"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_65_127_OCTETS,Frames with length from 65"
|
|
rgroup.long 0x8140++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_PKTS_128_255_OCTETS,Frames with length from 128"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_128_255_OCTETS,Frames with length from 128"
|
|
rgroup.long 0x8144++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_PKTS_256_511_OCTETS,Frames with length from 256"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_256_511_OCTETS,frames with length from 256"
|
|
rgroup.long 0x8148++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_PKTS_512_1023_OCTETS,Frames with length from 512"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_512_1023_OCTETS,Frames with length from 512"
|
|
rgroup.long 0x814C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_PKTS_1024_1518_OCTETS,Frames with length from 1024"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_1024_1518_OCTETS,Frames with length from 1024"
|
|
rgroup.long 0x8150++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_PKTS_1519_TO_MAX,Frames with length from 1519"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_1519_TO_MAX,Frames with length from 1519"
|
|
rgroup.long 0x8154++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_OVERSIZED_PKTS,Frames with length exceeding FRM_LENGTH good CRC"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_OVERSIZED_PKTS,Frames with length exceeding FRM_LENGTH good CRC"
|
|
rgroup.long 0x8158++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_JABBERS,Frames with length exceeding FRM_LENGTH bad CRC"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_JABBERS,Frames with length exceeding FRM_LENGTH bad CRC"
|
|
rgroup.long 0x815C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_ETHER_STATS_FRAGMENTS,Frames with length less 64 and bad CRC"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_FRAGMENTS,Frames with length less 64 and bad CRC"
|
|
rgroup.long 0x8160++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_A_MAC_CONTROL_FRAMES_RECEIVED,Good Frames with type 0x8808 (incl. Pause)"
|
|
hexmask.long 0x00 0.--31. 1. "A_MAC_CONTROL_FRAMES_RECEIVED,Good Frames with type 0x8808"
|
|
rgroup.long 0x8164++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_A_FRAME_TOO_LONG,Total frames exceeding FRAME_LENGTH good & bad"
|
|
hexmask.long 0x00 0.--31. 1. "A_FRAME_TOO_LONG,Total frames exceeding FRAME_LENGTH good & bad"
|
|
rgroup.long 0x816C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_STACKED_VLAN_OK,Good with stacked VLAN (two VLAN tags)"
|
|
hexmask.long 0x00 0.--31. 1. "STACKED_VLAN_OK,Good with stacked VLAN (two VLAN tags)"
|
|
rgroup.long 0x8170++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_RX_HUB_DISCARD,Frames discarded by the HUB/DLR module"
|
|
hexmask.long 0x00 0.--31. 1. "HUB_DISCARD,Frames discarded by the HUB/DLR module"
|
|
rgroup.long 0x8180++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_OCTETS,Total octets good and bad frames"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_OCTETS,Total octets good and bad frames"
|
|
rgroup.long 0x8184++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_OCTETS_OK,Total good"
|
|
hexmask.long 0x00 0.--31. 1. "TX_OCTETS_OK,Total good"
|
|
rgroup.long 0x818C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_A_PAUSE_MAC_CTRL_FRAMES,Good pause transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TX_A_PAUSE_MAC_CTRL_FRAMES,Good pause transmitted"
|
|
rgroup.long 0x8190++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_FRAMES_OK,Good pause transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TX_FRAMES_OK,Good transmitted"
|
|
rgroup.long 0x8194++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_CRC_ERRORS,Transmitted with error but good length (ff_tx_err)"
|
|
hexmask.long 0x00 0.--31. 1. "TX_CRC_ERRORS,Transmitted with error but good length"
|
|
rgroup.long 0x8198++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_VLAN_OK,Good VLAN tagged"
|
|
hexmask.long 0x00 0.--31. 1. "TX_VLAN_OK,Good VLAN tagged"
|
|
rgroup.long 0x819C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_IF_OUT_ERRORS,Any error (ff_tx_err toolong but not counting undersized)"
|
|
hexmask.long 0x00 0.--31. 1. "IF_OUT_ERRORS,Any error"
|
|
rgroup.long 0x81A0++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_IF_UCAST_PKTS,Good Unicast"
|
|
hexmask.long 0x00 0.--31. 1. "IF_UCAST_PKTS,Good Unicast"
|
|
rgroup.long 0x81A4++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_IF_MULTICAST_PKTS,Good Multicast"
|
|
hexmask.long 0x00 0.--31. 1. "IF_MULTICAST_PKTS,Good Multicast"
|
|
rgroup.long 0x81A8++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_IF_BROADCAST_PKTS,Good Broadcast"
|
|
hexmask.long 0x00 0.--31. 1. "IF_BROADCAST_PKTS,Good Broadcast"
|
|
rgroup.long 0x81AC++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_DROP_EVENTS,Counts undersized frames transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_DROP_EVENTS,Counts undersized frames transmitted"
|
|
rgroup.long 0x81B0++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_PKTS,Total frames good & bad"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS,Total frames good & bad"
|
|
rgroup.long 0x81B4++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_UNDERSIZE_PKTS,Frames with length less 64 bytes and good CRC"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_UNDERSIZE_PKTS,Frames with length less 64 bytes and good CRC"
|
|
rgroup.long 0x81B8++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_PKTS_64_OCTETS,Frames with length of 64 bytes"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_64_OCTETS,Frames with length of 64 bytes"
|
|
rgroup.long 0x81BC++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_PKTS_65_127_OCTETS,Frames with length from 65"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_65_127_OCTETS,Frames with length from 65"
|
|
rgroup.long 0x81C0++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_PKTS_128_255_OCTETS,Frames with length from 128"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_128_255_OCTETS,Frames with length from 128"
|
|
rgroup.long 0x81C4++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_PKTS_256_511_OCTETS,Frames with length from 256"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_256_511_OCTETS,Frames with length from 256"
|
|
rgroup.long 0x81C8++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_PKTS_512_1023_OCTETS,Frames with length from 512"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_512_1023_OCTETS,Frames with length from 512"
|
|
rgroup.long 0x81CC++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_PKTS_1024_1518_OCTETS,Frames with length from 1024"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_1024_1518_OCTETS,Frames with length from 1024"
|
|
rgroup.long 0x81D0++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_PKTS_1519_TO_MAX,Frames with length from 1519"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_1519_TO_MAX,Frames with length from 1519"
|
|
rgroup.long 0x81D4++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_OVERSIZED_PKTS,Frames with length exceeding FRM_LENGTH good CRC"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_OVERSIZED_PKTS,Frames with length exceeding FRM_LENGTH good"
|
|
rgroup.long 0x81D8++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_JABBERS,Frames with length exceeding FRM_LENGTH bad CRC"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_JABBERS,Frames with length exceeding FRM_LENGTH bad"
|
|
rgroup.long 0x81DC++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_ETHER_STATS_FRAGMENTS,Frames with length less 64 and bad CRC"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_FRAGMENTS,Frames with length less 64 bytes and marked erronenous"
|
|
rgroup.long 0x81E0++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_A_MAC_CONTOL_FRAMES,Good frames with type 0x8808 (incl. Pause)"
|
|
hexmask.long 0x00 0.--31. 1. "A_MAC_CONTOL_FRAMES,Good frames with type 0x8808"
|
|
rgroup.long 0x81E4++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_A_FRAME_TOO_LONG,Total frames exceeding FRAME_LENGTH good & bad"
|
|
hexmask.long 0x00 0.--31. 1. "TX_A_FRAME_TOO_LONG,Total frames exceeding FRAME_LENGTH good & bad"
|
|
rgroup.long 0x81E8++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_A_DEFERRED,Not implemented always 0"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x81EC++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_A_MULTIPLE_COLLISIONS,Successful transmissions after multiple collisions"
|
|
hexmask.long 0x00 0.--31. 1. "A_MULTIPLE_COLLISIONS,Successful transmissions after multiple collisions"
|
|
rgroup.long 0x81F0++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_A_SINGLE_COLLISIONS,Successful transmissions after one collision"
|
|
hexmask.long 0x00 0.--31. 1. "A_SINGLE_COLLISIONS,Successful transmissions after one collisions"
|
|
rgroup.long 0x81F4++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_A_LATE_COLLISIONS,Frames transmitted in error due to late collisions"
|
|
hexmask.long 0x00 0.--31. 1. "A_LATE_COLLISIONS,Frames transmitted in error due to late collisions"
|
|
rgroup.long 0x81F8++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_0_TX_A_EXCESS_COLLISIONS,Frames dropped due to excessive collisions (16 unsuccessful transmits)"
|
|
hexmask.long 0x00 0.--31. 1. "A_EXCESS_COLLISIONS,Frames dropped due to excessive collisions (16 unsuccessful transmits)"
|
|
rgroup.long 0xA000++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_REV,Design Revision"
|
|
hexmask.long.word 0x00 16.--31. 1. "CUSTOMER_REVISION,Customer specific revision"
|
|
hexmask.long.word 0x00 0.--15. 1. "CORE_REVISION,Core revision"
|
|
group.long 0xA004++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_SCRATCH,Scratch Register"
|
|
hexmask.long 0x00 0.--31. 1. "SCRATCH,Scratch register"
|
|
group.long 0xA008++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_COMMAND_CONFIG,Command Register"
|
|
bitfld.long 0x00 31. "CNT_RESET,Self-Clearing Counter Reset Command" "0,1"
|
|
bitfld.long 0x00 27.--30. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "RX_ERR_DISC,Receive Errored Frame Discard Enable" "0,1"
|
|
bitfld.long 0x00 25. "ENA,10Mbps Interface Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "NO_LGTH_CHECK,Payload Length Check Disable" "0,1"
|
|
bitfld.long 0x00 23. "CNTL_FRM_ENA,MAC Control Frame Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "LOOP_ENA,Enable GMII / MII loopback when set to 1 normal operation when set to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "MHASH_SEL,Multicast Address Resolution Hash Code Option" "0,1"
|
|
bitfld.long 0x00 13. "SW_RESET,Self-Clearing Software Reset Command" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
bitfld.long 0x00 10. "HD_ENA,Half duplex enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "TX_ADDR_INS,Set MAC address on transmit" "0,1"
|
|
bitfld.long 0x00 8. "PAUSE_IGNORE,Ignore Pause Frame Quanta" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "PAUSE_FWD,Terminate / Forward Pause Frames" "0,1"
|
|
bitfld.long 0x00 6. "CRC_FWD,Terminate / Forward Received CRC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PAD_EN,Enable / Disable Frame Padding" "0,1"
|
|
bitfld.long 0x00 4. "PROMIS_EN,Enable / Disable MAC promiscuous operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ETH_SPEED,Enable Gigabit Ethernet operation (GMII) when set to 1 enable 10/100Mbps Ethernet operation (MII) when set to 0" "0,1"
|
|
bitfld.long 0x00 2. "TX_CRC_FWD,Write 0 always" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RX_ENA,Enable / Disable MAC receive path" "0,1"
|
|
bitfld.long 0x00 0. "TX_ENA,Enable / Disable MAC transmit path" "0,1"
|
|
group.long 0xA014++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_FRM_LENGTH,Maximum Frame Length"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--13. 1. "MAX_FRM_LNGTH,Maximum Frame Length"
|
|
group.long 0xA018++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_PAUSE_QUANT,Receive Pause Quanta"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED0,MAC_0_PAUSE_QUANT bit0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RX_PAUSE_QUANT,Receive Pause Quanta"
|
|
rgroup.long 0xA01C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_SECTION_EMPTY,Receive FIFO section empty threshold"
|
|
hexmask.long 0x00 0.--31. 1. "RX_SECTION_EMPTY,Receive FIFO section empty threshold"
|
|
rgroup.long 0xA020++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_SECTION_FULL,Receive FIFO section full threshold"
|
|
hexmask.long 0x00 0.--31. 1. "RX_SECTION_FULL,Receive FIFO section full threshold"
|
|
group.long 0xA024++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_SECTION_EMPTY,Transmit FIFO section empty threshold"
|
|
hexmask.long 0x00 0.--31. 1. "TX_SECTION_EMPTY,Transmit FIFO section empty threshold"
|
|
group.long 0xA028++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_SECTION_FULL,Transmit FIFO section full threshold"
|
|
hexmask.long 0x00 0.--31. 1. "TX_SECTION_FULL,Transmit FIFO section full threshold"
|
|
rgroup.long 0xA02C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ALMOST_EMPTY,Receive FIFO almost empty threshold"
|
|
hexmask.long 0x00 0.--31. 1. "RX_ALMOST_EMPTY,Receive FIFO almost empty threshold"
|
|
rgroup.long 0xA030++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ALMOST_FULL,Receive FIFO almost full threshold"
|
|
hexmask.long 0x00 0.--31. 1. "RX_ALMOST_FULL,Receive FIFO almost full threshold"
|
|
rgroup.long 0xA034++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ALMOST_EMPTY,Transmit FIFO almost empty threshold"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ALMOST_EMPTY,Transmit FIFO almost empty threshold"
|
|
rgroup.long 0xA038++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ALMOST_FULL,Transmit FIFO almost full threshold"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ALMOST_FULL,Transmit FIFO almost full threshold"
|
|
rgroup.long 0xA058++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_STATUS,Status information for both MACs"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 14. "MAC_1_CURR_HD_SET,Current Halfduplex setting" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "MAC_1_CURR_ENA,Current ena_10" "0,1"
|
|
bitfld.long 0x00 12. "MAC_1_CURR_SPD,Current Speed" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
bitfld.long 0x00 10. "MAC_0_CURR_HD_SET,Current Halfduplex setting" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "MAC_0_CURR_ENA,Current ena_10" "0,1"
|
|
bitfld.long 0x00 8. "MAC_0_CURR_SPD,Current Speed" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "REG_IF_ERR,Register interface error occured" "0,1"
|
|
group.long 0xA05C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_IPG_LENGTH,Programmable Inter-Packet Gap"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0.--4. "TX_IPG_LENGTH,Programmable Inter-Packet Gap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xA100++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_OCTETS,Total octets good and bad frames"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_OCTETS,Total octets good and bad frames"
|
|
rgroup.long 0xA104++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_OCTETS_OK,Total octets good frames only"
|
|
hexmask.long 0x00 0.--31. 1. "OCTETS_OK,Total octets good frames only"
|
|
rgroup.long 0xA108++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_A_ALIGNMENT_ERRORS,Counts when mii_rx_dv deasserted but no SFD (0xd5) was detected (i.e. missing frame start)"
|
|
hexmask.long 0x00 0.--31. 1. "A_ALIGNMENT_ERRORS,Counts when mii_rx_dv deasserted but no SFD (0xd5) was detected (i.e. missing frame start)"
|
|
rgroup.long 0xA10C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_A_PAUSE_MAC_CTRL_FRAMES,Good pause frames received"
|
|
hexmask.long 0x00 0.--31. 1. "A_PAUSE_MAC_CTRL_FRAMES,Good pause frames received"
|
|
rgroup.long 0xA110++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_FRAMES_OK,Good frames received"
|
|
hexmask.long 0x00 0.--31. 1. "FRAMES_OK,Good frames received"
|
|
rgroup.long 0xA114++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_CRC_ERRORS,Wrong CRC but good length (64..MTU)"
|
|
hexmask.long 0x00 0.--31. 1. "CRC_ERRORS,Wrong CRC but good length"
|
|
rgroup.long 0xA118++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_VLAN_OK,Good VLAN tagged"
|
|
hexmask.long 0x00 0.--31. 1. "VLAN_OK,Good VLAN tagged"
|
|
rgroup.long 0xA11C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_IFLN_ERRORS,Counts for any receive errors"
|
|
hexmask.long 0x00 0.--31. 1. "IFLN_ERRORS,Counts for any receive errors"
|
|
rgroup.long 0xA120++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_IFLN_UCAST_PKTS,Good Unicast"
|
|
hexmask.long 0x00 0.--31. 1. "IFLN_UCAST_PKTS,Good Unicast"
|
|
rgroup.long 0xA124++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_IFLN_MULTICAST_PKTS,Good Multicast"
|
|
hexmask.long 0x00 0.--31. 1. "IFLN_MULTICAST_PKTS,Good Multicast"
|
|
rgroup.long 0xA128++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_IFLN_BROADCAST_PKTS,Good Broadcast"
|
|
hexmask.long 0x00 0.--31. 1. "IFLN_BROADCAST_PKTS,Good Broadcast"
|
|
rgroup.long 0xA12C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_DROP_EVENTS,Increments when frames are dropped due to receive FIFO full at begin of frame"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_DROP_EVENTS,Increments when frames are dropped due to receive FIFO full at begin of frame"
|
|
rgroup.long 0xA130++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_PKTS,Total frames good & bad"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS,Total frames good & bad"
|
|
rgroup.long 0xA134++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_UNDERSIZE_PKTS,Frames with length less 64 bytes and good CRC"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_UNDERSIZE_PKTS,Frames with length less 64 bytes and good CRC"
|
|
rgroup.long 0xA138++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_PKTS_64_OCTETS,Frames with length of 64 bytes"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_64_OCTETS,Frames with length of 64 bytes"
|
|
rgroup.long 0xA13C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_PKTS_65_127_OCTETS,Frames with length from 65"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_65_127_OCTETS,Frames with length from 65"
|
|
rgroup.long 0xA140++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_PKTS_128_255_OCTETS,Frames with length from 128"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_128_255_OCTETS,Frames with length from 128"
|
|
rgroup.long 0xA144++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_PKTS_256_511_OCTETS,Frames with length from 256"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_256_511_OCTETS,frames with length from 256"
|
|
rgroup.long 0xA148++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_PKTS_512_1023_OCTETS,Frames with length from 512"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_512_1023_OCTETS,Frames with length from 512"
|
|
rgroup.long 0xA14C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_PKTS_1024_1518_OCTETS,Frames with length from 1024"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_1024_1518_OCTETS,Frames with length from 1024"
|
|
rgroup.long 0xA150++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_PKTS_1519_TO_MAX,Frames with length from 1519"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_PKTS_1519_TO_MAX,Frames with length from 1519"
|
|
rgroup.long 0xA154++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_OVERSIZED_PKTS,Frames with length exceeding FRM_LENGTH good CRC"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_OVERSIZED_PKTS,Frames with length exceeding FRM_LENGTH good CRC"
|
|
rgroup.long 0xA158++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_JABBERS,Frames with length exceeding FRM_LENGTH bad CRC"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_JABBERS,Frames with length exceeding FRM_LENGTH bad CRC"
|
|
rgroup.long 0xA15C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_ETHER_STATS_FRAGMENTS,Frames with length less 64 and bad CRC"
|
|
hexmask.long 0x00 0.--31. 1. "ETHER_STATS_FRAGMENTS,Frames with length less 64 and bad CRC"
|
|
rgroup.long 0xA160++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_A_MAC_CONTROL_FRAMES_RECEIVED,Good Frames with type 0x8808 (incl. Pause)"
|
|
hexmask.long 0x00 0.--31. 1. "A_MAC_CONTROL_FRAMES_RECEIVED,Good Frames with type 0x8808"
|
|
rgroup.long 0xA164++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_A_FRAME_TOO_LONG,Total frames exceeding FRAME_LENGTH good & bad"
|
|
hexmask.long 0x00 0.--31. 1. "A_FRAME_TOO_LONG,Total frames exceeding FRAME_LENGTH good & bad"
|
|
rgroup.long 0xA16C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_STACKED_VLAN_OK,Good with stacked VLAN (two VLAN tags)"
|
|
hexmask.long 0x00 0.--31. 1. "STACKED_VLAN_OK,Good with stacked VLAN (two VLAN tags)"
|
|
rgroup.long 0xA170++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_RX_HUB_DISCARD,Frames discarded by the HUB/DLR module"
|
|
hexmask.long 0x00 0.--31. 1. "HUB_DISCARD,Frames discarded by the HUB/DLR module"
|
|
rgroup.long 0xA180++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_OCTETS,Total octets good and bad frames"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_OCTETS,Total octets good and bad frames"
|
|
rgroup.long 0xA184++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_OCTETS_OK,Total good"
|
|
hexmask.long 0x00 0.--31. 1. "TX_OCTETS_OK,Total good"
|
|
rgroup.long 0xA18C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_A_PAUSE_MAC_CTRL_FRAMES,Good pause transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TX_A_PAUSE_MAC_CTRL_FRAMES,Good pause transmitted"
|
|
rgroup.long 0xA190++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_FRAMES_OK,Good pause transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TX_FRAMES_OK,Good transmitted"
|
|
rgroup.long 0xA194++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_CRC_ERRORS,Transmitted with error but good length (ff_tx_err)"
|
|
hexmask.long 0x00 0.--31. 1. "TX_CRC_ERRORS,Transmitted with error but good length"
|
|
rgroup.long 0xA198++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_VLAN_OK,Good VLAN tagged"
|
|
hexmask.long 0x00 0.--31. 1. "TX_VLAN_OK,Good VLAN tagged"
|
|
rgroup.long 0xA19C++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_IF_OUT_ERRORS,Any error (ff_tx_err toolong but not counting undersized)"
|
|
hexmask.long 0x00 0.--31. 1. "IF_OUT_ERRORS,Any error"
|
|
rgroup.long 0xA1A0++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_IF_UCAST_PKTS,Good Unicast"
|
|
hexmask.long 0x00 0.--31. 1. "IF_UCAST_PKTS,Good Unicast"
|
|
rgroup.long 0xA1A4++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_IF_MULTICAST_PKTS,Good Multicast"
|
|
hexmask.long 0x00 0.--31. 1. "IF_MULTICAST_PKTS,Good Multicast"
|
|
rgroup.long 0xA1A8++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_IF_BROADCAST_PKTS,Good Broadcast"
|
|
hexmask.long 0x00 0.--31. 1. "IF_BROADCAST_PKTS,Good Broadcast"
|
|
rgroup.long 0xA1AC++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_DROP_EVENTS,Counts undersized frames transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_DROP_EVENTS,Counts undersized frames transmitted"
|
|
rgroup.long 0xA1B0++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_PKTS,Total frames good & bad"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS,Total frames good & bad"
|
|
rgroup.long 0xA1B4++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_UNDERSIZE_PKTS,Frames with length less 64 bytes and good CRC"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_UNDERSIZE_PKTS,Frames with length less 64 bytes and good CRC"
|
|
rgroup.long 0xA1B8++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_PKTS_64_OCTETS,Frames with length of 64 bytes"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_64_OCTETS,Frames with length of 64 bytes"
|
|
rgroup.long 0xA1BC++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_PKTS_65_127_OCTETS,Frames with length from 65"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_65_127_OCTETS,Frames with length from 65"
|
|
rgroup.long 0xA1C0++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_PKTS_128_255_OCTETS,Frames with length from 128"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_128_255_OCTETS,Frames with length from 128"
|
|
rgroup.long 0xA1C4++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_PKTS_256_511_OCTETS,Frames with length from 256"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_256_511_OCTETS,Frames with length from 256"
|
|
rgroup.long 0xA1C8++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_PKTS_512_1023_OCTETS,Frames with length from 512"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_512_1023_OCTETS,Frames with length from 512"
|
|
rgroup.long 0xA1CC++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_PKTS_1024_1518_OCTETS,Frames with length from 1024"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_1024_1518_OCTETS,Frames with length from 1024"
|
|
rgroup.long 0xA1D0++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_PKTS_1519_TO_MAX,Frames with length from 1519"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_PKTS_1519_TO_MAX,Frames with length from 1519"
|
|
rgroup.long 0xA1D4++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_OVERSIZED_PKTS,Frames with length exceeding FRM_LENGTH good CRC"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_OVERSIZED_PKTS,Frames with length exceeding FRM_LENGTH good"
|
|
rgroup.long 0xA1D8++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_JABBERS,Frames with length exceeding FRM_LENGTH bad CRC"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_JABBERS,Frames with length exceeding FRM_LENGTH bad"
|
|
rgroup.long 0xA1DC++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_ETHER_STATS_FRAGMENTS,Frames with length less 64 and bad CRC"
|
|
hexmask.long 0x00 0.--31. 1. "TX_ETHER_STATS_FRAGMENTS,Frames with length less 64 bytes and marked erronenous"
|
|
rgroup.long 0xA1E0++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_A_MAC_CONTOL_FRAMES,Good frames with type 0x8808 (incl. Pause)"
|
|
hexmask.long 0x00 0.--31. 1. "A_MAC_CONTOL_FRAMES,Good frames with type 0x8808"
|
|
rgroup.long 0xA1E4++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_A_FRAME_TOO_LONG,Total frames exceeding FRAME_LENGTH good & bad"
|
|
hexmask.long 0x00 0.--31. 1. "TX_A_FRAME_TOO_LONG,Total frames exceeding FRAME_LENGTH good & bad"
|
|
rgroup.long 0xA1E8++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_A_DEFERRED,Not implemented always 0"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0xA1EC++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_A_MULTIPLE_COLLISIONS,Successful transmissions after multiple collisions"
|
|
hexmask.long 0x00 0.--31. 1. "A_MULTIPLE_COLLISIONS,Successful transmissions after multiple collisions"
|
|
rgroup.long 0xA1F0++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_A_SINGLE_COLLISIONS,Successful transmissions after one collision"
|
|
hexmask.long 0x00 0.--31. 1. "A_SINGLE_COLLISIONS,Successful transmissions after one collisions"
|
|
rgroup.long 0xA1F4++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_A_LATE_COLLISIONS,Frames transmitted in error due to late collisions"
|
|
hexmask.long 0x00 0.--31. 1. "A_LATE_COLLISIONS,Frames transmitted in error due to late collisions"
|
|
rgroup.long 0xA1F8++0x03
|
|
line.long 0x00 "SWITCH_3P_MAC_1_TX_A_EXCESS_COLLISIONS,Frames dropped due to excessive collisions (16 unsuccessful transmits)"
|
|
hexmask.long 0x00 0.--31. 1. "A_EXCESS_COLLISIONS,Frames dropped due to excessive collisions (16 unsuccessful transmits)"
|
|
rgroup.long 0xC000++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_VERSION,TSM Version"
|
|
hexmask.long 0x00 0.--31. 1. "VERSION,TSM Version"
|
|
group.long 0xC004++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_CONFIG,Module configuration and interrupt enable mask"
|
|
hexmask.long 0x00 0.--31. 1. "UNUSED,Module configuration and interrupt enable mask"
|
|
group.long 0xC008++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_IRQ_STAT_ACK,Interrupt Status / Acknowledge"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "IRQ_TX,Per Port Transmit Timestamp Capture Interrupt"
|
|
hexmask.long.byte 0x00 5.--11. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "IRQ_TEST,Test interrupt pending" "0,1"
|
|
bitfld.long 0x00 3. "IRQ_ATIME_OVER,Overflow interrupt pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "IRQ_EVT_PERIOD,Periodical interrupt pending" "0,1"
|
|
bitfld.long 0x00 1. "IRQ_EVT_OFFSET,Offset interrupt pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IRQ_EN,Interrupt pending status" "0,1"
|
|
rgroup.long 0xC00C++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_PEERDELAY,Peer-to-Peer delay value"
|
|
hexmask.long 0x00 0.--31. 1. "PEERDELAY,Peer-to-Peer delay value"
|
|
group.long 0xC020++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_PORT0_CTRL,Port 0 timestamp control/status"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2. "TS_KEEP,Keep last timestamp in the receive timestamp registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TS_OVR,A newer timestamp has overwritten the last stored timestamp" "0,1"
|
|
bitfld.long 0x00 0. "TS_VALID,A valid timestamp is available" "0,1"
|
|
rgroup.long 0xC024++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_PORT0_TIME,Port 0 Memorized timestamp"
|
|
hexmask.long 0x00 0.--31. 1. "PORT0_TIME,Port 0 Memorized timestamp"
|
|
group.long 0xC028++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_PORT1_CTRL,Port 1 timestamp control/status"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 2. "TS_KEEP,Keep last timestamp in the receive timestamp registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TS_OVR,A newer timestamp has overwritten the last stored timestamp" "0,1"
|
|
bitfld.long 0x00 0. "TS_VALID,A valid timestamp is available" "0,1"
|
|
rgroup.long 0xC02C++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_PORT1_TIME,Port 1 Memorized timestamp"
|
|
hexmask.long 0x00 0.--31. 1. "PORT1_TIME,Port 1 Memorized timestamp"
|
|
group.long 0xC120++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_ATIME_CTRL,Timer Control"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 12. "PLUS1,Increment the timer counter by 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CAPTURE,Capture timer value" "0,1"
|
|
bitfld.long 0x00 10. "PIN_OVR,unused write 0 always" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "RESTART,Resets the timer to zero" "0,1"
|
|
bitfld.long 0x00 8. "PIN_OVR_ALLRST,unused write 0 always" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "PIN_PERIOD_ENA,Enable external pin ts_evt_period assertion on period event when set" "0,1"
|
|
bitfld.long 0x00 6. "PIN_OFFSET_ENA,unused write 0 always" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "EVT_PERIOD_RST,Reset timer on periodical event" "0,1"
|
|
bitfld.long 0x00 4. "EVT_PERIOD_ENA,Enable periodical event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EVT_OFFSET_RST,unused write 0 always" "0,1"
|
|
bitfld.long 0x00 2. "EVT_OFFSET_ENA,Enable offset event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ONE_SHOT,Avoid timer wrap around" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE,When set (1) the timer starts incrementing" "0,1"
|
|
group.long 0xC124++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_ATIME,Timer value"
|
|
hexmask.long 0x00 0.--31. 1. "ATIME,Timer value"
|
|
group.long 0xC128++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_ATIME_OFFSET,Value to used for performing offset corrections without changing the drift correction"
|
|
hexmask.long 0x00 0.--31. 1. "ATIME_OFFSET,Value to used for performing offset corrections"
|
|
group.long 0xC12C++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_ATIME_EVT_PERIOD,Value for generating periodic events"
|
|
hexmask.long 0x00 0.--31. 1. "ATIME_EVT_PERIOD,Value for generating periodic events"
|
|
group.long 0xC130++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_ATIME_CORR,Correction value (drift correction)"
|
|
bitfld.long 0x00 31. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long 0x00 0.--30. 1. "ATIME_CORR,Drift correction value"
|
|
group.long 0xC134++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_ATIME_INC,Bits[6:0]:Clock period of the timestamping clock (ts_clk) in nanoseconds"
|
|
hexmask.long.word 0x00 23.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--22. 1. "OFFS_CORR_INCR_VAL,Offset correction increment value"
|
|
newline
|
|
bitfld.long 0x00 15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "CORR_INCR_VAL,Correction increment value"
|
|
newline
|
|
bitfld.long 0x00 7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "TIMESTAMP_CLK_PERIOD,Clock period of the timestamping clock"
|
|
group.long 0xC138++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_ATIME_SEC,Seconds time value"
|
|
hexmask.long 0x00 0.--31. 1. "ATIME_SEC,Seconds time value"
|
|
group.long 0xC13C++0x03
|
|
line.long 0x00 "SWITCH_3P_TSM_ATIME_CORR_OFFS,Offset correction Counter"
|
|
hexmask.long 0x00 0.--31. 1. "ATIME_CORR_OFFS,Offset correction Counter"
|
|
group.long 0xE000++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_CONTROL,DLR Control register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 8.--15. 1. "MS_CYCLE,Number of cycles required for 1 microsecond for the host interface clock"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "IGN_INV_BCN_TIMER,Enable ignore Beacon frames with invalid timeout timer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "ENABLE,Enable DLR extension module" "0,1"
|
|
rgroup.long 0xE004++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_STATUS,DLR Status register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED3,Current network Topology"
|
|
bitfld.long 0x00 24. "CURR_NET_TOPOLOGY,Current network Topology" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18.--23. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--17. "LNK_STAT,Link status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--9. "LCL_NODE_CURR_STATE,Local node current state" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. "LST_BCN_RX_PORT,Last Beacon receive port" "0,1,2,3"
|
|
group.long 0xE008++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_ETH_TYP,DLR Ethernet Type"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "ETH_TYP,Ethernet Type to compare for DLR frame detection"
|
|
group.long 0xE00C++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_IRQ_CTRL,Interrupt Control"
|
|
bitfld.long 0x00 31. "ATOMIC_AND,When set during a register-write the enable bits are AND'ed with the current setting of the register (i.e. clearing bits)" "0,1"
|
|
bitfld.long 0x00 30. "ATOMIC_OR,When set during a register-write the enable bits are OR'ed into the current setting of the register (i.e. setting bits)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "LOW_INT_EN,Enable active low interrupt" "0,1"
|
|
hexmask.long.word 0x00 16.--28. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 15. "IRQ_FRM_DSCRD1,Enable Interrupt on Frame discard due to source address match with the local address on Port 1" "0,1"
|
|
bitfld.long 0x00 14. "IRQ_FRM_DSCRD0,Enable Interrupt on Frame discard due to source address match with the local address on Port 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "IRQ_BEC_RCV1_ENA,Enable Interrupt on Beacon frame detection on Port 1" "0,1"
|
|
bitfld.long 0x00 12. "IRQ_BEC_RCV0_ENA,Enable Interrupt on Beacon frame detection on Port 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IRQ_INVALID_TMR_ENA,Enable Interrupt on invalid range for beacon timeout timer value detection" "0,1"
|
|
bitfld.long 0x00 10. "IRQ_IP_ADDR_CHNG_ENA,Enable interrupt on IP address change detection within beacon frame from ring supervisor" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "IRQ_SUP_IGNORD_ENA,Enable interrupt on beacon frame detection from a supervisor with lower precedence than the current ring supervisor or lower numeric value for MAC address when precedence is same" "0,1"
|
|
bitfld.long 0x00 8. "IRQ_LINK_CHNG1_ENA,Enable Link change interrupt event for Port 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IRQ_LINK_CHNG0_ENA,Enable Link change interrupt event for Port 0" "0,1"
|
|
bitfld.long 0x00 6. "IRQ_SUPR_CHNG_ENA,Enable interrupt on ring supervisor change" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IRQ_BEC_TMR1_EXP_ENA,Enable interrupt on beacon timeout timer expire for port1" "0,1"
|
|
bitfld.long 0x00 4. "IRQ_BEC_TMR0_EXP_ENA,Enable interrupt on beacon timeout timer expire for port0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IRQ_STOP_NBCHK1_ENA,Enable Stop neighbor check timeout timer interrupt for port1" "0,1"
|
|
bitfld.long 0x00 2. "IRQ_STOP_NBCHK0_ENA,Enable Stop neighbor check timeout timer interrupt for port0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "IRQ_FLUSH_MAC_ADDR_ENA,Enable flush local MAC address table interrupt" "0,1"
|
|
bitfld.long 0x00 0. "IRQ_STATE_CHANGE_ENA,Enable interrupt for state change" "0,1"
|
|
group.long 0xE010++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_IRQ_STAT_ACK,Interrupt Status/Acknowledgement"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 15. "FRM_DSCRD1_IRQ_PENDING,Latched event on Frame discard due to source address match with the local address on Port 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "FRM_DSCRD0_IRQ_PENDING,Latched event on Frame discard due to source address match with the local address on Port 0" "0,1"
|
|
bitfld.long 0x00 13. "BEC_RCV1_IRQ_PENDING,Latched event on Beacon frame detection on Port 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "BEC_RCV0_IRQ_PENDING,Latched event on Beacon frame detection on Port 0" "0,1"
|
|
bitfld.long 0x00 11. "INVALID_TMR_IRQ_PENDING,Latched event on invalid beacon timeout timer value detection within beacon frame on port0 or port1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "IP_CHNG_INTERRUPT_PENDING,Latched IP address change event" "0,1"
|
|
bitfld.long 0x00 9. "SUP_IGNORED_IRQ_PENDING,Latched event for beacon frame detection from ignored supervisor" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "LINK1_IRQ_PENDING,Latched link status change event" "0,1"
|
|
bitfld.long 0x00 7. "LINK0_IRQ_PENDING,Latched link status change event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SUPR_CHNG_IRQ_PENDING,Latched supervisor change event" "0,1"
|
|
bitfld.long 0x00 5. "BEC_TMR1_IRQ_PENDING,Beacon timeout timer expire interrupt for port1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "BEC_TMR0_IRQ_PENDING,Beacon timeout timer expire interrupt for port0" "0,1"
|
|
bitfld.long 0x00 3. "NBCHK1_IRQ_PENDING,Stop event for neighbor check timeout timer for port1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "NBCHK0_IRQ_PENDING,Stop event for neighbor check timeout timer for port0" "0,1"
|
|
bitfld.long 0x00 1. "FLUSH_IRQ_PENDING,Latched flush event for MAC address learning table" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "STATE_CHNG_IRQ_PENDING,Latched state change event" "0,1"
|
|
group.long 0xE014++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_LOC_MAC_LO,First 4 octets of the local MAC address for loop filter"
|
|
hexmask.long 0x00 0.--31. 1. "LOC_MAC_LO,First 4 octets of the local MAC address for loop filter"
|
|
group.long 0xE018++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_LOC_MAC_HI,Last 2 octets of local MAC address for loop filter"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--15. 1. "LOC_MAC_HI,Last 2 octets of local MAC address for loop filter"
|
|
rgroup.long 0xE020++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_SUPR_MAC_LO,First 4 octets of the active ring supervisor's MAC address extracted from Destination Address field of the Beacon frame"
|
|
hexmask.long 0x00 0.--31. 1. "SUPR_MAC_LO,First 4 octets of the active ring supervisor's MAC address"
|
|
rgroup.long 0xE024++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_SUPR_MAC_HI,Last 2 octets of active ring supervisor's MAC address extracted from the Destination Address field of the Beacon frame"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SUPR_PREC,The supervisor's precedence value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "SUPR_MAC_HI,Last 2 octets of active ring supervisor's MAC address"
|
|
rgroup.long 0xE028++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_STATE_VLAN,VLAN State Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "TAG_CTRL,802.1Q VLAN Tag control field"
|
|
hexmask.long.byte 0x00 9.--15. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 8. "VALID,VLAN valid" "0,1"
|
|
bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "STATE,DLR ring state" "0,1,2,3"
|
|
rgroup.long 0xE02C++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_BEC_TMOUT,Beacon timeout timer value"
|
|
hexmask.long 0x00 0.--31. 1. "BEC_TMOUT,Beacon timeout timer value"
|
|
rgroup.long 0xE030++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_BEC_INTRVL,Beacon interval extracted from the Beacon Interval field of the Beacon frame"
|
|
hexmask.long 0x00 0.--31. 1. "BEC_INTRVL,Beacon interval"
|
|
rgroup.long 0xE034++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_SUPR_IP_ADR,Ring supervisor's IP address extracted from the Source IP address field of the Beacon frame"
|
|
hexmask.long 0x00 0.--31. 1. "SUPR_IP_ADR,Ring supervisor's IP address"
|
|
rgroup.long 0xE038++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_ETH_STYP_VER,Ethernet Subtype Version"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SRC_PORT,Source port"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "P_VER,DLR Ring Protocol Version"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ETH_STYP,DLR Ring Ether sub Type"
|
|
rgroup.long 0xE03C++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_INV_TMOUT,Last out of range Beacon timeout timer value"
|
|
hexmask.long 0x00 0.--31. 1. "INV_TMOUT,Last out of range Beacon timeout timer value"
|
|
rgroup.long 0xE040++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_SEQ_ID,Sequence ID of the last Beacon frame"
|
|
hexmask.long 0x00 0.--31. 1. "SEQ_ID,Sequence ID of the last Beacon frame"
|
|
rgroup.long 0xE060++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_RX_STAT0,Number of Beacon frames received on port 0"
|
|
hexmask.long 0x00 0.--31. 1. "RX_STAT0,Number of Beacon frames received on port 0"
|
|
rgroup.long 0xE064++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_RX_ERR_STAT0,Number of Beacon frames received with crc error on port 0"
|
|
hexmask.long 0x00 0.--31. 1. "RX_ERR_STAT0,Number of Beacon frames received with crc error on port 0"
|
|
rgroup.long 0xE068++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_TX_STAT0,Number of Beacon frames forwarded through the HUB from port1 to port0"
|
|
hexmask.long 0x00 0.--31. 1. "TX_STAT0,Number of Beacon frames forwarded through the HUB from port 1 to port0"
|
|
rgroup.long 0xE070++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_RX_STAT1,Number of Beacon frames received on port 1"
|
|
hexmask.long 0x00 0.--31. 1. "RX_STAT1,Number of Beacon frames received on port 1"
|
|
rgroup.long 0xE074++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_RX_ERR_STAT1,Number of Beacon frames received with crc error on port 1"
|
|
hexmask.long 0x00 0.--31. 1. "RX_ERR_STAT1,Number of Beacon frames received with crc error on port 1"
|
|
rgroup.long 0xE078++0x03
|
|
line.long 0x00 "SWITCH_3P_DLR_TX_STAT1,Number of Beacon frames forwarded through the HUB from port0 to port1"
|
|
hexmask.long 0x00 0.--31. 1. "TX_STAT1,Number of Beacon frames forwarded through the HUB from port 0 to port1"
|
|
tree.end
|
|
tree "PCIE"
|
|
base ad:0xF8050000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCIE_AWBASE0,AXI Window Base 0"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "AWBASE,Window Base"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "AWBASE_RESERVED,Window Base Reserved (fixed 0x0)"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "MSIZE,AXI Master Size" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WE,AXI Window enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCIE_AWMASK0,AXI Window Mask 0"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "AWMASK,Window Mask"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "AWMASK_RESERVED,Window Mask Reserved (fixed 0xFFF)"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCIE_ADEST0,AXI Destination 0"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "ADEST,Destination"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "ADEST_RESERVED,Destination Reserved (fixed 0x0)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCIE_AWBASE1,AXI Window Base 1"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "AWBASE,Window Base"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "AWBASE_RESERVED,Window Base Reserved (fixed 0x0)"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "MSIZE,AXI Master Size" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WE,AXI Window enable" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PCIE_AWMASK1,AXI Window Mask 1"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "AWMASK,Window Mask"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "AWMASK_RESERVED,Window Mask Reserved (fixed 0xFFF)"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PCIE_ADEST1,AXI Destination 1"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "ADEST,Destination"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "ADEST_RESERVED,Destination Reserved (fixed 0x0)"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCIE_AWBASE2,AXI Window Base 2"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "AWBASE,Window Base"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "AWBASE_RESERVED,Window Base Reserved (fixed 0x0)"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "MSIZE,AXI Master Size" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WE,AXI Window enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PCIE_AWMASK2,AXI Window Mask 2"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "AWMASK,Window Mask"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "AWMASK_RESERVED,Window Mask Reserved (fixed 0xFFF)"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PCIE_ADEST2,AXI Destination 2"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "ADEST,Destination"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "ADEST_RESERVED,Destination Reserved (fixed 0x0)"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PCIE_AWBASE3,AXI Window Base 3"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "AWBASE,Window Base"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "AWBASE_RESERVED,Window Base Reserved (fixed 0x0)"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "MSIZE,AXI Master Size" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WE,AXI Window enable" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PCIE_AWMASK3,AXI Window Mask 3"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "AWMASK,Window Mask"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "AWMASK_RESERVED,Window Mask Reserved (fixed 0xFFF)"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PCIE_ADEST3,AXI Destination 3"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "ADEST,Destination"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "ADEST_RESERVED,Destination Reserved (fixed 0x0)"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCIE_PWBASE0,PCIe Window Base 0"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "PWBASE,PCIe Window Base"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "PWBASE_RESERVED,PCIe Window Base Reserved (fixed 0x0)"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "WE,PCIe Window Enable" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCIE_PWMASK0,PCIe Window Mask 0"
|
|
bitfld.long 0x00 31. "RESERVED,Reserved 2" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 12.--30. 1. "PWMASK,Window Mask"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "PWMASK_RESERVED,Window Mask Reserved (fixed 0xFFF)"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PCIE_PDSET0_L,PCIe Destination 0 (Lower)"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "PDEST,PCIe Destination (lower)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "PDEST_RESERVED,PCIe Destination (Lower) (fixed 0x0)"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PCIE_PDSET0_U,PCIe Destination 0 (Upper)"
|
|
hexmask.long 0x00 0.--31. 1. "PDEST,PCIe Destination (upper)"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PCIE_PWBASE1,PCIe Window Base 1"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "PWBASE,PCIe Window Base"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "PWBASE_RESERVED,PCIe Window Base Reserved (fixed 0x0)"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "WE,PCIe Window Enable" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PCIE_PWMASK1,PCIe Window Mask 1"
|
|
bitfld.long 0x00 31. "RESERVED,Reserved 2" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 12.--30. 1. "PWMASK,Window Mask"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "PWMASK_RESERVED,Window Mask Reserved (fixed 0xFFF)"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PCIE_PDSET1_L,PCIe Destination 1 (Lower)"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "PDEST,PCIe Destination (lower)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "PDEST_RESERVED,PCIe Destination (Lower) (fixed 0x0)"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PCIE_PDSET1_U,PCIe Destination 1 (Upper)"
|
|
hexmask.long 0x00 0.--31. 1. "PDEST,PCIe Destination (upper)"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PCIE_PWBASE2,PCIe Window Base 2"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "PWBASE,PCIe Window Base"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "PWBASE_RESERVED,PCIe Window Base Reserved (fixed 0x0)"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "WE,PCIe Window Enable" "0,1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "PCIE_PWMASK2,PCIe Window Mask 2"
|
|
bitfld.long 0x00 31. "RESERVED,Window Mask" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 12.--30. 1. "PWMASK,Window Mask"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "PWMASK_RESERVED_1,Window Mask Reserved (fixed 0xFFF)"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PCIE_PDSET2_L,PCIe Destination 2 (Lower)"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "PDEST,PCIe Destination (lower)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "PDEST_RESERVED,PCIe Destination (Lower) (fixed 0x0)"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCIE_PDSET2_U,PCIe Destination 2 (Upper)"
|
|
hexmask.long 0x00 0.--31. 1. "PDEST,PCIe Destination (upper)"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PCIE_PWBASE3,PCIe Window Base 3"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "PWBASE,PCIe Window Base"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "PWBASE_RESERVED,PCIe Window Base Reserved (fixed 0x0)"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "WE,PCIe Window Enable" "0,1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PCIE_PWMASK3,PCIe Window Mask 3"
|
|
bitfld.long 0x00 31. "RESERVED,Window Mask" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 12.--30. 1. "PWMASK,Window Mask"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESERVED_1,Window Mask Reserved (fixed 0xFFF)"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PCIE_PDSET3_L,PCIe Destination 3 (Lower)"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "PDEST,PCIe Destination (lower)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "PDEST_RESERVED,PCIe Destination (Lower) (fixed 0x0)"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PCIE_PDSET3_U,PCIe Destination 3 (Upper)"
|
|
hexmask.long 0x00 0.--31. 1. "PDEST,PCIe Destination (upper)"
|
|
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "PCIE_REQDAT$1,Request Data Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "REQDAT,Request Data"
|
|
repeat.end
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PCIE_REQ_REC_DAT,Request Recevie Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "REQ_REC_DAT,Request Receive Data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PCIE_REQ_ADDR_1,Request Address Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REQ_ADDR_1,Request Address 1"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PCIE_REQ_ADDR_2,Request Address Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "REQ_ADDR_1,Request Address 2"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PCIE_REQ_BYTE_EN,Request Byte Enable Register"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "REQ_BYTE_EN,Request Byte Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "PCIE_REQ_ISSUE,Request Issue Register"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED_3,Reserved 3"
|
|
newline
|
|
bitfld.long 0x00 22. "REQ_REJECT,Request Rejection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "MOR_CD_PERR,MOR CD PERR (Data error)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "MOR_CH_PERR,MOR CH PERR (Header error)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "MOR_EP_PERR,MOR EP PERR (Poisoned Completion TLP)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "MOR_STATUS,MOR Status" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "RESERVED_2,Reserved 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TR_TYPE,TR Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED_1,Reserved 1"
|
|
newline
|
|
bitfld.long 0x00 0. "REQ_ISSUE,Request Issue" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PCIE_MSI_REC_WIN_ADDR,MSI Recevie Window Address"
|
|
hexmask.long 0x00 3.--31. 1. "MSI_REC_WIN_ADDR,MSI Receive Window Address"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "WE,Receive Window Enable" "0,1"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "PCIE_MSI_REC_WIN_MASK,MSI Recevie Window Mask"
|
|
hexmask.long 0x00 2.--31. 1. "MSI_REC_WIN_MASK,MSI Receive Window Mask"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PCIE_PCI_INT_REC_EN,PCI INTx Receive Interrupt Enable"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "MSI_REC_EN,MSI Receive Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INTD_REC_EN,INTD Receive Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTC_REC_EN,INTC Receive Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "INTB_REC_EN,INTB Receive Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTA_REC_EN,INTA Receive Interrupt Enable" "0,1"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "PCIE_PCI_INT_REC_STATUS,PCI INTx Receive Interrupt Status"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "MSI_REC_STATUS,MSI Receive Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INTD_REC_STATUS,INTD Receive Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTC_REC_STATUS,INTC Receive Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "INTB_REC_STATUS,INTB Receive Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTA_REC_STATUS,INTA Receive Interrupt Status" "0,1"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "PCIE_PCI_INT_OUT_STATUS,PCI INTx Out Status"
|
|
hexmask.long 0x00 4.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 3. "INTD_OUT_STATUS,INTD Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTC_OUT_STATUS,INTC Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "INTB_OUT_STATUS,INTB Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTA_OUT_STATUS,INTA Status" "0,1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PCIE_MSG_REC_INT_EN,Message Receive Interrupt Enable"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_3,Reserved 3"
|
|
newline
|
|
bitfld.long 0x00 24. "MSG_REC_INT_EN,Message Receive Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RESERVED_22,Reserved 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19. "PME_ACT_STATE_NAK,PME Active State Nak Receive Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "PM_PME,PM PME Receive Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "PME_TURN_OFF,PME Turn Off Receive Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PME_TO_ACK,PME to ACK Receive Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESERVED_1,Reserved 1"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PCIE_MSG_REC_INT_STATUS,Message Receive Interrupt Status"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_3,Reserved 3"
|
|
newline
|
|
bitfld.long 0x00 24. "MSG_REC_INT_EN,Message Receive Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RESERVED_22,Reserved 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19. "PME_ACT_STATE_NAK,PME Active State Nak Receive Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "PM_PME,PM PME Receive Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "PME_TURN_OFF,PME Turn Off Receive Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PME_TO_ACK,PME to ACK Receive Interrupt" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESERVED_1,Reserved 1"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "PCIE_MSG_CODE,Message Code"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_2,Reserved 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MSG_CODE,Message Code"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "ROUTING,Routing" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 1.--4. "RESERVED_1,Reserved 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "MSG_PAYLOAD,Message Payload" "0,1"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "PCIE_MSG_DAT,Message Data"
|
|
hexmask.long 0x00 0.--31. 1. "MSG_DAT,Message Data"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "PCIE_MSG_HEAD_3RD_DW,Message Header 3rdDW"
|
|
hexmask.long 0x00 0.--31. 1. "MSG_HEAD_3RD_DW,Message Header 3rd DW"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "PCIE_MSG_HEAD_4RD_DW,Message Header 4thDW"
|
|
hexmask.long 0x00 0.--31. 1. "MSG_HEAD_4TH_DW,Message Header 4th DW"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "PCIE_INT_TABLE,Interrupt Table"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DMA_INT,Monitor Register for DMAC Interruption"
|
|
newline
|
|
bitfld.long 0x00 23. "INT_SERR_FATAL,Monitor Register for System Error Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "INT_SERR_NONFATAL,Monitor Register for System Error Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "INT_SERR_COR,Monitor Register for System Error Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "INT_SERR,Monitor Register for System Error Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "INT_CRS,Monitor Register for CRS receiving Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "INT_PM_PME,Monitor Register for PM_PME receiving Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "INT_HOT_PLUG,Monitor Register for Hot-Plug Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "INT_LINK_BANDWIDTH,Monitor Register for Change Link Bandwidth Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "RESERVED_2,Reserved 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "AXI_ERR_INT,Monitor Register for Error Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PCIE_EVT_INT,Monitor Register for Event Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "MSG_INT,Monitor Register for Message Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "RESERVED_1,Reserved 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4. "INT_MSI_RC,Monitor Register for MSI Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INTD_RC,Monitor Register for INTD Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTC_RC,Monitor Register for INTC Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "INTB_RC,Monitor Register for INTB Interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTA_RC,Monitor Register for INTA Interruption" "0,1"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PCIE_PCI_EVENT_INT_EN_0,PCIe Event Interrupt Enable 0"
|
|
bitfld.long 0x00 31. "RESERVED_4,Reserved 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "UI_LINK_WIDTH_CHANGE_DONE_EN,Enable for Up/Down Configure operation done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "UI_LINK_SPEED_CHANGE_DONE_EN,Enable for Speed Change operation done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "REQUEST_DONE_EN,Request Done EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "RESERVED_3,Reserved 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24. "CA_EN,Enable for Completion Abort" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "DEBUG_5,Debug 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_2,Reserved 2" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 14.--20. 1. "DEBUG_4,Debug 4"
|
|
newline
|
|
bitfld.long 0x00 13. "CFG_POWER_STATE_EN,Enable for CFG_POWER_STATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "RX_DLLP_PM_ENTER_L23_EN,Enable for RX_DLLP_PM_ENTER_L23_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "DEBUG_3,Debug 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "ASPM_L1_REJECTED_EN,Enable for ASPM L1 Rejceted" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "DL_DOWN_EN,Enable for DL_Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--8. "DEBUG_2,Debug 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "RESERVED_1,Reserved 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "DEBUG_1,Debug_1" "0,1"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "PCIE_PCI_EVENT_INT_STATUS_0,PCIe Event Interrupt Status 0"
|
|
bitfld.long 0x00 31. "RESERVED_4,Reserved 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "UI_LINK_WIDTH_CHANGE_DONE,Up/Down Configure operation done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "UI_LINK_SPEED_CHANGE_DONE,Speed Change operation done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "REQUEST_DONE,Request Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "RESERVED_3,Reserved 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24. "CA,Completion Abort" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "DEBUG_5,Debug 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_2,Reserved 2" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 14.--20. 1. "DEBUG_4,Debug 4"
|
|
newline
|
|
bitfld.long 0x00 13. "CFG_POWER_STATE,CFG_POWER_STATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "RX_DLLP_PM_ENTER_L23,RX_DLLP_PM_ENTER_L23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "DEBUG_3,Debug 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "ASPM_L1_REJECTED,ASPM L1 Rejected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "DL_UPDOWN,DL_UpDown status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--8. "DEBUG_2,Debug 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "MOR_STATUS,PCI_EVENT_INT_STATUS_0 bit1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "DEBUG_1,Debug 1" "0,1"
|
|
repeat 2. (strings "0" "1" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x208)++0x03
|
|
line.long 0x00 "PCIE_DBG_CTRL$1,Debug Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "PCIE_AXI_MS_ERR_INT_EN,AXI Master Error Interrupt Enable"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED_2,Reserved 2"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "WRITE_MSTERR_INT_EN,Erite Error Response Interrupt Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "RESERVED_1,Reserved 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "READ_MSTERR_INT_EN,Read Error Response Interrupt Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "PCIE_AXI_MS_ERR_INT_STATUS,AXI Master Error Interrupt Status"
|
|
bitfld.long 0x00 28.--31. "Reserved_4,Reserved 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "WRITE_ERR_ID,Write Error ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RESERVED_32,Reserved 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "READ_ERR_ID,Read Error ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "RESERVED_2,Reserved 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "WRITE_MSTERR_INT,Reserved 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "RESERVED_1,Reserved 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "READ_MSTERR_INT,Indicates the error detection on AXI Master Port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "PCIE_AXI_SL_ERR_INT_EN,AXI Slave Error Interrupt 1 Enable"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED_2,Reserved 2"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "WRITE_SLVERR_INT_EN,Write Slave Error Interrupt Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "RESERVED_1,Reserved 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "READ_SLVERR_INT_EN,Read Slave Error Interrupt Enable" "0,1,2,3"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "PCIE_AXI_SL_ERR_INT_STATUS,AXI Slave Error Interrupt 1 Status"
|
|
hexmask.long.word 0x00 16.--31. 1. "ERR_ID,Error ID"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "RESERVED_2,Reserved 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "WRITE_SLVERR_INT,Write Slave Error Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "RESERVED_1,Reserved 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "READ_SLVERR_INT,Read Slave Error Interrupt" "0,1,2,3"
|
|
repeat 2. (strings "2" "3" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x228)++0x03
|
|
line.long 0x00 "PCIE_DBG_CTRL$1,Debug Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "PCIE_PERMISSION,Permission Register"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 2. "CFG_HWINIT_EN,Register access control in CFGU" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PIPE_PHY_REG_EN,PIPE PHY Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "STEALTH_EN,Stealth Enable" "0,1"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "PCIE_SW_RST,Reset"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED_2,Reserved 2"
|
|
newline
|
|
bitfld.long 0x00 16. "FORCE_TO_D0,After PME_TO_Ack transfer it forcibly changes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "RESERVED_1,Reserved 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DEBUG,Debug" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "RST_PREG_B,Reset to Pipe (Phy Logfic) block" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RST_OUT_B,Reset output to Endpoint device" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RST_PS_B,Reset to PCI express core" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RST_LOAD_B,Reset to Configuration Register in this macro" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RST_CFG_B,Reset to Configuration Register in this macro" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RST_RSM_B,Reset to a Sticky register is performed" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RST_GP_B,Reset to PCIe Core" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RST_B,Reset to PCIe Core" "0,1"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "PCIE_MODE_SET_0,Mode Set 0 Register"
|
|
bitfld.long 0x00 31. "RESERVED_4,Reserved 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--30. "AWPROT,Sets the Protection type when PCIe to AXI transaction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "AWCACHE_L,Indicates the value of MAWCACHE [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_3,Reserved 3" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "AWLOCK2,Set the Locked access type when PCIe to AXI transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "AWCACHE_D,Indicate the value of MAWCACHE [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 15. "RESERVED_2,Reserved 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "ARPROT,Set the Protection type when CPIe to AXI transaction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "RESERVED_1,Reserved 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "ARLOCK,Set the Locked access type when PCIe to AXI transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "ARCACHE_D,Set the Cache type when PCIe to AXI transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "PCIE_MODE_SET_1,Mode Set 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_2,Reserved 2"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "MAX_ISSUE_WRITE,AXI Max Issue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "MAX_ISSUE_READ,AXI Max Issue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "MST_MAX_BURST,AXI Master Max Burst" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RESERVED_1,Reserved 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "RAM_PARITY_CHECK_EN,RAM parity enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PCIE_REQ_ORD,PCIe Request Order" "0,1"
|
|
repeat 2. (strings "4" "5" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x31C)++0x03
|
|
line.long 0x00 "PCIE_DBG_CTRL$1,Debug Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x380)++0x03
|
|
line.long 0x00 "PCIE_GPO_$1,General Purpose Output"
|
|
hexmask.long 0x00 0.--31. 1. "GPO,General purpose output"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
rgroup.long ($2+0x390)++0x03
|
|
line.long 0x00 "PCIE_GPI_$1,General Purpose Input"
|
|
hexmask.long 0x00 0.--31. 1. "GPI,General purpose input"
|
|
repeat.end
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PCIE_PCI_CORE_MODE_SET_1,PCIe Core Mode Set Register 1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_43,Reserved 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 29. "DEBUG_6,Debug 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DEBUG_5,Debug 5" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "ASPM_L1_INTERVAL_TIME,Interval setup of ASPM L1 requierment"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "RESERVED_3,Reserved 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12. "MODE_LINK_UPCONFIGURE_CAPABILITY_DISABLED,Set to a Link Upconfigure Capability bit on TS-OS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RESERVED_2,Reserved 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "DEBUG_4,Debug 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "DEBUG_3,Debug 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "MODE_SELECTABLE_DEEMPHASIS,Set to driver De-emphasis when use Endpoint mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "DEBUG_2,Debug 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "DEBUG_1,Debug 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RESERVED_1,Reserved 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "MODE_PORT,Set to a device type (endpoint / root complex)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MODE_PORT_EN_B,Mode Port Enable" "0,1"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "PCIE_PCI_CORE_CTRL_1,PCIe Core Control Register 1"
|
|
bitfld.long 0x00 29.--31. "RESERVED_4,Reserved 4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 28. "DEBUG_8,Debug 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "RESERVED_3,Reserved 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24. "DEBUG_7,Debug 7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_2,Reserved 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 21. "DEBUG_6,Debug 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "DEBUG_5,Debug 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "UI_RC_REJECT_ASPML1,ASPM L1 changes refusal control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "AUTO_PM_ACTIVE_STATE_NAK,ASPM L1 changes refusal control (Root Complex mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "UI_ENTER_L2,Control to L2 state Change" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "UI_ENTER_TXL0S,Control to TxL0s state change" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 4.--15. 1. "RESERVED_1,Reserved 1"
|
|
newline
|
|
bitfld.long 0x00 3. "DEBUG_4,Debug 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DEBUG_3,Debug 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DEBUG_2,Debug 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DEBUG_1,Debug 1" "0,1"
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "PCIE_PCI_CORE_STATUS_1,PCIe Core Status Register 1"
|
|
bitfld.long 0x00 28.--31. "RESERVED_5,Reserved 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 27. "TURN_OFF_EVENT_ACK,Monitor register for TURN_OFF_EVENT_ACK input signal (Endpoint only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "TURN_OFF_EVENT,Monitor register for TURN_OFF_EVENT output signal (Endpoint only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "D3_EVENT_ACK,Monitor register for D3_EVENT_ACK input signal (Endpoint only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "D3_EVENT,Monitor register for D3_EVENT output signal (Endpoint only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RESERVED_4,Reserved 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "DEBUG,Bit" "0: Debug 1 Bit,1: Debug 2 Bit,2: Debug 3,?..."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "RESERVED_3,Reserved 3" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "BME_DOWN,It indicates the TX side in macro cannot be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "SUSPEND_BME,It is shown that the use by the side of TX in macro should be controlled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "RESERVED_2,Reserved 2" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "LTSSM_STATE,Indicates the LTSSM status"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PMU_LINKSTATE,Link state monitor register for Power management control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "RESERVED_1,Reserved 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ORT_TRANSACTION_PENDING,Oustanding Request monitor register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "STATE_VC0_NEGOTIATIO_PENDING,Flow Control initialization operation monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DL_DOWN_STATUS,Indicate the DL_Down or DL_Up on PCIe core" "0,1"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "PCIE_PCI_LP_TST,PCIe Loopback Test Register"
|
|
bitfld.long 0x00 26.--31. "RESERVED_3,Reserved 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 25. "TEST_LOOPBACK_SLOT_POWER_MSG_FAIL,Msg Loopback Test Fail Monitor Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "TEST_LOOPBACK_SLOT_POWER_MSG_PASS,Msg Loopback Test Passl Monitor Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18.--23. "RESERVED_2,Reserved 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 17. "TEST_LOOPBACK_SLOT_POWER_MSG_SEND,Msg Loopback Test Start Control Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "TEST_LOOPBACK_SLOT_POWER_MSG_EN,Msg Loopback Test Enable control" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MODE_LOOPBACK_BIST_RESULT,Result of PHY Loopback Test output Monitor Register"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "RESERVED_1,Reserved 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "MODE_LOOPBACK_BIST,Bit" "0: Set to PHY Loopback Test Operation mode 1 Bit,1: Set to PHY Loopback Test Operation mode 2,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "MODE_LOOPBACK_RST,Reset control to PHY Loopback Test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MODE_LOOPBACK_MST_EN,Reset control to PHY Loopback Test" "0,1"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "PCIE_PCI_CORE_CTRL_2,PCIe Core Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "UI_LINK_WIDTH_CHANGE_EN,Set to Link Width"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "RESERVED_4,Reserved 4"
|
|
newline
|
|
bitfld.long 0x00 16. "UI_LINK_WIDTH_CHANGE_REQ,Control Link Width change requierment" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_3,Reserved 3"
|
|
newline
|
|
bitfld.long 0x00 8. "UI_LINK_SPEED_CHANGE,Set to Link Speed" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "RESERVED_2,Reserved 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4. "UI_LINK_CHANGE_AUTONOMOUS,Set to Link Width/Speed change resons" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "RESERVED_1,Reserved 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "UI_LINK_SPEED_CHANGE_REQ,Control Link Speed change requierment" "0,1"
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "PCIE_PCI_CORE_STATUS_2,PCIe Core Status Register 2"
|
|
bitfld.long 0x00 30.--31. "RESERVED_43,Reserved 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 29. "UI_LINK_WIDTH_CHANGE_DONE,Indicates the Link Width Change operation done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "UI_LINK_SPEED_CHANGE_DONE,Indicates the Link Speed Change operation done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "RESERVED_3,Reserved 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24. "STATE_UPCONFIGURE_CAPABLE,Upconfigure Capable bit of an opposite device is shown" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RESERVED_2,Reserved 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "STATE_NEGOTIATED_LANE_END2,Last lane of negotiated lane configuration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. "RESERVED_1,Reserved 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "STATE_NEGOTIATED_LANE_START,Master lane of negotiated lane configuration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "STATE_RECEIVER_DETECTED,Indicates the result of Receiver Detect sequence"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "STATE_DATA_RATE_ID_RECEIVED,Indicates the Data Rate Identifier field in TS2 received from remote node"
|
|
repeat 2. (strings "0" "1" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x418)++0x03
|
|
line.long 0x00 "PCIE_DBG_MON_$1,Debug Monitor Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "20" "21" )(list 0x00 0x04 0x08 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 )
|
|
rgroup.long ($2+0x420)++0x03
|
|
line.long 0x00 "PCIE_DBG_CTRL$1,Debug Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" "32" "33" "34" "35" "36" "37" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x474)++0x03
|
|
line.long 0x00 "PCIE_DBG_CTRL$1,Debug Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" "48" "49" "50" "51" "52" "53" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x4B4)++0x03
|
|
line.long 0x00 "PCIE_DBG_CTRL$1,Debug Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 3. (strings "54" "55" "56" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x4F4)++0x03
|
|
line.long 0x00 "PCIE_DBG_CTRL$1,Debug Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x700)++0x03
|
|
line.long 0x00 "PCIE_DBG_$1,Debug Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "PCIE_DMAC_CTRL,DMA Control Register"
|
|
hexmask.long 0x00 3.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "D_PMRS,DMAC PCIe Max Read Request Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "PCIE_DMAC_INT_EN,DMAC Interrupt Enable Register"
|
|
bitfld.long 0x00 31. "CH7_ERR_EN,Interruption Enable for CH7 Error" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 30. "CH7_QUE_EMP_EN,Interruption Enable for CH7 Que Empty" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 29. "CH7_STOP_EN,Interruption Enable for CH7 Stop" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 28. "CH7_END_EN,Interruption Enable for CH7 operation done" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 27. "CH6_ERR_EN,Interruption Enable for CH6 Error" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 26. "CH6_QUE_EMP_EN,Interruption Enable for CH6 Que Empty" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 25. "CH6_STOP_EN,Interruption Enable for CH6 Stop" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 24. "CH6_END_EN,Interruption Enable for CH6 operation done" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 23. "CH5_ERR_EN,Interruption Enable for CH5 Error" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 22. "CH5_QUE_EMP_EN,Interruption Enable for CH5 Que Empty" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 21. "CH5_STOP_EN,Interruption Enable for CH5 Stop" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 20. "CH5_END_EN,Interruption Enable for CH5 operation done" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 19. "CH4_ERR_EN,Interruption Enable for CH4 Error" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 18. "CH4_QUE_EMP_EN,Interruption Enable for CH4 Que Empty" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 17. "CH4_STOP_EN,Interruption Enable for CH4 Stop" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 16. "CH4_END_EN,Interruption Enable for CH4 operation done" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 15. "CH3_ERR_EN,Interruption Enable for CH3 Error" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 14. "CH3_QUE_EMP_EN,Interruption Enable for CH3 Que Empty" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 13. "CH3_STOP_EN,Interruption Enable for CH3 Stop" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 12. "CH3_END_EN,Interruption Enable for CH3 operation done" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 11. "CH2_ERR_EN,Interruption Enable for CH2 Error" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 10. "CH2_QUE_EMP_EN,Interruption Enable for CH2 Que Empty" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 9. "CH2_STOP_EN,Interruption Enable for CH2 Stop" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 8. "CH2_END_EN,Interruption Enable for CH2 operation done" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 7. "CH1_ERR_EN,Interruption Enable for CH1 Error" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 6. "CH1_QUE_EMP_EN,Interruption Enable for CH1 Que Empty" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 5. "CH1_STOP_EN,Interruption Enable for CH1 Stop" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 4. "CH1_END_EN,Interruption Enable for CH1 operation done" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 3. "CH0_ERR_EN,Interruption Enable for CH0 Error" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 2. "CH0_QUE_EMP_EN,Interruption Enable for CH0 Que Empty" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 1. "CH0_STOP_EN,Interruption Enable for CH0 Stop" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 0. "CH0_END_EN,Interruption Enable for CH0 operation done" "0: Disable,1: Enable"
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "PCIE_DMAC_INT_STATUS,DMAC Interrupt Status Register"
|
|
bitfld.long 0x00 31. "CH7_ERR,It is set when Error occurs in AXI or PCIe duaring a DMA transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CH7_QUE_EMP,It is set when a list is extracted and QUE (moving to an execution descriptor list) becomes empty from descriptor cue" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "CH7_STOP,It is set when DMAC has stopped on the way" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "CH7_END,It is set when DMAC is completed normally" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "CH6_ERR,It is set when Error occurs in AXI or PCIe duaring a DMA transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "CH6_QUE_EMP,It is set when a list is extracted and QUE (moving to an execution descriptor list) becomes empty from descriptor cue" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "CH6_STOP,It is set when DMAC has stopped on the way" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "CH6_END,It is set when DMAC is completed normally" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "CH5_ERR,It is set when Error occurs in AXI or PCIe duaring a DMA transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "CH5_QUE_EMP,It is set when a list is extracted and QUE (moving to an execution descriptor list) becomes empty from descriptor cue" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "CH5_STOP,It is set when DMAC has stopped on the way" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "CH5_END,It is set when DMAC is completed normally" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CH4_ERR,It is set when Error occurs in AXI or PCIe duaring a DMA transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CH4_QUE_EMP,It is set when a list is extracted and QUE (moving to an execution descriptor list) becomes empty from descriptor cue" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CH4_STOP,It is set when DMAC has stopped on the way" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CH4_END,It is set when DMAC is completed normally" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "CH3_ERR,It is set when Error occurs in AXI or PCIe duaring a DMA transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CH3_QUE_EMP,It is set when a list is extracted and QUE (moving to an execution descriptor list) becomes empty from descriptor cue" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CH3_STOP,It is set when DMAC has stopped on the way" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "CH3_END,It is set when DMAC is completed normally" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CH2_ERR,It is set when Error occurs in AXI or PCIe duaring a DMA transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH2_QUE_EMP,It is set when a list is extracted and QUE (moving to an execution descriptor list) becomes empty from descriptor cue" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH2_STOP,It is set when DMAC has stopped on the way" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH2_END,It is set when DMAC is completed normally" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CH1_ERR,It is set when Error occurs in AXI or PCIe duaring a DMA transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CH1_QUE_EMP,It is set when a list is extracted and QUE (moving to an execution descriptor list) becomes empty from descriptor cue" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CH1_STOP,It is set when DMAC has stopped on the way" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CH1_END,It is set when DMAC is completed normally" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "CH0_ERR,It is set when Error occurs in AXI or PCIe duaring a DMA transfer" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "CH0_QUE_EMP,It is set when a list is extracted and QUE (moving to an execution descriptor list) becomes empty from descriptor cue" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CH0_STOP,It is set when DMAC has stopped on the way" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "CH0_END,It is set when DMAC is completed normally" "0,1"
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "PCIE_DMAC_CH0_CTRL,DMAC Channel Control Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
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bitfld.long 0x00 8. "QUE_CLR,QUE Clear" "0,1"
|
|
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bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
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bitfld.long 0x00 1. "QUE_EN,QUE Clear" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "RDMA_EN,Register DMA Enable" "0,1"
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "PCIE_DMAC_CH0_Q_ENTRY_LOWER,DMAC Que Entry Register (Lower)"
|
|
hexmask.long 0x00 0.--31. 1. "QUE_ENTRY,It is a register for a descriptor Que List setup"
|
|
group.long 0x90C++0x03
|
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line.long 0x00 "PCIE_DMAC_CH0_Q_ENTRY_UPPER,DMAC Que Entry Register (Upper)"
|
|
bitfld.long 0x00 26.--31. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
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bitfld.long 0x00 25. "QUE_ENTRY_EI,Enable of interruption (Interrupt Status CHx_END) when completion of processing of a descriptor list" "0: Disable (Not reported),1: Enable (Reported)"
|
|
newline
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bitfld.long 0x00 24. "QUE_ENTRY_LS,Enable of DMA stop when completion of processing of a descriptor list" "0: Disable (Not stop),1: Enable (stop)"
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|
newline
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hexmask.long.byte 0x00 16.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "QUE_ENTRY_LABEL,The label of a list is shown"
|
|
rgroup.long 0x920++0x03
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line.long 0x00 "PCIE_DMAC_CH0_DESC_CTRL,DMAC Descriptor Control Register"
|
|
bitfld.long 0x00 28.--31. "DSCFM,This field shows the DSCFM value of the descriptor table under transmittion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x00 27. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
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bitfld.long 0x00 26. "WBD,This bit shows the WBD value of the descriptor table under transmittion" "0,1"
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|
newline
|
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bitfld.long 0x00 25. "LE,This bit shows the LE value of the descriptor table under transmittion" "0,1"
|
|
newline
|
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bitfld.long 0x00 24. "LV,This bit shows the LV value of the descriptor table under transmittion" "0,1"
|
|
newline
|
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bitfld.long 0x00 23. "D,This bit shows the D value of the descriptor table under transmittion" "0,1"
|
|
newline
|
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hexmask.long.byte 0x00 16.--22. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "STS,This bit shows the STS value of the descriptor table under transmittion"
|
|
group.long 0x924++0x03
|
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line.long 0x00 "PCIE_DMAC_CH0_SRC_ADDR,DMAC Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DMA_S_ADDR,Sets up the start address of the source which performs a DMA transfer"
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "PCIE_DMAC_CH0_DST_ADDR,DMAC Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DMA_D_ADDR,Sets up the destination address of the source which performs a DMA transfer"
|
|
group.long 0x92C++0x03
|
|
line.long 0x00 "PCIE_DMAC_CH0_SIZE,DMAC Size Register"
|
|
hexmask.long 0x00 0.--31. 1. "DMA_SIZE,Set to a number of byte on DMA transmittion"
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "PCIE_DMAC_CH0_PU_ADDR,DMAC PCIe Upper Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DMA_PU_ADDR,Sets to the start address on the PCIe side [63:32]"
|
|
group.long 0x934++0x03
|
|
line.long 0x00 "PCIE_DMAC_CH0_TRANS_CTRL,DMAC Transaction Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "CCH_L,Shows the Cache Type (A*CACHE[3:0]) value issued to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x00 16.--19. "CCH_D,Shows the Cache Type (A*CACHE[3:0]) value issued to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 15. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "DMA_TC,Set the Trafic Class issued to PCIe" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 10.--11. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "DMA_ATB,Set the attribute issued to PCIe" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA_DIR,Set the direction of a DMA transfer" "0: PCIe to AXI,1: AXI to PCIe"
|
|
rgroup.long 0x93C++0x03
|
|
line.long 0x00 "PCIE_DMAC_CH0_LP,DMAC Link Pointer Register"
|
|
hexmask.long 0x00 0.--31. 1. "DMA_LP,Shows the Byte number which the DMA transfer has not completed"
|
|
rgroup.long 0x950++0x03
|
|
line.long 0x00 "PCIE_DMAC_CH0_REST_SIZE,DMAC Rest Size Register"
|
|
hexmask.long 0x00 0.--31. 1. "DMAC_CH0_REST_SIZE,Shows AXI transmission adderss"
|
|
rgroup.long 0x954++0x03
|
|
line.long 0x00 "PCIE_DMAC_CH0_AXI_REQ_ADDR,DMAC AXI Request Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "AXI_REQ_ADDR,Shows AXI transmission address"
|
|
rgroup.long 0x958++0x03
|
|
line.long 0x00 "PCIE_DMAC_CH0_PCIE_REQ_ADDR_LOWER,DMAC PCIe Request Address Register (Lower)"
|
|
hexmask.long 0x00 0.--31. 1. "PCIE_REQ_ADDR,Shows PCIe transmission adderss (Lower 32bits)"
|
|
rgroup.long 0x95C++0x03
|
|
line.long 0x00 "PCIE_DMAC_CH0_PCIE_REQ_ADDR_UPPER,DMAC PCIe Request Address Register (Upper)"
|
|
hexmask.long 0x00 0.--31. 1. "PCIE_REQ_ADDR,Shows PCIe transmission adderss (Upper 32bits)"
|
|
rgroup.long 0x960++0x03
|
|
line.long 0x00 "PCIE_DMAC_CH0_QUE_STATUS,DMAC Que Status Register"
|
|
hexmask.long 0x00 5.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 4. "GO_LIST,This bit shows the existence of the descriptor list which should be performed" "0: Nothing,1: Go List"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "LIST_NUM,This field shows the number of the descriptor lists which exist in QUE (list of under present execution is not included)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x968++0x03
|
|
line.long 0x00 "PCIE_DMAC_CH0_ERR_STATUS,DMAC Error Status Register"
|
|
hexmask.long.word 0x00 19.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 18. "CFG_BM_DIS_EP,Set: End Point Mode and Bus Master Enable Off (PCIe Configuration Register Device Control[2] =0) is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "BME_SUP,Set: The suspend signal from a PCIe core is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "BME_DOWN,Set: The stop signal from a PCIe core is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 13. "MOR_CD_PERR,Set: MOR_CD_PERR is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "MOR_CH_PERR,Set: MOR_CH_PERR is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "MOR_EP_ERR,Set: Poisoned Completion is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MOR_STATUS,The value is shown when it is except 000b (Success)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2. "AXI_LEN_ERR,Set: When less than (or more than) the length which Read Data from AXI Slave required" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "AXI_RESP,The slave response at the time of an AXI Master transaction is shown" "0,1,2,3"
|
|
rgroup.long 0x1000++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_ID,'PCIe Common Configuration Space - ID Register'"
|
|
hexmask.long.word 0x00 16.--31. 1. "DEVICE_ID,Device ID"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "VENDOR_ID,Vendor ID"
|
|
rgroup.long 0x1004++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_STAT_CMD,'PCIe Common Configuration Space - Status and Command Register'"
|
|
hexmask.long.word 0x00 16.--31. 1. "STATUS,Status"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "COMMAND,Command"
|
|
rgroup.long 0x1008++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_CLASS_REV,'PCIe Common Configuration Space - Class and Revision Register'"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "CLASS_CODE,Class Code"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "REVISION_ID,Revision ID"
|
|
rgroup.long 0x100C++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_HDR_TY,'PCIe Common Configuration Space - Header Type and Cash Line Size Register'"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BIST,BIST"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "HEADER_TYPE,Header Type"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MST_LATENCY_TIMER,Master Latency Timer"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CASH_LINE_SIZE,Cash Line Size"
|
|
rgroup.long 0x1010++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BAR0,'PCIe Type0 Configuration Space EP - Base Address Register 0'"
|
|
hexmask.long 0x00 0.--31. 1. "BAR_0,Base Address Register 0"
|
|
rgroup.long 0x1014++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BAR1,'PCIe Type0 Configuration Space EP - Base Address Register 1'"
|
|
hexmask.long 0x00 0.--31. 1. "BAR_1,Base Address Register 1"
|
|
rgroup.long 0x1018++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BAR2,'PCIe Type0 Configuration Space EP - Base Address Register 2'"
|
|
hexmask.long 0x00 0.--31. 1. "BAR_2,Base Address Register 2"
|
|
rgroup.long 0x101C++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BAR3,'PCIe Type0 Configuration Space EP - Base Address Register 3'"
|
|
hexmask.long 0x00 0.--31. 1. "BAR_3,Base Address Register 3"
|
|
rgroup.long 0x1020++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BAR4,'PCIe Type0 Configuration Space EP - Base Address Register 4'"
|
|
hexmask.long 0x00 0.--31. 1. "BAR_4,Base Address Register 4"
|
|
rgroup.long 0x1024++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BAR5,'PCIe Type0 Configuration Space EP - Base Address Register 5'"
|
|
hexmask.long 0x00 0.--31. 1. "BAR_5,Basic Address Register 5"
|
|
rgroup.long 0x1028++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_CIS_PNTR,'PCIe Type0 Configuration Space EP - Card-bus CIS Pointer'"
|
|
hexmask.long 0x00 0.--31. 1. "CB_CIS_PNTR,Card Bus CIS Pointer"
|
|
rgroup.long 0x102C++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_SSID,'PCIe Type0 Configuration Space EP - Subsystem ID Register'"
|
|
hexmask.long.word 0x00 16.--31. 1. "SS_ID,Subsystem ID"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "SS_VENDOR_ID,Subsystem Vendor ID"
|
|
rgroup.long 0x1030++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_EXP_ROM_BA,'PCIe Type0 Configuration Space EP - Expansion ROM Base Address'"
|
|
hexmask.long 0x00 0.--31. 1. "EXP_ROM_BA,Expansion ROM Base Address"
|
|
rgroup.long 0x1034++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_CAP_PNTR,'PCIe Type0 Configuration Space EP - Capabilities Pointer'"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAP_PNTR,Capabilities Pointer"
|
|
rgroup.long 0x103C++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_INT,'PCIe Type0 Configuration Space EP - Interrupr Pin and Line'"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAX_LAT,Max Lat"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "MIN_GNT,Min Gnt"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "INT_LINE,Interrupt Line"
|
|
rgroup.long 0x1040++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_PWR_MAN_CAP,'PCIe Power Management Capability Structure - Power Management Capability Register'"
|
|
hexmask.long.word 0x00 16.--31. 1. "PCI_CR_PWR_MAN_CAP,Power Management Capability Register"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "NEXT_CAPABILITY_POINTER,Next Capability Pointer"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPABILITY_ID,Capability ID"
|
|
rgroup.long 0x1044++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_PWR_MAN_STAT,'PCIe Power Management Capability Structure - Power Management Status Register'"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA,Data"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "PWR_MAN_STAT_REG,Power Management Status Register"
|
|
rgroup.long 0x1050++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_MSI_CAP,'PCIe MSI and MSI-X Capability Structure - MSI Capability Register'"
|
|
hexmask.long 0x00 0.--31. 1. "MSI_CAP_REG,MSI Capability Register"
|
|
rgroup.long 0x1054++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_MSI_ADDR_L,'PCIe MSI and MSI-X Capability Structure - MSI Address Lower 32 Bits'"
|
|
hexmask.long 0x00 0.--31. 1. "MSI_ADDR_L,MSI Address Low 32 Bits"
|
|
rgroup.long 0x1058++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_MSI_ADDR_U,'PCIe MSI and MSI-X Capability Structure - MSI Address Upper 32 Bits'"
|
|
hexmask.long 0x00 0.--31. 1. "MSI_ADDR_U,MSI Address Upper 32 Bits"
|
|
rgroup.long 0x105C++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_MSI_DAT,'PCIe MSI and MSI-X Capability Structure - MSI Data'"
|
|
hexmask.long 0x00 0.--31. 1. "MSI_DATA,MSI Data"
|
|
rgroup.long 0x1060++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_CAP,'PCIe MSI and MSI-X Capability Structure - PCI Express Capability '"
|
|
hexmask.long.word 0x00 16.--31. 1. "PCIE_CAP_REG,PCI Express Capability Register"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "NEXT_CAP_PNTR,Next Cap Pointer"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "PCIE_CAP_ID,PCIe Cap ID"
|
|
rgroup.long 0x1064++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_DEV_CAP,'PCIe MSI and MSI-X Capability Structure - PCI Express Devices Capabilities'"
|
|
hexmask.long 0x00 0.--31. 1. "DEV_CAP,Device Capabilities"
|
|
rgroup.long 0x1068++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_DEV_STAT_CTRL,'PCIe MSI and MSI-X Capability Structure - PCI Express Devices Status and Control'"
|
|
hexmask.long.word 0x00 16.--31. 1. "DEV_STAT,Device Status"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DEV_CTRL,Device Control"
|
|
rgroup.long 0x106C++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_LINK_CAP,'PCIe MSI and MSI-X Capability Structure - PCI Express Link Capabilities'"
|
|
hexmask.long 0x00 0.--31. 1. "LINK_CAP,Link Capabilities"
|
|
rgroup.long 0x1070++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_LINK_STAT_CTRL,'PCIe MSI and MSI-X Capability Structure - PCI Express Link Status and Control'"
|
|
hexmask.long.word 0x00 16.--31. 1. "LINK_STAT,Link Status"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "LINK_CTRL,Link Control"
|
|
rgroup.long 0x1084++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_DEV_CAP2,'PCIe MSI and MSI-X Capability Structure - PCI Express Devices Capabilities 2'"
|
|
hexmask.long 0x00 0.--31. 1. "DEV_CAP_2,Device Capability 2"
|
|
rgroup.long 0x1088++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_DEV_STAT_CTRL2,'PCIe MSI and MSI-X Capability Structure - PCI Express Devices Status and Control 2'"
|
|
hexmask.long.word 0x00 16.--31. 1. "DEV_STAT_2,Device Status 2"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DEV_CTRL_2,Device Control 2"
|
|
rgroup.long 0x108C++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_LINK_CAP2,'PCIe MSI and MSI-X Capability Structure - PCI Express Link Capabilities 2'"
|
|
hexmask.long 0x00 0.--31. 1. "LINK_CAP_2,Link Capabilities 2"
|
|
rgroup.long 0x1090++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_LINK_STAT_CTRL2,'PCIe MSI and MSI-X Capability Structure - PCI Express Link Status and Control 2'"
|
|
hexmask.long.word 0x00 16.--31. 1. "LINK_STAT_2,Link Status 2"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "LINK_CTRL_2,Link Control 2"
|
|
rgroup.long 0x10A0++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BAR_MSK00_L,'Special Register - Base Address Register Mask00 (Lower)'"
|
|
hexmask.long 0x00 0.--31. 1. "BAR_MSK00_L,Basic Address Register Mask00 (Lower)"
|
|
rgroup.long 0x10A4++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BAR_MSK00_U,'Special Register - Base Address Register Mask00 (Upper)'"
|
|
hexmask.long 0x00 0.--31. 1. "BAR_MSK00_U,Basic Address Register Mask00 (Upper)"
|
|
rgroup.long 0x10A8++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BAR_MSK01_L,'Special Register - Base Address Register Mask01 (Lower)'"
|
|
hexmask.long 0x00 0.--31. 1. "BAR_MSK01_L,Basic Address Register Mask01 (Lower)"
|
|
rgroup.long 0x10AC++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BAR_MSK01_U,'Special Register - Base Address Register Mask01 (Upper)'"
|
|
hexmask.long 0x00 0.--31. 1. "BAR_MSK01_U,Basic Address Register Mask01 (Upper)"
|
|
rgroup.long 0x10B0++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BAR_MSK02_L,'Special Register - Base Address Register Mask02 (Lower)'"
|
|
hexmask.long 0x00 0.--31. 1. "BAR_MSK02_L,Basic Address Register Mask02 (Lower)"
|
|
rgroup.long 0x10B4++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BAR_MSK02_U,'Special Register - Base Address Register Mask02 (Upper)'"
|
|
hexmask.long 0x00 0.--31. 1. "BAR_MSK02_U,Basic Address Register Mask02 (Upper)"
|
|
rgroup.long 0x10C0++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BASE_SIZE00,'Special Register - Base Size 00'"
|
|
hexmask.long 0x00 0.--31. 1. "BASE_SIZE00,Base Size00"
|
|
rgroup.long 0x10C4++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BASE_SIZE01,'Special Register - Base Size 01'"
|
|
hexmask.long 0x00 0.--31. 1. "BASE_SIZE01,Base Size01"
|
|
rgroup.long 0x10C8++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_BASE_SIZE02,'Special Register - Base Size 02'"
|
|
hexmask.long 0x00 0.--31. 1. "BASE_SIZE02,Base Size02"
|
|
rgroup.long 0x10D0++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_TYPE_SUPP,Type Supported"
|
|
hexmask.long 0x00 0.--31. 1. "TYPE_SUPP,Type Supported"
|
|
rgroup.long 0x1100++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_AER_ENH_CAP,'Advanced Error Reporting (AER) Capability - PCI Express Enhanced Capability Header'"
|
|
hexmask.long 0x00 0.--31. 1. "PCIE_ENH_CAP_HDR,PCI Express Enhanced Capability Header"
|
|
rgroup.long 0x1104++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_AER_UNCOR_ERR_STAT,'Advanced Error Reporting (AER) Capability - Uncorrectable Error Status Register'"
|
|
hexmask.long 0x00 0.--31. 1. "UNCOR_ERR_STAT,Uncorrectable Error Status Register"
|
|
rgroup.long 0x1108++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_AER_UNCOR_ERR_MSK,'Advanced Error Reporting (AER) Capability - Uncorrectable Error Mask Register'"
|
|
hexmask.long 0x00 0.--31. 1. "UNCOR_ERR_MSK,Uncorrectable Error Mask Register"
|
|
rgroup.long 0x110C++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_AER_UNCOR_ERR_SEV,'Advanced Error Reporting (AER) Capability - Uncorrectable Error Severity Register'"
|
|
hexmask.long 0x00 0.--31. 1. "UNCOR_ERR_SEV,Uncorrectable Error Severity Register"
|
|
rgroup.long 0x1110++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_AER_COR_ERR_STAT,'Advanced Error Reporting (AER) Capability - Correctable Error Status Register'"
|
|
hexmask.long 0x00 0.--31. 1. "COR_ERR_STAT,Correctable Error Status Register"
|
|
rgroup.long 0x1114++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_AER_COR_ERR_MSK,'Advanced Error Reporting (AER) Capability - Correctable Error Mask Register'"
|
|
hexmask.long 0x00 0.--31. 1. "COR_ERR_MSK,Correctable Error Mask Register"
|
|
rgroup.long 0x1118++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_AER_CAP_CTRL,'Advanced Error Reporting (AER) Capability - Advanced Error Capabilities and Control Register'"
|
|
hexmask.long 0x00 0.--31. 1. "AER_CAP_CTRL,Advanced Error Capabilities and Control Register"
|
|
rgroup.long 0x111C++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_AER_HEAD_LOG0,'Advanced Error Reporting (AER) Capability - Header Log Register 0'"
|
|
hexmask.long 0x00 0.--31. 1. "HEAD_LOG_0,Header Log Register 0"
|
|
rgroup.long 0x1120++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_AER_HEAD_LOG1,'Advanced Error Reporting (AER) Capability - Header Log Register 1'"
|
|
hexmask.long 0x00 0.--31. 1. "HEAD_LOG_1,Header Log Register 1"
|
|
rgroup.long 0x1124++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_AER_HEAD_LOG2,'Advanced Error Reporting (AER) Capability - Header Log Register 2'"
|
|
hexmask.long 0x00 0.--31. 1. "HEAD_LOG_2,Header Log Register 2"
|
|
rgroup.long 0x1128++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_AER_HEAD_LOG3,'Advanced Error Reporting (AER) Capability - Header Log Register 3'"
|
|
hexmask.long 0x00 0.--31. 1. "HEAD_LOG_3,Header Log Register 3"
|
|
rgroup.long 0x1140++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_ENH_CAP_HEAD,'Device Serial Number Capability - PCI Express Enhanced Capability Header'"
|
|
hexmask.long 0x00 0.--31. 1. "PCIE_ENH_CAP_HEAD,PCI Express Enhanced Capability Header"
|
|
rgroup.long 0x1144++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_SER_NBR_L,'Device Serial Number Capability - Serial Number Register (Lower DW)'"
|
|
hexmask.long 0x00 0.--31. 1. "SER_NBR_L,Serial Nmber Register (Lower DW)"
|
|
rgroup.long 0x1148++0x03
|
|
line.long 0x00 "PCIE_PCI_CR_SER_NBR_U,'Device Serial Number Capability - Serial Number Register (Upper DW)'"
|
|
hexmask.long 0x00 0.--31. 1. "SER_NBR_U,Serial Number Register (Upper DW)"
|
|
repeat 5. (strings "1" "2" "3" "4" "5" )(list 0x00 0x08 0x10 0x18 0x20 )
|
|
group.long ($2+0x2000)++0x03
|
|
line.long 0x00 "PCIE_DRV_V_LV_CTRL_$1,Driver Voltage Level Control Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 3. (strings "1" "2" "3" )(list 0x00 0x08 0x10 )
|
|
group.long ($2+0x2028)++0x03
|
|
line.long 0x00 "PCIE_DRV_E_LV_CTRL_$1,Driver Emphasis Level Control Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
group.long 0x2040++0x03
|
|
line.long 0x00 "PCIE_REC_CTRL,Recevier Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x2048++0x03
|
|
line.long 0x00 "PCIE_PIPE_CTRL,Pipe Logic Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x2050++0x03
|
|
line.long 0x00 "PCIE_MON,Monitor Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat 16. (strings "57" "58" "59" "60" "61" "62" "63" "64" "65" "66" "67" "68" "69" "70" "71" "72" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x20C0)++0x03
|
|
line.long 0x00 "PCIE_DBG_CTRL$1,Debug Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "73" "74" "75" "76" "77" "78" "79" "80" "81" "82" "83" "84" "85" "86" "87" "88" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x2100)++0x03
|
|
line.long 0x00 "PCIE_DBG_CTRL$1,Debug Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 16. (strings "89" "90" "91" "92" "93" "94" "95" "96" "97" "98" "99" "100" "101" "102" "103" "104" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x2140)++0x03
|
|
line.long 0x00 "PCIE_DBG_CTRL$1,Debug Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 4. (strings "105" "106" "107" "108" )(list 0x00 0x04 0x08 0x0C )
|
|
rgroup.long ($2+0x2180)++0x03
|
|
line.long 0x00 "PCIE_DBG_CTRL$1,Debug Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
repeat 12. (strings "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
|
|
rgroup.long ($2+0x21C0)++0x03
|
|
line.long 0x00 "PCIE_DBG_MON$1,Debug Monitor Register"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
repeat.end
|
|
tree.end
|
|
tree "USB_HOST"
|
|
base ad:0xF9000000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "USB_HOST_HCREVISION,HcRevision register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "REVISION,Indicates the version of the HCI Specification implemented in this host controller"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USB_HOST_HCCONTROL,HcControl register"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 10. "RWE,Specify whether to assert PME" "0: Do not assert PME when Resume is detected,1: Assert PME when Resume is detected"
|
|
newline
|
|
bitfld.long 0x00 9. "RWC,RemoteWakeUp Connect" "0: RemoteWakeUp is not supported,1: RemoteWakeUp is supported"
|
|
newline
|
|
bitfld.long 0x00 8. "IR,Interrupt Routing" "0: INTA,1: SMI"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "HCFS,Host Controller Functional State" "0: USB reset,1: USB resume,2: USB operational,3: USB suspend"
|
|
newline
|
|
bitfld.long 0x00 5. "BLE,Bulk List Enable" "0: Do not process the bulk list,1: Process the bulk list"
|
|
newline
|
|
bitfld.long 0x00 4. "CLE,Control List Enable" "0: Do not process the control list,1: Process the control list"
|
|
newline
|
|
bitfld.long 0x00 3. "IE,Isochronous Enable" "0: Do not process Isochronous transfer,1: Process Isochronous transfer"
|
|
newline
|
|
bitfld.long 0x00 2. "PLE,Periodic List Enable" "0: Do not process the periodic frame list,1: Process the periodic frame list"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CBSR,Control Bulk Service Ratio" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USB_HOST_HCCOMMANDSTATUS,HcCommandStatus register"
|
|
hexmask.long.word 0x00 18.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "SOC,Scheduling Overrun Count" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 4.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 3. "OCR,Ownership Change Request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "BLF,Bulk List Field" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CLF,Control List Field" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "HCR,Host Controller Reset" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USB_HOST_HCINTERRUPTSTATUS,HcInterruptStatus register"
|
|
hexmask.long 0x00 7.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "RHSC,Root Hub Status Change" "0: No RHSC interrupt has occurred,1: An RHSC interrupt has occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "FNO,Frame Number Overflow" "0: No FNO interrupt has occurred,1: An FNO interrupt has occurred"
|
|
newline
|
|
bitfld.long 0x00 4. "UE,Unrecoverable Error" "0: No UE interrupt has occurred,1: An UE interrupt has occurred"
|
|
newline
|
|
bitfld.long 0x00 3. "RD,Resume Detected" "0: No RD interrupt has occurred,1: An RD interrupt has occurred"
|
|
newline
|
|
bitfld.long 0x00 2. "SF,Start Of Frame" "0: No SF interrupt has occurred,1: An SF interrupt has occurred"
|
|
newline
|
|
bitfld.long 0x00 1. "WDH,Writeback Done Head" "0: WDH interrupt has occurred,1: WDH interrupt has occurred"
|
|
newline
|
|
bitfld.long 0x00 0. "SO,Scheduling Overrun" "0: No SO interrupt has occurred,1: An SO interrupt has occurred"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USB_HOST_HCINTERRUPTENABLE,HcInterruptEnable register"
|
|
bitfld.long 0x00 31. "MIE,Master Interrupt Enable" "0: Ignore,1: Enable the"
|
|
newline
|
|
hexmask.long.tbyte 0x00 7.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "RHSCE,Root Hub Status Change Enable" "0: Ignore,1: Enable the RHSC"
|
|
newline
|
|
bitfld.long 0x00 5. "FNOE,Frame Number Overflow Enable" "0: Ignore,1: Enable the FNO"
|
|
newline
|
|
bitfld.long 0x00 4. "UEE,Unrecoverable Error Enable" "0: Ignore,1: Enable the UE"
|
|
newline
|
|
bitfld.long 0x00 3. "RDE,Resume Detected Enable" "0: Ignore,1: Enable the RD"
|
|
newline
|
|
bitfld.long 0x00 2. "SFE,Start Of Frame Enbale" "0: Ignore,1: Enable the SF"
|
|
newline
|
|
bitfld.long 0x00 1. "WDHE,Writeback Done Head Enable" "0: Ignore,1: Enable the WDH"
|
|
newline
|
|
bitfld.long 0x00 0. "SOE,Scheduling Overrun Enable" "0: Ignore,1: Enable the SO"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USB_HOST_HCINTERRUPTDISABLE,HcInterruptDisable register"
|
|
bitfld.long 0x00 31. "MID,Master Interrupt Disable" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 7.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6. "RHSCD,Root Hub Status Change Disable" "0: Ignore,1: Disable the RHSC"
|
|
newline
|
|
bitfld.long 0x00 5. "FNOD,Frame Number Overflow Disable" "0: Ignore,1: Disable the FNOD"
|
|
newline
|
|
bitfld.long 0x00 4. "UED,Unrecoverable Error Disable" "0: Ignore,1: Disable the UE"
|
|
newline
|
|
bitfld.long 0x00 3. "RDD,Resume Detected Disable" "0: Ignore,1: Disable the RD"
|
|
newline
|
|
bitfld.long 0x00 2. "SFD,Start Of Frame Disable" "0: Ignore,1: Disable the SF"
|
|
newline
|
|
bitfld.long 0x00 1. "WDHD,Writeback Done Head Disable" "0: Ignore,1: Disable the WDH"
|
|
newline
|
|
bitfld.long 0x00 0. "SOD,Scheduling Overrun Disable" "0: Ignore,1: Disable the SO"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "USB_HOST_HCHCCA,HcHCCA register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "HCHCCA,Set the RAM base address assigned to the Host Controller Communication Area (HCCA)"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USB_HOST_HCPERIODCURRENTED,HcPeriodicCurrentED register"
|
|
hexmask.long 0x00 4.--31. 1. "PERIODICCURRENTED,Indicates the physical address of the current ED in the periodic frame list"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "USB_HOST_HCCONTROLHEADED,HcControlHeadED register"
|
|
hexmask.long 0x00 4.--31. 1. "CONTROLHEADED,Specify the physical address of the first ED in the control list"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "USB_HOST_HCCONTROLCURRENTED,HcControlCurrentED register"
|
|
hexmask.long 0x00 4.--31. 1. "CONTROLCURRENTED,Indicates the physical address of the current ED in the control list"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x28++0x03
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line.long 0x00 "USB_HOST_HCBULKHEADED,HcBulkHeadED register"
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hexmask.long 0x00 4.--31. 1. "BULKHEADED,Specify the physical address of the first ED in the bulk list"
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bitfld.long 0x00 0.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x2C++0x03
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line.long 0x00 "USB_HOST_HCBULKCURRENTED,HcBulkCurrentED register"
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hexmask.long 0x00 4.--31. 1. "BULKCURRENTED,Indicates the physical address of the current ED in the bulk list"
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bitfld.long 0x00 0.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x30++0x03
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line.long 0x00 "USB_HOST_HCDONEHEAD,HcDoneHead register"
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hexmask.long 0x00 4.--31. 1. "DONEHEAD,Indicates the physical address of HcDoneHead in the host controller"
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bitfld.long 0x00 0.--3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x34++0x03
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line.long 0x00 "USB_HOST_HCFMINTERVAL,Hc Frame Interval register"
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bitfld.long 0x00 31. "FIT,Frame Interval Toggle" "0,1"
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hexmask.long.word 0x00 16.--30. 1. "FSMPS,FS Largest Data Packet"
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|
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bitfld.long 0x00 14.--15. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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hexmask.long.word 0x00 0.--13. 1. "FI,Frame Interval"
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rgroup.long 0x38++0x03
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line.long 0x00 "USB_HOST_HCFMREMAINING,Hc Frame Remaining register"
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bitfld.long 0x00 31. "FRT,Frame Remaining Toggle" "0,1"
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hexmask.long.tbyte 0x00 14.--30. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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|
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hexmask.long.word 0x00 0.--13. 1. "FR,Frame Remaining"
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rgroup.long 0x3C++0x03
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line.long 0x00 "USB_HOST_HCFMNUMBER,Hc Frame Number register"
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hexmask.long.word 0x00 16.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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|
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hexmask.long.word 0x00 0.--15. 1. "FRAMENUMBER,Indicates the number of frames that have passed"
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group.long 0x40++0x03
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line.long 0x00 "USB_HOST_HCPERIODICSTART,HcPeriodicStart register"
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hexmask.long.tbyte 0x00 14.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.word 0x00 0.--13. 1. "PERIODICSTART,Indicates the time when the host controller starts periodic frame list processing within a frame"
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group.long 0x44++0x03
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line.long 0x00 "USB_HOST_HCLSTHRESHOLD,HcLSThreshold register"
|
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hexmask.long.tbyte 0x00 12.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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|
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hexmask.long.word 0x00 0.--11. 1. "HCLSTHRESHOLD,Use this bit to specify the threshold value at which transfer can be performed for the remaining frame time during an LS transfer"
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group.long 0x48++0x03
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line.long 0x00 "USB_HOST_HCRHDESCRIPTORA,HcRhDescriptorA register"
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hexmask.long.byte 0x00 24.--31. 1. "POTPGT,Power On To Power Good Time"
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hexmask.long.word 0x00 13.--23. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 12. "NOCP,No Over Current Protection" "0: Support the overcurrent status,1: Do not support the overcurrent status"
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bitfld.long 0x00 11. "OCPM,Over Current Protection Mode" "0: The overcurrent status is reported collectively,1: The overcurrent status is reported on a.."
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bitfld.long 0x00 10. "DT,Device Type" "0,1"
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bitfld.long 0x00 9. "NPS,No Power Switching" "0: The power can be switched on or off,1: The power remains on while the host controller"
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bitfld.long 0x00 8. "PSM,Power Switching Mode" "0: All ports are powered at the same time,1: Each port is powered individually"
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hexmask.long.byte 0x00 0.--7. 1. "NDP,Number Downstream Port"
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group.long 0x4C++0x03
|
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line.long 0x00 "USB_HOST_HCRHDESCRIPTORB,HcRhDescriptorB register"
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hexmask.long.word 0x00 16.--31. 1. "PPCM,Port Power Control Mask"
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hexmask.long.word 0x00 0.--15. 1. "DR,Device Removable"
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group.long 0x50++0x03
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line.long 0x00 "USB_HOST_HCRHSTATUS,HcRhStatus register"
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bitfld.long 0x00 31. "CRWE,Clear Remote Wakeup Enable" "0,1"
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hexmask.long.word 0x00 18.--30. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 17. "OCIC,Over Current Indicate Change" "0: The overcurrent status has not changed,1: The overcurrent status has changed"
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bitfld.long 0x00 16. "R_LPSC__W_SGP,On Read: Local Power Status Change" "0,1"
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bitfld.long 0x00 15. "R_DRWE__W_SRWE,On Read: Device Remote Wakeup Enable" "0: ConnectStatusChange is not a RemoteWakeup event,1: ConnectStatusChange is a RemoteWakeup event"
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hexmask.long.word 0x00 2.--14. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 1. "OCI,Over Current Indicator" "0: The port is normal,1: The port is in the overcurrent state"
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bitfld.long 0x00 0. "R_LPS__W_CGP,On Read: Local Power Status" "0,1"
|
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group.long 0x54++0x03
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line.long 0x00 "USB_HOST_HCRHPORTSTATUS1,HcRhPortStatus1 register"
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hexmask.long.word 0x00 21.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 20. "PRSC,Port Reset Status Change" "0: The port reset has not finished or PRS has not,1: The port reset has finished"
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bitfld.long 0x00 19. "OCIC,Over Current Indicate Change" "0: The overcurrent status has not changed,1: The overcurrent status has changed"
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bitfld.long 0x00 18. "PSSC,Port Suspend Status Change" "0: Resume processing has not finished,1: Resume processing has finished"
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bitfld.long 0x00 17. "PESC,Port Enable Status Change" "0: The PES status has not changed,1: The PES status has changed"
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bitfld.long 0x00 16. "CSC,Connect Status Change" "0: CCS status has not changed,1: CCS status has changed"
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bitfld.long 0x00 10.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 9. "R_LSDA__W_CPP,Read: Low Speed Device Attached" "0: FS device,1: LS device"
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bitfld.long 0x00 8. "R_PPS__W_SPP,Read: Port Power Status" "0: Port power is off,1: Port power is on"
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bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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|
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bitfld.long 0x00 4. "R_PRS__W_SPR,Read: Port Reset Status" "0: The port is normal,1: The port is in the overcurrent state"
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newline
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bitfld.long 0x00 3. "R_POCI__W_CSS,Read: Port Over Current Indicator" "0: The port is normal,1: The port is in the overcurrent state"
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newline
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bitfld.long 0x00 2. "R_PSS__W_SPS,Read: Port Suspend Status" "0: Port is used for transfer normally,1: Port is in the suspend state"
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newline
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bitfld.long 0x00 1. "R_PES__W_SPE,Read: Port Enable Status" "0: Port is disabled,1: Port is enabled"
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newline
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bitfld.long 0x00 0. "R_CCS__W_CPE,Read: Current Connect Status" "0: No device is connected,1: A device is connected"
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group.long 0x58++0x03
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line.long 0x00 "USB_HOST_HCRHPORTSTATUS2,HcRhPortStatus2 register"
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hexmask.long.word 0x00 21.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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newline
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bitfld.long 0x00 20. "PRSC,Port Reset Status Change" "0: The port reset has not finished or PRS has not,1: The port reset has finished"
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newline
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bitfld.long 0x00 19. "OCIC,Over Current Indicate Change" "0: The overcurrent status has not changed,1: The overcurrent status has changed"
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bitfld.long 0x00 18. "PSSC,Port Suspend Status Change" "0: Resume processing has not finished,1: Resume processing has finished"
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bitfld.long 0x00 17. "PESC,Port Enable Status Change" "0: The PES status has not changed,1: The PES status has changed"
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bitfld.long 0x00 16. "CSC,Connect Status Change" "0: CCS status has not changed,1: CCS status has changed"
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bitfld.long 0x00 10.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 9. "R_LSDA__W_CPP,Read: Low Speed Device Attached" "0: FS device,1: LS device"
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bitfld.long 0x00 8. "R_PPS__W_SPP,Read: Port Power Status" "0: Port power is off,1: Port power is on"
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bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "R_PRS__W_SPR,Read: Port Reset Status" "0: The port is normal,1: The port is in the overcurrent state"
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newline
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bitfld.long 0x00 3. "R_POCI__W_CSS,Read: Port Over Current Indicator" "0: The port is normal,1: The port is in the overcurrent state"
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newline
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bitfld.long 0x00 2. "R_PSS__W_SPS,Read: Port Suspend Status" "0: Port is used for transfer normally,1: Port is in the suspend state"
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newline
|
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bitfld.long 0x00 1. "R_PES__W_SPE,Read: Port Enable Status" "0: Port is disabled,1: Port is enabled"
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newline
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bitfld.long 0x00 0. "R_CCS__W_CPE,Read: Current Connect Status" "0: No device is connected,1: A device is connected"
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rgroup.long 0x1000++0x03
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line.long 0x00 "USB_HOST_CAPL_VERSION,HCIVERSION and CAPLENGTH register (EHCI)"
|
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hexmask.long.word 0x00 16.--31. 1. "INTERFACE_VERSION_NUMBER,Indicates the version of the EHCI Specification implemented in this host controller"
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hexmask.long.byte 0x00 8.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPABILITY_REGISTERS_LENGTH,Indicates the start address of the host controller operational register"
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rgroup.long 0x1004++0x03
|
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line.long 0x00 "USB_HOST_HCSPARAMS,HCSPARAMS register"
|
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hexmask.long.byte 0x00 24.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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|
newline
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bitfld.long 0x00 20.--23. "DEBUG_PORT_NUMBER2,Indicates that the host controller ports are provided for debugging" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 17.--19. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 16. "P_INDICATOR,Indicates whether the host controller supports port indicator control" "0,1"
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|
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|
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bitfld.long 0x00 12.--15. "N_CC,Indicates the number of OHCI host controllers related to the EHCI host controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "N_PCC,Indicates the number of ports supported by one OHCI host controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 7. "PORT_ROUTING_RULES,Indicates how each port is mapped on the OHCI host controller" "0,1"
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|
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|
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bitfld.long 0x00 5.--6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3"
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|
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|
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bitfld.long 0x00 4. "PPC,Indicates how the host controller controls the port power" "0,1"
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|
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|
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bitfld.long 0x00 0.--3. "N_PORTS,Indicates the number of physical downstream ports used in this subsystem" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x1008++0x03
|
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line.long 0x00 "USB_HOST_HCCPARAMS,HCCPARAMS register"
|
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hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
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|
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hexmask.long.byte 0x00 8.--15. 1. "EECP,Indicates the offset address of the EHCI extend registers (EHCI Extend Capabilities Registers)"
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|
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|
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bitfld.long 0x00 4.--7. "ISOCHRONOUS_SCHEDULING_THRESHOLD,This bit shows 0h which indicates that the host controller does not support the isochronous data structure cache of the overall frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 3. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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|
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|
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bitfld.long 0x00 2. "ASYNCHRONOUS_SCHEDULE_PARK_CAPABILITY,Indicates whether Park mode for High Speed QH (Queue Head) in the asynchronous schedule is supported" "0,1"
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|
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bitfld.long 0x00 1. "PROGRAMMING_FRAME_LIST_FLAG,Indicates the setting for the frame list size that can be used by software" "0,1"
|
|
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|
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bitfld.long 0x00 0. "BIT64_ADDRESSING_CAPABILITY,Indicates whether the data structure uses memory pointers of 32-bit address or 64-bit address" "0,1"
|
|
rgroup.long 0x100C++0x03
|
|
line.long 0x00 "USB_HOST_HCSP_PORTROUTE,HCSP_PORTROUTE register"
|
|
hexmask.long 0x00 0.--31. 1. "COMPANION_PORT_ROUTE,Indicates the port for which the OHCI host controller is responsible"
|
|
group.long 0x1020++0x03
|
|
line.long 0x00 "USB_HOST_USBCMD,USBCMD register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
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|
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abitfld.long 0x00 16.--23. "INTERRUPT_THRESHOLD_CONTROL,Indicates the maximum rate until the host controller generates an interrupt" "0x00=0: Reserved,0x01=1: 1 micro-frame,0x02=2: 2 micro-frames,0x04=4: 4 micro-frames,0x08=8: 8 micro-frames (1 ms),0x10=16: 16 micro-frames (2 ms),0x20=32: 32 micro-frames (4 ms),0x40=64: 64 micro-frames (8 ms)"
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|
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bitfld.long 0x00 12.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 11. "ASYNCHRONOUS_SCHEDULE_PARK_MODE_ENABLE,Specify whether to enable or disable Park mode" "0: Disable,1: Enable"
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|
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|
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bitfld.long 0x00 10. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
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|
|
bitfld.long 0x00 8.--9. "ASYNCHRONOUS_SCHEDULE_PARK_MODE_COUNT,Specify the number of transactions that can be executed succesively from one QH (queue head)" "0,1,2,3"
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|
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|
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bitfld.long 0x00 7. "LIGHT_HOST_CONTROLLER_RESET,Indicates the status of executing a light host controller reset" "0,1"
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|
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|
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bitfld.long 0x00 6. "INTERRUPT_ON_ASYNC_ADVANCE_DOORBELL,This bit is used by software as a doorbell" "0,1"
|
|
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|
|
bitfld.long 0x00 5. "ASYNCHRONOUS_SCHEDULE_ENABLE,Specify whether to continue or skip asynchronous list processing" "0: Do not continue (skip) asynchronous list,1: Continue (do not skip) asynchronous list"
|
|
newline
|
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bitfld.long 0x00 4. "PERIODIC_SCHEDULE_ENABLE,Specify whether to continue or skip periodic list processing" "0: Do not continue (skip) periodic list processing,1: Continue (do not skip) periodic list processing"
|
|
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|
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bitfld.long 0x00 2.--3. "FRAME_LIST_SIZE,Specify the frame list size" "0: 1024 elements (4096 bytes),1: 512 elements (2048 bytes),2: 256 elements (1024 bytes),3: Reserved"
|
|
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|
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bitfld.long 0x00 1. "HCRESET,Host Controller Reset" "0,1"
|
|
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|
|
bitfld.long 0x00 0. "RS,Run/Stop" "0: Stop (The host controller finished a..,1: Run (The host controller executes scheduling.)"
|
|
group.long 0x1024++0x03
|
|
line.long 0x00 "USB_HOST_USBSTS,USBSTS register"
|
|
hexmask.long.word 0x00 16.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 15. "ASYNCHRONOUS_SCHEDULE_STATUS,Indicates the current asynchronous scheduling status" "0: Disable asynchronous scheduling,1: Enable asyncrhonous scheduling"
|
|
newline
|
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bitfld.long 0x00 14. "PERIODIC_SCHEDULE_STATUS,Indicates the current periodic scheduling status" "0: Disable periodic scheduling,1: Enable periodic scheduling"
|
|
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|
|
bitfld.long 0x00 13. "RECLAMATION,Use this bit to detect an empty asyncronous schedule" "0,1"
|
|
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|
|
bitfld.long 0x00 12. "HCHALTED,This bit shows 0b when bit 0 (RS) of the USBCMD register is 1b" "0: The EHCI host controller is running,1: The EHCI host controller has stopped"
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|
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|
|
bitfld.long 0x00 6.--11. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
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|
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bitfld.long 0x00 5. "INTERRUPT_ON_ASYNC_ADVANCE,Indicates the Async Advance interrupt status" "0: No Async Advance has occurred,1: An Async Advance has occurred"
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|
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|
|
bitfld.long 0x00 4. "HOST_SYSTEM_ERROR,This bit is set to 1b when a serious error such as a parity error in the PCI system occurs on the host controller" "0: No system error has occurred,1: A system error has occurred"
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|
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bitfld.long 0x00 3. "FRAME_LIST_ROLLOVER,The host controller sets this bit to 1b when the Frame Index bit of the FRINDEX register rolled over from its maximum value to 000h" "0: The frame list count has not rolled over to be,1: The frame list count rolled over to be 000h"
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|
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|
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bitfld.long 0x00 2. "PORT_CHANGE_DETECT,Indicates the change in the port status" "0,1"
|
|
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|
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bitfld.long 0x00 1. "USBERRINT,USB Error Interrupt" "0: The USB transaction normally completed,1: The USB transaction terminated due to an error"
|
|
newline
|
|
bitfld.long 0x00 0. "USBINT,USB Interrupt" "0: The USB transfer has not completed,1: The USB transfer normally completed"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "USB_HOST_USBINTR,USBINTR register"
|
|
hexmask.long 0x00 6.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
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|
|
bitfld.long 0x00 5. "INTERRUPT_ON_ASYNC_ADVANCE_ENABLE,Specify whether to enable or disable the interrupt of bit 5 (Interrupt on Async Advance) of the USBSTS register" "0: Disable,1: Enable"
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|
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|
|
bitfld.long 0x00 4. "HOST_SYSTEM_ERROR_ENABLE,Specify whether to enable or disable the interrupt of bit 4 (Host System Error) of the USBSTS register" "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x00 3. "FRAME_LIST_ROLLOVER_ENABLE,Specify whether to enable or disable the interrupt of bit 3 (Frame List Rollover) of the USBSTS register" "0: Disable,1: Enable"
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bitfld.long 0x00 2. "PORT_CHANGE_INTERRUPT_ENABLE,Specify whether to enable or disable the interrupt of bit 2 (Port Change Detect) of the USBSTS register" "0: Disable,1: Enable"
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bitfld.long 0x00 1. "USB_ERROR_INTERRUPT_ENABLE,Specify whether to enable or disable the interrupt of bit 1 (USBERRINT) of the USBSTS register" "0: Disable,1: Enable"
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bitfld.long 0x00 0. "USB_INTERRUPT_ENABLE,Specify whether to enable or disable the interrupt of bit 0 (USBINT) of the USBSTS register" "0: Disable,1: Enable"
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group.long 0x102C++0x03
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line.long 0x00 "USB_HOST_FRINDEX,Frame Index register"
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hexmask.long.tbyte 0x00 14.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.word 0x00 0.--13. 1. "FRAME_INDEX,This bit is used by the host controller to index a periodic frame list"
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rgroup.long 0x1030++0x03
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line.long 0x00 "USB_HOST_CTRLDSSEGMENT,CTRLDSSEGMENT register"
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hexmask.long 0x00 0.--31. 1. "CTRLDSSEGMENT,This register is not used because the host controller does not support 64-bit addressing"
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group.long 0x1034++0x03
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line.long 0x00 "USB_HOST_PERIODICLISTBASE,PERIODICLISTBASE register"
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hexmask.long.tbyte 0x00 12.--31. 1. "BASEADDRESS,Indicates the base address of the periodic frame list on the system memory"
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hexmask.long.word 0x00 0.--11. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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group.long 0x1038++0x03
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line.long 0x00 "USB_HOST_ASYNCLISTADDR,ASYNCLISTADDR register"
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hexmask.long 0x00 5.--31. 1. "LPL,Link Pointer Low"
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bitfld.long 0x00 0.--4. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x1060++0x03
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line.long 0x00 "USB_HOST_CONFIGFLAG,CONFIGFLAG register"
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hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 0. "CF,Configure Flag: Use this bit to control whether the port routing control circuit routes OHCI or EHCI by default" "0: The port routing control circuit route each..,1: The port routing control circuit route each.."
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group.long 0x1064++0x03
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line.long 0x00 "USB_HOST_PORTSC1,PORTSC1 register"
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hexmask.long.word 0x00 23.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 22. "WKOC_E,Wake on Over-current Enable" "0,1"
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bitfld.long 0x00 21. "WKDSCNNT_E,Wake on Disconnect Enable" "0,1"
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bitfld.long 0x00 20. "WKCNNT_E,Wake on Connect Enable" "0,1"
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bitfld.long 0x00 16.--19. "PORT_TEST_CONTROL,Use this bit to control the test mode" "0: Normal,1: Test J_STATE,2: Test K_STATE,3: Test SE0_NAK,4: Test Packet,5: Test FORCE_ENABLE Other,?..."
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bitfld.long 0x00 14.--15. "PORT_INDICATOR_CONTROL,This bit shows 00b which indicates that the host controller does not support port indicator control" "0,1,2,3"
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bitfld.long 0x00 13. "PORT_OWNER,Indicates which of OHCI and EHCI host controllers has the port ownership" "0: EHCI host controller,1: OHCI host controller"
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bitfld.long 0x00 12. "PP,Use this bit to control the power supply to ports" "0: Do not supply power to ports,1: Supply power to ports"
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bitfld.long 0x00 10.--11. "LINE_STATUS1,Indicates the current logical level of D+/D- on USB ports (bit 11: D+ bit 10: D-) Use this bit to detect an LS device before starting a port reset sequence or a port enable sequence" "?,?,2: D-) Use this bit,3: D+ bit"
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bitfld.long 0x00 9. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 8. "PORT_RESET,Indicates the port reset status" "0: Ports are not being reset,1: Ports are being reset"
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bitfld.long 0x00 7. "SUSPEND,Indicates the port suspend status" "0: Ports are not in the suspend state,1: Ports are in the suspend state"
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bitfld.long 0x00 6. "FORCE_PORT_RESUME,Indicates the detection of the port resume state" "0: No resume signal (K state) has been detected or,1: A resume signal (K state) has been detected or"
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bitfld.long 0x00 5. "OVER_CURRENT_CHANGE,Indicates the change inbit 4 (Over-current Active)" "0: No change,1: Bit 4 (Over-current"
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newline
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bitfld.long 0x00 4. "OVER_CURRENT_ACTIVE,Indicates the port overcurrent status" "0: Ports are not in the overcurrent state,1: Ports are in the overcurrent state"
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bitfld.long 0x00 3. "PORT_ENABLE_DISABLE_CHANGE,Indicates the change in the port enable/disable status" "0: No change,1: Ports are disabled"
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bitfld.long 0x00 2. "PORT_ENABLED_DISABLED,Indicates the port enable/disable status" "0: Ports are disabled,1: Ports are enabled"
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bitfld.long 0x00 1. "CONNECT_STATUS_CHANGE,Indicates the change in bit 0 (Current Connect Status)" "0: No change,1: Bit 0 (Current Connect"
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bitfld.long 0x00 0. "CURRENT_CONNECT_STATUS,Indicates the port connection status" "0: No device is connected to ports,1: A device is connected to a port"
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group.long 0x1068++0x03
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line.long 0x00 "USB_HOST_PORTSC2,PORTSC2 register"
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hexmask.long.word 0x00 23.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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newline
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bitfld.long 0x00 22. "WKOC_E,Wake on Over-current Enable" "0,1"
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bitfld.long 0x00 21. "WKDSCNNT_E,Wake on Disconnect Enable" "0,1"
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bitfld.long 0x00 20. "WKCNNT_E,Wake on Connect Enable" "0,1"
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|
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bitfld.long 0x00 16.--19. "PORT_TEST_CONTROL,Use this bit to control the test mode" "0: Normal,1: Test J_STATE,2: Test K_STATE,3: Test SE0_NAK,4: Test Packet,5: Test FORCE_ENABLE Other,?..."
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bitfld.long 0x00 14.--15. "PORT_INDICATOR_CONTROL,This bit shows 00b which indicates that the host controller does not support port indicator control" "0,1,2,3"
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bitfld.long 0x00 13. "PORT_OWNER,Indicates which of OHCI and EHCI host controllers has the port ownership" "0: EHCI host controller,1: OHCI host controller"
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bitfld.long 0x00 12. "PP,Use this bit to control the power supply to ports" "0: Do not supply power to ports,1: Supply power to ports"
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bitfld.long 0x00 10.--11. "LINE_STATUS1,Indicates the current logical level of D+/D- on USB ports (bit 11: D+ bit 10: D-) Use this bit to detect an LS device before starting a port reset sequence or a port enable sequence" "?,?,2: D-) Use this bit,3: D+ bit"
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bitfld.long 0x00 9. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 8. "PORT_RESET,Indicates the port reset status" "0: Ports are not being reset,1: Ports are being reset"
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bitfld.long 0x00 7. "SUSPEND,Indicates the port suspend status" "0: Ports are not in the suspend state,1: Ports are in the suspend state"
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newline
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bitfld.long 0x00 6. "FORCE_PORT_RESUME,Indicates the detection of the port resume state" "0: No resume signal (K state) has been detected or,1: A resume signal (K state) has been detected or"
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newline
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bitfld.long 0x00 5. "OVER_CURRENT_CHANGE,Indicates the change inbit 4 (Over-current Active)" "0: No change,1: Bit 4 (Over-current"
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|
newline
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bitfld.long 0x00 4. "OVER_CURRENT_ACTIVE,Indicates the port overcurrent status" "0: Ports are not in the overcurrent state,1: Ports are in the overcurrent state"
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bitfld.long 0x00 3. "PORT_ENABLE_DISABLE_CHANGE,Indicates the change in the port enable/disable status" "0: No change,1: Ports are disabled"
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|
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|
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bitfld.long 0x00 2. "PORT_ENABLED_DISABLED,Indicates the port enable/disable status" "0: Ports are disabled,1: Ports are enabled"
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bitfld.long 0x00 1. "CONNECT_STATUS_CHANGE,Indicates the change in bit 0 (Current Connect Status)" "0: No change,1: Bit 0 (Current Connect"
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bitfld.long 0x00 0. "CURRENT_CONNECT_STATUS,Indicates the port connection status" "0: No device is connected to ports,1: A device is connected to a port"
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rgroup.long 0x10000++0x03
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line.long 0x00 "USB_HOST_VID_DID_OHCI,Device ID - Vendor ID (OHCI)"
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hexmask.long.word 0x00 16.--31. 1. "DEVICE_ID,Indicates the device type"
|
|
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|
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hexmask.long.word 0x00 0.--15. 1. "VENDOR_ID,Indicates the device vendor"
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group.long 0x10004++0x03
|
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line.long 0x00 "USB_HOST_CMND_STS_OHCI,Status - Command (OHCI)"
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bitfld.long 0x00 31. "DETECTED_PARITY_ERROR,Indicates the parity error status" "0,1"
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|
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bitfld.long 0x00 30. "SIGNALED_SYSTEM_ERROR,Indicates the SERR status" "0,1"
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|
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bitfld.long 0x00 29. "RECEIVED_MASTER_ABORT,Indicates the Master-Master Abort status" "0,1"
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|
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|
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bitfld.long 0x00 28. "RECEIVED_TARGET_ABORT,Indicates the Master-Target Abort status" "0,1"
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|
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|
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bitfld.long 0x00 27. "SIGNALED_TARGET_ABORT,Indicates the Slave Target Abort status" "0,1"
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|
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|
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bitfld.long 0x00 25.--26. "DEVSEL_TIMING,Indicates the DEVSEL response speed" "0,1,2,3"
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newline
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bitfld.long 0x00 24. "DATA_PARITY_ERROR_DETECTED,This bit is set when the host controller serving as a master detects a parity error" "0,1"
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bitfld.long 0x00 23. "FAST_BACK_TO_BACK_CAPABLE,Indicates whether Fast Back to Back is supported" "0,1"
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bitfld.long 0x00 21.--22. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
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|
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bitfld.long 0x00 20. "CAPABILITIES_LIST,Indicates whether power management mode is supported" "0,1"
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hexmask.long.word 0x00 10.--19. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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newline
|
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bitfld.long 0x00 9. "FAST_BACK_TO_BACK_ENABLE,Use this bit to enable Fast Back to Back" "0,1"
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|
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|
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bitfld.long 0x00 8. "SERR_ENABLE,Use this bit to enable system error response" "0: Do not assert SERR0,1: Assert SERR0"
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|
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bitfld.long 0x00 7. "WAIT_CYCLE_CONTROL,Use this bit to enable wait cycle control" "0,1"
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|
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|
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bitfld.long 0x00 6. "PARITY_ERROR_RESPONSE,Use this bit to enable parity error response" "0: Do not assert SERR0,1: Assert SERR0"
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bitfld.long 0x00 5. "VGA_PALETTE_SNOOP,Use this bit to enable VGA Palette Snoop" "0,1"
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bitfld.long 0x00 4. "MEMORY_WRITE_AND_INVALIDATE_ENABLE,Use this bit to enable Memory Write and Invalidate" "0,1"
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bitfld.long 0x00 3. "SPECIAL_CYCLE,Use this bit to enable Special Cycle" "0,1"
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bitfld.long 0x00 2. "BUS_MASTER,Use this bit to enable the bus master" "0,1"
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bitfld.long 0x00 1. "MEMORY_SPACE,Use this bit to enable accessing to the memory spaces" "0,1"
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bitfld.long 0x00 0. "I_O_SPACE,Use this bit to enable accessing to the I/O spaces" "0,1"
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rgroup.long 0x10008++0x03
|
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line.long 0x00 "USB_HOST_REVID_CC_OHCI,Class Code - Revision ID (OHCI)"
|
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hexmask.long.byte 0x00 24.--31. 1. "BASE_CLASS,Indicates the base class defined in the PCI specification"
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|
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hexmask.long.byte 0x00 16.--23. 1. "SUB_CLASS,Indicates the subclass defined in the PCI specification"
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|
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|
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hexmask.long.byte 0x00 8.--15. 1. "PROGRAMMING_I_F,Indicates the program interface defined in the PCI specification"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "REVISION_ID,Indicates the host controller revision"
|
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group.long 0x1000C++0x03
|
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line.long 0x00 "USB_HOST_CLS_LT_HT_BIST_OHCI,BIST - Header Type - Latency Timer - Cache Line Size (OHCI)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BIST,This bit is used for self-testing"
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|
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hexmask.long.byte 0x00 16.--23. 1. "HEADER_TYPE,Use this bit to report the header type to the system"
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|
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hexmask.long.byte 0x00 8.--15. 1. "LATENCY_TIMER,Use this bit to report the latency timer to the system"
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|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CACHE_LINE_SIZE,Use this bit to report the cache line size to the system"
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group.long 0x10010++0x03
|
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line.long 0x00 "USB_HOST_BASEAD_OHCI,OHCI Base Address"
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hexmask.long 0x00 4.--31. 1. "OHCI_BASE_ADDRESS,Use bits [31:12] to specify the base address of the operational register"
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bitfld.long 0x00 3. "PREFETCHABLE,This bit is fixed to 0b because the host controller does not support prefetching in memory read cycles" "0,1"
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newline
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bitfld.long 0x00 1.--2. "TYPE,Indicates that the base address of the OHCI operational registers is 32-bit width and thus the registers can be allocated to any location in a 32-bit memory space" "0,1,2,3"
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newline
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bitfld.long 0x00 0. "MEMORY_SPACE_INDICATOR,Indicates that the OHCI operational registers are mapped on a system memory space" "0,1"
|
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group.long 0x10014++0x03
|
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line.long 0x00 "USB_HOST_WIN1_BASEAD,PCI-AHB Window1 Base Address"
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bitfld.long 0x00 28.--31. "PCI_WIN1_BASEADR,Specify the base address of the PCI-AHB Window 1 space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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hexmask.long.tbyte 0x00 4.--27. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
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bitfld.long 0x00 3. "PREFETCH,Indicates whether prefetching data is enabled or disabled" "0,1"
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|
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|
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bitfld.long 0x00 1.--2. "TYPE,Indicates the base address type" "0,1,2,3"
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newline
|
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bitfld.long 0x00 0. "MEM,Indicates that Indicates that the field specified by the base address is in the memory space" "0,1"
|
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group.long 0x10018++0x03
|
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line.long 0x00 "USB_HOST_WIN2_BASEAD,PCI-AHB Window2 Base Address"
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|
bitfld.long 0x00 28.--31. "PCI_WIN2_BASEADR,Specify the base address of the PCI-AHB Window 2 space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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hexmask.long.tbyte 0x00 4.--27. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
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bitfld.long 0x00 3. "PREFETCH,Indicates whether prefetching data is enabled or disabled" "0,1"
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|
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|
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bitfld.long 0x00 1.--2. "TYPE,Indicates the base address type" "0,1,2,3"
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newline
|
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bitfld.long 0x00 0. "MEM,Indicates that Indicates that the field specified by the base address is in the memory space" "0,1"
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rgroup.long 0x1002C++0x03
|
|
line.long 0x00 "USB_HOST_SSVID_SSID_OHCI,Subsystem ID - Subsystem Vendor ID (OHCI)"
|
|
hexmask.long.word 0x00 16.--31. 1. "SUBSYSTEM_ID,Indicates the device type"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "SUBSYSTEM_VENDOR_ID,Indicates the device vendor"
|
|
rgroup.long 0x10030++0x03
|
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line.long 0x00 "USB_HOST_EROM_BASEAD_OHCI,Expansion ROM Base Address (OHCI)"
|
|
hexmask.long.word 0x00 20.--31. 1. "EXPANSION_ROM_BASE_ADDRESS,This field is fixed to 000000h because decoding the expansion ROM is prohibited"
|
|
newline
|
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hexmask.long.word 0x00 10.--19. 1. "EXPANSION_ROM_BASE_ADDRESS1,This field is fixed to 000000h because decoding the expansion ROM is prohibited"
|
|
newline
|
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hexmask.long.word 0x00 1.--9. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 0. "ROM_DECODE_ENABLE,This bit is fixed to 0b because decoding the expansion ROM is prohibited" "0,1"
|
|
rgroup.long 0x10034++0x03
|
|
line.long 0x00 "USB_HOST_CAPPTR_OHCI,Capability Pointer (OHCI)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPABILITY_POINTER,This is a pointer to the capability identifier"
|
|
group.long 0x1003C++0x03
|
|
line.long 0x00 "USB_HOST_INTR_LINE_PIN_OHCI,Max_Lat - Min_Gnt - Interrupt Pin - Interrupt Line (OHCI)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAX_LATENCY,Indicates the maximum acquisition frequency of the PCI bus"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "MIN_GNT,Indicates the minimum burst transfer time"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "INTERRUPT_PIN,Indicates the interrupt output pin"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "INTERRUPT_LINE,Indicates the interrupt line"
|
|
rgroup.long 0x10040++0x03
|
|
line.long 0x00 "USB_HOST_CAPID_NIP_PMCAP_OHCI,Capability Identifier - Next Item Pointer - Power Management Capabilities (OHCI)"
|
|
bitfld.long 0x00 27.--31. "PME_SUPPORT,[31] : Indicates whether the D3 Cold state is supported.This bit is fixed to 0b because the D3 Cold state is not supported [30:27] : Indicates that PME interrupt generation is supported in all PCI power states (D0 to D3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x00 26. "D2_SUPPORT,Power Management Capabilities - Indicates that the PCI power state D2 is supported" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "D1_SUPPORT,Power Management Capabilities - Indicates that the PCI power state D1 is supported" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "AUX_CURRENT,Power Management Capabilities - Indicates the specified current value required for the 3.3 V auxiliary power supply" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 21. "DSI,Power Management Capabilities - Indicates that no special initialization is required for using power management" "0,1"
|
|
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|
|
bitfld.long 0x00 20. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "PME_CLK,Power Management Capabilities - Indicates that PCLK is not required for generating PME interrupts" "0,1"
|
|
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|
|
bitfld.long 0x00 16.--18. "VERSION,Power Management Capabilities - Indicates that this system is compliant with PCI power management interface specification release 1.1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "NEXT_ITEM_POINTER,Indicates that there is no subsequent item"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPABILITY_IDENTIFIER,Indicates the PCI power management register ID"
|
|
group.long 0x10044++0x03
|
|
line.long 0x00 "USB_HOST_PMC_STS_PMCSR_OHCI,Power Management Control and Status - PMCSR Bridge Support Extensions (OHCI)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA,This bit is fixed to 00h"
|
|
newline
|
|
bitfld.long 0x00 23. "BPCC_ENABLE,This bit is fixed to 0b" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B2_B3,This bit is fixed to 0b" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "PME_STATUS,Indicates the PME interrupt status" "0,1"
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bitfld.long 0x00 9.--14. "DATA_SCALE,Bit" "0: This bit is fixed to 0h,1: This bit is fixed to 0h,2: This bit is fixed to 0h,3: This bit is fixed to 0h,4: This bit is fixed to 00b,5: This bit is fixed to 00b,?..."
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bitfld.long 0x00 8. "PME_ENABLE,Specify whether or not to use PME" "0,1"
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bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--1. "POWER_STATE,Indicates the PCI power status" "0: D0 State,1: D1 State,2: D2 State,3: D3 hot State"
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group.long 0x100E0++0x03
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line.long 0x00 "USB_HOST_EXT1_OHCI,EXT1 Register (OHCI)"
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hexmask.long.byte 0x00 24.--31. 1. "POTPGT,Specify the setting for bits [31:24] (PPOTPGT) of the OHCI HcRhDescriptorA register"
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bitfld.long 0x00 19.--23. "HYPER_SPEED_TRANSFER_CONTROL_2,Setting other than 02h (HS Asynchronous FIFO threshold = 64 bytes) is prohibited" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--18. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13. "HYPER_SPEED_TRANSFER_CONTROL,(HS Async OUT advance Mode) Specify the hyper-speed transfer mode feature used for asynchronous OUT transfer" "0,1"
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bitfld.long 0x00 8.--12. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "ID_WRITE_ENABLE,Control write protection for parameters Subsystem ID Subsystem Vendor ID Max Latency and Min Gnt" "0: Write protected,1: Enable"
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bitfld.long 0x00 3.--6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 2. "PPCNT,Specify the setting for bit 4 (PPC) of the EHCI HCSPARAMS register" "0: Set the PPC bit to 0b,1: Set the PPC bit to 1b"
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bitfld.long 0x00 0.--1. "PORT_NO,Specify the number of valid USB downstream ports" "?,1: Port 1,2: Ports 1 and 2,?..."
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group.long 0x100E4++0x03
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line.long 0x00 "USB_HOST_EXT2_OHCI,EXT2 register (OHCI)"
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hexmask.long.word 0x00 19.--31. 1. "RESERVED1,Reserevd"
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bitfld.long 0x00 18. "RAM_CONNECT_CHECK_RESULT,Indicates the result of RAM connection check" "0: NG,1: OK"
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bitfld.long 0x00 17. "RAM_CONNECT_CHECK_END_FLAG,Indicates the end of RAM connection check" "0: Connection check has not been performed/has not,1: Connection check finished"
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bitfld.long 0x00 16. "RUN_RAM_CONNECT_CHECK,Use this bit to trigger a RAM connection check" "0,1"
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hexmask.long.word 0x00 2.--15. 1. "RESERVED0,Reserevd"
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bitfld.long 0x00 1. "HYPER_SPEED_TRANSFER_CONTROL,Specify the hyper-speed transfer mode feature used for asynchronous IN/OUT transfer" "0,1"
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bitfld.long 0x00 0. "EHCI_MASK,Specify whether to enable or disable the EHCI host controller" "0: Enable the EHCI host controller,1: Disable the EHCI host controller"
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group.long 0x100F4++0x03
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line.long 0x00 "USB_HOST_UTMICTRL_OHCI,UTMI + Operation Mode Control register (OHCI)"
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hexmask.long.word 0x00 18.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16.--17. "REPSEL,Specify the interval of periodic terminal resistance adjustment" "0,1,2,3"
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hexmask.long.word 0x00 0.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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rgroup.long 0x10100++0x03
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line.long 0x00 "USB_HOST_VID_DID_EHCI,Device ID - Vendor ID (EHCI)"
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hexmask.long.word 0x00 16.--31. 1. "DEVICE_ID,Indicates the device type"
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hexmask.long.word 0x00 0.--15. 1. "VENDOR_ID,Indicates the device vendor"
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group.long 0x10104++0x03
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line.long 0x00 "USB_HOST_CMND_STS_EHCI,Status - Command (EHCI)"
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bitfld.long 0x00 31. "DETECTED_PARITY_ERROR,Parity error status bit" "0,1"
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bitfld.long 0x00 30. "SIGNALED_SYSTEM_ERROR,SERR status bit" "0,1"
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bitfld.long 0x00 29. "RECEIVED_MASTER_ABORT,Master_Master Abort status bit" "0,1"
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bitfld.long 0x00 28. "RECEIVED_TARGET_ABORT,Master_Target Abort status bit" "0,1"
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bitfld.long 0x00 27. "SIGNALED_TARGET_ABORT,Slave Target Abort status bit" "0,1"
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bitfld.long 0x00 25.--26. "DEVSEL_TIMING,Indicates the DEVSEL response speed" "0,1,2,3"
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bitfld.long 0x00 24. "DATA_PARITY_ERROR_DETECTED,This bit is set when a parity error has been detected during Master operation" "0,1"
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bitfld.long 0x00 23. "FAST_BACK_TO_BACK_CAPABLE,Indicates whether Fast Back to Back is supported" "0,1"
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bitfld.long 0x00 22. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 21. "MHZ66_CAPABLE,Indicates whether operation is possible with 66 MHz" "0,1"
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bitfld.long 0x00 20. "CAPABILITIES_LIST,Indicates that Power Management Mode is supported" "0,1"
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hexmask.long.word 0x00 10.--19. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 9. "FAST_BACK_TO_BACK_ENABLE,Enables Fast Back to Back" "0,1"
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bitfld.long 0x00 8. "SERR_ENABLE,Enables a system error response" "0: SERR0 is not asserted,1: SERR0 is asserted"
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bitfld.long 0x00 7. "WAIT_CYCLE_CONTROL,Enables Wait Cycle Control" "0,1"
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bitfld.long 0x00 6. "PARITY_ERROR_RESPONSE,Enables a Parity Error response" "0: PERR0 is not asserted,1: PERR0 is asserted"
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bitfld.long 0x00 5. "VGA_PALETTE_SNOOP,Enables VGA Palette Snoop" "0,1"
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bitfld.long 0x00 4. "MEMORY_WRITE_AND_INVALIDATE_ENABLE,Enables Memory Write and Invalidate" "0: The Memory write and invalidate command is,1: The Memory write and invalidate command is.."
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bitfld.long 0x00 3. "SPECIAL_CYCLE,Enables Special Cycle" "0,1"
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bitfld.long 0x00 2. "BUS_MASTER,Enables bus Master" "0,1"
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bitfld.long 0x00 1. "MEMORY_SPACE,Enables access to the memory space" "0,1"
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bitfld.long 0x00 0. "I_O_SPACE,Enables access to the I_O space" "0,1"
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rgroup.long 0x10108++0x03
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line.long 0x00 "USB_HOST_REVID_CC_EHCI,Class Code - Revision ID (EHCI)"
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hexmask.long.byte 0x00 24.--31. 1. "BASE_CLASS,Indicates the base class defined in the PCI specification"
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hexmask.long.byte 0x00 16.--23. 1. "SUB_CLASS,Indicates the subclass defined in the PCI specification"
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hexmask.long.byte 0x00 8.--15. 1. "PROGRAMMING_I_F,Indicates the program interface defined in the PCI specification"
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hexmask.long.byte 0x00 0.--7. 1. "REVISION_ID,Indicates the host controller revision"
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group.long 0x1010C++0x03
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line.long 0x00 "USB_HOST_CLS_LT_HT_BIST_EHCI,BIST - Header Type - Latency Timer - Cache Line Size (EHCI)"
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hexmask.long.byte 0x00 24.--31. 1. "BIST,This bit is used for self-testing"
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hexmask.long.byte 0x00 16.--23. 1. "HEADER_TYPE,Use this bit to report the header type to the system"
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hexmask.long.byte 0x00 8.--15. 1. "LATENCY_TIMER,Use this bit to report the latency timer to the system"
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hexmask.long.byte 0x00 0.--7. 1. "CACHE_LINE_SIZE,Use this bit to report the cache line size to the system"
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group.long 0x10110++0x03
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line.long 0x00 "USB_HOST_BASEAD_EHCI,EHCI Base Address"
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hexmask.long 0x00 4.--31. 1. "EHCI_BASE_ADDRESS,Use bits [31:8] to specify the base address of the operational register"
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bitfld.long 0x00 3. "PREFETCHABLE,This bit is fixed to 0b because the host controller does not support prefetching in memory read cycles" "0,1"
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bitfld.long 0x00 1.--2. "TYPE,Indicates that the base address of the EHCI operational registers is 32-bit width and thus the registers can be allocated to any location in a 32-bit memory space" "0,1,2,3"
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bitfld.long 0x00 0. "MEMORY_SPACE_INDICATOR,Indicates that the EHCI operational registers are mapped on a system memory space" "0,1"
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rgroup.long 0x1012C++0x03
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line.long 0x00 "USB_HOST_SSVID_SSID_EHCI,Subsystem ID - Subsystem Vendor ID (EHCI)"
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hexmask.long.word 0x00 16.--31. 1. "SUBSYSTEM_ID,Indicates the device type"
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hexmask.long.word 0x00 0.--15. 1. "SUBSYSTEM_VENDOR_ID,Indicates the device vendor"
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rgroup.long 0x10130++0x03
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line.long 0x00 "USB_HOST_EROM_BASEAD_EHCI,Expansion ROM Base Address (EHCI)"
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hexmask.long.word 0x00 20.--31. 1. "EXPANSION_ROM_BASE_ADDRESS,This field is fixed to 000000h because decoding the expansion ROM is prohibited"
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hexmask.long.word 0x00 10.--19. 1. "EXPANSION_ROM_BASE_ADDRESS1,This field is fixed to 000000h because decoding the expansion ROM is prohibited"
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hexmask.long.word 0x00 1.--9. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 0. "ROM_DECODE_ENABLE,This bit is fixed to 0b because decoding the expansion ROM is prohibited" "0,1"
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rgroup.long 0x10134++0x03
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line.long 0x00 "USB_HOST_CAPPTR_EHCI,Capability Pointer (EHCI)"
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hexmask.long.tbyte 0x00 8.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.byte 0x00 0.--7. 1. "CAPABILITY_POINTER,This is a pointer to the capability identifier"
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group.long 0x1013C++0x03
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line.long 0x00 "USB_HOST_INTR_LINE_PIN_EHCI,Max_Lat - Min_Gnt - Interrupt Pin - Interrupt Line (EHCI)"
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hexmask.long.byte 0x00 24.--31. 1. "MAX_LATENCY,Indicates the maximum acquisition frequency of the PCI bus"
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hexmask.long.byte 0x00 16.--23. 1. "MIN_GNT,Indicates the minimum burst transfer time"
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hexmask.long.byte 0x00 8.--15. 1. "INTERRUPT_PIN,Indicates the interrupt output pin"
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hexmask.long.byte 0x00 0.--7. 1. "INTERRUPT_LINE,Indicates the interrupt line"
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rgroup.long 0x10140++0x03
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line.long 0x00 "USB_HOST_CAPID_NIP_PMCAP_EHCI,Capability Identifier - Next Item Pointer - Power Management Capabilities (EHCI)"
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bitfld.long 0x00 27.--31. "PME_SUPPORT,[31] : Indicates whether the D3 Cold state is supported.This bit is fixed to 0b because the D3 Cold state is not supported [30:27] : Indicates that PME interrupt generation is supported in all PCI power states (D0 to D3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 26. "D2_SUPPORT,Power Management Capabilities - Indicates that the PCI power state D2 is supported" "0,1"
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bitfld.long 0x00 25. "D1_SUPPORT,Power Management Capabilities - Indicates that the PCI power state D1 is supported" "0,1"
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bitfld.long 0x00 22.--24. "AUX_CURRENT,Power Management Capabilities - Indicates the specified current value required for the 3.3 V auxiliary power supply" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 21. "DSI,Power Management Capabilities - Indicates that no special initialization is required for using power management" "0,1"
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bitfld.long 0x00 20. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
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bitfld.long 0x00 19. "PME_CLK,Power Management Capabilities - Indicates that PCLK is not required for generating PME interrupts" "0,1"
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bitfld.long 0x00 16.--18. "VERSION,Power Management Capabilities - Indicates that this system is compliant with PCI power management interface specification release 1.1" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x00 8.--15. 1. "NEXT_ITEM_POINTER,Indicates that there is no subsequent item"
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hexmask.long.byte 0x00 0.--7. 1. "CAPABILITY_IDENTIFIER,Indicates the PCI power management register ID"
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group.long 0x10144++0x03
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line.long 0x00 "USB_HOST_PMC_STS_PMCSR_EHCI,Power Management Control and Status - PMCSR Bridge Support Extensions(EHCI)"
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hexmask.long.byte 0x00 24.--31. 1. "DATA,This bit is fixed to 00h"
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bitfld.long 0x00 23. "BPCC_ENABLE,This bit is fixed to 0b" "0,1"
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bitfld.long 0x00 22. "B2_B3,This bit is fixed to 0b" "0,1"
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bitfld.long 0x00 16.--21. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "PME_STATUS,Indicates the PME interrupt status" "0,1"
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bitfld.long 0x00 9.--14. "DATA_SCALE,Bit" "0: This bit is fixed to 0h,1: This bit is fixed to 0h,2: This bit is fixed to 0h,3: This bit is fixed to 0h,4: This bit is fixed to 00b,5: This bit is fixed to 00b,?..."
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bitfld.long 0x00 8. "PME_ENABLE,Specify whether or not to use PME" "0,1"
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bitfld.long 0x00 2.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--1. "POWER_STATE,Indicates the PCI power status" "0: D0 State,1: D1 State,2: D2 State,3: D3 hot State"
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group.long 0x10160++0x03
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line.long 0x00 "USB_HOST_SBRN_FLADJ_PW,SBRN - FLADJ - PORTWAKECAP"
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hexmask.long.word 0x00 16.--31. 1. "PORTWAKECAP,Use this bit to mask among connected devices which one is used as the wakeup event"
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hexmask.long.byte 0x00 8.--15. 1. "FLADJ,Use this bit to adjust the length of 1 microframe in 16HS bit time units"
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hexmask.long.byte 0x00 0.--7. 1. "SBRN,Indicates the serial bus release number"
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group.long 0x101E0++0x03
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line.long 0x00 "USB_HOST_EXT1_EHCI,EXT1 Register (EHCI)"
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hexmask.long.byte 0x00 24.--31. 1. "POTPGT,Specify the setting for bits [31:24] (PPOTPGT) of the OHCI HcRhDescriptorA register"
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bitfld.long 0x00 19.--23. "HYPER_SPEED_TRANSFER_CONTROL_2,Setting other than 02h (HS Asynchronous FIFO threshold = 64 bytes) is prohibited" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--18. "bf_align2,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13. "HYPER_SPEED_TRANSFER_CONTROL,(HS Async OUT advance Mode) Specify the hyper-speed transfer mode feature used for asynchronous OUT transfer" "0,1"
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bitfld.long 0x00 8.--12. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "ID_WRITE_ENABLE,Control write protection for parameters Subsystem ID Subsystem Vendor ID Max Latency and Min Gnt" "0: Write protected,1: Enable"
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bitfld.long 0x00 3.--6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 2. "PPCNT,Specify the setting for bit 4 (PPC) of the EHCI HCSPARAMS register" "0: Set the PPC bit to 0b,1: Set the PPC bit to 1b"
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bitfld.long 0x00 0.--1. "PORT_NO,Specify the number of valid USB downstream ports" "?,1: Port 1,2: Ports 1 and 2,?..."
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group.long 0x101E4++0x03
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line.long 0x00 "USB_HOST_EXT2_EHCI,EXT2 register (EHCI)"
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hexmask.long.word 0x00 19.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 18. "RAM_CONNECT_CHECK_RESULT,Indicates the result of RAM connection check" "0: NG,1: OK"
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bitfld.long 0x00 17. "RAM_CONNECT_CHECK_END_FLAG,Indicates the end of RAM connection check" "0: Connection check has not been performed/has not,1: Connection check finished"
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bitfld.long 0x00 16. "RUN_RAM_CONNECT_CHECK,Use this bit to trigger a RAM connection check" "0,1"
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hexmask.long.word 0x00 2.--15. 1. "RESERVED0,Reserevd"
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bitfld.long 0x00 1. "HYPER_SPEED_TRANSFER_CONTROL,Specify the hyper-speed transfer mode feature used for asynchronous IN/OUT transfer" "0,1"
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bitfld.long 0x00 0. "EHCI_MASK,Specify whether to enable or disable the EHCI host controller" "0: Enable the EHCI host controller,1: Disable the EHCI host controller"
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group.long 0x101F4++0x03
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line.long 0x00 "USB_HOST_UTMICTRL_EHCI,UTMI+ Operation Mode Control Register (EHCI)"
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hexmask.long.word 0x00 18.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
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bitfld.long 0x00 16.--17. "REPSEL,Specify the interval of periodic terminal resistance adjustment" "0,1,2,3"
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|
|
hexmask.long.word 0x00 0.--15. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0x10800++0x03
|
|
line.long 0x00 "USB_HOST_PCIAHB_WIN1_CTR,This register is used to specify the settings for accessing the AHB from the host controller"
|
|
bitfld.long 0x00 28.--31. "AHB_BASEADR,Specify the base address of the AHB bus used by the host controller to access the PCI-AHB Window 1 space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.tbyte 0x00 9.--27. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "ENDIAN_CTR,Specify how to convert endianness used for transfers to the AHB bus" "0: No conversion,1: Access type data swapping,2: Byte data swapping,3: Halfword swapping,4: Address conversion others,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "PREFETCH,Specify whether to prefetch data on the AHB bus for a read request from the host controller" "0: Do not prefetch,1: Enable prefetch (Up to 4 burst),2: Enable prefetch (Up to 8 burst),3: Enable prefetch (Up to 16 burst)"
|
|
group.long 0x10804++0x03
|
|
line.long 0x00 "USB_HOST_PCIAHB_WIN2_CTR,This register is used to specify the settings for accessing the AHB from the host controller"
|
|
bitfld.long 0x00 28.--31. "AHB_BASEADR,Specify the base address of the AHB bus used by the host controller to access the PCI-AHB Window 2 space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.tbyte 0x00 9.--27. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "ENDIAN_CTR,Specify how to convert endianness used for transfers to the AHB bus" "0: No conversion,1: Access type data swapping,2: Byte data swapping,3: Halfword swapping,4: Address conversion Others,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--5. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "PREFETCH,Specify whether to prefetch data on the AHB bus for a read request from the host controller" "0: Do not prefetch,1: Enable prefetch (Up to 4 burst),2: Enable prefetch (Up to 8 burst),3: Enable prefetch (Up to 16 burst)"
|
|
group.long 0x10810++0x03
|
|
line.long 0x00 "USB_HOST_AHBPCI_WIN1_CTR,This register is used to specify the settings for accessing the PCI configuration space"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "PCIWIN1_BASEADR,Specify the base address of the PCI bus used to access the AHB-PCI Window 1 space from the AHB"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--10. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "PCICMD,Specify the PCI bus cycle type" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
group.long 0x10814++0x03
|
|
line.long 0x00 "USB_HOST_AHBPCI_WIN2_CTR,This register is used to specify the settings for accessing the OHCI operational register area"
|
|
hexmask.long.word 0x00 16.--31. 1. "PCIWIN2_BASEADR,Specify the base address of the PCI bus used to access the AHB-PCI Window 2 space from the AHB"
|
|
newline
|
|
hexmask.long.word 0x00 6.--15. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 5. "BURST_EN,Enable burst transfer for the PCI bus" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "bf_align1,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "PCICMD,Specify the PCI bus cycle type" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "bf_align0,bitField alignment value for aeabi compatibility" "0,1"
|
|
group.long 0x10820++0x03
|
|
line.long 0x00 "USB_HOST_PCI_INT_ENABLE,This register is used to specify whether to enable or disable interrupt sources shown in the PCI_INT_STATUS register"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 19. "USBH_PMEEN,Specify whether to enable or disable the interrupt of bit 19 (USBH_PME) of the PCI_INT_STATUS register" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 18. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "USBH_INTBEN,Specify whether to enable or disable the interrupt of bit 17 (USBH_INTB) of the PCI_INT_STATUS register" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 16. "USBH_INTAEN,Specify whether to enable or disable the interrupt of bit 16 (USBH_INTA) of the PCI_INT_STATUS register" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 13. "PCIAHB_WIN2_INTEN,Specify whether to enable or disable the interrupt of bit 13 (PCIAHB_WIN2_INT) of the PCI_INT_STATUS register" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 12. "PCIAHB_WIN1_INTEN,Specify whether to enable or disable the interrupt of bit 12 (PCIAHB_WIN1_INT) of the PCI_INT_STATUS register" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RESERR_INTEN,Specify whether to enable or disable the interrupt of bit 5 (RESERR_INT) of the PCI_INT_STATUS register" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 4. "SIGSERR_INTEN,Specify whether to enable or disable the interrupt of bit 4 (SIGSERR_INT) of the PCI_INT_STATUS register" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 3. "PERR_INTEN,Specify whether to enable or disable the interrupt of bit 3 (PERR_INT) of the PCI_INT_STATUS register" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 2. "REMARBORT_INTEN,Specify whether to enable or disable the interrupt of bit 2 (REMABORT_INT) of the PCI_INT_STATUS register" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 1. "RETABORT_INTEN,Specify whether to enable or disable the interrupt of bit 1 (RETABORT_INT) of the PCI_INT_STATUS register" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 0. "SIGTABORT_INTEN,Specify whether to enable or disable the interrupt of bit 0 (SIGTABORT_INT) of the PCI_INT_STATUS register" "0: Disable,1: Enable"
|
|
group.long 0x10824++0x03
|
|
line.long 0x00 "USB_HOST_PCI_INT_STATUS,This register indicates the status of AHB-PCI Bridge interrupt sources and the interrupt signals from the host controller"
|
|
hexmask.long.word 0x00 20.--31. 1. "bf_align3,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 19. "USBH_PME,Indicates the status of the PME" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "bf_align2,bitField alignment value for aeabi compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "USBH_INTB,Indicates the status of the INTB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "USBH_INTA,Indicates the status of the INTA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 13. "PCIAHB_WIN2_INT,Indicates that an AHB bus error has occurred in PCIAHB Window 2" "0: No AHB bus error has occurred,1: An AHB bus error has occurred"
|
|
newline
|
|
bitfld.long 0x00 12. "PCIAHB_WIN1_INT,Indicates that an AHB bus error has occurred in PCIAHB Window 1" "0: No AHB bus error has occurred,1: An AHB bus error has occurred"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RESERR_INT,Indicates the status of the interrupt caused by SERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SIGSERR_INT,Indicates the status of the interrupt caused by SERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PERR_INT,Indicates the status of the interrupt caused by PERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "REMABORT_INT,Indicates that MasterAbort is received during PCI master operation" "0: Master Abort has not been received,1: Master Abort has been received"
|
|
newline
|
|
bitfld.long 0x00 1. "RETABORT_INT,Indicates that Target Abort is reported during PCI master operation" "0: Target Abort has not been reported,1: Target Abort has been reported"
|
|
newline
|
|
bitfld.long 0x00 0. "SIGTABORT_INT,Indicates that Target Abort is reported during PCI slave operation" "0: Target Abort has not been reported,1: Target Abort has been reported"
|
|
group.long 0x10830++0x03
|
|
line.long 0x00 "USB_HOST_AHB_BUS_CTR,This register is used to specify AHB master/slave features of the host controller"
|
|
hexmask.long.word 0x00 18.--31. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 17. "SMODE_READY_CTR,Use this bit to control the wait operation when the host controller serves as an AHB slave" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 8.--16. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 7. "MMODE_HBUSREQ,Use this bit to control the HBUSREQ deasserting timing when the host controller serves as an AHB master" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--6. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2. "MMODE_WR_INCR,Specify the undefined-length burst transfer use condition when the host controller serves as an AHB master" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "MMODE_BYTE_BURST,Specify whether to enable or disable 16-bit or 8-bit burst transfer when the host controller serves as an AHB master" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MMODE_HTRANS,Specify the HTRANS signal operating mode when the host controller serves as an AHB master" "0,1"
|
|
group.long 0x10834++0x03
|
|
line.long 0x00 "USB_HOST_USBCTR,This register is used to specify the host controller settings"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PCI_AHB_WIN1_SIZE,Use this bit to control the PCI-AHB Window 1 area" "0: 256 MB,1: 512 MB,2: 1 GB,3: 2 GB"
|
|
newline
|
|
bitfld.long 0x00 9. "PCI_AHB_WIN2_EN,Use this bit to enable the PCI-AHB Window 2" "0: PCI-AHB Window 2 cannot be used,1: PCI-AHB Window 2 can be used"
|
|
newline
|
|
bitfld.long 0x00 8. "DIRPD,If this bit is set to 1b the direct power-down state can be entered" "0: Normal operation,1: Direct power-down state"
|
|
newline
|
|
bitfld.long 0x00 3.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2. "PLL_RST,Use this bit to control the reset signal supplied to the PLL" "0: Cancel the PLL reset,1: Request a PLL reset"
|
|
newline
|
|
bitfld.long 0x00 1. "PCICLK_MASK,Use this bit to stop PCI clock supply to the host controller" "0: Supply the PCI clock,1: Stop the PCI clock"
|
|
newline
|
|
bitfld.long 0x00 0. "USBH_RST,Use this bit to control the reset signal supplied to the host controller" "0: Cancel the host controller reset,1: Request a host controller reset"
|
|
group.long 0x10840++0x03
|
|
line.long 0x00 "USB_HOST_PCI_ARBITER_CTR,This register is used to specify the PCI bus arbitration settings"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "bf_align1,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 12. "PCIBP_MODE,Specify the PCI bus parking master" "0: This unit,1: The node that accessed"
|
|
newline
|
|
hexmask.long.word 0x00 2.--11. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
bitfld.long 0x00 1. "PCIREQ1,Specify whether to enable or disable the PCI bus request signal from the host controller" "0: Disable the request signal,1: Enable the request signal"
|
|
newline
|
|
bitfld.long 0x00 0. "PCIREQ0,Specify whether to enable or disable the PCI bus request signal from this unit" "0: Disable the request signal,1: Enable the request signal"
|
|
rgroup.long 0x10848++0x03
|
|
line.long 0x00 "USB_HOST_PCI_UNIT_REV,This register shows the version of the AHB-PCI bridge macro"
|
|
hexmask.long.word 0x00 16.--31. 1. "MAJOR_REVISION_ID,Indicates the major Revision ID of this unit"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MINOR_REVISION_ID,Indicates the minor Revision ID of this unit"
|
|
tree.end
|
|
tree "INTRAMHS0_DPM_MIRROR_P"
|
|
base ad:0xF9210000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "intramhs_base,Internal Handshake RAM start address"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xFFFC++0x03
|
|
line.long 0x00 "intramhs_end,Internal Handshake RAM end address"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
tree "INTRAMHS1_DPM_MIRROR_P"
|
|
base ad:0xF9250000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "intramhs_base,Internal Handshake RAM start address"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
group.long 0xFFFC++0x03
|
|
line.long 0x00 "intramhs_end,Internal Handshake RAM end address"
|
|
hexmask.long 0x00 0.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
tree.end
|
|
tree "NOC"
|
|
base ad:0xFB200000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "NOC_observer_error_main_ErrorLogger_0_Id_CoreId,Core ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "NOC_observer_error_main_ErrorLogger_0_Id_RevisionId,Revision ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code"
|
|
hexmask.long.byte 0x00 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "NOC_observer_error_main_ErrorLogger_0_FaultEn,Fault Enable Register"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "FAULTEN,Set to 1 to enable output signal Fault" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "NOC_observer_error_main_ErrorLogger_0_ErrVld,Error Valid Register"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "ERRVLD,1 indicates an error has been logged" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "NOC_observer_error_main_ErrorLogger_0_ErrClr,Error Clear Register"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "ERRCLR,Set to 1 to clear ErrVld" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "NOC_observer_error_main_ErrorLogger_0_ErrLog0,Error Log Register 0"
|
|
bitfld.long 0x00 31. "FORMAT,The Format field is always set to 1" "0,1"
|
|
hexmask.long.byte 0x00 23.--30. 1. "bf_align2,bitField alignment value for aeabi compatibility"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "LEN1,The Len1 field indicates the number of payload bytes minus 1 handled by the transaction"
|
|
bitfld.long 0x00 11.--15. "bf_align1,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "ERRCODE,The ErrCode field indicates the type of error" "0: Target error detected by slave,1: Address decode error,?,3: Access to disconnected slave,?,5: Firewall error,?..."
|
|
bitfld.long 0x00 5.--7. "bf_align0,bitField alignment value for aeabi compatibility" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 1.--4. "OPC,The Opc field indicates the transaction type" "0: ,1: ,?..."
|
|
bitfld.long 0x00 0. "LOCK,The Lock field shows that the transaction was locked" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "NOC_observer_error_main_ErrorLogger_0_ErrLog1,Error Log Register 1"
|
|
hexmask.long.word 0x00 23.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. "RouteId,The RouteId field identifies an initiator-mapping-target-mapping pair"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "NOC_observer_error_main_ErrorLogger_0_ErrLog3,Error Log Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "Addr,The Addr field contains the start address of the transaction"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "NOC_Link_A9_NETX_Resp_main_RateAdapter_Id_CoreId,Core ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "NOC_Link_A9_NETX_Resp_main_RateAdapter_Id_RevisionId,Revision ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code"
|
|
hexmask.long.byte 0x00 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "NOC_Link_A9_NETX_Resp_main_RateAdapter_Rate,Configuration Register for higher to lower throughput ratio"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
hexmask.long.word 0x00 0.--9. 1. "RATE,The ratio from higher to lower throughput"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "NOC_Link_A9_NETX_Resp_main_RateAdapter_Bypass,Configuration Register for RateAdapter bypass"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "BYPASS,Bypass the rate-adapter" "0,1"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "NOC_Link_R7_AXIRAM_Resp_main_RateAdapter_Id_CoreId,Core ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "NOC_Link_R7_AXIRAM_Resp_main_RateAdapter_Id_RevisionId,Revision ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code"
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hexmask.long.byte 0x00 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself"
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group.long 0x188++0x03
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line.long 0x00 "NOC_Link_R7_AXIRAM_Resp_main_RateAdapter_Rate,Configuration Register for higher to lower throughput ratio"
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hexmask.long.tbyte 0x00 10.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
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hexmask.long.word 0x00 0.--9. 1. "RATE,The ratio from higher to lower throughput"
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group.long 0x18C++0x03
|
|
line.long 0x00 "NOC_Link_R7_AXIRAM_Resp_main_RateAdapter_Bypass,Configuration Register for RateAdapter bypass"
|
|
hexmask.long 0x00 1.--31. 1. "bf_align0,bitField alignment value for aeabi compatibility"
|
|
bitfld.long 0x00 0. "BYPASS,Bypass the rate-adapter" "0,1"
|
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tree.end
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autoindent.off
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newline
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