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Gen4_R-Car_Trace32/2_Trunk/perneoversee1.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: Neoverse-E1 On-Chip Peripherals
; @Props: Released
; @Author: BGI, PIW, NEJ
; @Changelog: 2020-01-22 BGI
; 2022-04-04 PIW
; 2023-01-09 NEJ
; @Manufacturer: ARM - ARM Ltd.
; @Doc: DDI0487E_a_armv8_arm.pdf (Rev. E.a, 2019-07-05)
; arm_neoverse_e1_trm_101560_0102_00_en.pdf (Rev. r1p2, 2022-03-26)
; dsu_trm_100453_0401_03_en.pdf (Rev. r4p1, 2019-10-31)
; @Core: Neoverse-E1
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perneoversee1.per 15676 2023-01-25 13:24:01Z kwisniewski $
ASSERT VERSION.BUILD.BASE()>=80109.
sif PER.isNOTIFICATION()
base AVM:0x00000000
wgroup AVM:0x00++0
textline " Peripheral File Notification - "
button "show missing files" "DIALOG.MESSAGE ""Please check your installation for the possibly missing files:""+CONV.CHAR(0xa)+PER.NOTIFICATION.MISSINGFILES()"
textline " ---------------------------------------------------------------"
textline " The peripheral file for this SoC cannot be displayed. "
textline " Possible reasons are: "
textline " - it is missing in the local installation or under development "
textline " - it is confidential "
textline " "
textline " As fallback only the core registers are shown. "
textline " Please check www.lauterbach.com/scripts.html "
textline " or contact support@lauterbach.com . "
textline " "
endif
AUTOINDENT.ON center tree
tree.open ("AArch64")
tree "ID Registers"
rgroup.quad spr:0x30000++0x00
line.quad 0x00 "MIDR_EL1,Main ID Register"
hexmask.quad.byte 0x00 24.--31. 1. "IMPL,Implementer code"
bitfld.quad 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme"
newline
hexmask.quad.word 0x00 4.--15. 1. "PART,Primary part number"
bitfld.quad 0x00 0.--3. "REV,Revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,Processor Feature Register 0"
bitfld.quad 0x00 60.--63. "CSV3,Data loaded under speculation can be used to form an address/generate condition codes" "Reserved,Disclosed/No,?..."
bitfld.quad 0x00 56.--59. "CSV2,Branch targets trained in one context can affect speculative execution" "Reserved,Disclosed/No,?..."
newline
bitfld.quad 0x00 28.--31. "RAS,RAS extension version" "Reserved,Version 1,?..."
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface implemented" "Not implemented,Implemented,?..."
newline
bitfld.quad 0x00 20.--23. "ASIMD,Advanced SIMD" "Reserved,Half-Precision,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Reserved,Half-Precision,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
newline
bitfld.quad 0x00 12.--15. "EL3_ELH,EL3 exception level handling" "Not implemented,AArch64,?..."
bitfld.quad 0x00 8.--11. "EL2_ELH,EL2 exception level handling" "Not implemented,AArch64,?..."
newline
bitfld.quad 0x00 4.--7. "EL1_ELH,EL1 exception level handling" "Not implemented,AArch64,?..."
bitfld.quad 0x00 0.--3. "EL0_ELH,EL0 exception level handling" "Not implemented,AArch64,?..."
rgroup.quad spr:0x30050++0x00
line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register"
bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware" "Reserved,2,?..."
bitfld.quad 0x00 20.--23. "WRPS,Number of watchpoints" "Reserved,Reserved,Reserved,4,?..."
bitfld.quad 0x00 12.--15. "BRPS,Number of breakpoints" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
newline
bitfld.quad 0x00 8.--11. "PMEV,Performance monitor extension version" "Reserved,Reserved,Reserved,Reserved,PMUv3,?..."
bitfld.quad 0x00 4.--7. "TEV,Trace extension version" "Not implemented,?..."
bitfld.quad 0x00 0.--3. "DAV,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,v8-A,?..."
rgroup.quad spr:0x30060++0x00
line.quad 0x00 "ID_AA64ISAR0_EL1,Instruction Set Attribute Register 0"
bitfld.quad 0x00 44.--47. "DP,Indicates whether Dot Product support instructions are implemented" "Not implemented,Implemented,?..."
newline
bitfld.quad 0x00 28.--31. "RDM,Rounding double multiply add/Subtract instructions support" "Not supported,Supported,?..."
bitfld.quad 0x00 20.--23. "ATOMIC,Atomic instructions in AArch64" "Reserved,Reserved,Implemented,?..."
newline
bitfld.quad 0x00 16.--19. "CRC32,Indicates whether CRC32 instructions are implemented" "Reserved,Implemented,?..."
bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions in AArch64" "Not implemented,Implemented,?..."
newline
bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions in AArch64" "Not implemented,Implemented,?..."
bitfld.quad 0x00 4.--7. "AES,AES instruction in AArch64" "Not implemented,Reserved,AESE/AESD/AESMC/AESIMC,AESE/AESD/AESMC/AESIMC/PMULL/PMULL2,?..."
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "TGRAN4,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "TGRAN64,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "TGRAN16,16KB granule supported" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "BIGENDEL0,Mixed-endian support at EL0" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16TB,?..."
rgroup.quad spr:0x30041++0x00
line.quad 0x00 "ID_AA64PFR1_EL1,Processor Feature Register 1"
bitfld.quad 0x00 4.--7. "SSBS,Speculative store bypassing safe" "Reserved,Not implemented,?..."
rgroup.quad spr:0x30051++0x00
line.quad 0x00 "ID_AA64DFR1_EL1,Debug Feature Register 1"
rgroup.quad spr:0x30061++0x00
line.quad 0x00 "ID_AA64ISAR1_EL1,Instruction Set Attribute Register 1"
bitfld.quad 0x00 20.--23. "LRCPC,Implemented LDAPRB LDAPRH and LDAPR instructions" "Reserved,Implemented,?..."
bitfld.quad 0x00 0.--3. "DPB,DC CVAP support in AArch64" "Reserved,Supported,?..."
rgroup.quad spr:0x30071++0x00
line.quad 0x00 "ID_AA64MMFR1_EL1,Memory Model Feature Register 1"
bitfld.quad 0x00 28.--31. "XNX,EL0/EL1 execute control distinction at stage2 bit support" "Reserved,Supported,?..."
bitfld.quad 0x00 24.--27. "SPECSEI,Describes whether the PE can generate SError interrupt exceptions" "Not possible,?..."
newline
bitfld.quad 0x00 20.--23. "PAN,Privileged access never support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 16.--19. "LO,Limited order regions support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "HD,Hierarchical permission disabled support" "Reserved,Reserved,Supported,?..."
newline
bitfld.quad 0x00 8.--11. "VH,Virtualization host extensions support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "VMID,Number of VMID bits" "Reserved,Reserved,16 bits,?..."
bitfld.quad 0x00 0.--3. "HAFDBS,Hardware updates of the access and dirty" "Reserved,Reserved,Access/Dirty supported,?..."
rgroup.quad spr:0x30072++0x00
line.quad 0x00 "ID_AA64MMFR2_EL1,Memory Model Feature Register 2"
bitfld.quad 0x00 12.--15. "IESB,IESB bits support" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "LSM,LSMAOE and nTLSMD bits support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "UAO,User access override support" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "CNP,Common not private support" "Reserved,Supported,?..."
rgroup.quad spr:0x30054++0x00
line.quad 0x00 "ID_AA64AFR0_EL1,Auxiliary Feature Register 0"
rgroup.quad spr:0x30055++0x00
line.quad 0x00 "ID_AA64AFR1_EL1,Auxiliary Feature Register 1"
rgroup.quad spr:0x33001++0x00
line.quad 0x00 "CTR_EL0,Cache Type Register"
bitfld.quad 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x00 14.--15. "VIPT,L1 instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.quad 0x00 0.--3. "IMINLINE,I-cache minimum line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
rgroup.quad spr:0x30005++0x00
line.quad 0x00 "MPIDR_EL1,Multiprocessor Affinity Register"
hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Highest level affinity field"
bitfld.quad 0x00 30. "U,Uniprocessor" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach" "Reserved,Very interdependent"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Second highest level affinity field"
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Third highest level affinity field"
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Lowest level affinity field"
rgroup.quad spr:0x30006++0x00
line.quad 0x00 "REVIDR_EL1,Revision ID Register"
rgroup.quad spr:0x33007++0x00
line.quad 0x00 "DCZID_EL0,Data Cache Zero ID Register"
bitfld.quad 0x00 4. "DZP,Data zero prohibited" "Permitted,Prohibited"
bitfld.quad 0x00 0.--3. "BLOCK,Log2 of the block size in words" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
rgroup.quad spr:0x30030++0x00
line.quad 0x00 "MVFR0_EL1,AArch32 Media and VFP Feature Register 0"
bitfld.quad 0x00 28.--31. "FPROUND,Indicates the rounding modes supported by the floating-point hardware" "Reserved,Supported,?..."
bitfld.quad 0x00 24.--27. "FPSHVEC,Indicates the hardware support for floating-point short vectors" "Not supported,?..."
bitfld.quad 0x00 20.--23. "FPSQRT,Indicates the hardware support for floating-point square root operations" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "FPDIVIDE,Indicates the hardware support for floating-point divide operations" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "FPTRAP,Indicates whether the floating-point hardware implementation supports exception trapping" "Not supported,?..."
bitfld.quad 0x00 8.--11. "FPDP,Indicates the hardware support for floating-point double-precision operations" "Reserved,Reserved,VFPv3/VFPv4,?..."
newline
bitfld.quad 0x00 4.--7. "FPSP,Indicates the hardware support for floating-point single-precision operations" "Reserved,Reserved,VFPv3/VFPv4,?..."
bitfld.quad 0x00 0.--3. "SIMDREG,Indicates support for the advanced SIMD register bank" "Reserved,Reserved,32x64-bit,?..."
rgroup.quad spr:0x30031++0x00
line.quad 0x00 "MVFR1_EL1,AArch32 Media and VFP Feature Register 1"
bitfld.quad 0x00 28.--31. "SIMDFMAC,Indicates whether the floating-point and advanced SIMD implementation includes the fused multiply accumulate instructions" "Reserved,Implemented,?..."
bitfld.quad 0x00 24.--27. "FPHP,Indicates whether the floating-point implementation provides half-precision floating-point conversion instructions" "Reserved,Reserved,Reserved,Data processing instructions,?..."
bitfld.quad 0x00 20.--23. "SIMDHP,Indicates whether the floating-point and advanced SIMD implementation provides half-precision floating-point conversion instructions" "Reserved,Reserved,Data processing instructions,?..."
newline
bitfld.quad 0x00 16.--19. "SIMDSP,Indicates whether the floating-point and advanced SIMD implementation provides single-precision floating-point instructions" "Reserved,Implemented,?..."
bitfld.quad 0x00 12.--15. "SIMDINT,Indicates whether the floating-point and advanced SIMD implementation provides integer instructions" "Reserved,Implemented,?..."
bitfld.quad 0x00 8.--11. "SIMDLS,Indicates whether the floating-point and advanced SIMD implementation provides load/store instructions" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 4.--7. "FPDNAN,Indicates whether the VFP hardware implementation supports only the default NaN mode" "Reserved,Propagation of NaN values,?..."
bitfld.quad 0x00 0.--3. "FPFTZ,Indicates whether the VFP hardware implementation supports only the flush-to-zero mode of operation" "Reserved,Full denormalized number arithmetic,?..."
rgroup.quad spr:0x30032++0x00
line.quad 0x00 "MVFR2_EL1,AArch32 Media and VFP Feature Register 2"
bitfld.quad 0x00 4.--7. "FPMISC,Indicates support for miscellaneous VFP features" "Reserved,Reserved,Reserved,Reserved,Floating-point,?..."
bitfld.quad 0x00 0.--3. "SIMDMISC,Indicates support for miscellaneous advanced SIMD features" "Reserved,Reserved,Reserved,Floating-point,?..."
rgroup.quad spr:0x31007++0x00
line.quad 0x00 "AIDR_EL1,Auxiliary ID Register"
group.quad spr:0x34000++0x00
line.quad 0x00 "VPIDR_EL2,Virtualization Processor ID Register"
hexmask.quad.byte 0x00 24.--31. 1. "IMPL,Implementer code"
bitfld.quad 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 16.--19. "ARCH,Architecture" "Reserved,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme"
hexmask.quad.word 0x00 4.--15. 1. "PART,Primary part number"
newline
bitfld.quad 0x00 0.--3. "REV,Revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.quad spr:0x34005++0x00
line.quad 0x00 "VMPIDR_EL2,Virtualization Multiprocessor ID Registers"
hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Affinity level 3 - highest level affinity field"
bitfld.quad 0x00 30. "U,Uniprocessor" "Multiprocessor,Uniprocessor"
bitfld.quad 0x00 24. "MT,Lowest level affinity using a multi-threading" "Largely independent,Very interdependent"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2 - second highest level affinity field"
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1 - third highest level affinity field"
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0 - lowest level affinity field"
tree.end
tree "System Control and Configuration"
group.quad spr:0x36111++0x00
line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register"
bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in secure user mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in secure user mode" "Disabled,Enabled"
group.quad spr:0x30100++0x00
line.quad 0x00 "SCTLR_EL1,System Control Register"
bitfld.quad 0x00 44. "DSSBS,Set the new PSTATE bit" "0,1"
newline
bitfld.quad 0x00 26. "UCI,EL0 access in AArch64 for DC CVAU/ DC CIVAC/ DC CVAC and IC IVAU instructions enable" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big"
newline
bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Set,Unchanged"
bitfld.quad 0x00 21. "IESB,Implicit error synchronization barrier enable" "Disabled,Enabled"
bitfld.quad 0x00 19. "WXN,Write permission implies XN (execute never)" "Not forced,Forced"
newline
bitfld.quad 0x00 18. "NTWE,WFE instruction executed at EL0" "Executed,Not executed"
bitfld.quad 0x00 16. "NTWI,WFI instruction executed at EL0" "Executed,Not executed"
bitfld.quad 0x00 15. "UCT,EL0 access in AArch64 to the CTR_EL0 enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 14. "DZE,Access to DC ZVA instruction at EL0" "Prohibited,Allowed"
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
bitfld.quad 0x00 9. "UMA,User mask access controls access to interrupt masks from EL0 when EL0 is using AArch64" "Disabled,Enabled"
newline
bitfld.quad 0x00 8. "SED,SETEND instruction availability" "No,Yes"
bitfld.quad 0x00 5. "CP15BEN,CP15 barrier operation enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "SA0,Stack alignment check enable for EL0" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,Stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Alignment check" "Low,High"
newline
bitfld.quad 0x00 0. "M,MMU enable" "Disabled,Enabled"
group.quad spr:0x34100++0x00
line.quad 0x00 "SCTLR_EL2,System Control Register"
bitfld.quad 0x00 44. "DSSBS,Set the new PSTATE bit" "0,1"
newline
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies XN (execute never)" "Not forced,Forced"
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,Stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Alignment check" "Low,High"
newline
bitfld.quad 0x00 0. "M,MMU enable" "Disabled,Enabled"
group.quad spr:0x35100++0x00
line.quad 0x00 "SCTLR_EL12,System Control Register"
bitfld.quad 0x00 44. "DSSBS,Set the new PSTATE bit" "0,1"
newline
bitfld.quad 0x00 26. "UCI,EL0 access in AArch64 for DC CVAU/ DC CIVAC/ DC CVAC and IC IVAU instructions enable" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big"
newline
bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Set,Unchanged"
bitfld.quad 0x00 21. "IESB,Implicit error synchronization barrier enable" "Disabled,Enabled"
bitfld.quad 0x00 19. "WXN,Write permission implies XN (execute never)" "Not forced,Forced"
newline
bitfld.quad 0x00 18. "NTWE,WFE instruction executed at EL0" "Executed,Not executed"
bitfld.quad 0x00 16. "NTWI,WFI instruction executed at EL0" "Executed,Not executed"
bitfld.quad 0x00 15. "UCT,EL0 access in AArch64 to the CTR_EL0 enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 14. "DZE,Access to DC ZVA instruction at EL0" "Prohibited,Allowed"
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
bitfld.quad 0x00 9. "UMA,User mask access controls access to interrupt masks from EL0 when EL0 is using AArch64" "Disabled,Enabled"
newline
bitfld.quad 0x00 8. "SED,SETEND instruction availability" "No,Yes"
bitfld.quad 0x00 5. "CP15BEN,CP15 barrier operation enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "SA0,Stack alignment check enable for EL0" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,Stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Alignment check" "Low,High"
newline
bitfld.quad 0x00 0. "M,MMU enable" "Disabled,Enabled"
group.quad spr:0x36100++0x00
line.quad 0x00 "SCTLR_EL3,System Control Register"
bitfld.quad 0x00 44. "DSSBS,Set the new PSTATE bit" "0,1"
newline
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.quad 0x00 21. "IESB,Implicit error synchronization barrier enable" "Disabled,Enabled"
bitfld.quad 0x00 19. "WXN,Write permission implies XN (execute never)" "Not forced,Forced"
bitfld.quad 0x00 12. "I,Global instruction cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,Stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Global enable for data and unifies caches" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Alignment check" "Low,High"
newline
bitfld.quad 0x00 0. "M,Global enable for the EL3 MMU" "Disabled,Enabled"
newline
group.quad spr:0x30101++0x00
line.quad 0x00 "ACTLR_EL1,Auxiliary Control Register 1"
group.quad spr:0x34101++0x00
line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register 2"
bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance management registers enable" "Not accessible,Accessible"
bitfld.quad 0x00 11. "SMEN,Scheme management registers enable" "Not accessible,Accessible"
newline
bitfld.quad 0x00 10. "TSIDEN,Thread scheme ID register enable" "Not accessible,Accessible"
bitfld.quad 0x00 7. "PWREN,Power control registers enable" "Not accessible,Accessible"
newline
bitfld.quad 0x00 5. "ERXPFGEN,Error record registers enable" "Not accessible,Accessible"
newline
bitfld.quad 0x00 1. "ECTLREN,Extended control registers enable" "Not accessible,Accessible"
bitfld.quad 0x00 0. "ACTLREN,Auxiliary control registers enable" "Not accessible,Accessible"
group.quad spr:0x36101++0x00
line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register 3"
bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance management registers enable" "Not accessible,Accessible"
bitfld.quad 0x00 11. "SMEN,Scheme management registers enable" "Not accessible,Accessible"
newline
bitfld.quad 0x00 10. "TSIDEN,Thread scheme ID register enable" "Not accessible,Accessible"
newline
bitfld.quad 0x00 7. "PWREN,Power control registers enable" "Not accessible,Accessible"
newline
bitfld.quad 0x00 5. "ERXPFGEN,Error record registers enable" "Not accessible,Accessible"
newline
bitfld.quad 0x00 4. "AMEN,Activity monitor enable" "Trapped,Not trapped"
newline
bitfld.quad 0x00 1. "ECTLREN,Extended control registers enable" "Not accessible,Accessible"
bitfld.quad 0x00 0. "ACTLREN,Auxiliary control registers enable" "Not accessible,Accessible"
group.quad spr:0x30F10++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
newline
group.quad spr:0x30F14++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 38.--39. "ATOMIC,Force most cacheable atomic instructions to be executed far in the L3 cache or beyond and near in the L1 cache" "Near - hit/unique | Far - miss/shared,Near,Far,Near - load | Far - store"
newline
bitfld.quad 0x00 37. "L2FLUSH,L2 cache flush" "Enabled,Disabled"
newline
bitfld.quad 0x00 28.--29. "L3WSCTL,Write streaming no-L3-allocate threshold" "128,1024,4096,Disabled"
bitfld.quad 0x00 26.--27. "L2WSCTL,Write streaming no-L2-allocate threshold" "16,128,512,Disabled"
newline
bitfld.quad 0x00 24.--25. "L1WSCTL,Write streaming no-L1-allocate threshold" "4,64,128,Disabled"
bitfld.quad 0x00 22. "STBPFDIS,Store buffer STB access disable" "No,Yes"
newline
bitfld.quad 0x00 13.--15. "L1PCTL,L1 allowed data prefetch control" "Disabled,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--12. "L3PCTL,L3 data prefetch distance control" "16 lines,32 lines,Reserved,Reserved,Disabled,2 lines,4 lines,8 lines"
newline
bitfld.quad 0x00 0. "EXTLLC,External last level cache" "Internal,?..."
newline
group.quad spr:0x36F80++0x00
line.quad 0x00 "CPUPSELR_EL3,CPU Private Selection Register"
group.quad spr:0x36F81++0x00
line.quad 0x00 "CPUPCR_EL3,CPU Private Control Register"
group.quad spr:0x36F83++0x00
line.quad 0x00 "CPUPMR_EL3,CPU Private Mask Register"
group.quad spr:0x36F82++0x00
line.quad 0x00 "CPUPOR_EL3,CPU Private Operation Register"
newline
group.quad spr:0x30102++0x00
line.quad 0x00 "CPACR_EL1,Architectural Feature Access Control Register EL1"
bitfld.quad 0x00 20.--21. "FPEN,Floating point and advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,Not trapped"
group.quad spr:0x35102++0x00
line.quad 0x00 "CPACR_EL12,Architectural Feature Access Control Register EL12"
bitfld.quad 0x00 20.--21. "FPEN,Floating Point and advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,Not trapped"
if (((per.l(spr:0x34110))&0x400000000)==(0x400000000))
group.quad spr:0x34112++0x00
line.quad 0x00 "CPTR_EL2,Architectural Feature Trap Register EL2"
bitfld.quad 0x00 31. "TCPAC,Trap coprocessor access control" "Not trapped,Trapped"
bitfld.quad 0x00 20. "TTA,Trap Trace Access" "Not trapped,Trapped"
bitfld.quad 0x00 10. "TFP,Trap floating point and advanced SIMD execution" "Not trapped,Trapped"
else
group.quad spr:0x34112++0x00
line.quad 0x00 "CPTR_EL2,Architectural Feature Trap Register EL2"
bitfld.quad 0x00 31. "TCPAC,Trap coprocessor access control" "Not trapped,Trapped"
bitfld.quad 0x00 28. "TTA,Trap Trace Access" "Not trapped,Trapped"
bitfld.quad 0x00 20.--21. "FPEN,Floating Point and advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1/EL2,EL0,EL0/EL1/EL2,Not trapped"
endif
group.quad spr:0x36112++0x00
line.quad 0x00 "CPTR_EL3,Architectural Feature Trap Register EL3"
bitfld.quad 0x00 10. "TFP,Trap floating point and advanced SIMD execution" "Not trapped,Trapped"
newline
group.quad spr:0x36110++0x00
line.quad 0x00 "SCR_EL3,Secure Configuration Register"
bitfld.quad 0x00 15. "TERR,Trap Error record accesses" "No Trap,Trap"
bitfld.quad 0x00 14. "TLOR,Trap access to the LOR Registers from Non-secure EL1 and EL2 to EL3" "No trap,Trap"
newline
bitfld.quad 0x00 13. "TWE,Trap WFE" "No trap,Trap"
bitfld.quad 0x00 12. "TWI,Trap WFI" "No trap,Trap"
bitfld.quad 0x00 11. "ST,Enables Secure EL1 access to the CNTPS_TVAL_EL1 CNTPS_CTL_EL1 CNTPS_CVAL_EL1[63:0] registers" "Disabled,Enabled"
newline
bitfld.quad 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64"
bitfld.quad 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.quad 0x00 8. "HCE,Hyp Call enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "SMD,Secure Monitor Call disable at EL1 EL2 or EL3" "No,Yes"
bitfld.quad 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
bitfld.quad 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
newline
bitfld.quad 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
bitfld.quad 0x00 0. "NS,Secure mode" "Secure,Non-secure"
newline
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hyp Configuration Register"
bitfld.quad 0x00 52. "TOCU,Trap IC IVAU/ICIMVAU IC IALLU/ICIALLU DC CVAU/DCCMVAU" "Not trapped,Trapped"
bitfld.quad 0x00 50. "TICAB,Trap IC IALLUIS" "Not trapped,Trapped"
bitfld.quad 0x00 49. "TID4,Trap CLIDR_EL1/CSSELR_EL1/CCSIDR_EL1/CCSIDR2_EL1" "Not trapped,Trapped"
newline
bitfld.quad 0x00 38. "MIOCNCE,Mismatched inner/outer cacheable non-coherency enable" "Not lost,Lost"
newline
bitfld.quad 0x00 37. "TEA,Route synchronous external aborts to EL2" "Not routed,Routed"
bitfld.quad 0x00 36. "TERR,Trap error record accesses" "Not trapped,Trapped"
bitfld.quad 0x00 35. "TLOR,Trap access to the LOR Registers from Non-secure EL1 to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 34. "E2H,EL2 host" "Disabled,Enabled"
bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes"
newline
bitfld.quad 0x00 30. "TRVM,Trap read of virtual memory controls" "Disabled,Enabled"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap general exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap virtual memory controls to EL2" "Disabled,Enabled"
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 24. "TPU,Trap cache maintenance instructions to point of unification to EL2" "Disabled,Enabled"
bitfld.quad 0x00 23. "TPC,Trap data/Unified cache maintenance instructions to point of coherency to EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap data/Unified cache maintenance instructions by set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap auxiliary control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap implementation dependent functionality" "Disabled,Enabled"
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
newline
bitfld.quad 0x00 18. "TID3,Trap ID group 3" "Disabled,Enabled"
bitfld.quad 0x00 17. "TID2,Trap ID group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "DC,Default cacheable" "Disabled,Enabled"
bitfld.quad 0x00 10.--11. "BSU,Barrier shareability upgrade - determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual system error/Asynchronous abort" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ interrupt" "Not pending,Pending"
bitfld.quad 0x00 6. "VF,Virtual FIQ interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled"
bitfld.quad 0x00 4. "IMO,Physical IRQ routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected table walk" "Disabled,Enabled"
bitfld.quad 0x00 0. "VM,Second stage of translation enable" "Disabled,Enabled"
group.quad spr:0x30510++0x00
line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Registers"
group.quad spr:0x35510++0x00
line.quad 0x00 "AFSR0_EL12,Auxiliary Fault Status Registers"
group.quad spr:0x30511++0x00
line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Registers"
group.quad spr:0x35511++0x00
line.quad 0x00 "AFSR1_EL12,Auxiliary Fault Status Registers"
group.quad spr:0x34510++0x00
line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Registers"
group.quad spr:0x34511++0x00
line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Registers"
group.quad spr:0x36510++0x00
line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Registers"
group.quad spr:0x36511++0x00
line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Registers"
tree.open "Exception Syndrome Registers"
if (((per.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
elif (((per.l(spr:0x30520))&0xFC000000)==0x04000000)
if (((per.l(spr:0x30520))&0x01000000)==0x01000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
if (((per.l(spr:0x30520))&0x01000000)==0x01000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
if (((per.l(spr:0x30520))&0x01000000)==0x01000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.l(spr:0x30520))&0xFC000000)==0x18000000)
if (((per.l(spr:0x30520))&0x01000000)==0x01000000)
if (((per.l(spr:0x30520))&0x08)==0x00)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
else
if (((per.l(spr:0x30520))&0x08)==0x00)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
endif
elif (((per.l(spr:0x30520))&0xFC000000)==0x1C000000)
if (((per.l(spr:0x30520))&0x01000000)==0x01000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
else
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
endif
elif (((per.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.l(spr:0x30520))&0xFC000000)==0x60000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 20.--21. "OP0,The Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "OP2,The Op2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "OP1,The Op1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIR,Indicates the direction of the trapped instruction" "Write/MSR,Read/MRS"
elif (((per.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
if (((per.l(spr:0x30520))&0x3F)==0x10)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,CE/UEO"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
else
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
endif
elif (((per.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
if (((per.l(spr:0x30520))&0x3F)==0x10)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is sixty-four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,UEO/CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
else
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
endif
elif (((per.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
if (((per.l(spr:0x30520))&0x3F)==0x10)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,CE/UEO"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
else
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
endif
elif (((per.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped fault valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped fault valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.l(spr:0x30520))&0xFD000000)==0xBC000000)
if (((per.l(spr:0x30520))&0x3F)==0x11)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 13. "IESB,Implicit error synchronization barrier" "Not synchronized,Synchronized"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous error type" "UC,UEU,?..."
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
else
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
newline
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
endif
elif (((per.l(spr:0x30520))&0xFD000000)==0xBD000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,IMPLEMENTATION DEFINED syndrome information"
elif (((per.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.l(spr:0x30520))&0xFD000000)==(0xC9000000||0xCD000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 8. "CM,Data came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((per.l(spr:0x35520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
elif (((per.l(spr:0x35520))&0xFC000000)==0x04000000)
if (((per.l(spr:0x35520))&0x01000000)==0x01000000)
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.l(spr:0x35520))&0xFC000000)==(0x0C000000||0x14000000))
if (((per.l(spr:0x35520))&0x01000000)==0x01000000)
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.l(spr:0x35520))&0xFC000000)==(0x10000000||0x30000000))
if (((per.l(spr:0x35520))&0x01000000)==0x01000000)
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.l(spr:0x35520))&0xFC000000)==0x18000000)
if (((per.l(spr:0x35520))&0x01000000)==0x01000000)
if (((per.l(spr:0x35520))&0x08)==0x00)
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
else
if (((per.l(spr:0x35520))&0x08)==0x00)
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
endif
elif (((per.l(spr:0x35520))&0xFC000000)==0x1C000000)
if (((per.l(spr:0x35520))&0x01000000)==0x01000000)
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
else
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
endif
elif (((per.l(spr:0x35520))&0xFC000000)==(0x44000000||0x54000000))
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.l(spr:0x35520))&0xFC000000)==0x60000000)
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 20.--21. "OP0,The Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "OP2,The Op2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "OP1,The Op1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIR,Indicates the direction of the trapped instruction" "Write/MSR,Read/MRS"
elif (((per.l(spr:0x35520))&0xFC000000)==(0x80000000||0x84000000))
if (((per.l(spr:0x35520))&0x3F)==0x10)
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
else
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
endif
elif (((per.l(spr:0x35520))&0xFD000000)==(0x91000000||0x95000000))
if (((per.l(spr:0x35520))&0x3F)==0x10)
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
else
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is sixty-four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
endif
elif (((per.l(spr:0x35520))&0xFD000000)==(0x90000000||0x94000000))
if (((per.l(spr:0x35520))&0x3F)==0x10)
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
else
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
endif
elif (((per.l(spr:0x35520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped fault valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.l(spr:0x35520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped fault valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.l(spr:0x35520))&0xFD000000)==0xBC000000)
if (((per.l(spr:0x35520))&0x3F)==0x11)
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 13. "IESB,Implicit error synchronization barrier" "Not synchronized,Synchronized"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous error type" "UC,UEU,UEO,UER,CE,?..."
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
else
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
newline
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
endif
elif (((per.l(spr:0x35520))&0xFD000000)==0xBD000000)
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
elif (((per.l(spr:0x35520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.l(spr:0x35520))&0xFD000000)==(0xC9000000||0xCD000000))
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.l(spr:0x35520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.l(spr:0x35520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.l(spr:0x35520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((per.l(spr:0x34520))&0xFC000000)==(0x00000000||0x24000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
elif (((per.l(spr:0x34520))&0xFC000000)==0x04000000)
if (((per.l(spr:0x34520))&0x01000000)==0x01000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
if (((per.l(spr:0x34520))&0x01000000)==0x01000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
if (((per.l(spr:0x34520))&0x01000000)==0x01000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.l(spr:0x34520))&0xFC000000)==0x18000000)
if (((per.l(spr:0x34520))&0x01000000)==0x01000000)
if (((per.l(spr:0x34520))&0x08)==0x00)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
else
if (((per.l(spr:0x34520))&0x08)==0x00)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
endif
elif (((per.l(spr:0x34520))&0xFC000000)==0x1C000000)
if (((per.l(spr:0x34520))&0x01000000)==0x01000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
endif
elif (((per.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000||0x5C000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.l(spr:0x34520))&0xFC000000)==0x4C000000)
if (((per.l(spr:0x34520))&0x00080000)==0x00080000)
if (((per.l(spr:0x34520))&0x01000000)==0x01000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
endif
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
endif
elif (((per.l(spr:0x34520))&0xFC000000)==0x60000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 20.--21. "OP0,The Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "OP2,The Op2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "OP1,The Op1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIR,Indicates the direction of the trapped instruction" "Write/MSR,Read/MRS"
elif (((per.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
if (((per.l(spr:0x34520))&0x3F)==0x10)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,CE/UEO"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
endif
elif (((per.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
if (((per.l(spr:0x34520))&0x3F)==0x10)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,UEO/CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
endif
elif (((per.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
if (((per.l(spr:0x34520))&0x3F)==0x10)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,CE/UEO"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
endif
elif (((per.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped fault valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped fault valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.l(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Implementation defined syndrome information"
elif (((per.l(spr:0x34520))&0xFD000000)==0xBC000000)
if (((per.l(spr:0x34520))&0x3F)==0x11)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 13. "IESB,Implicit error synchronization event" "Not synchronized,Synchronized"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous error type" "UC,UEU,?..."
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
newline
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
endif
elif (((per.l(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
elif (((per.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
if (((per.l(spr:0x34520))&0x01000000)==0x01000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
elif (((per.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((per.l(spr:0x36520))&0xFC000000)==(0x00000000||0x24000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
elif (((per.l(spr:0x36520))&0xFC000000)==0x04000000)
if (((per.l(spr:0x36520))&0x1000000)==0x1000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
if (((per.l(spr:0x36520))&0x1000000)==0x1000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
if (((per.l(spr:0x36520))&0x1000000)==0x1000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.l(spr:0x36520))&0xFC000000)==0x18000000)
if (((per.l(spr:0x36520))&0x1000000)==0x1000000)
if (((per.l(spr:0x36520))&0x08)==0x00)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
else
if (((per.l(spr:0x36520))&0x08)==0x00)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
endif
elif (((per.l(spr:0x36520))&0xFC000000)==0x1C000000)
if (((per.l(spr:0x36520))&0x1000000)==0x1000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
endif
elif (((per.l(spr:0x36520))&0xFC000000)==0x4C000000)
if (((per.l(spr:0x36520))&0x00080000)==0x00080000)
if (((per.l(spr:0x36520))&0x01000000)==0x01000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
endif
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
endif
elif (((per.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000||0x5C000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.l(spr:0x36520))&0xFC000000)==0x60000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 20.--21. "OP0,The Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "OP2,The Op2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "OP1,The Op1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIR,Indicates the direction of the trapped instruction" "Write/MSR,Read/MRS"
elif (((per.l(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.long 0x00 0.--24. 1. "IMPL_DEF,Implementation defined"
elif (((per.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
if (((per.l(spr:0x36520))&0x3F)==0x10)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,CE/UEO"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
endif
elif (((per.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
if (((per.l(spr:0x36520))&0x3F)==0x10)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,CE/UEO"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
endif
elif (((per.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
if (((per.l(spr:0x36520))&0x3F)==0x10)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,CE/UEO"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
endif
elif (((per.l(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped fault valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.l(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped fault valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.l(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Implementation defined syndrome information"
elif (((per.l(spr:0x36520))&0xFD000000)==0xBC000000)
if (((per.l(spr:0x36520))&0x3F)==0x11)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 13. "IESB,Implicit error synchronization event" "Not synchronized,Synchronized"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous error type" "UC,UEU,?..."
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
newline
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
endif
elif (((per.l(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
newline
newline
elif (((per.l(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
tree.end
newline
group.quad spr:0x30C11++0x00
line.quad 0x00 "DISR_EL1,Deferred Interrupt Status Register"
bitfld.quad 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.quad 0x00 24. "IDS,Indicates whether the deferred SError interrupt was IMPL_DEF type" "Architecturally defined,?..."
bitfld.quad 0x00 10.--12. "AET,Asynchronous error type" "UC,UEU,UEO,UER,Reserved,Reserved,CE,?..."
newline
bitfld.quad 0x00 0.--5. "DFSC,Fault status code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
group.quad spr:0x34523++0x00
line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "0,1"
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Implementation defined SError interrupt syndrome"
group.quad spr:0x34C11++0x00
line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 Using The AArch64"
bitfld.quad 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,?..."
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Implementation defined SError interrupt syndrome"
group.quad spr:0x30600++0x00
line.quad 0x00 "FAR_EL1,Fault Address Register"
group.quad spr:0x35600++0x00
line.quad 0x00 "FAR_EL12,Fault Address Register"
group.quad spr:0x34600++0x00
line.quad 0x00 "FAR_EL2,Fault Address Register"
group.quad spr:0x36600++0x00
line.quad 0x00 "FAR_EL3,Fault Address Register"
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hyp IPA Fault Address Register"
hexmask.quad.byte 0x00 40.--43. 0x01 "FIPA[51:48],Bits [51:48] of the faulting intermediate physical address"
hexmask.quad 0x00 4.--39. 0x10 "FIPA[47:12],Bits [47:12] of the faulting intermediate physical address"
group.quad spr:0x30C00++0x00
line.quad 0x00 "VBAR_EL1,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x08 "VBA,Vector base address"
group.quad spr:0x35C00++0x00
line.quad 0x00 "VBAR_EL12,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x08 "VBA,Vector base address"
group.quad spr:0x34C00++0x00
line.quad 0x00 "VBAR_EL2,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x08 "VBA,Vector base address"
group.quad spr:0x36C00++0x00
line.quad 0x00 "VBAR_EL3,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x08 "VBA,Vector base address"
rgroup.quad spr:0x36C01++0x00
line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register"
group.quad spr:0x36C02++0x00
line.quad 0x00 "RMR_EL3,Reset Management Register"
bitfld.quad 0x00 1. "RR,Reset request" "Not requested,Requested"
rgroup.quad spr:0x30C10++0x00
line.quad 0x00 "ISR_EL1,Interrupt Status Register"
bitfld.quad 0x00 8. "A,SError pending bit" "Not pending,Pending"
bitfld.quad 0x00 7. "I,IRQ pending bit" "Not pending,Pending"
bitfld.quad 0x00 6. "F,FIQ pending bit" "Not pending,Pending"
group.quad spr:0x30D01++0x00
line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register"
group.quad spr:0x35D01++0x00
line.quad 0x00 "CONTEXTIDR_EL12,Context ID Register"
group.quad spr:0x34D01++0x00
line.quad 0x00 "CONTEXTIDR_EL2,Context ID Register"
group.quad spr:0x33D02++0x00
line.quad 0x00 "TPIDR_EL0,Software Thread ID Registers"
group.quad spr:0x33D03++0x00
line.quad 0x00 "TPIDRRO_EL0,Software Thread ID Registers"
group.quad spr:0x30D04++0x00
line.quad 0x00 "TPIDR_EL1,Software Thread ID Registers"
group.quad spr:0x34D02++0x00
line.quad 0x00 "TPIDR_EL2,Software Thread ID Registers"
group.quad spr:0x36D02++0x00
line.quad 0x00 "TPIDR_EL3,Software Thread ID Registers"
group.quad spr:0x34300++0x00
line.quad 0x00 "DACR32_EL2,Domain Access Control Register"
bitfld.quad 0x00 30.--31. "D15,Domain 15 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 28.--29. "D14,Domain 14 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 26.--27. "D13,Domain 13 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 24.--25. "D12,Domain 12 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 22.--23. "D11,Domain 11 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 20.--21. "D10,Domain 10 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 18.--19. "D9,Domain 9 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 16.--17. "D8,Domain 8 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 14.--15. "D7,Domain 7 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 12.--13. "D6,Domain 6 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 10.--11. "D5,Domain 5 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 8.--9. "D4,Domain 4 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 6.--7. "D3,Domain 3 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 4.--5. "D2,Domain 2 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 2.--3. "D1,Domain 1 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 0.--1. "D0,Domain 0 access permission" "No access,Client,Reserved,Manager"
tree.end
tree "System Instructions"
wgroup.quad spr:0x10710++0x00
line.quad 0x00 "IC_IALLUIS,IC_IALLUIS"
wgroup.quad spr:0x10750++0x00
line.quad 0x00 "IC_IALLU,IC_IALLU"
wgroup.quad spr:0x13751++0x00
line.quad 0x00 "IC_IVAU,IC_IVAU"
wgroup.quad spr:0x13741++0x00
line.quad 0x00 "DC_ZVA,DC_ZVA"
wgroup.quad spr:0x10761++0x00
line.quad 0x00 "DC_IVAC,DC_IVAC"
wgroup.quad spr:0x10762++0x00
line.quad 0x00 "DC_ISW,DC_ISW"
wgroup.quad spr:0x137A1++0x00
line.quad 0x00 "DC_CVAC,DC_CVAC"
wgroup.quad spr:0x137C1++0x00
line.quad 0x00 "DC_CVAP,DC_CVAP"
wgroup.quad spr:0x107A2++0x00
line.quad 0x00 "DC_CSW,DC_CSW"
wgroup.quad spr:0x137B1++0x00
line.quad 0x00 "DC_CVAU,DC_CVAU"
wgroup.quad spr:0x137E1++0x00
line.quad 0x00 "DC_CIVAC,DC_CIVAC"
wgroup.quad spr:0x107E2++0x00
line.quad 0x00 "DC_CISW,DC_CISW"
wgroup.quad spr:0x10780++0x00
line.quad 0x00 "AT_S1E1R,AT_S1E1R"
wgroup.quad spr:0x10781++0x00
line.quad 0x00 "AT_S1E1W,AT_S1E1W"
wgroup.quad spr:0x10782++0x00
line.quad 0x00 "AT_S1E0R,AT_S1E0R"
wgroup.quad spr:0x10790++0x00
line.quad 0x00 "AT_S1E1RP,AT_S1E1RP"
wgroup.quad spr:0x10791++0x00
line.quad 0x00 "AT_S1E1WP,AT_S1E1WP"
wgroup.quad spr:0x10783++0x00
line.quad 0x00 "AT_S1E0W,AT_S1E0W"
wgroup.quad spr:0x14784++0x00
line.quad 0x00 "AT_S12E1R,AT_S12E1R"
wgroup.quad spr:0x14785++0x00
line.quad 0x00 "AT_S12E1W,AT_S12E1W"
wgroup.quad spr:0x14786++0x00
line.quad 0x00 "AT_S12E0R,AT_S12E0R"
wgroup.quad spr:0x14787++0x00
line.quad 0x00 "AT_S12E0W,AT_S12E0W"
wgroup.quad spr:0x14780++0x00
line.quad 0x00 "AT_S1E2R,AT_S1E2R"
wgroup.quad spr:0x14781++0x00
line.quad 0x00 "AT_S1E2W,AT_S1E2W"
wgroup.quad spr:0x16780++0x00
line.quad 0x00 "AT_S1E3R,AT_S1E3R"
wgroup.quad spr:0x16781++0x00
line.quad 0x00 "AT_S1E3W,AT_S1E3W"
wgroup.quad spr:0x10870++0x00
line.quad 0x00 "TLBI_VMALLE1,TLBI_VMALLE1"
wgroup.quad spr:0x10871++0x00
line.quad 0x00 "TLBI_VAE1,TLBI_VAE1"
wgroup.quad spr:0x10872++0x00
line.quad 0x00 "TLBI_ASIDE1,TLBI_ASIDE1"
wgroup.quad spr:0x10873++0x00
line.quad 0x00 "TLBI_VAAE1,TLBI_VAAE1"
wgroup.quad spr:0x10875++0x00
line.quad 0x00 "TLBI_VALE1,TLBI_VALE1"
wgroup.quad spr:0x10877++0x00
line.quad 0x00 "TLBI_VAALE1,TLBI_VAALE1"
wgroup.quad spr:0x10830++0x00
line.quad 0x00 "TLBI_VMALLE1IS,TLBI_VMALLE1IS"
wgroup.quad spr:0x10831++0x00
line.quad 0x00 "TLBI_VAE1IS,TLBI_VAE1IS"
wgroup.quad spr:0x10832++0x00
line.quad 0x00 "TLBI_ASIDE1IS,TLBI_ASIDE1IS"
wgroup.quad spr:0x10833++0x00
line.quad 0x00 "TLBI_VAAE1IS,TLBI_VAAE1IS"
wgroup.quad spr:0x10835++0x00
line.quad 0x00 "TLBI_VALE1IS,TLBI_VALE1IS"
wgroup.quad spr:0x10837++0x00
line.quad 0x00 "TLBI_VAALE1IS,TLBI_VAALE1IS"
wgroup.quad spr:0x14801++0x00
line.quad 0x00 "TLBI_IPAS2E1IS,TLBI_IPAS2E1IS"
wgroup.quad spr:0x14805++0x00
line.quad 0x00 "TLBI_IPAS2LE1IS,TLBI_IPAS2LE1IS"
wgroup.quad spr:0x14841++0x00
line.quad 0x00 "TLBI_IPAS2E1,TLBI_IPAS2E1"
wgroup.quad spr:0x14845++0x00
line.quad 0x00 "TLBI_IPAS2LE1,TLBI_IPAS2LE1"
wgroup.quad spr:0x14871++0x00
line.quad 0x00 "TLBI_VAE2,TLBI_VAE2"
wgroup.quad spr:0x14875++0x00
line.quad 0x00 "TLBI_VALE2,TLBI_VALE2"
wgroup.quad spr:0x14876++0x00
line.quad 0x00 "TLBI_VMALLS12E1,TLBI_VMALLS12E1"
wgroup.quad spr:0x14831++0x00
line.quad 0x00 "TLBI_VAE2IS,TLBI_VAE2IS"
wgroup.quad spr:0x14835++0x00
line.quad 0x00 "TLBI_VALE2IS,TLBI_VALE2IS"
wgroup.quad spr:0x14836++0x00
line.quad 0x00 "TLBI_VMALLS12E1IS,TLBI_VMALLS12E1IS"
wgroup.quad spr:0x16871++0x00
line.quad 0x00 "TLBI_VAE3,TLBI_VAE3"
wgroup.quad spr:0x16875++0x00
line.quad 0x00 "TLBI_VALE3,TLBI_VALE3"
wgroup.quad spr:0x16831++0x00
line.quad 0x00 "TLBI_VAE3IS,TLBI_VAE3IS"
wgroup.quad spr:0x16835++0x00
line.quad 0x00 "TLBI_VALE3IS,TLBI_VALE3IS"
wgroup.quad spr:0x14870++0x00
line.quad 0x00 "TLBI_ALLE2,TLBI_ALLE2"
wgroup.quad spr:0x14830++0x00
line.quad 0x00 "TLBI_ALLE2IS,TLBI_ALLE2IS"
wgroup.quad spr:0x14874++0x00
line.quad 0x00 "TLBI_ALLE1,TLBI_ALLE1"
wgroup.quad spr:0x14834++0x00
line.quad 0x00 "TLBI_ALLE1IS,TLBI_ALLE1IS"
wgroup.quad spr:0x16870++0x00
line.quad 0x00 "TLBI_ALLE3,TLBI_ALLE3"
wgroup.quad spr:0x16830++0x00
line.quad 0x00 "TLBI_ALLE3IS,TLBI_ALLE3IS"
tree.end
tree "Memory Management Unit"
rgroup.quad spr:0x34113++0x00
line.quad 0x00 "HSTR_EL2,Hyp System Trap Register"
group.quad spr:0x34117++0x00
line.quad 0x00 "HACR_EL2,Hyp Auxiliary Configuration Register"
group.quad spr:0x30200++0x00
line.quad 0x00 "TTBR0_EL1,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 0x01 "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common"
group.quad spr:0x30201++0x00
line.quad 0x00 "TTBR1_EL1,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 0x01 "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common"
group.quad spr:0x35200++0x00
line.quad 0x00 "TTBR0_EL12,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 0x01 "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common"
group.quad spr:0x35201++0x00
line.quad 0x00 "TTBR1_EL12,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 0x01 "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common"
group.quad spr:0x34200++0x00
line.quad 0x00 "TTBR0_EL2,Translation Table Base Registers"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address"
bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common"
group.quad spr:0x34201++0x00
line.quad 0x00 "TTBR1_EL2,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 0x01 "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common"
group.quad spr:0x36200++0x00
line.quad 0x00 "TTBR0_EL3,Translation Table Base Registers"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address"
bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common"
group.quad spr:0x34210++0x00
line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register"
hexmask.quad.word 0x00 48.--63. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 4.--47. 0x10 "BADDR[47:4],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Registers"
bitfld.quad 0x00 42. "HPD1,Hierarchical permission disable for the TTBR1 region" "No,Yes"
bitfld.quad 0x00 41. "HPD0,Hierarchical permission disable for the TTBR0 region" "No,Yes"
newline
bitfld.quad 0x00 40. "HD,Hardware update of the dirty bit enable - stage 1" "Disabled,Enabled"
bitfld.quad 0x00 39. "HA,Hardware update of the access bit enable - stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 38. "TBI1,Top byte ignored" "Used,Ignored"
bitfld.quad 0x00 37. "TBI0,Top byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8 bit,16 bit"
bitfld.quad 0x00 32.--34. "IPS,IPASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TByte,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,16KByte,4KByte,64KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attributes for TTBR1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attributes for TTBR1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation Table walk disable for TTBR1 as described in LPAE" "No,Yes"
bitfld.quad 0x00 22. "A1,ASID definition from TTBR0 or TTBR1" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region for TTBR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for TTBR0 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for TTBR0 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 7. "EPD0,Translation table walk disable for TTBR0 as described in LPAE" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region for TTBR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.quad spr:0x35202++0x00
line.quad 0x00 "TCR_EL12,Translation Control Registers"
bitfld.quad 0x00 42. "HPD1,Hierarchical permission disable for the TTBR1 region" "No,Yes"
bitfld.quad 0x00 41. "HPD0,Hierarchical permission disable for the TTBR0 region" "No,Yes"
newline
bitfld.quad 0x00 40. "HD,Hardware update of the dirty bit enable - stage 1" "Disabled,Enabled"
bitfld.quad 0x00 39. "HA,Hardware update of the access bit enable - stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 38. "TBI1,Top byte ignored" "Used,Ignored"
bitfld.quad 0x00 37. "TBI0,Top byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8 bit,16 bit"
bitfld.quad 0x00 32.--34. "IPS,IPASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TByte,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,16KByte,4KByte,64KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attributes for TTBR1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attributes for TTBR1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation Table walk disable for TTBR1 as described in LPAE" "No,Yes"
bitfld.quad 0x00 22. "A1,ASID definition from TTBR0 or TTBR1" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region for TTBR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for TTBR0 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for TTBR0 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 7. "EPD0,Translation table walk disable for TTBR0 as described in LPAE" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region for TTBR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
if (((per.q(spr:0x34110))&0x400000000)==0x000000000)
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Registers"
bitfld.quad 0x00 24. "HPD,Hierarchical permission disable" "No,Yes"
bitfld.quad 0x00 22. "HD,Hardware update of the dirty bit enable - stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "HA,Hardware update of the access bit enable - stage 1" "Enabled,Disabled"
bitfld.quad 0x00 20. "TBI,Top byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TByte,?..."
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR_ELx as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for TTBR_ELx as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for TTBR_ELx as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for TTBR_ELx" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Registers"
bitfld.quad 0x00 42. "HPD1,Hierarchical permission disable for the TTBR1 region" "No,Yes"
bitfld.quad 0x00 41. "HPD0,Hierarchical permission disable for the TTBR0 region" "No,Yes"
newline
bitfld.quad 0x00 40. "HD,Hardware update of the dirty bit enable - stage 1" "Disabled,Enabled"
bitfld.quad 0x00 39. "HA,Hardware update of the access bit enable - stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 38. "TBI1,Top byte ignored" "Used,Ignored"
bitfld.quad 0x00 37. "TBI0,Top byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8 bit,16 bit"
bitfld.quad 0x00 32.--34. "IPS,IPASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TByte,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,16KByte,4KByte,64KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attributes for TTBR1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attributes for TTBR1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation Table walk disable for TTBR1 as described in LPAE" "No,Yes"
bitfld.quad 0x00 22. "A1,ASID definition from TTBR0 or TTBR1" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region for TTBR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for TTBR0 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for TTBR0 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 7. "EPD0,Translation table walk disable for TTBR0 as described in LPAE" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region for TTBR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Registers"
bitfld.quad 0x00 24. "HPD,Hierarchical permission disable" "No,Yes"
bitfld.quad 0x00 22. "HD,Hardware update of the dirty bit enable - stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "HA,Hardware update of the access bit enable - stage 1" "Disabled,Enabled"
bitfld.quad 0x00 20. "TBI,Top byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TByte,?..."
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR_ELx as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for TTBR_ELx as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for TTBR_ELx as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for TTBR_ELx" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
if (((per.q(spr:0x34212))&0xC000)==0x00)
group.quad spr:0x34212++0x00
line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 22. "HD,Hardware update of the dirty bit enable - stage 2" "Disabled,Enabled"
bitfld.quad 0x00 21. "HA,Hardware update of the access bit enable - stage 2" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "VS,VMID Size" "8 bit,16 bit"
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TByte,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,VTTBR0_EL2 granule size" "4KByte,64KByte,16KByte,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for VTTBR_EL2 as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for VTTBR_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for VTTBR_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 6.--7. "SL0,Starting level of the VTCR_EL2 addressed region" "Level 2,Level 1,Level 0,?..."
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for VTTBR_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x34212))&0xC000)==0xC000)
group.quad spr:0x34212++0x00
line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 22. "HD,Hardware update of the dirty bit enable - stage 2" "Disabled,Enabled"
bitfld.quad 0x00 21. "HA,Hardware update of the access bit enable - stage 2" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "VS,VMID Size" "8 bit,16 bit"
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TByte,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,VTTBR0_EL2 granule size" "4KByte,64KByte,16KByte,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for VTTBR_EL2 as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for VTTBR_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for VTTBR_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for VTTBR_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.quad spr:0x34212++0x00
line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 22. "HD,Hardware update of the dirty bit enable - stage 2" "Disabled,Enabled"
bitfld.quad 0x00 21. "HA,Hardware update of the access bit enable - stage 2" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "VS,VMID Size" "8 bit,16 bit"
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TByte,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,VTTBR0_EL2 granule size" "4KByte,64KByte,16KByte,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for VTTBR_EL2 as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for VTTBR_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for VTTBR_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 6.--7. "SL0,Starting level of the VTCR_EL2 addressed region" "Level 3,Level 2,Level 1,?..."
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for VTTBR_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-nGnRE,Reserved,Reserved,Reserved,Device-nGRE,Reserved,Reserved,Reserved,Device-GRE,?..."
newline
hexmask.quad 0x00 12.--47. 0x10 "PA,Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif (((per.q(spr:0x30740))&0x01)==0x00)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Normal Memory/Inner Write-through transient/W allocate,Normal Memory/Inner Write-through transient/R allocate,Normal Memory/Inner Write-through transient/RW allocate,Normal Memory/Inner Non-Cacheable,Normal Memory/Inner Write-back transient/W allocate,Normal Memory/Inner Write-back transient/R allocate,Normal Memory/Inner Write-back transient/RW allocate,Normal Memory/Inner Write-through non-transient,Normal Memory/Inner Write-through non-transient/W allocate,Normal Memory/Inner Write-through non-transient/R allocate,Normal Memory/Inner Write-through non-transient/RW allocate,Normal Memory/Inner Write-back non-transient,Normal Memory/Inner Write-back non-transient/W allocate,Normal Memory/Inner Write-back non-transient/R allocate,Normal Memory/Inner Write-back non-transient/RW allocate"
newline
hexmask.quad 0x00 12.--47. 0x10 "PA,Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size fault/0st level/TTBR,Address size fault/1st level,Address size fault/2st level,Address size fault/3st level,Translation fault/0st level,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Synchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/0st level,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Unsupported atomic hardware update fault,Reserved,Reserved,Lockdown,Unsupported exclusive or atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section domain fault,Page domain fault,?..."
newline
newline
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
newline
tree.open "Memory Attribute Indirection Registers"
group.quad spr:0x30A20++0x00
line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
group.quad spr:0x35A20++0x00
line.quad 0x00 "MAIR_EL12,Memory Attribute Indirection Register"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
group.quad spr:0x34A20++0x00
line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
group.quad spr:0x36A20++0x00
line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
group.quad spr:0x30A30++0x00
line.quad 0x00 "AMAIR_EL1,Auxiliary Memory Attribute Indirection Register"
group.quad spr:0x35A30++0x00
line.quad 0x00 "AMAIR_EL12,Auxiliary Memory Attribute Indirection Register"
group.quad spr:0x34A30++0x00
line.quad 0x00 "AMAIR_EL2,Auxiliary Memory Attribute Indirection Register"
group.quad spr:0x36A30++0x00
line.quad 0x00 "AMAIR_EL3,Auxiliary Memory Attribute Indirection Register"
tree.end
newline
rgroup.quad spr:0x33F00++0x00
line.quad 0x00 "CDBGDR0_EL3,Cache Debug Data Register 0"
rgroup.quad spr:0x33F01++0x00
line.quad 0x00 "CDBGDR1_EL3,Cache Debug Data Register 1"
rgroup.quad spr:0x33F02++0x00
line.quad 0x00 "CDBGDR2_EL3,Cache Debug Data Register 2"
wgroup.quad spr:0x33F20++0x00
line.quad 0x00 "CDBGDCT_EL3,Data Cache Tag Read Operation Register"
wgroup.quad spr:0x33F21++0x00
line.quad 0x00 "CDBGICT_EL3,Instruction Cache Tag Read Operation Register"
wgroup.quad spr:0x33f22++0x00
line.quad 0x00 "CDBGTT_EL3,TLB Tag Read Operation Register"
wgroup.quad spr:0x33F40++0x00
line.quad 0x00 "CDBGDCD_EL3,Data Cache Data Read Operation Register"
wgroup.quad spr:0x33F41++0x00
line.quad 0x00 "CDBGICD_EL3,Instruction Cache Data Read Operation Register"
wgroup.quad spr:0x33F42++0x00
line.quad 0x00 "CDBGTD_EL3,TLB Data Read Operation Register"
tree.end
tree "Virtualization Extensions"
group.quad spr:0x34111++0x00
line.quad 0x00 "MDCR_EL2,Monitor Debug Configuration Register"
bitfld.quad 0x00 17. "HPMD,Hyp performance monitors disable" "No,Yes"
bitfld.quad 0x00 14. "TPMS,Trap performance monitor sampling" "No effect,Trapped"
bitfld.quad 0x00 12.--13. "E2PB,EL2 profiling buffer" "EL2 regime/trapped,Reserved,EL0&1 regime/trapped,EL0&1 regime/no effect"
newline
bitfld.quad 0x00 11. "TDRA,Trap valid EL1 and EL0 access to debug ROM address registers to EL2" "No effect,Trapped"
bitfld.quad 0x00 10. "TDOSA,Trap valid accesses to OS-related debug registers to EL2" "No effect,Trapped"
bitfld.quad 0x00 9. "TDA,Trap valid non-secure accesses to debug registers to EL2" "No effect,Trapped"
newline
bitfld.quad 0x00 8. "TDE,Route debug exceptions from non-secure EL1 and EL0 to EL2" "Disabled,Enabled"
bitfld.quad 0x00 7. "HPME,Hypervisor performance monitors enable" "Disabled,Enabled"
bitfld.quad 0x00 6. "TPM,Trap non-secure EL0 and EL1 accesses to performance monitors registers that are not UNALLOCATED to EL2" "No effect,Trapped"
newline
bitfld.quad 0x00 5. "TPMCR,Trap non-secure EL0 and EL1 accesses to PMCR_EL0 to EL2" "No effect,Trapped"
bitfld.quad 0x00 0.--4. "HPMN,Defines the number of performance monitors counters accessible from non-secure EL0/EL1" "0,1,2,3,4,5,?..."
group.quad spr:0x36131++0x00
line.quad 0x00 "MDCR_EL3,Monitor Debug Configuration Register"
bitfld.quad 0x00 21. "EPMAD,External debugger register access disable" "No,Yes"
bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 16. "SDD,Secure (monitor) debug disable" "No,Yes"
bitfld.quad 0x00 12.--13. "NSPB,Non-secure profiling buffer" "Secure EL1&EL2,Secure EL3,Non-secure EL1&EL2,Non-secure EL1"
newline
bitfld.quad 0x00 10. "TDOSA,Trap valid accesses to OS-related debug registers to EL3" "No effect,Trapped"
bitfld.quad 0x00 9. "TDA,Trap valid Non-secure accesses to debug registers to EL3" "No effect,Trapped"
bitfld.quad 0x00 6. "TPM,Trap performance monitors accesses" "No effect,Trapped"
tree.end
tree "Cache Control and Configuration"
rgroup.quad spr:0x30F00++0x00
line.quad 0x00 "CPUCFR_EL1,CPU Configuration Register"
bitfld.quad 0x00 0.--1. "ECC,Indicates whether ECC is present or not" "Not present,Present,?..."
group.quad spr:0x30F27++0x00
line.quad 0x00 "CPUPWRCTLR_EL1,Power Control Register"
bitfld.quad 0x00 10.--12. "SIMD_RET_CTRL,Advanced SIMD and floating-point retention control" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
bitfld.quad 0x00 7.--9. "FE_RET_CTRL,CPU WFE retention control" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
newline
bitfld.quad 0x00 4.--6. "WFI_RET_CTRL,CPU WFI retention control" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
bitfld.quad 0x00 0. "CORE_PWRDN_EN,Indicates to the power controller if the CPU wants to power down when it enters WFI state" "Not requested,Requested"
rgroup.quad spr:0x33001++0x00
line.quad 0x00 "CTR_EL0,Cache Type Register"
bitfld.quad 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x00 14.--15. "VIPT,L1 instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.quad 0x00 0.--3. "IMINLINE,I-cache minimum line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
if (((per.l(spr:0x32000))&0x0F)>=0x04)
group.quad spr:0x32000++0x00
line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register"
bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..."
elif (((per.l(spr:0x32000))&0xE)==0x02)
group.quad spr:0x32000++0x00
line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register"
bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..."
bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,?..."
elif (((per.l(spr:0x32000))&0x01)==0x01)
group.quad spr:0x32000++0x00
line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register"
bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Reserved,Level 3,?..."
bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
else
group.quad spr:0x32000++0x00
line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register"
bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..."
bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
endif
rgroup.quad spr:0x31000++0x00
line.quad 0x00 "CCSIDR_EL1,Cache Size and ID Register"
bitfld.quad 0x00 31. "WT,Write-through" "Not Supported,?..."
bitfld.quad 0x00 30. "WB,Write-back" "Not Supported,Supported"
newline
bitfld.quad 0x00 29. "RA,Read-allocate" "Not Supported,Supported"
bitfld.quad 0x00 28. "WA,Write-allocate" "Not Supported,Supported"
newline
hexmask.quad.word 0x00 13.--27. 1. 1. "SETS,Number of sets"
hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.quad 0x00 0.--2. "LSIZE,Line size" "16 bytes,32 bytes,64 bytes,128 bytes,?..."
newline
rgroup.quad spr:0x31001++0x00
line.quad 0x00 "CLIDR_EL1,Cache Level ID Register"
bitfld.quad 0x00 30.--32. "ICB,Inner cache boundary" "Reserved,No levels,Per-core L2/cluster L2,Per-core L2 and cluster L3,?..."
newline
bitfld.quad 0x00 27.--29. "LOUU,Level of unification uniprocessor" "No levels,?..."
bitfld.quad 0x00 24.--26. "LOC,Level of coherency" "Reserved,No levels,Per-core L2/cluster L2,Per-core L2 and cluster L3,?..."
newline
bitfld.quad 0x00 21.--23. "LOUIS,Level of unification inner shareable" "No levels,?..."
newline
bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3 (per-core L2/cluster L3)" "All other,Reserved,Reserved,Reserved,Both present,?..."
newline
bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2 (per-core L2/cluster L2)" "All other,Reserved,Reserved,Reserved,Either present,?..."
bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate,?..."
rgroup.quad spr:0x33F00++0x00
line.quad 0x00 "CDBGDR0_EL3,Cache Debug Data Register 0"
rgroup.quad spr:0x33F01++0x00
line.quad 0x00 "CDBGDR1_EL3,Cache Debug Data Register 1"
rgroup.quad spr:0x33F02++0x00
line.quad 0x00 "CDBGDR2_EL3,Cache Debug Data Register 2"
wgroup.quad spr:0x33F20++0x00
line.quad 0x00 "CDBGDCT_EL3,Data Cache Tag Read Operation Register"
wgroup.quad spr:0x33F21++0x00
line.quad 0x00 "CDBGICT_EL3,Instruction Cache Tag Read Operation Register"
wgroup.quad spr:0x33f22++0x00
line.quad 0x00 "CDBGTT_EL3,TLB Tag Read Operation Register"
wgroup.quad spr:0x33F40++0x00
line.quad 0x00 "CDBGDCD_EL3,Data Cache Data Read Operation Register"
wgroup.quad spr:0x33F41++0x00
line.quad 0x00 "CDBGICD_EL3,Instruction Cache Data Read Operation Register"
wgroup.quad spr:0x33F42++0x00
line.quad 0x00 "CDBGTD_EL3,TLB Data Read Operation Register"
tree.end
tree "System Performance Monitor"
group.quad spr:0x339C0++0x00
line.quad 0x00 "PMCR_EL0,Performance Monitors Control Register"
hexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code"
rbitfld.quad 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
bitfld.quad 0x00 6. "LC,Long cycle counter enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "DP,Disable CCNT when event counting prohibited" "No,Yes"
bitfld.quad 0x00 4. "X,Export of events enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "D,Clock divider" "Every cycle,64th cycle"
bitfld.quad 0x00 2. "C,Clock counter reset" "No reset,Reset"
newline
bitfld.quad 0x00 1. "P,Performance counter reset" "No reset,Reset"
bitfld.quad 0x00 0. "E,All counters enable" "Disabled,Enabled"
group.quad spr:0x339C1++0x00
line.quad 0x00 "PMCNTENSET_EL0,Count Enable Set Register"
bitfld.quad 0x00 31. "C,CCNT overflow interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 5. "P5,Event counter PMN 5 enable bit" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "P4,Event counter PMN 4 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled"
group.quad spr:0x339C2++0x00
line.quad 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register"
bitfld.quad 0x00 31. "C,Disables the cycle counter Register" "Disabled,Enabled"
bitfld.quad 0x00 5. "P5,Event counter PMN 5 enable clear bit" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "P4,Event counter PMN 4 enable clear bit" "Disabled,Enabled"
bitfld.quad 0x00 3. "P3,Event counter PMN 3 enable clear bit" "Disabled,Enabled"
bitfld.quad 0x00 2. "P2,Event counter PMN 2 enable clear bit" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "P1,Event counter PMN 1 enable clear bit" "Disabled,Enabled"
bitfld.quad 0x00 0. "P0,Event counter PMN 0 enable clear bit" "Disabled,Enabled"
group.quad spr:0x339C3++0x00
line.quad 0x00 "PMOVSCLR_EL0,Overflow Status Flags Clear Register"
eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
wgroup.quad spr:0x339C4++0x00
line.quad 0x00 "PMSWINC_EL0,Software Increment Register"
bitfld.quad 0x00 5. "P5,PMN5 software increment" "Disabled,Enabled"
bitfld.quad 0x00 4. "P4,PMN4 software increment" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "P3,PMN3 software increment" "Disabled,Enabled"
bitfld.quad 0x00 2. "P2,PMN2 software increment" "Disabled,Enabled"
bitfld.quad 0x00 1. "P1,PMN1 software increment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "P0,PMN0 software increment" "Disabled,Enabled"
group.quad spr:0x339C5++0x00
line.quad 0x00 "PMSELR_EL0,Event Counter Selection Register"
bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.open "Common Event Identification Registers"
rgroup.quad spr:0x339C6++0x00
line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register"
bitfld.quad 0x00 31. "L1D_CACHE_ALLOCATE,Level 1 data cache allocate" "Not implemented,?..."
bitfld.quad 0x00 30. "CHAIN,Chain" "Reserved,Implemented"
bitfld.quad 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented"
newline
bitfld.quad 0x00 28. "TTBR_WRITE_RETIRED,TTBR write retired" "Reserved,Implemented"
bitfld.quad 0x00 27. "INST_SPEC,Instruction speculatively executed" "Reserved,Implemented"
bitfld.quad 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented"
newline
bitfld.quad 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented"
bitfld.quad 0x00 24. "L2D_CACHE_WB,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.quad 0x00 23. "L2D_CACHE_REFILL,Level 2 data cache refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 22. "L2D_CACHE,Level 2 data cache access" "Not implemented,Implemented"
bitfld.quad 0x00 21. "L1D_CACHE_WB,Level 1 data cache write-back" "Reserved,Implemented"
bitfld.quad 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Reserved,Implemented"
newline
bitfld.quad 0x00 19. "MEM_ACCESS,Data memory access" "Reserved,Implemented"
bitfld.quad 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Reserved,Implemented"
bitfld.quad 0x00 17. "CPU_CYCLES,CPU cycle" "Reserved,Implemented"
newline
bitfld.quad 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Reserved,Implemented"
bitfld.quad 0x00 15. "UNALIGNED_LDST_RETIRED,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,?..."
bitfld.quad 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Reserved,Implemented"
newline
bitfld.quad 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Reserved,Implemented"
bitfld.quad 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Reserved,Implemented"
bitfld.quad 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Reserved,Implemented"
newline
bitfld.quad 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Reserved,Implemented"
bitfld.quad 0x00 9. "EXC_TAKEN,Exception taken" "Reserved,Implemented"
bitfld.quad 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Reserved,Implemented"
newline
bitfld.quad 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Reserved,Implemented"
bitfld.quad 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Reserved,Implemented"
bitfld.quad 0x00 5. "L1D_TLB_REFILL,Level 1 data TLB refill" "Reserved,Implemented"
newline
bitfld.quad 0x00 4. "L1D_CACHE,Level 1 data cache access" "Reserved,Implemented"
bitfld.quad 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Reserved,Implemented"
bitfld.quad 0x00 2. "L1I_TLB_REFILL,Level 1 instruction TLB refill" "Reserved,Implemented"
newline
bitfld.quad 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Reserved,Implemented"
bitfld.quad 0x00 0. "SW_INCR,Instruction architecturally executed condition check pass software increment" "Reserved,Implemented"
newline
rgroup.quad spr:0x339C7++0x00
line.quad 0x00 "PMCEID1_EL0,Common Event Identification Register"
bitfld.quad 0x00 24. "REMOTE_ACCESS_RD,Access to another socket in a multi-socket system" "Reserved,Implemented"
newline
bitfld.quad 0x00 23. "LL_CACHE_MISS_RD,Last Level cache miss read" "Reserved,Implemented"
bitfld.quad 0x00 22. "LL_CACHE_RD,Last Level cache access read" "Reserved,Implemented"
bitfld.quad 0x00 21. "ITLB_WALK,Access to instruction TLB that caused a page table walk" "Reserved,Implemented"
newline
bitfld.quad 0x00 20. "DTLB_WALK,Access to data TLB that caused a page table walk" "Reserved,Implemented"
bitfld.quad 0x00 16. "L2I_TLB,Attributable Level 2 instruction TLB access" "Not implemented,?..."
newline
bitfld.quad 0x00 15. "L2D_TLB,Level 2 data or unified TLB access" "Reserved,Implemented"
bitfld.quad 0x00 14. "L2I_TLB_REFILL,Attributable Level 2 instruction TLB refill" "Not implemented,?..."
bitfld.quad 0x00 13. "L2D_TLB_REFILL,Level 2 data or unified TLB refill" "Reserved,Implemented"
newline
bitfld.quad 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Not implemented,?..."
bitfld.quad 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Not implemented,Implemented"
bitfld.quad 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 9. "L3D_CACHE_ALLOCATE,E Attributable Level 3 data or unified cache allocation without refill" "Not implemented,Implemented"
bitfld.quad 0x00 8. "L2I_CACHE_REFILL,Attributable Level 2 instruction cache refill" "Not implemented,?..."
bitfld.quad 0x00 7. "L2I_CACHE,Attributable Level 2 instruction cache access" "Not implemented,?..."
newline
bitfld.quad 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Reserved,Implemented"
bitfld.quad 0x00 5. "L1D_TLB,Level 1 data TLB access" "Reserved,Implemented"
bitfld.quad 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Reserved,Implemented"
newline
bitfld.quad 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Reserved,Implemented"
bitfld.quad 0x00 2. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Reserved,Implemented"
bitfld.quad 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Reserved,Implemented"
newline
bitfld.quad 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocate without refill" "Reserved,Implemented"
tree.end
newline
group.quad spr:0x339D0++0x00
line.quad 0x00 "PMCCNTR_EL0,Performance Monitors Cycle Count Register"
if (((per.q(spr:0x339C5))&0x1F)==0x1F)
group.quad spr:0x339D1++0x00
line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
elif (((per.q(spr:0x339C5))&0x1F)<=0x05)
group.quad spr:0x339D1++0x00
line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event to count"
else
rgroup.quad spr:0x339D1++0x00
line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
endif
group.quad spr:0x339D2++0x00
line.quad 0x00 "PMXEVCNTR_EL0,Selected Event Counter Register"
group.quad spr:0x339E0++0x00
line.quad 0x00 "PMUSERENR_EL0,User Enable Register"
bitfld.quad 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "SW,Software increment write enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "EN,EL0 access enable bit" "Disabled,Enabled"
group.quad spr:0x309E1++0x00
line.quad 0x00 "PMINTENSET_EL1,Interrupt Enable Set Register"
bitfld.quad 0x00 31. "C,CCNT overflow interrupt request enable" "Disabled,Enabled"
bitfld.quad 0x00 5. "P5,PMCNT5 overflow interrupt enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "P4,PMCNT4 overflow interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "P3,PMCNT3 overflow interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "P2,PMCNT2 overflow interrupt enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "P1,PMCNT1 overflow interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "P0,PMCNT0 overflow interrupt enable" "Disabled,Enabled"
group.quad spr:0x309E2++0x00
line.quad 0x00 "PMINTENCLR_EL1,Interrupt Enable Clear Register"
eventfld.long 0x00 31. "C,CCNT overflow interrupt request disable" "Disabled,Enabled"
eventfld.long 0x00 5. "P5,PMCNT5 overflow interrupt enable clear" "Disabled,Enabled"
newline
eventfld.long 0x00 4. "P4,PMCNT4 overflow interrupt enable clear" "Disabled,Enabled"
eventfld.long 0x00 3. "P3,PMCNT3 overflow interrupt enable clear" "Disabled,Enabled"
eventfld.long 0x00 2. "P2,PMCNT2 overflow interrupt enable clear" "Disabled,Enabled"
newline
eventfld.long 0x00 1. "P1,PMCNT1 overflow interrupt enable clear" "Disabled,Enabled"
eventfld.long 0x00 0. "P0,PMCNT0 overflow interrupt enable clear" "Disabled,Enabled"
group.quad spr:0x339E3++0x00
line.quad 0x00 "PMOVSSET_EL0,Overflow Status Flags Set Register"
bitfld.quad 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
bitfld.quad 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
newline
bitfld.quad 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
bitfld.quad 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
bitfld.quad 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
newline
bitfld.quad 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
bitfld.quad 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
group.quad spr:(0x33E80+0x0)++0x00
line.quad 0x00 "PMEVCNTR0_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x1)++0x00
line.quad 0x00 "PMEVCNTR1_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x2)++0x00
line.quad 0x00 "PMEVCNTR2_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x3)++0x00
line.quad 0x00 "PMEVCNTR3_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x4)++0x00
line.quad 0x00 "PMEVCNTR4_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x5)++0x00
line.quad 0x00 "PMEVCNTR5_EL0,Event Counter Register"
group.quad spr:(0x33EC0+0x0)++0x00
line.quad 0x00 "PMEVTYPER0_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x1)++0x00
line.quad 0x00 "PMEVTYPER1_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x2)++0x00
line.quad 0x00 "PMEVTYPER2_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x3)++0x00
line.quad 0x00 "PMEVTYPER3_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x4)++0x00
line.quad 0x00 "PMEVTYPER4_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x5)++0x00
line.quad 0x00 "PMEVTYPER5_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:0x33EF7++0x00
line.quad 0x00 "PMCCFILTR_EL0,Event Type and Cycle Counter Filter Register"
bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.quad spr:0x33E00++0x00
line.quad 0x00 "CNTFRQ_EL0,Counter-timer Frequency Register"
rgroup.quad spr:0x33E01++0x00
line.quad 0x00 "CNTPCT_EL0,Counter-timer Physical Count Register"
rgroup.quad spr:0x33E02++0x00
line.quad 0x00 "CNTVCT_EL0,Counter-timer Virtual Count Register"
group.quad spr:0x34E03++0x00
line.quad 0x00 "CNTVOFF_EL2,Counter-timer Virtual Offset Register"
group.quad spr:0x30E10++0x00
line.quad 0x00 "CNTKCTL_EL1,Counter-timer Kernel Control Register"
bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI generates an event when the event stream is enabled" "0 to 1,1 to 0"
newline
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter CNTVCT and the frequency register CNTFRQ are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter CNTPCT and the frequency register CNTFRQ are accessible from EL0 mode" "Disabled,Enabled"
group.quad spr:0x35E10++0x00
line.quad 0x00 "CNTKCTL_EL12,Counter-timer Kernel Control Register"
bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI generates an event when the event stream is enabled" "0 to 1,1 to 0"
newline
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter CNTVCT and the frequency register CNTFRQ are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter CNTPCT and the frequency register CNTFRQ are accessible from EL0 mode" "Disabled,Enabled"
if (((per.q(spr:0x34110))&0x400000000)==0x000000000)
group.quad spr:0x34E10++0x00
line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control Register"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI generates an event when the event stream is enabled" "0 to 1,1 to 0"
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL1PCEN,Controls whether the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
newline
bitfld.quad 0x00 0. "EL1PCTEN,Controls whether the physical counter CNTPCT is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
else
group.quad spr:0x34E10++0x00
line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control Register"
bitfld.quad 0x00 11. "EL1PTEN,Physical timer register accessing instructions are accessible from Non-secure EL1 and EL0" "Not accessible,Accessible"
bitfld.quad 0x00 10. "EL1PCTEN,Physical counter is accessible from Non-secure EL1 and EL0" "Not accessible,Accessible"
bitfld.quad 0x00 9. "EL0PTEN,Physical timer register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible"
bitfld.quad 0x00 8. "EL0VTEN,Virtual timer register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible"
newline
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI generates an event when the event stream is enabled" "0 to 1,1 to 0"
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL0VCTEN,Virtual counter register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible"
newline
bitfld.quad 0x00 0. "EL0PCTEN,Physical counter is accessible from Non-secure EL0 modes" "Not accessible,Accessible"
endif
group.quad spr:0x33E20++0x00
line.quad 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue Register"
group.quad spr:0x35E20++0x00
line.quad 0x00 "CNTP_TVAL_EL02,Counter-timer Physical Timer TimerValue Register"
if (((per.l(spr:0x33E21))&0x01)==0x00)
group.quad spr:0x33E21++0x00
line.quad 0x00 "CNTP_CTL_EL0,Counter-timer Physical Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.quad spr:0x33E21++0x00
line.quad 0x00 "CNTP_CTL_EL0,Counter-timer Physical Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
if (((per.l(spr:0x35E21))&0x01)==0x00)
group.quad spr:0x35E21++0x00
line.quad 0x00 "CNTP_CTL_EL02,Counter-timer Physical Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.quad spr:0x35E21++0x00
line.quad 0x00 "CNTP_CTL_EL02,Counter-timer Physical Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
group.quad spr:0x33E22++0x00
line.quad 0x00 "CNTP_CVAL_EL0,Counter-timer Physical Timer CompareValue Register"
group.quad spr:0x35E22++0x00
line.quad 0x00 "CNTP_CVAL_EL02,Counter-timer Physical Timer CompareValue Register"
newline
group.quad spr:0x33E30++0x00
line.quad 0x00 "CNTV_TVAL_EL0,Counter-timer Virtual Timer TimerValue Register"
group.quad spr:0x35E30++0x00
line.quad 0x00 "CNTV_TVAL_EL02,Counter-timer Virtual Timer TimerValue Register"
if (((per.l(spr:0x33E31))&0x01)==0x00)
group.quad spr:0x33E31++0x00
line.quad 0x00 "CNTV_CTL_EL0,Counter-Timer Virtual Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.quad spr:0x33E31++0x00
line.quad 0x00 "CNTV_CTL_EL0,Counter-Timer Virtual Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
if (((per.q(spr:0x35E31))&0x01)==0x00)
group.quad spr:0x35E31++0x00
line.quad 0x00 "CNTV_CTL_EL02,Counter-Timer Virtual Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
newline
else
group.quad spr:0x35E31++0x00
line.quad 0x00 "CNTV_CTL_EL02,Counter-Timer Virtual Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
newline
endif
group.quad spr:0x33E32++0x00
line.quad 0x00 "CNTV_CVAL_EL0,Counter-timer Virtual Timer CompareValue Register"
group.quad spr:0x35E32++0x00
line.quad 0x00 "CNTV_CVAL_EL02,Counter-timer Virtual Timer CompareValue Register"
newline
group.quad spr:0x34E20++0x00
line.quad 0x00 "CNTHP_TVAL_EL2,Counter-timer Hypervisor Physical Timer TimerValue Register"
if (((per.l(spr:0x34E21))&0x01)==0x00)
group.quad spr:0x34E21++0x00
line.quad 0x00 "CNTHP_CTL_EL2,Counter-timer Hypervisor Physical Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
newline
else
group.quad spr:0x34E21++0x00
line.quad 0x00 "CNTHP_CTL_EL2,Counter-Timer Hypervisor Physical Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
newline
endif
group.quad spr:0x34E22++0x00
line.quad 0x00 "CNTHP_CVAL_EL2,Counter-timer Hypervisor Physical CompareValue Register"
newline
group.quad spr:0x34E30++0x00
line.quad 0x00 "CNTHV_TVAL_EL2,Counter-timer Hypervisor Virtual Timer Value Register"
if (((per.l(spr:0x34E31))&0x01)==0x00)
group.quad spr:0x34E31++0x00
line.quad 0x00 "CNTHV_CTL_EL2,Counter-timer Hypervisor Virtual Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.quad spr:0x34E31++0x00
line.quad 0x00 "CNTHV_CTL_EL2,Counter-timer Hypervisor Virtual Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
group.quad spr:0x34E32++0x00
line.quad 0x00 "CNTHV_CVAL_EL2,Counter-timer Hypervisor Virtual Timer CompareValue Register"
newline
group.quad spr:0x37E20++0x00
line.quad 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical Secure Timer TimerValue Register"
if (((per.l(spr:0x37E21))&0x01)==0x00)
group.quad spr:0x37E21++0x00
line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.quad spr:0x37E21++0x00
line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
group.quad spr:0x37E22++0x00
line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue Register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch64 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.quad spr:0x30C84++0x00
line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 28. "P28,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 26. "P26,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 25. "P25,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 22. "P22,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 21. "P21,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 19. "P19,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 13. "P13,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 11. "P11,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 10. "P10,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 7. "P7,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 6. "P6,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 4. "P4,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 0 interrupt active priorities" "No interrupt,Interrupt"
group.quad spr:0x30C90++0x00
line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 28. "P28,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 26. "P26,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 25. "P25,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 22. "P22,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 21. "P21,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 19. "P19,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 13. "P13,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 11. "P11,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 10. "P10,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 7. "P7,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 6. "P6,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 4. "P4,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 1 interrupt active priorities" "No interrupt,Interrupt"
tree.end
newline
if (((per.q(spr:0x30CB6))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Alternate SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list/Aff(3:1),All PEs/not self"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
newline
else
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Alternate SGI Generation Register 1"
newline
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list/Aff(3:1),All PEs/not self"
newline
bitfld.quad 0x00 24.--27. "INTID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad spr:0x30C83++0x00
line.quad 0x00 "ICC_BPR0_EL1,Binary Point Register 0"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.quad spr:0x30CC3++0x00
line.quad 0x00 "ICC_BPR1_EL1,Binary Point Register 1"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control (Non-secure/Secure)" "Reserved,Reserved,---/[7:3]-[2:0],[7:3]-[2:0]/[7:4]-[3:0],[7:4]-[3:0]/[7:5]-[4:0],[7:5]-[4:0]/[7:6]-[5:0],[7:6]-[5:0]/[7]-[6:0],[7]-[6:0]/No preemption-[7:0]"
group.quad spr:0x30CC4++0x00
line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)"
rbitfld.quad 0x00 15. "A3V,Affinity 3 valid" "Reserved,Non-zero"
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,?..."
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
newline
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.quad 0x00 6. "PMHE,Indicates whether the priority mask register is used as a hint for interrupt distribution" "Disabled,Enabled"
bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an end of interrupt register also deactivates the interrupt" "Both,Priority drop"
newline
bitfld.quad 0x00 0. "CBPR,Controls whether the same register is used for interrupt preemption of both group 0 and group 1 interrupts" "Separate,Common"
group.quad spr:0x36CC4++0x00
line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)"
rbitfld.quad 0x00 17. "NDS,Disable security not supported" "Reserved,Not supported"
rbitfld.quad 0x00 15. "A3V,Affinity 3 valid" "Reserved,Valid"
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,?..."
newline
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.quad 0x00 6. "PMHE,Priority mask hint enable" "Disabled,Enabled"
newline
rbitfld.quad 0x00 5. "RM,Routing modifier" "0,?..."
newline
bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End Of Interrupt register also deactivates the interrupt (non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop"
bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End Of Interrupt register also deactivates the interrupt (secure EL1)" "Priority drop/Deactivation,Priority drop"
bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt (EL3)" "Priority drop/Deactivation,Priority drop"
newline
bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both group 0 and group 1 non-secure interrupts at EL1" "Separate registers,Same register"
bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both group 0 and group 1 secure interrupts in secure non-monitor modes" "Separate registers,Same register"
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Deactivate Interrupt Register"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,End Of Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0_EL1 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,End Of Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1_EL1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Highest Priority Pending Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Highest Priority Pending Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
hgroup.quad spr:0x30C80++0x00
hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0"
in
hgroup.quad spr:0x30CC0++0x00
hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1"
in
newline
group.quad spr:0x30CC6++0x00
line.quad 0x00 "ICC_IGRPEN0_EL1,Interrupt Group 0 Enable Register (EL1)"
bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad spr:0x30CC7++0x00
line.quad 0x00 "ICC_IGRPEN1_EL1,Interrupt Group 1 Enable Register (EL1)"
bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad spr:0x36CC7++0x00
line.quad 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)"
bitfld.quad 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.quad 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
group.quad spr:0x30460++0x00
line.quad 0x00 "ICC_PMR_EL1,Priority Mask Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.quad spr:0x30CB3++0x00
line.quad 0x00 "ICC_RPR_EL1,Running Priority Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
if (((per.q(spr:0x30CB7))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,SGI Generation Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list/Aff(3:1),All PEs/not self"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
else
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,SGI Generation Register 0"
newline
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list/Aff3/2/1,All PEs/not self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
if (((per.q(spr:0x30CB5))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list/Aff(3:1),All PEs/not self"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
newline
else
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,SGI Generation Register 1"
newline
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list/Aff3/2/1,All PEs/not self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad spr:0x30CC5++0x00
line.quad 0x00 "ICC_SRE_EL1,Interrupt Controller System Register Enable register (EL1)"
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
rbitfld.quad 0x00 0. "SRE,System register enable" "Reserved,Enabled"
group.quad spr:0x34C95++0x00
line.quad 0x00 "ICC_SRE_EL2,Interrupt Controller System Register Enable register (EL2)"
rbitfld.quad 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Reserved,Enabled"
newline
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
rbitfld.quad 0x00 0. "SRE,System register enable" "Reserved,Enabled"
group.quad spr:0x36CC5++0x00
line.quad 0x00 "ICC_SRE_EL3,Interrupt Controller System Register Enable register (EL3)"
rbitfld.quad 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Reserved,Enabled"
newline
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
rbitfld.quad 0x00 0. "SRE,System register enable" "Reserved,Enabled"
tree.end
tree "AArch64 GIC Virtual CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.quad spr:0x30C84++0x00
line.quad 0x00 "ICV_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 28. "P28,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 26. "P26,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 25. "P25,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 22. "P22,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 21. "P21,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 19. "P19,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 13. "P13,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 11. "P11,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 10. "P10,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 7. "P7,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 6. "P6,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 4. "P4,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 0 interrupt active priorities" "No interrupt,Interrupt"
group.quad spr:0x30C90++0x00
line.quad 0x00 "ICV_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 28. "P28,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 26. "P26,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 25. "P25,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 22. "P22,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 21. "P21,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 19. "P19,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 13. "P13,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 11. "P11,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 10. "P10,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 7. "P7,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 6. "P6,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 4. "P4,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 1 interrupt active priorities" "No interrupt,Interrupt"
tree.end
newline
group.quad spr:0x30C83++0x00
line.quad 0x00 "ICV_BPR0_EL1,Binary Point Register 0 (EL1)"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.quad spr:0x30CC3++0x00
line.quad 0x00 "ICV_BPR1_EL1,Binary Point Register 1 (EL1)"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control (Non-secure/Secure)" "Reserved,Reserved,---/[7:3]-[2:0],[7:3]-[2:0]/[7:4]-[3:0],[7:4]-[3:0]/[7:5]-[4:0],[7:5]-[4:0]/[7:6]-[5:0],[7:6]-[5:0]/[7]-[6:0],[7]-[6:0]/No preemption-[7:0]"
group.quad spr:0x30CC4++0x00
line.quad 0x00 "ICV_CTLR_EL1,Interrupt Controller Control Register (EL1)"
rbitfld.quad 0x00 15. "A3V,Affinity 3 valid" "Reserved,Non-zero"
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,?..."
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
newline
rbitfld.quad 0x00 8.--10. "PRIBITS,Priority bits" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.quad 0x00 1. "VEOIMODE,Indicates whether ICV_EOIR0 and ICV_EOIR1 provide both priority drop and interrupt deactivation functionality" "Both,Priority drop"
newline
bitfld.quad 0x00 0. "VCBPR,Common binary point register" "Separate,Common"
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICV_DIR_EL1,Deactivate Interrupt Register"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the virtual interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICV_EOIR0_EL1,End Of Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICV_IAR0_EL1 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICV_EOIR1_EL1,End Of Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICV_IAR1_EL1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICV_HPPIR0_EL1,Highest Priority Pending Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICV_HPPIR1_EL1,Highest Priority Pending Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.quad SPR:0x30C80++0x00
line.quad 0x00 "ICV_IAR0_EL1,Interrupt Controller Interrupt Acknowledge Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
rgroup.quad SPR:0x30CC0++0x00
line.quad 0x00 "ICV_IAR1_EL1,Interrupt Controller Interrupt Acknowledge Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
group.quad spr:0x30CC6++0x00
line.quad 0x00 "ICV_IGRPEN0_EL1,Interrupt Group 0 Enable register"
bitfld.quad 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.quad spr:0x30CC7++0x00
line.quad 0x00 "ICV_IGRPEN1_EL1,Interrupt Group 1 Enable register"
bitfld.quad 0x00 0. "ENABLE,Enables Group 1 interrupts" "Disabled,Enabled"
group.quad spr:0x30460++0x00
line.quad 0x00 "ICV_PMR_EL1,Priority Mask Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.quad spr:0x30CB3++0x00
line.quad 0x00 "ICV_RPR_EL1,Running Priority Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
tree.end
tree "AArch64 Virtual Interface Control System Registers"
tree.open "Interrupt Controller Hypervisor Active Priorities Registers"
group.quad spr:0x34C80++0x00
line.quad 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hyp Active Priorities Group 0 Register 0"
bitfld.quad 0x00 31. "P31,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 28. "P28,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 26. "P26,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 25. "P25,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 22. "P22,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 21. "P21,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 19. "P19,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 13. "P13,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 11. "P11,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 10. "P10,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 7. "P7,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 6. "P6,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 4. "P4,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 0 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 0 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 0 interrupt active priorities" "No interrupt,Interrupt"
group.quad spr:0x34C90++0x00
line.quad 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hyp Active Priorities Group 1 Register 0"
bitfld.quad 0x00 31. "P31,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 28. "P28,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 26. "P26,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 25. "P25,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 22. "P22,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 21. "P21,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 19. "P19,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 13. "P13,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 11. "P11,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 10. "P10,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 7. "P7,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 6. "P6,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 4. "P4,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 1 interrupt active priorities" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 1 interrupt active priorities" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 1 interrupt active priorities" "No interrupt,Interrupt"
tree.end
newline
rgroup.quad spr:0x34CB3++0x00
line.quad 0x00 "ICH_EISR_EL2,End of Interrupt Status Register"
bitfld.quad 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register ICH_LR3_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register ICH_LR2_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register ICH_LR1_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register ICH_LR0_EL2" "No interrupt,Interrupt"
rgroup.quad spr:0x34CB5++0x00
line.quad 0x00 "ICH_ELRSR_EL2,Empty List Register Status Register"
bitfld.quad 0x00 3. "STATUS3,Status bit for List register ICH_LR3_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "STATUS2,Status bit for List register ICH_LR2_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "STATUS1,Status bit for List register ICH_LR1_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "STATUS0,Status bit for List register ICH_LR0_EL2" "No interrupt,Interrupt"
group.quad spr:0x34CB0++0x00
line.quad 0x00 "ICH_HCR_EL2,Interrupt Controller Hyp Control Register"
bitfld.quad 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 14. "TDIR,Trap non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.quad 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,?..."
newline
bitfld.quad 0x00 12. "TALL1,Trap all non-secure EL1 accesses to ICC_* system registers for group 1 interrupts to EL2" "Not trapped,Trapped"
bitfld.quad 0x00 11. "TALL0,Trap all non-secure EL1 accesses to ICC_* system registers for group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.quad 0x00 10. "TC,Trap all non-secure EL1 accesses to system registers that are common to group 0 and group 1 to EL2" "Not trapped,Trapped"
newline
bitfld.quad 0x00 7. "VGRP1DIE,VM group 1 disabled interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 6. "VGRP1EIE,VM group 1 enabled interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 5. "VGRP0DIE,VM group 0 disabled interrupt enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "VGRP0EIE,VM group 0 enabled interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "NPIE,No pending interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "LRENPIE,List register entry not present interrupt enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "UIE,Underflow interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
newline
if (((per.q(spr:0x34CC0))&0x2000000000000000)==0x00)
group.quad spr:0x34CC0++0x00
line.quad 0x00 "ICH_LR0_EL2,List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
else
group.quad spr:0x34CC0++0x00
line.quad 0x00 "ICH_LR0_EL2,List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
endif
if (((per.q(spr:0x34CC1))&0x2000000000000000)==0x00)
group.quad spr:0x34CC1++0x00
line.quad 0x00 "ICH_LR1_EL2,List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
else
group.quad spr:0x34CC1++0x00
line.quad 0x00 "ICH_LR1_EL2,List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
endif
if (((per.q(spr:0x34CC2))&0x2000000000000000)==0x00)
group.quad spr:0x34CC2++0x00
line.quad 0x00 "ICH_LR2_EL2,List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
else
group.quad spr:0x34CC2++0x00
line.quad 0x00 "ICH_LR2_EL2,List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
endif
if (((per.q(spr:0x34CC3))&0x2000000000000000)==0x00)
group.quad spr:0x34CC3++0x00
line.quad 0x00 "ICH_LR3_EL2,List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
else
group.quad spr:0x34CC3++0x00
line.quad 0x00 "ICH_LR3_EL2,List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
endif
rgroup.quad spr:0x34CB2++0x00
line.quad 0x00 "ICH_MISR_EL2,Maintenance Interrupt State Register"
bitfld.quad 0x00 7. "VGRP1D,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 6. "VGRP1E,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 5. "VGRP0D,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 4. "VGRP0E,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
newline
bitfld.quad 0x00 3. "NP,No Pending maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 2. "LRENP,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 1. "U,Underflow maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 0. "EOI,End of Interrupt maintenance interrupt assertion" "Not asserted,Asserted"
newline
group.quad spr:0x34CB7++0x00
line.quad 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register"
hexmask.quad.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.quad 0x00 21.--23. "VBPR0,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.quad 0x00 18.--20. "VBPR1,Interrupt Priority Field Control And Interrupt Preemption Control (Non-secure/Secure)" "Reserved,Reserved,---/[7:3]-[2:0],[7:3]-[2:0]/[7:4]-[3:0],[7:4]-[3:0]/[7:5]-[4:0],[7:5]-[4:0]/[7:6]-[5:0],[7:6]-[5:0]/[7]-[6:0],[7]-[6:0]/No preemption-[7:0]"
newline
bitfld.quad 0x00 9. "VEOIM,Virtual EOI mode" "Disabled,Enabled"
bitfld.quad 0x00 4. "VCBPR,Virtual common binary point register" "Separate registers,Same register"
bitfld.quad 0x00 3. "VFIQEN,Virtual FIQ enable" "Reserved,Virtual FIQs"
newline
bitfld.quad 0x00 1. "VENG1,Virtual group 1 interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "VENG0,Virtual group 0 interrupt enable" "Disabled,Enabled"
rgroup.quad spr:0x34CB1++0x00
line.quad 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register"
bitfld.quad 0x00 29.--31. "PRIBITS,Priority bits" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.quad 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.quad 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
newline
bitfld.quad 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,?..."
bitfld.quad 0x00 21. "A3V,Affinity 3 valid" "Reserved,Non-zero"
bitfld.quad 0x00 20. "NV4,GICv4 direct injection of virtual interrupts" "Supported,?..."
newline
bitfld.quad 0x00 19. "TDS,Separate trapping of non-secure EL1 writes to ICV_DIR_EL1 supported" "Reserved,Supported"
bitfld.quad 0x00 0.--4. "LISTREGS,The number of implemented List registers" "Reserved,Reserved,Reserved,4,?..."
tree.end
tree.end
tree "Debug Registers"
rgroup.quad spr:0x23010++0x00
line.quad 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register"
bitfld.quad 0x00 30. "RXFULL,DBGDTRRX register full" "Empty,Full"
bitfld.quad 0x00 29. "TXFULL,DBGDTRTX register full" "Empty,Full"
group.quad spr:0x20020++0x00
line.quad 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable Register"
bitfld.quad 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled"
bitfld.quad 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled"
group.quad spr:0x23040++0x00
line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register"
hexmask.quad.long 0x00 32.--63. 1. "HIGHWORD,HighWord - write/read DTRRX/DTRTX value without changing RXfull/TXfull"
hexmask.quad.long 0x00 0.--31. 1. "LOWWORD,LowWord - write/read DTRTX/DTRRX value without changing TXfull/RXfull"
rgroup.quad spr:0x23050++0x00
line.quad 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register"
wgroup.quad spr:0x23050++0x00
line.quad 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register"
group.quad spr:0x20002++0x00
line.quad 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register"
if (((per.q(spr:0x20114)&0x02)==0x00))
group.quad spr:0x20022++0x00
line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
rbitfld.quad 0x00 30. "RXFULL,Save/Restore of EDSCR.RXfull" "Empty,Full"
rbitfld.quad 0x00 29. "TXFULL,Save/Restore of EDSCR.TXfull" "Empty,Full"
rbitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High"
rbitfld.quad 0x00 26. "TXU,Save/Restore of EDSCR.TXU" "Low,High"
newline
rbitfld.quad 0x00 22.--23. "INTDIS,Save/Restore of EDSCR.INTDIS" "0,1,2,3"
rbitfld.quad 0x00 21. "TDA,Save/Restore of EDSCR.TDA" "Low,High"
bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
rbitfld.quad 0x00 14. "HDE,Save/Restore of EDSCR.HDE" "Low,High"
newline
bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "No trapped,Trapped"
rbitfld.quad 0x00 6. "ERR,Save/Restore of EDSCR.ERR" "Low,High"
bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled"
else
group.quad spr:0x20022++0x00
line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
bitfld.quad 0x00 30. "RXFULL,Save/Restore of EDSCR.RXfull" "Empty,Full"
bitfld.quad 0x00 29. "TXFULL,Save/Restore of EDSCR.TXfull" "Empty,Full"
bitfld.quad 0x00 27. "RXO,Save/Restore of EDSCR.RXO" "Low,High"
bitfld.quad 0x00 26. "TXU,Save/Restore of EDSCR.TXU" "Low,High"
newline
bitfld.quad 0x00 22.--23. "INTDIS,Save/Restore of EDSCR.INTDIS" "0,1,2,3"
bitfld.quad 0x00 21. "TDA,Save/Restore of EDSCR.TDA" "Low,High"
bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
bitfld.quad 0x00 14. "HDE,Save/Restore of EDSCR.HDE" "Low,High"
newline
bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "No trapped,Trapped"
bitfld.quad 0x00 6. "ERR,Save/Restore of EDSCR.ERR" "Low,High"
bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled"
endif
group.quad spr:0x20032++0x00
line.quad 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register"
if (((per.l(spr:0x20114)&0x02)==0x02))
group.quad spr:0x20062++0x00
line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register"
bitfld.quad 0x00 7. 15. "NS[3],Coarse-grained Non-secure exception catch/return bit NSE[3] and NSR[3]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
bitfld.quad 0x00 6. 14. "NS[2],Coarse-grained Non-secure exception catch/return bit NSE[2] and NSR[2]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
bitfld.quad 0x00 5. 13. "NS[1],Coarse-grained Non-secure exception catch/return bit NSE[1] and NSR[1]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
bitfld.quad 0x00 4. 12. "NS[0],Coarse-grained Non-secure exception catch/return bit NSE[0] and NSR[0]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
newline
bitfld.quad 0x00 3. 11. "S[3],Coarse-grained Secure exception catch/return bit SE[3] and SR[3]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
bitfld.quad 0x00 2. 10. "S[2],Coarse-grained Secure exception catch/return bit SE[2] and SR[2]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
bitfld.quad 0x00 1. 9. "S[1],Coarse-grained Secure exception catch/return bit SE[1] and SR[1]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
bitfld.quad 0x00 0. 8. "S[0],Coarse-grained Secure exception catch/return bit SE[0] and SR[0]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
else
rgroup.quad spr:0x20062++0x00
line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register"
endif
rgroup.quad spr:0x20100++0x00
line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register"
hexmask.quad 0x00 12.--47. 0x10 "ROMADDR,ROM base physical address"
bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid"
wgroup.quad spr:0x20104++0x00
line.quad 0x00 "OSLAR_EL1,OS Lock Access Register"
bitfld.quad 0x00 0. "OSLK,OS lock" "Unlock,Lock"
rgroup.quad spr:0x20114++0x00
line.quad 0x00 "OSLSR_EL1,OS Lock Status Register"
bitfld.quad 0x00 2. "NTT,Not 32-bit access" "Low,High"
bitfld.quad 0x00 1. "OSLK,OS lock status" "Not locked,Locked"
bitfld.quad 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Implemented,?..."
group.quad spr:0x20134++0x00
line.quad 0x00 "OSDLR_EL1,OS Double-lock Register"
bitfld.quad 0x00 0. "DLK,OS double-lock control" "Not locked,Locked"
group.quad spr:0x20144++0x00
line.quad 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register"
bitfld.quad 0x00 0. "CORENPDRQ,Core no powerdown request" "Powered down,Emulated"
group.quad spr:0x20786++0x00
line.quad 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set"
bitfld.quad 0x00 7. "CT7,Claim tag 7 set" "Not set,Set"
bitfld.quad 0x00 6. "CT6,Claim tag 6 set" "Not set,Set"
bitfld.quad 0x00 5. "CT5,Claim tag 5 set" "Not set,Set"
bitfld.quad 0x00 4. "CT4,Claim tag 4 set" "Not set,Set"
newline
bitfld.quad 0x00 3. "CT3,Claim tag 3 set" "Not set,Set"
bitfld.quad 0x00 2. "CT2,Claim tag 2 set" "Not set,Set"
bitfld.quad 0x00 1. "CT1,Claim tag 1 set" "Not set,Set"
bitfld.quad 0x00 0. "CT0,Claim tag 0 set" "Not set,Set"
group.quad spr:0x20796++0x00
line.quad 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear"
bitfld.quad 0x00 7. "CT7,Claim tag 7 clear" "Not cleared,Cleared"
bitfld.quad 0x00 6. "CT6,Claim tag 6 clear" "Not cleared,Cleared"
bitfld.quad 0x00 5. "CT5,Claim tag 5 clear" "Not cleared,Cleared"
bitfld.quad 0x00 4. "CT4,Claim tag 4 clear" "Not cleared,Cleared"
newline
bitfld.quad 0x00 3. "CT3,Claim tag 3 clear" "Not cleared,Cleared"
bitfld.quad 0x00 2. "CT2,Claim tag 2 clear" "Not cleared,Cleared"
bitfld.quad 0x00 1. "CT1,Claim tag 1 clear" "Not cleared,Cleared"
bitfld.quad 0x00 0. "CT0,Claim tag 0 clear" "Not cleared,Cleared"
rgroup.quad spr:0x207E6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status Register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
tree.end
tree "Breakpoint Registers"
tree "Breakpoint 0"
if (((per.q(spr:0x20005+0x0))&0xF00000)<=0x100000)
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x0))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x0))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x700000)))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.l(spr:0x20005+0x0))&0xF00000)>=0x800000)&&(((per.l(spr:0x20005+0x0))&0xF00000)<=0x900000)&&(((per.l(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.l(spr:0x20005+0x0))&0xF00000)>=0x800000)&&(((per.l(spr:0x20005+0x0))&0xF00000)<=0x900000)&&(((per.l(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
elif ((((per.l(spr:0x20005+0x0))&0xF00000)>=0xA00000)&&(((per.l(spr:0x20005+0x0))&0xF00000)<=0xB00000)&&(((per.l(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.l(spr:0x20005+0x0))&0xF00000)>=0xA00000)&&(((per.l(spr:0x20005+0x0))&0xF00000)<=0xB00000)&&(((per.l(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xD00000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xF00000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
else
rgroup.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
endif
if (((per.q(spr:0x20005+0x0))&0x2000)==0x2000)
if (((per.q(spr:0x20005+0x0))&0xC000)==0x0000)
group.quad spr:(0x20005+0x0)++0x00
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x0))&0xC000)==0x4000)
group.quad spr:(0x20005+0x0)++0x00
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x0))&0xC000)==0x8000)
group.quad spr:(0x20005+0x0)++0x00
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x0)++0x00
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20005+0x0))&0xC000)==0xC000)
group.quad spr:(0x20005+0x0)++0x00
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x0)++0x00
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Breakpoint 1"
if (((per.q(spr:0x20005+0x10))&0xF00000)<=0x100000)
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x10))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x10))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x700000)))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.l(spr:0x20005+0x10))&0xF00000)>=0x800000)&&(((per.l(spr:0x20005+0x10))&0xF00000)<=0x900000)&&(((per.l(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.l(spr:0x20005+0x10))&0xF00000)>=0x800000)&&(((per.l(spr:0x20005+0x10))&0xF00000)<=0x900000)&&(((per.l(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
elif ((((per.l(spr:0x20005+0x10))&0xF00000)>=0xA00000)&&(((per.l(spr:0x20005+0x10))&0xF00000)<=0xB00000)&&(((per.l(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.l(spr:0x20005+0x10))&0xF00000)>=0xA00000)&&(((per.l(spr:0x20005+0x10))&0xF00000)<=0xB00000)&&(((per.l(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xD00000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xF00000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
else
rgroup.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
endif
if (((per.q(spr:0x20005+0x10))&0x2000)==0x2000)
if (((per.q(spr:0x20005+0x10))&0xC000)==0x0000)
group.quad spr:(0x20005+0x10)++0x00
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x10))&0xC000)==0x4000)
group.quad spr:(0x20005+0x10)++0x00
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x10))&0xC000)==0x8000)
group.quad spr:(0x20005+0x10)++0x00
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x10)++0x00
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20005+0x10))&0xC000)==0xC000)
group.quad spr:(0x20005+0x10)++0x00
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x10)++0x00
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Breakpoint 2"
if (((per.q(spr:0x20005+0x20))&0xF00000)<=0x100000)
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x20))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x20))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x700000)))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.l(spr:0x20005+0x20))&0xF00000)>=0x800000)&&(((per.l(spr:0x20005+0x20))&0xF00000)<=0x900000)&&(((per.l(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.l(spr:0x20005+0x20))&0xF00000)>=0x800000)&&(((per.l(spr:0x20005+0x20))&0xF00000)<=0x900000)&&(((per.l(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
elif ((((per.l(spr:0x20005+0x20))&0xF00000)>=0xA00000)&&(((per.l(spr:0x20005+0x20))&0xF00000)<=0xB00000)&&(((per.l(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.l(spr:0x20005+0x20))&0xF00000)>=0xA00000)&&(((per.l(spr:0x20005+0x20))&0xF00000)<=0xB00000)&&(((per.l(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xD00000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xF00000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
else
rgroup.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
endif
if (((per.q(spr:0x20005+0x20))&0x2000)==0x2000)
if (((per.q(spr:0x20005+0x20))&0xC000)==0x0000)
group.quad spr:(0x20005+0x20)++0x00
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x20))&0xC000)==0x4000)
group.quad spr:(0x20005+0x20)++0x00
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x20))&0xC000)==0x8000)
group.quad spr:(0x20005+0x20)++0x00
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x20)++0x00
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20005+0x20))&0xC000)==0xC000)
group.quad spr:(0x20005+0x20)++0x00
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x20)++0x00
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Breakpoint 3"
if (((per.q(spr:0x20005+0x30))&0xF00000)<=0x100000)
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x30))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x30))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x700000)))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.l(spr:0x20005+0x30))&0xF00000)>=0x800000)&&(((per.l(spr:0x20005+0x30))&0xF00000)<=0x900000)&&(((per.l(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.l(spr:0x20005+0x30))&0xF00000)>=0x800000)&&(((per.l(spr:0x20005+0x30))&0xF00000)<=0x900000)&&(((per.l(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
elif ((((per.l(spr:0x20005+0x30))&0xF00000)>=0xA00000)&&(((per.l(spr:0x20005+0x30))&0xF00000)<=0xB00000)&&(((per.l(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.l(spr:0x20005+0x30))&0xF00000)>=0xA00000)&&(((per.l(spr:0x20005+0x30))&0xF00000)<=0xB00000)&&(((per.l(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xD00000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xF00000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
else
rgroup.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
endif
if (((per.q(spr:0x20005+0x30))&0x2000)==0x2000)
if (((per.q(spr:0x20005+0x30))&0xC000)==0x0000)
group.quad spr:(0x20005+0x30)++0x00
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x30))&0xC000)==0x4000)
group.quad spr:(0x20005+0x30)++0x00
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x30))&0xC000)==0x8000)
group.quad spr:(0x20005+0x30)++0x00
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x30)++0x00
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20005+0x30))&0xC000)==0xC000)
group.quad spr:(0x20005+0x30)++0x00
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x30)++0x00
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Breakpoint 4"
if (((per.q(spr:0x20005+0x40))&0xF00000)<=0x100000)
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x40))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x40))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x700000)))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.l(spr:0x20005+0x40))&0xF00000)>=0x800000)&&(((per.l(spr:0x20005+0x40))&0xF00000)<=0x900000)&&(((per.l(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.l(spr:0x20005+0x40))&0xF00000)>=0x800000)&&(((per.l(spr:0x20005+0x40))&0xF00000)<=0x900000)&&(((per.l(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
elif ((((per.l(spr:0x20005+0x40))&0xF00000)>=0xA00000)&&(((per.l(spr:0x20005+0x40))&0xF00000)<=0xB00000)&&(((per.l(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.l(spr:0x20005+0x40))&0xF00000)>=0xA00000)&&(((per.l(spr:0x20005+0x40))&0xF00000)<=0xB00000)&&(((per.l(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xD00000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xF00000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
else
rgroup.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
endif
if (((per.q(spr:0x20005+0x40))&0x2000)==0x2000)
if (((per.q(spr:0x20005+0x40))&0xC000)==0x0000)
group.quad spr:(0x20005+0x40)++0x00
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x40))&0xC000)==0x4000)
group.quad spr:(0x20005+0x40)++0x00
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x40))&0xC000)==0x8000)
group.quad spr:(0x20005+0x40)++0x00
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x40)++0x00
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20005+0x40))&0xC000)==0xC000)
group.quad spr:(0x20005+0x40)++0x00
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x40)++0x00
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Breakpoint 5"
if (((per.q(spr:0x20005+0x50))&0xF00000)<=0x100000)
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x50))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x50))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x700000)))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.l(spr:0x20005+0x50))&0xF00000)>=0x800000)&&(((per.l(spr:0x20005+0x50))&0xF00000)<=0x900000)&&(((per.l(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.l(spr:0x20005+0x50))&0xF00000)>=0x800000)&&(((per.l(spr:0x20005+0x50))&0xF00000)<=0x900000)&&(((per.l(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
elif ((((per.l(spr:0x20005+0x50))&0xF00000)>=0xA00000)&&(((per.l(spr:0x20005+0x50))&0xF00000)<=0xB00000)&&(((per.l(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.l(spr:0x20005+0x50))&0xF00000)>=0xA00000)&&(((per.l(spr:0x20005+0x50))&0xF00000)<=0xB00000)&&(((per.l(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xD00000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xF00000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
else
rgroup.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
endif
if (((per.q(spr:0x20005+0x50))&0x2000)==0x2000)
if (((per.q(spr:0x20005+0x50))&0xC000)==0x0000)
group.quad spr:(0x20005+0x50)++0x00
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x50))&0xC000)==0x4000)
group.quad spr:(0x20005+0x50)++0x00
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x50))&0xC000)==0x8000)
group.quad spr:(0x20005+0x50)++0x00
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x50)++0x00
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20005+0x50))&0xC000)==0xC000)
group.quad spr:(0x20005+0x50)++0x00
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x50)++0x00
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
newline
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
tree.end
tree.end
tree "Watchpoint Registers"
tree "Watchpoint 0"
group.quad spr:(0x20006+0x0)++0x00
line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x04 "ADDRESS,Data address"
if (((per.l(spr:0x20007+0x0))&0x2000)==0x2000)
if (((per.l(spr:0x20007+0x0))&0xC000)==0x0000)
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.l(spr:0x20007+0x0))&0xC000)==0x4000)
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.l(spr:0x20007+0x0))&0xC000)==0x8000)
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
if (((per.l(spr:0x20007+0x0))&0xC000)==0xC000)
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Watchpoint 1"
group.quad spr:(0x20006+0x10)++0x00
line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x04 "ADDRESS,Data address"
if (((per.l(spr:0x20007+0x10))&0x2000)==0x2000)
if (((per.l(spr:0x20007+0x10))&0xC000)==0x0000)
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.l(spr:0x20007+0x10))&0xC000)==0x4000)
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.l(spr:0x20007+0x10))&0xC000)==0x8000)
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
if (((per.l(spr:0x20007+0x10))&0xC000)==0xC000)
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Watchpoint 2"
group.quad spr:(0x20006+0x20)++0x00
line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x04 "ADDRESS,Data address"
if (((per.l(spr:0x20007+0x20))&0x2000)==0x2000)
if (((per.l(spr:0x20007+0x20))&0xC000)==0x0000)
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.l(spr:0x20007+0x20))&0xC000)==0x4000)
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.l(spr:0x20007+0x20))&0xC000)==0x8000)
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
if (((per.l(spr:0x20007+0x20))&0xC000)==0xC000)
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Watchpoint 3"
group.quad spr:(0x20006+0x30)++0x00
line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x04 "ADDRESS,Data address"
if (((per.l(spr:0x20007+0x30))&0x2000)==0x2000)
if (((per.l(spr:0x20007+0x30))&0xC000)==0x0000)
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.l(spr:0x20007+0x30))&0xC000)==0x4000)
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.l(spr:0x20007+0x30))&0xC000)==0x8000)
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
if (((per.l(spr:0x20007+0x30))&0xC000)==0xC000)
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
endif
tree.end
tree.end
tree "LORegions Registers"
group.quad spr:0x30A40++0x00
line.quad 0x00 "LORSA_EL1,LORegion Start Address"
hexmask.quad.long 0x00 16.--47. 0x01 "SA,Start physical address bits[47:16]"
bitfld.quad 0x00 0. "VALID,Indicates whether the LORegion descriptor is enabled" "Not valid,Valid"
group.quad spr:0x30A41++0x00
line.quad 0x00 "LOREA_EL1,LORegion End Address"
hexmask.quad.long 0x00 16.--47. 0x01 "EA,End physical address bits[47:16]"
group.quad spr:0x30A42++0x00
line.quad 0x00 "LORN_EL1,LORegion Number"
bitfld.quad 0x00 0.--1. "NUM,LORegion number" "0,1,2,3"
group.quad spr:0x30A43++0x00
line.quad 0x00 "LORC_EL1,LORegion Control"
bitfld.quad 0x00 2.--3. "DS,Descriptor select" "0,1,2,3"
bitfld.quad 0x00 0. "EN,Enable" "Disabled,Enabled"
group.quad spr:0x30A47++0x00
line.quad 0x00 "LORID_EL1,LORegionID"
hexmask.quad.byte 0x00 16.--23. 1. "LD,Number of LOR descriptors supported by the implementation"
hexmask.quad.byte 0x00 0.--7. 1. "LR,Number of LORegions supported by the implementation"
tree.end
tree "DynamIQ Shared Unit"
tree "Error System Registers"
rgroup.quad spr:0x30530++0x00
line.long 0x00 "ERRIDR_EL1,Error Record ID Register (EL1)"
hexmask.long.word 0x00 0.--15. 1. "NUM,Number of records that can be accessed through the Error Record system registers"
group.quad spr:0x30531++0x00
line.quad 0x00 "ERRSELR_EL1,Error Record Select Register (EL1)"
bitfld.quad 0x00 0. "SEL,Selects the record accessed through the ERX registers" "Record 0,Record 1"
if (((per.q(spr:0x30531))&0x01)==0x00)
rgroup.quad spr:0x30540++0x00
line.quad 0x00 "ERXFR_EL1,Error Record Feature Register"
bitfld.quad 0x00 18.--19. "CEO,Corrected error overwrite" "Yes,?..."
bitfld.quad 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.quad 0x00 15. "RP,Repeat counter" "Reserved,Implemented"
newline
bitfld.quad 0x00 12.--14. "CEC,Corrected error counter" "Reserved,Reserved,8 bit standard CE,?..."
bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 8.--9. "UE,In-band uncorrected error reporting" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Implemented,?..."
bitfld.quad 0x00 2.--3. "DE,Defers errors enable" "Reserved,Enabled,?..."
newline
bitfld.quad 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Enabled,?..."
group.quad spr:0x30541++0x00
line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register"
bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 0. "ED,Error detection and correction enable" "Disabled,Enabled"
group.quad spr:0x30542++0x00
line.long 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register"
bitfld.long 0x00 31. "AV,Address valid" "Not valid,?..."
bitfld.long 0x00 30. "V,Status register valid" "Not valid,Valid"
bitfld.long 0x00 29. "UE,Uncorrected error" "No error,>=1 error"
newline
bitfld.long 0x00 28. "ER,Error reported" "No error,?..."
bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error"
bitfld.long 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid"
newline
bitfld.long 0x00 24.--25. "CE,Corrected errors" "No error,Reserved,>=1 error,?..."
bitfld.long 0x00 23. "DE,Deferred errors" "No error,>=1 error"
bitfld.long 0x00 22. "PN,Poison" "No distinction,Earlier poisoned"
newline
bitfld.long 0x00 20.--21. "UET,Uncorrected error type" "Uncontainable,?..."
newline
bitfld.long 0x00 8.--15. 1. "IERR,Implementation defined error code" "No error/Other RAMs,Error/L1 dirty RAM,Error/L3 snoop RAM,?..."
bitfld.long 0x00 0.--7. 1. "SERR,Primary error code" "No error,Reserved,ECC/internal data buffer,Reserved,Reserved,Reserved,ECC/Cache data RAM,ECC/Cache tag/Dirty RAM,Parity/TLB data RAM,Parity/TLB tag RAM,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Bus error,Reserved,Reserved,Deferred error,?..."
group.quad spr:0x30550++0x00
line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0"
bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow"
hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other"
bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow"
newline
hexmask.quad.byte 0x00 32.--38. 1. "CECR,Repeat error count"
bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.word 0x00 6.--17. 1. "INDX,Indicates the index that contained the error"
newline
bitfld.quad 0x00 1.--3. "L,Indicates the level that contained the error" "Level 1,Level 2,?..."
bitfld.quad 0x00 0. "IND,Indicates the type of cache that contained the error" "L1 data cache,L1 instruction cache"
else
rgroup.quad spr:0x30540++0x00
line.quad 0x00 "ERXFR_EL1,Error Record Feature Register"
bitfld.quad 0x00 18.--19. "CEO,Corrected error overwrite" "Yes,?..."
bitfld.quad 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.quad 0x00 15. "RP,Repeat counter" "Reserved,Implemented"
newline
bitfld.quad 0x00 12.--14. "CEC,Corrected error counter" "Reserved,Reserved,8 bit standard CE,?..."
bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 8.--9. "UE,In-band uncorrected error reporting" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 2.--3. "DE,Defers errors enable" "Reserved,Enabled,?..."
newline
bitfld.quad 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Enabled,?..."
group.quad spr:0x30541++0x00
line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register"
bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 0. "ED,Error reporting and logging enable" "Disabled,Enabled"
group.quad spr:0x30542++0x00
line.long 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register"
bitfld.long 0x00 31. "AV,Address valid" "Not valid,?..."
bitfld.long 0x00 30. "V,Status register valid" "Not valid,Valid"
bitfld.long 0x00 29. "UE,Uncorrected error" "No error,>=1 error"
newline
bitfld.long 0x00 28. "ER,Error reported" "No error,?..."
bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error"
bitfld.long 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid"
newline
bitfld.long 0x00 24.--25. "CE,Corrected errors" "No error,Reserved,>=1 error,?..."
bitfld.long 0x00 23. "DE,Deferred errors" "No error,>=1 error"
bitfld.long 0x00 22. "PN,Poison" "No distinction,Earlier poisoned"
newline
bitfld.long 0x00 20.--21. "UET,Uncorrected error type" "Uncontainable,?..."
newline
bitfld.long 0x00 8.--15. 1. "IERR,Implementation defined error code" "No error/Other RAMs,Reserved,Error/L3 snoop RAM,?..."
bitfld.long 0x00 0.--7. 1. "SERR,Primary error code" "No error,Reserved,ECC/internal data buffer,Reserved,Reserved,Reserved,ECC/Cache data RAM,ECC/Cache tag/Dirty RAM,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Bus error,?..."
group.quad spr:0x30550++0x00
line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0"
bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow"
hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other"
bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow"
newline
hexmask.quad.byte 0x00 32.--38. 1. "CECR,Repeat error count"
bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error"
newline
bitfld.quad 0x00 1.--3. "L,Indicates the level that contained the error" "Reserved,Reserved,Level 3,?..."
bitfld.quad 0x00 0. "IND,Indicates the type of cache that contained the error" "L3 cache,?..."
endif
group.quad spr:0x30551++0x00
line.quad 0x00 "ERXMISC1_EL1,Selected Error Record Miscellaneous Register 1"
group.quad spr:0x30F22++0x00
line.long 0x00 "ERXPFGCDN_EL1,Selected Error Pseudo Fault Generation Count Down Register"
group.quad spr:0x30F21++0x00
line.long 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register"
bitfld.long 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled"
bitfld.long 0x00 30. "R,Restartable bit" "Disabled,Enabled"
bitfld.long 0x00 6. "CE,Corrected error generation enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DE,Deferred error generation enable" "Disabled,Enabled"
bitfld.long 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled"
if (((per.q(spr:0x30531))&0x01)==0x00)
rgroup.quad spr:0x30F20++0x00
line.long 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register"
bitfld.long 0x00 31. "PGF,Pseudo fault generation" "Reserved,Supported"
bitfld.long 0x00 30. "R,Restartable bit" "Reserved,Supported"
bitfld.long 0x00 6. "CE,Corrected error generation" "Reserved,Supported"
newline
bitfld.long 0x00 5. "DE,Deferred error generation" "Reserved,Supported"
bitfld.long 0x00 4. "UEO,Latent or restartable error generation" "Not supported,?..."
bitfld.long 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,Supported"
newline
bitfld.long 0x00 1. "UC,Uncontainable error generation" "Reserved,Supported"
else
rgroup.quad spr:0x30F20++0x00
line.long 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register"
bitfld.long 0x00 31. "PGF,Pseudo fault generation" "Not supported,Supported"
bitfld.long 0x00 30. "R,Restartable bit" "Not supported,Supported"
bitfld.long 0x00 6. "CE,Corrected error generation" "Not supported,Supported"
newline
bitfld.long 0x00 5. "DE,Deferred error generation" "Not supported,Supported"
bitfld.long 0x00 4. "UEO,Latent or restartable error generation" "Not supported,Supported"
bitfld.long 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,Supported"
newline
bitfld.long 0x00 2. "UEU,Unrecoverable error generation" "Not supported,Supported"
bitfld.long 0x00 1. "UC,Uncontainable error generation" "Not supported,Supported"
endif
tree.end
tree.end
tree.end
AUTOINDENT.OFF
newline
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