woody/Gen4_R-Car_Trace32
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
main
Gen4_R-Car_Trace32/2_Trunk/permini51.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

5174 lines
556 KiB
Plaintext
Raw Permalink Blame History

; --------------------------------------------------------------------------------
; @Title: MINI51 On-Chip Peripherals
; @Props: Released
; @Author: NEJ, KRZ
; @Changelog: 2023-09-08 NEJ
; 2023-11-09 KRZ
; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
; @Doc: Generated (TRACE32, build: 164352.), based on:
; MINI51XAE_v1.svd (Rev. 1.0), MINI51DE_v1.svd (Rev. 1.0),
; MINI51AN_v1.svd (Rev. 1.0)
; @Core: Cortex-M0
; @Chip: MINI51FDE, MINI51LDE, MINI51TDE, MINI51ZDE, MINI52FDE,
; MINI52LDE, MINI52TDE, MINI52ZDE, MINI54FDE, MINI54FHC,
; MINI54LDE, MINI54TDE, MINI54ZDE
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: permini51.per 16971 2023-11-09 16:09:22Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M0)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ACMP (Analog Comparator)"
base ad:0x400D0000
sif (cpuis("MINI5?XAE"))
group.long 0x0++0xF
line.long 0x0 "ACMP_CTL0,Analog Comparator 0 Control Register"
bitfld.long 0x0 29.--30. "POSSEL,Analog Comparator 0 Positive Input Selection" "0: CPP0 is from P1.5 pin,1: CPP0 is from P1.0 pin,?,?"
bitfld.long 0x0 12. "SMPTSEL,Analog Comparator 0 Speed Mode Selection" "0: Slow mode,1: Fast mode"
newline
bitfld.long 0x0 9. "FTRGEN,Analog Comparator 0 Falling Edge Trigger Enable\nNote: The bit is only effective while analog comparator 0 triggers PWM or Timer." "0: Analog comparator 0 falling edge trigger PWM or..,1: Analog comparator 0 falling edge trigger disabled"
bitfld.long 0x0 8. "RTRGEN,Analog Comparator 0 Rising Edge Trigger Enable\nNote: The bit is only effective while analog comparator 0 triggers PWM or Timer." "0: Analog comparator 0 rising edge trigger PWM or..,1: Analog comparator 0 rising edge trigger disabled"
newline
bitfld.long 0x0 4. "NEGSEL,Analog Comparator 0 Negative Input Selection" "0: The source of the negative comparator input is..,1: The source of the negative comparator input is.."
bitfld.long 0x0 2.--3. "HYSSEL,Analog Comparator 0 Hysteresis Selection" "0: CMP0 Hysteresis Disabled,1: CMP0 Hysteresis typical range is 15mV,?,?"
newline
bitfld.long 0x0 1. "ACMPIE,Analog Comparator 0 Interrupt Enable Control" "0: Interrupt function Disabled,1: Interrupt function Enabled"
bitfld.long 0x0 0. "ACMPEN,Analog Comparator 0 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after this bit is set." "0: Analog Comparator 0 Disabled,1: Analog Comparator 1 Enabled"
line.long 0x4 "ACMP_CTL1,Analog Comparator 1 Control Register"
bitfld.long 0x4 29.--30. "POSSEL,Comparator 1 Positive Input Selection" "0: CPP1 is from P3.1 pin,1: CPP1 is from P3.2 pin,?,?"
bitfld.long 0x4 12. "SMPTSEL,Analog Comparator 1 Speed Mode Selection" "0: Slow mode,1: Fast mode"
newline
bitfld.long 0x4 9. "FTRGEN,Analog Comparator 1 Falling Edge Trigger Enable\nNote: The bit is only effective while analog comparator 1 triggers PWM or Timer." "0: Analog comparator 1 falling edge trigger PWM or..,1: Analog comparator 1 falling edge trigger disabled"
bitfld.long 0x4 8. "RTRGEN,Analog Comparator 1 Rising Edge Trigger Enable\nNote: The bit is only effective while analog comparator 1 triggers PWM or Timer." "0: Analog comparator 1 rising edge trigger PWM or..,1: Analog comparator 1 rising edge trigger disabled"
newline
bitfld.long 0x4 4. "NEGSEL,Analog Comparator 1 Negative Input Selection" "0: The source of the negative comparator input is..,1: The source of the negative comparator input is.."
bitfld.long 0x4 2.--3. "HYSSEL,Analog Comparator 1 Hysteresis Selction" "0: CMP0 Hysteresis Disabled,1: CMP0 Hysteresis typical range is 15mV,?,?"
newline
bitfld.long 0x4 1. "ACMPIE,Analog Comparator 1 Interrupt Enable Control" "0: Interrupt function Disabled,1: Interrupt function Enabled"
bitfld.long 0x4 0. "ACMPEN,Analog Comparator 1 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after this bit is set.." "0: Analog Comparator 1 Disabled,1: Analog Comparator 1 Enabled"
line.long 0x8 "ACMP_STATUS,Analog Comparator 0/1 Status Register"
bitfld.long 0x8 3. "ACMPO1,Analog Comparator 1 Output" "0: Analog comparator 1 outputs 0,1: Analog comparator 1 outputs 1"
bitfld.long 0x8 2. "ACMPO0,Analog Comparator 0 Output" "0: Analog comparator 0 outputs 0,1: Analog comparator 0 outputs 1"
newline
bitfld.long 0x8 1. "ACMPIF1,Analog Comparator 1 Flag\nNote: Software can write 1 to clear this bit to zero." "0: Analog comparator 1 output does not change,1: Analog comparator 1 output changed"
bitfld.long 0x8 0. "ACMPIF0,Analog Comparator 0 Flag\nNote: Software can write 1 to clear this bit to zero." "0: Analog comparator 0 output does not change,1: Analog comparator 0 output changed"
line.long 0xC "ACMP_VREF,Analog Comparator Reference Voltage Control Register"
bitfld.long 0xC 7. "IREFSEL,CRV Module Output Selection" "0: Band-gap voltage,1: Internal comparator reference voltage"
hexmask.long.byte 0xC 0.--3. 1. "CRVCTL,Internal Reference Selection"
endif
sif (cpuis("MINI5??DE"))
group.long 0x0++0xF
line.long 0x0 "ACMP_CR0,Analog Comparator 0 Control Register"
bitfld.long 0x0 29.--30. "CPP0SEL,Analog Comparator 0 Positive Input Selection\n" "0: CPP0 is from P1.5 pin,1: CPP0 is from P1.0 pin,?,?"
bitfld.long 0x0 9. "FALLING,Analog Comparator 0 Falling Edge Trigger Enable Control\nNote: The bit is only effective while analog comparator 0 triggers PWM or Timer." "0: Analog comparator 0 falling edge trigger Disabled,1: Analog comparator 0 falling edge trigger PWM or.."
newline
bitfld.long 0x0 8. "RISING,Analog Comparator 0 Rising Edge Trigger Enable Control\nNote: The bit is only effective while analog comparator 0 triggers PWM or Timer." "0: Analog comparator 0 rising edge trigger Disabled,1: Analog comparator 0 rising edge trigger PWM or.."
bitfld.long 0x0 4. "NEGSEL,Analog Comparator 0 Negative Input Selection\n" "0: The source of the negative comparator input is..,1: The source of the negative comparator input is.."
newline
bitfld.long 0x0 2. "HYSEN,Analog Comparator 0 Hysteresis Enable Control\n" "0: Hysteresis function Disabled,1: Hysteresis function Enabled"
bitfld.long 0x0 1. "ACMPIE,Analog Comparator 0 Interrupt Enable Control\n" "0: Interrupt function Disabled,1: Interrupt function Enabled"
newline
bitfld.long 0x0 0. "ACMPEN,Analog Comparator 0 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after this bit is set." "0: Analog Comparator 0 Disabled,1: Analog Comparator 1 Enabled"
line.long 0x4 "ACMP_CR1,Analog Comparator 1 Control Register"
bitfld.long 0x4 29.--30. "CPP1SEL,Analog Comparator 1 Positive Input Selection\n" "0: CPP1 is from P3.1 pin,1: CPP1 is from P3.2 pin,?,?"
bitfld.long 0x4 9. "FALLING,Analog Comparator 1 Falling Edge Trigger Enable Control\nNote: The bit is only effective while analog comparator 1 triggers PWM or Timer." "0: Analog comparator 1 falling edge trigger Disabled,1: Analog comparator 1 falling edge trigger PWM or.."
newline
bitfld.long 0x4 8. "RISING,Analog Comparator 1 Rising Edge Trigger Enable Control\nNote: The bit is only effective while analog comparator 1 triggers PWM or Timer." "0: Analog comparator 1 rising edge trigger Disabled,1: Analog comparator 1 rising edge trigger PWM or.."
bitfld.long 0x4 4. "NEGSEL,Analog Comparator 1 Negative Input Selection\n" "0: The source of the negative comparator input is..,1: The source of the negative comparator input is.."
newline
bitfld.long 0x4 2. "HYSEN,Analog Comparator 1 Hysteresis Enable Control\n" "0: Hysteresis function Disabled,1: Hysteresis function Enabled"
bitfld.long 0x4 1. "ACMPIE,Analog Comparator 1 Interrupt Enable Control\n" "0: Interrupt function Disabled,1: Interrupt function Enabled"
newline
bitfld.long 0x4 0. "ACMPEN,Analog Comparator 1 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after this bit is set." "0: Analog Comparator 1 Disabled,1: Analog Comparator 1 Enabled"
line.long 0x8 "ACMP_SR01,Analog Comparator 0/1 Status Register"
bitfld.long 0x8 3. "ACMPO1,Analog Comparator 1 Output\n" "0: Analog comparator 1 outputs 0,1: Analog comparator 1 outputs 1"
bitfld.long 0x8 2. "ACMPO0,Analog Comparator 0 Output\n" "0: Analog comparator 0 outputs 0,1: Analog comparator 0 outputs 1"
newline
bitfld.long 0x8 1. "ACMPF1,Analog Comparator 1 Flag\nNote: Software can write 1 to clear this bit to 0." "0: Analog comparator 1 output does not change,1: Analog comparator 1 output changed"
bitfld.long 0x8 0. "ACMPF0,Analog Comparator 0 Flag\nNote: Software can write 1 to clear this bit to 0." "0: Analog comparator 0 output does not change,1: Analog comparator 0 output changed"
line.long 0xC "ACMP_RVCR,Analog Comparator Reference Voltage Control Register"
bitfld.long 0xC 7. "OUT_SEL,CRV Module Output Selection\n" "0: Band-gap voltage,1: Internal comparator reference voltage"
hexmask.long.byte 0xC 0.--3. 1. "CRVS,Comparator Reference Voltage Setting\n"
endif
sif (cpuis("MINI5?AN"))
group.long 0x0++0xF
line.long 0x0 "CMP0CR,Comparator0 Control Register"
bitfld.long 0x0 29.--30. "CPP0SEL,Comparator0 Positive Input Selection\n" "0: From P1.5,1: From P1.0,?,?"
bitfld.long 0x0 9. "CMP0_FALLING,Comparator0 Falling Edge Trigger Enable\nNote: The bit is only effective while comparator0 triggers PWM/Timer." "0: Disable comparator0 trigger PWM/Timer on falling..,1: Enable comparator0 trigger PWM/Timer on falling.."
newline
bitfld.long 0x0 8. "CMP0_RISING,Comparator0 Trigger PWM/Timer on Rising Edge Enable\nNote: The bit is only effective while comparator0 triggers PWM/Timer." "0: Disable comparator0 trigger PWM/Timer on rising..,1: Enable comparator0 trigger PWM/Timer on rising.."
bitfld.long 0x0 4. "CN0,Comparator0 Negative Input Selection\n" "0: The comparator reference pin CPN0 is selected as..,1: The internal comparator reference voltage (Vref.."
newline
bitfld.long 0x0 2. "CMP0_HYSEN,Comparator0 Hysteresis Enable\n" "0: CMP0 Hysteresis function Disabled (Default),1: CMP0 Hysteresis function at comparator 0 Enabled.."
bitfld.long 0x0 1. "CMP0IE,Comparator0 Interrupt Enable\nInterrupt is generated if CMP0IE bit is set to 1 after CMP0 conversion finished." "0: CMP0 interrupt function Disabled,1: CMP0 interrupt function Enabled"
newline
bitfld.long 0x0 0. "CMP0EN,Comparator0 Enable\nComparator output needs to wait 10 us stable time after CMP0EN is set." "0: Disabled,1: Enabled"
line.long 0x4 "CMP1CR,Comparator1 Control Register"
bitfld.long 0x4 29.--30. "CPP1SEL,Comparator1 Positive Input Selection\n" "0: From P3.1,1: From P3.2,?,?"
bitfld.long 0x4 9. "CMP1_FALLING,Comparator1 Falling Edge Trigger Enable\nNote: The bit is only effective while comparator1 triggers PWM/Timer." "0: Disable comparator1 trigger PWM/Timer on falling..,1: Enable comparator1 trigger PWM/Timer on falling.."
newline
bitfld.long 0x4 8. "CMP1_RISING,Comparator1 Trigger PWM/Timer on Rising Edge Enable\nNote: The bit is only effective while comparator1 triggers PWM/Timer." "0: Disable comparator1 trigger PWM/Timer on rising..,1: Enable comparator1 trigger PWM/Timer on rising.."
bitfld.long 0x4 4. "CN1,Comparator1 Negative Input Selection\n" "0: The comparator reference pin CPN0 is selected as..,1: The internal comparator reference voltage.."
newline
bitfld.long 0x4 2. "CMP1_HYSEN,Comparator1 Hysteresis Enable\n" "0: CMP0 Hysteresis function Disabled (Default),1: CMP0 Hysteresis function at comparator 0 Enabled.."
bitfld.long 0x4 1. "CMP1IE,Comparator1 Interrupt Enable\nInterrupt is generated if CMP1IE bit is set to 1 after CMP1 conversion finished." "0: CMP1 interrupt function Disabled,1: CMP1 interrupt function Enabled"
newline
bitfld.long 0x4 0. "CMP1EN,Comparator1 Enable\nComparator output needs to wait 10 us stable time after CMP1EN is set." "0: Disabled,1: Enabled"
line.long 0x8 "CMPSR,Comparator Status Register"
bitfld.long 0x8 3. "CO1,Comparator1 Output\n" "0,1"
bitfld.long 0x8 2. "CO0,Comparator0 Output\n" "0,1"
newline
bitfld.long 0x8 1. "CMPF1,Comparator1 Flag\nThis bit is set by hardware whenever the comparator1 output changes state. This will cause an interrupt if CMP1IE set.\nSoftware can write 1 to clear this bit to zero." "0,1"
bitfld.long 0x8 0. "CMPF0,Comparator0 Flag\nThis bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if CMP0IE set.\nSoftware can write 1 to clear this bit to zero." "0,1"
line.long 0xC "CMPRVCR,Comparator Reference Voltage Control Register"
bitfld.long 0xC 7. "OUT_SEL,CRV Module Output Selection\n" "0: Band-gap 1.22 V voltage Selected,1: CRVS setting voltage Selected"
hexmask.long.byte 0xC 0.--3. 1. "CRVS,Comparator Reference Voltage Setting\n"
endif
tree.end
tree "ADC (Analog-to-Digital Converter)"
base ad:0x400E0000
sif (cpuis("MINI5?XAE"))
rgroup.long 0x0++0x3
line.long 0x0 "ADC_DAT,ADC Data Register"
bitfld.long 0x0 17. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read." "0: Data in RESULT[9:0] bits not valid,1: Data in RESULT[9:0] bits valid"
bitfld.long 0x0 16. "OV,Over Run Flag\nIf converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after the ADC_DAT register is read." "0: Data in RESULT[9:0] is recent conversion result,1: Data in RESULT[9:0] overwrote"
newline
hexmask.long.word 0x0 0.--9. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC."
group.long 0x20++0x13
line.long 0x0 "ADC_CTL,ADC Control Register"
bitfld.long 0x0 12. "VREFSEL,Reference Voltage Selection Signal" "0: Connect VDD5V to internal reference,1: Connect VREF (AIN0) pin to internal reference"
bitfld.long 0x0 11. "SWTRG,A/D Conversion Start\nSWTRG bit can be set to 1 from two sources: software and external pin STADC. SWTRG will be cleared to 0 by hardware automatically after conversion complete." "0: Conversion stopped and A/D converter entered..,1: Conversion start"
newline
bitfld.long 0x0 8. "HWTRGEN,External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled the SWTRG bit can be set to 1 by the selected hardware trigger source." "0: External trigger Disabled,1: External trigger Enabled"
bitfld.long 0x0 6. "HWTRGCOND,External Trigger Condition\nThis bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger." "0: Falling edge,1: Raising edge"
newline
bitfld.long 0x0 4.--5. "HWTRGSEL,Hardware Trigger Source\nNote: Software should disable HWTRGEN and SWTRG before change HWTRGSEL." "0: A/D conversion is started by external STADC pin,?,?,?"
bitfld.long 0x0 1. "ADCIEN,A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADCIEN bit is set to 1." "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled"
newline
bitfld.long 0x0 0. "ADCEN,A/D Converter Enable\nNote: Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption." "0: A/D Converter Disabled,1: A/D Converter Enabled"
line.long 0x4 "ADC_CHEN,ADC Channel Enable Register"
bitfld.long 0x4 13. "BGEN,Band-Gap Voltage Measurement\nNote: User can set BGEN high to use ADC to measure Band-Gap voltage directly to instead of enabling PRESET and CHEN7." "0: Disabled,1: Enabled"
bitfld.long 0x4 12. "CHEN11,Analog Input Channel 11 Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x4 11. "CHEN10,Analog Input Channel 10 Enable" "0: Disabled,1: Enabled"
bitfld.long 0x4 10. "CHEN9,Analog Input Channel 9 Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x4 9. "CHEN8,Analog Input Channel 8 Enable" "0: Disabled,1: Enabled"
bitfld.long 0x4 8. "CH7SEL,Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7 the ADC clock rate needs to be limited to lower than 300 kHz." "0: External analog input,1: Internal band-gap voltage (VBG)"
newline
bitfld.long 0x4 7. "CHEN7,Analog Input Channel 7 Enable" "0: Channel 7 Disabled,1: Channel 7 Enabled"
bitfld.long 0x4 6. "CHEN6,Analog Input Channel 6 Enable" "0: Channel 6 Disabled,1: Channel 6 Enabled"
newline
bitfld.long 0x4 5. "CHEN5,Analog Input Channel 5 Enable" "0: Channel 5 Disabled,1: Channel 5 Enabled"
bitfld.long 0x4 4. "CHEN4,Analog Input Channel 4 Enable" "0: Channel 4 Disabled,1: Channel 4 Enabled"
newline
bitfld.long 0x4 3. "CHEN3,Analog Input Channel 3 Enable" "0: Channel 3 Disabled,1: Channel 3 Enabled"
bitfld.long 0x4 2. "CHEN2,Analog Input Channel 2 Enable" "0: Channel 2 Disabled,1: Channel 2 Enabled"
newline
bitfld.long 0x4 1. "CHEN1,Analog Input Channel 1 Enable" "0: Channel 1 Disabled,1: Channel 1 Enabled"
bitfld.long 0x4 0. "CHEN0,Analog Input Channel 0 Enable\nNote: If software enables more than one channel the channel with the smallest number will be selected and the other enabled channels will be ignored." "0: Channel 0 Disabled,1: Channel 0 Enabled"
line.long 0x8 "ADC_CMP0,ADC Compare Register 0"
hexmask.long.word 0x8 16.--25. 1. "CMPDAT,Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel."
hexmask.long.byte 0x8 8.--11. 1. "CMPMCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT +1) the ADCMPFx.."
newline
hexmask.long.byte 0x8 3.--6. 1. "CMPCH,Compare Channel Selection"
bitfld.long 0x8 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMCNT +1) the ADCMPFx bit will be set." "0: Set the compare condition as that when a 10-bit..,1: Set the compare condition as that when a 10-bit.."
newline
bitfld.long 0x8 1. "ADCMPIE,Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT ADCMPFx bit will be asserted in the meanwhile if CMPCOND is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
bitfld.long 0x8 0. "ADCMPEN,Compare Enable\nSet 1 to this bit to enable comparing CMPDAT[9:0] with specified channel conversion results when converted data is loaded into the ADC_DAT register." "0: Compare function Disabled,1: Compare function Enabled"
line.long 0xC "ADC_CMP1,ADC Compare Register 1"
hexmask.long.word 0xC 16.--25. 1. "CMPDAT,Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel."
hexmask.long.byte 0xC 8.--11. 1. "CMPMCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT +1) the ADCMPFx.."
newline
hexmask.long.byte 0xC 3.--6. 1. "CMPCH,Compare Channel Selection"
bitfld.long 0xC 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMCNT +1) the ADCMPFx bit will be set." "0: Set the compare condition as that when a 10-bit..,1: Set the compare condition as that when a 10-bit.."
newline
bitfld.long 0xC 1. "ADCMPIE,Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT ADCMPFx bit will be asserted in the meanwhile if CMPCOND is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
bitfld.long 0xC 0. "ADCMPEN,Compare Enable\nSet 1 to this bit to enable comparing CMPDAT[9:0] with specified channel conversion results when converted data is loaded into the ADC_DAT register." "0: Compare function Disabled,1: Compare function Enabled"
line.long 0x10 "ADC_STATUS,ADC Status Register"
rbitfld.long 0x10 16. "OV,OV Flag (Read Only)\nIt is a mirror to OV bit in ADC_DAT register." "0,1"
rbitfld.long 0x10 8. "VALID,Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in ADC_DAT register." "0,1"
newline
rbitfld.long 0x10 4.--6. "CHANNEL,Current Conversion Channel (Read Only)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x10 3. "BUSY,BUSY/IDLE (Read Only)\nThis bit is mirror of as SWTRG bit in ADC_CTL" "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
newline
bitfld.long 0x10 2. "ADCMPF1,Compare Flag 1\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP1 this bit is set to 1. Software can write 1 to clear this bit to zero." "0: Conversion result in ADC_DAT does not meet the..,1: Conversion result in ADC_DAT meets the ADC_CMP1.."
bitfld.long 0x10 1. "ADCMPF0,Compare Flag 0\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP0 this bit is set to 1. Software can write 1 to clear this bit to zero." "0: Conversion result in ADC_DAT does not meet the..,1: Conversion result in ADC_DAT meets the ADC_CMP0.."
newline
bitfld.long 0x10 0. "ADIF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. ADIF is set to 1 When A/D conversion ends.\nSoftware can write 1 to clear this bit to zero." "0,1"
group.long 0x44++0xB
line.long 0x0 "ADC_TRGDLY,ADC Trigger Delay Control Register"
hexmask.long.byte 0x0 0.--7. 1. "DELAY,PWM Trigger Delay Timer\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * DELAY) * system clock."
line.long 0x4 "ADC_EXTSMPT,ADC Sampling Time Counter Register"
hexmask.long.byte 0x4 0.--3. 1. "EXTSMPT,ADC Sampling Counter\nADC sampling counters are 6 ADC clock is suggestion."
line.long 0x8 "ADC_SEQCTL,ADC PWM Sequential Mode Control Register"
bitfld.long 0x8 18.--19. "TRG2SRC,ADC Sequential Mode Trigger2 Source" "0: PWM0,1: PWM2,?,?"
bitfld.long 0x8 16.--17. "TRG2TYPE,ADC Sequential Mode Trigger2 Type" "0: Rising of the selected PWM,1: Center of the selected PWM,?,?"
newline
bitfld.long 0x8 10.--11. "TRG1SRC,ADC Sequential Mode Trigger1 Source" "0: PWM0,1: PWM2,?,?"
bitfld.long 0x8 8.--9. "TRG1TYPE,ADC Sequential Mode Trigger1 Type" "0: Rising of the selected PWM,1: Center of the selected PWM,?,?"
newline
bitfld.long 0x8 2.--3. "MODESEL,ADC Sequential Mode Selection" "0: Issue ADC_INT after Channel 0 then Channel 1..,1: Issue ADC_INT after Channel 1 then Channel 2..,?,?"
bitfld.long 0x8 1. "SEQTYPE,ADC Sequential Mode Type" "0: ADC delay time is only inserted before the first..,1: ADC delay time is inserted before each.."
newline
bitfld.long 0x8 0. "SEQEN,ADC Sequential Mode Enable\nWhen ADC sequential mode is enabled two of three ADC channels from 0 to 2 will automatically convert analog data in the sequence of channel [0 1] or channel[1 2] or channel[0 2] defined by SEQ_MODE[1:0]." "0: ADC sequential mode Disabled,1: ADC sequential mode Enabled"
rgroup.long 0x50++0x7
line.long 0x0 "ADC_SEQDAT0,ADC PWM Sequential Mode Result Register 0"
bitfld.long 0x0 17. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read." "0: Data in RESULT [9:0] bits not valid,1: Data in RESULT. ADC_TRGDLY [9:0] bits valid"
bitfld.long 0x0 16. "OV,Over Run Flag\nIf converted data in RESULT [9:0] has not been read before the new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after the ADC_DAT register is read." "0: Data in RESULT [9:0] is recent conversion result,1: Data in RESULT [9:0] overwritten"
newline
hexmask.long.word 0x0 0.--9. 1. "RESULT,A/D PWM Sequential Mode Conversion Result\nThis field contains conversion result of ADC."
line.long 0x4 "ADC_SEQDAT1,ADC PWM Sequential Mode Result Register 1"
bitfld.long 0x4 17. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read." "0: Data in RESULT [9:0] bits not valid,1: Data in RESULT. ADC_TRGDLY [9:0] bits valid"
bitfld.long 0x4 16. "OV,Over Run Flag\nIf converted data in RESULT [9:0] has not been read before the new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after the ADC_DAT register is read." "0: Data in RESULT [9:0] is recent conversion result,1: Data in RESULT [9:0] overwritten"
newline
hexmask.long.word 0x4 0.--9. 1. "RESULT,A/D PWM Sequential Mode Conversion Result\nThis field contains conversion result of ADC."
endif
sif (cpuis("MINI5??DE"))
rgroup.long 0x0++0x3
line.long 0x0 "ADDR,ADC Data Register"
bitfld.long 0x0 17. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADDR register is read." "0: Data in RSLT (ADDR[9:0]) bits not valid,1: Data in RSLT (ADDR[9:0]) bits valid"
bitfld.long 0x0 16. "OVERRUN,Over Run Flag\nIf converted data in RSLT[9:0] has not been read before the new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after the ADDR register is read." "0: Data in RSLT (ADDR[9:0])is recent conversion..,1: Data in RSLT (ADDR[9:0])overwrote"
newline
hexmask.long.word 0x0 0.--9. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC."
group.long 0x20++0x13
line.long 0x0 "ADCR,ADC Control Register"
bitfld.long 0x0 11. "ADST,A/D Conversion Start\nADST bit can be set to 1 from three sources: software or PWM trigger and external pin STADC. ADST will be cleared to 0 by hardware automatically after conversion complete.\n" "0: Conversion stopped and A/D converter entered..,1: Conversion start"
bitfld.long 0x0 8. "TRGEN,External Trigger Enable Control\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled the ADST bit can be set to 1 by the selected hardware trigger source.\n" "0: External trigger Disabled,1: External trigger Enabled"
newline
bitfld.long 0x0 6. "TRGCOND,External Trigger Condition\nThis bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger.\n" "0: Falling edge,1: Raising edge"
bitfld.long 0x0 4.--5. "TRGS,Hardware Trigger Source\nNote: Software should disable TRGEN and ADST before change TRGS." "0: A/D conversion is started by external STADC pin,?,?,?"
newline
bitfld.long 0x0 1. "ADIE,A/D Interrupt Enable Control\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.\n" "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled"
bitfld.long 0x0 0. "ADEN,A/D Converter Enable Control\nNote: Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption." "0: A/D Converter Disabled,1: A/D Converter Enabled"
line.long 0x4 "ADCHER,ADC Channel Enable Control Register"
bitfld.long 0x4 8. "PRESEL,Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7 the ADC clock rate needs to be limited to lower than 300 kHz." "0: External analog input,1: Internal band-gap voltage (VBG)"
bitfld.long 0x4 7. "CHEN7,Analog Input Channel 7 Enable Control\n" "0: Channel 7 Disabled,1: Channel 7 Enabled"
newline
bitfld.long 0x4 6. "CHEN6,Analog Input Channel 6 Enable Control\n" "0: Channel 6 Disabled,1: Channel 6 Enabled"
bitfld.long 0x4 5. "CHEN5,Analog Input Channel 5 Enable Control\n" "0: Channel 5 Disabled,1: Channel 5 Enabled"
newline
bitfld.long 0x4 4. "CHEN4,Analog Input Channel 4 Enable Control\n" "0: Channel 4 Disabled,1: Channel 4 Enabled"
bitfld.long 0x4 3. "CHEN3,Analog Input Channel 3 Enable Control\n" "0: Channel 3 Disabled,1: Channel 3 Enabled"
newline
bitfld.long 0x4 2. "CHEN2,Analog Input Channel 2 Enable Control\n" "0: Channel 2 Disabled,1: Channel 2 Enabled"
bitfld.long 0x4 1. "CHEN1,Analog Input Channel 1 Enable Control\n" "0: Channel 1 Disabled,1: Channel 1 Enabled"
newline
bitfld.long 0x4 0. "CHEN0,Analog Input Channel 0 Enable Control\nNote: If software enables more than one channel the channel with the smallest number will be selected and the other enabled channels will be ignored." "0: Channel 0 Disabled,1: Channel 0 Enabled"
line.long 0x8 "ADCMPR0,ADC Compare Register 0"
hexmask.long.word 0x8 16.--25. 1. "CMPD,Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel."
hexmask.long.byte 0x8 8.--11. 1. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the CMPFx.."
newline
bitfld.long 0x8 3.--5. "CMPCH,Compare Channel Selection\n" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,?,?,?,?,?,?"
bitfld.long 0x8 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 10-bit..,1: Set the compare condition as that when a 10-bit.."
newline
bitfld.long 0x8 1. "CMPIE,Compare Interrupt Enable Control\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is.." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
bitfld.long 0x8 0. "CMPEN,Compare Enable Control\nSet 1 to this bit to enable comparing CMPD[9:0] with specified channel conversion results when converted data is loaded into the ADDR register.\n" "0: Compare function Disabled,1: Compare function Enabled"
line.long 0xC "ADCMPR1,ADC Compare Register 1"
hexmask.long.word 0xC 16.--25. 1. "CMPD,Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel."
hexmask.long.byte 0xC 8.--11. 1. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the CMPFx.."
newline
bitfld.long 0xC 3.--5. "CMPCH,Compare Channel Selection\n" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,?,?,?,?,?,?"
bitfld.long 0xC 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 10-bit..,1: Set the compare condition as that when a 10-bit.."
newline
bitfld.long 0xC 1. "CMPIE,Compare Interrupt Enable Control\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is.." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
bitfld.long 0xC 0. "CMPEN,Compare Enable Control\nSet 1 to this bit to enable comparing CMPD[9:0] with specified channel conversion results when converted data is loaded into the ADDR register.\n" "0: Compare function Disabled,1: Compare function Enabled"
line.long 0x10 "ADSR,ADC Status Register"
rbitfld.long 0x10 16. "OVERRUN,Overrun Flag (Read Only)\nIt is a mirror to OVERRUN (ADSR[16]) bit in ADDR register." "0,1"
rbitfld.long 0x10 8. "VALID,Data Valid Flag (Read Only)\nIt is a mirror of VALID (ADDR[17]) bit in ADDR register." "0,1"
newline
rbitfld.long 0x10 4.--6. "CHANNEL,Current Conversion Channel (Read Only)\n" "0,1,2,3,4,5,6,7"
rbitfld.long 0x10 3. "BUSY,BUSY/IDLE (Read Only)\nThis bit is mirror of as ADST bit in ADCR\n" "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
newline
bitfld.long 0x10 2. "CMPF1,Compare Flag 1\nWhen the selected channel A/D conversion result meets the setting condition in ADCMPR1 this bit is set to 1. Software can write 1 to clear this bit to 0.\n" "0: Conversion result in ADDR does not meet the..,1: Conversion result in ADDR meets the ADCMPR1.."
bitfld.long 0x10 1. "CMPF0,Compare Flag 0\nWhen the selected channel A/D conversion result meets the setting condition in ADCMPR0 this bit is set to 1. Software can write 1 to clear this bit to 0.\n" "0: Conversion result in ADDR does not meet the..,1: Conversion result in ADDR meets the ADCMPR0.."
newline
bitfld.long 0x10 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. ADF is set to 1 When A/D conversion ends.\nSoftware can write 1 to clear this bit to 0." "0,1"
group.long 0x44++0x7
line.long 0x0 "ADTDCR,ADC Trigger Delay Control Register"
hexmask.long.byte 0x0 0.--7. 1. "PTDT,PWM Trigger Delay Timer\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * PTDT) * system clock."
line.long 0x4 "ADSAMP,ADC Sampling Time Counter Register"
hexmask.long.byte 0x4 0.--3. 1. "ADSAMPCNT,ADC Sampling Counter\nIf the ADC input is unstable user can set this register to increase the sampling time to get a stable ADC input signal. The default sampling time is 1 ADC clock. The additional clock number will be inserted to lengthen.."
endif
sif (cpuis("MINI5?AN"))
rgroup.long 0x0++0x3
line.long 0x0 "ADDR,A/D Data Register"
bitfld.long 0x0 17. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADDR register is read." "0: Data in RSLT[9:0] bits not valid,1: Data in RSLT[9:0] bits valid"
bitfld.long 0x0 16. "OVERRUN,Over Run Flag\nIf converted data in RSLT[9:0] has not been read before the new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after the ADDR register is read." "0: Data in RSLT[9:0] is recent conversion result,1: Data in RSLT[9:0] overwritten"
newline
hexmask.long.word 0x0 0.--9. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC."
group.long 0x20++0x13
line.long 0x0 "ADCR,A/D Control Register"
bitfld.long 0x0 11. "ADST,A/D Conversion Start\nADST bit can be set to 1 from two sources: software and external pin STADC. ADST will be cleared to 0 by hardware automatically." "0: Conversion stopped and A/D converter entered..,1: Conversion start"
bitfld.long 0x0 8. "TRGEN,External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 6. "TRGCOND,External Trigger Condition\nThis bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger.\n" "0: Falling edge,1: Raising edge"
bitfld.long 0x0 4.--5. "TRGS,Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS.\nIn hardware trigger mode the ADST bit is set by the external trigger from STADC." "0: A/D conversion is started by external STADC pin,?,?,?"
newline
bitfld.long 0x0 1. "ADIE,A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1." "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled"
bitfld.long 0x0 0. "ADEN,A/D Converter Enable\nBefore starting the A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption." "0: Disabled,1: Enabled"
line.long 0x4 "ADCHER,A/D Channel Enable Register"
bitfld.long 0x4 8. "PRESEL,Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7 the ADC clock rate needs to be limited to lower than 300 kHz." "0: Analog Input Channel 7,1: Band-gap (VBG) Analog Input"
bitfld.long 0x4 7. "CHEN7,Analog Input Channel 7 Enable\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x4 6. "CHEN6,Analog Input Channel 6 Enable\n" "0: Disabled,1: Enabled"
bitfld.long 0x4 5. "CHEN5,Analog Input Channel 5 Enable\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x4 4. "CHEN4,Analog Input Channel 4 Enable\n" "0: Disabled,1: Enabled"
bitfld.long 0x4 3. "CHEN3,Analog Input Channel 3 Enable\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x4 2. "CHEN2,Analog Input Channel 2 Enable\n" "0: Disabled,1: Enabled"
bitfld.long 0x4 1. "CHEN1,Analog Input Channel 1 Enable\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x4 0. "CHEN0,Analog Input Channel 0 Enable\nNote: If software enables more than one channel the channel with the lowest number will be selected and the other enabled channels will be ignored. That means channel 0 is the highest priority." "0: Disabled,1: Enabled"
line.long 0x8 "ADCMPR0,A/D Compare Register 0"
hexmask.long.word 0x8 16.--25. 1. "CMPD,Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel."
hexmask.long.byte 0x8 8.--11. 1. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the.."
newline
bitfld.long 0x8 3.--5. "CMPCH,Compare Channel Selection\n" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 10-bit..,1: Set the compare condition as that when a 10-bit.."
newline
bitfld.long 0x8 1. "CMPIE,Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
bitfld.long 0x8 0. "CMPEN,Compare Enable\nSet 1 to this bit to enable comparing CMPD[9:0] with specified channel conversion results when converted data is loaded into the ADDR register." "0: Compare function Disabled,1: Compare function Enabled"
line.long 0xC "ADCMPR1,A/D Compare Register 1"
hexmask.long.word 0xC 16.--25. 1. "CMPD,Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel."
hexmask.long.byte 0xC 8.--11. 1. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the.."
newline
bitfld.long 0xC 3.--5. "CMPCH,Compare Channel Selection\n" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 10-bit..,1: Set the compare condition as that when a 10-bit.."
newline
bitfld.long 0xC 1. "CMPIE,Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
bitfld.long 0xC 0. "CMPEN,Compare Enable\nSet 1 to this bit to enable comparing CMPD[9:0] with specified channel conversion results when converted data is loaded into the ADDR register." "0: Compare function Disabled,1: Compare function Enabled"
line.long 0x10 "ADSR,A/D Status Register"
bitfld.long 0x10 16. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADDR." "0,1"
bitfld.long 0x10 8. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADDR." "0,1"
newline
bitfld.long 0x10 4.--6. "CHANNEL,Current Conversion Channel\nIt is read only." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 3. "BUSY,BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only." "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
newline
bitfld.long 0x10 2. "CMPF1,Compare Flag #1\nWhen the selected channel A/D conversion result meets the setting condition in ADCMPR1 this bit is set to 1. Software can write 1 to clear this bit to zero.\n" "0: Conversion result in ADDR does not meet the..,1: Conversion result in ADDR meets the ADCMPR1.."
bitfld.long 0x10 1. "CMPF0,Compare Flag #0\nWhen the selected channel A/D conversion result meets the setting condition in ADCMPR0 this bit is set to 1. Software can write 1 to clear this bit to zero.\n" "0: Conversion result in ADDR does not meet the..,1: Conversion result in ADDR meets the ADCMPR0.."
newline
bitfld.long 0x10 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 When A/D conversion ends.\nSoftware can write 1 to clear this bit to zero." "0,1"
group.long 0x44++0x3
line.long 0x0 "ADTDCR,A/D Trigger Delay Control Register"
hexmask.long.byte 0x0 0.--7. 1. "PTDT,PWM Trigger Delay Timer\nSet this field will delay ADC start conversion time after PWM trigger is coming.\nPWM trigger delay time is (4 * PTDT) * system clock"
endif
tree.end
tree "CLK (Clock Controller)"
base ad:0x50000200
sif (cpuis("MINI5?XAE"))
group.long 0x0++0x1F
line.long 0x0 "CLK_PWRCTL,System Power-down Control Register"
bitfld.long 0x0 10.--11. "HXTGAIN,HXT Gain Selection" "0: Full gain for the frequency up to 24MHz,1: 3/4 gain for the frequency up to 16MHz,?,?"
bitfld.long 0x0 9. "PDLXT,Enable LXT In Power-Down Mode\nThis bit controls the crystal oscillator active or not in Power-down mode." "0: No effect to Power-down mode,1: If XTLEN[1:0] = 10 LXT is still active in.."
newline
bitfld.long 0x0 7. "PDEN,System Power-Down Enable Bit (Write Protect)\nWhen chip wakes up from Power-down mode this bit is cleared by hardware. User needs to set this bit again for next Power-down.\nIn Power-down mode 4~24 MHz external high speed crystal oscillator (HXT) .." "0: Chip operating normally or chip in Idle mode..,1: Chip enters Power-down mode instantly or waits.."
bitfld.long 0x0 6. "PDWKIF,Power-Down Mode Wake-Up Interrupt Status\nSet by 'Power-down wake-up event' which indicates that resume from Power-down mode'\nThe flag is set if the GPIO UART WDT ACMP Timer or BOD wake-up occurred.\nNote: This bit works only if PDWKIEN.." "0,1"
newline
bitfld.long 0x0 5. "PDWKIEN,Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect)\nNote: The interrupt will occur when both PDWKIF and PDWKIEN are high." "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "PDWKDLY,Wake-Up Delay Counter Enable Control (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at 4~24.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
newline
bitfld.long 0x0 3. "LIRCEN,10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protest)" "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).."
bitfld.long 0x0 2. "HIRCEN,44.2368 MHz Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect)\nNote: The default of HIRCEN bit is 1." "0: 44.2368 MHz internal high speed RC oscillator..,1: 44.2368 MHz internal high speed RC oscillator.."
newline
bitfld.long 0x0 0.--1. "XTLEN,External HXT Or LXT Crystal Oscillator Enable Control (Write Protect)\nThe default clock source is from HIRC. These two bits are default set to '00' and the XTAL1 and XTAL2 pins are GPIO.\nNote: To enable external XTAL function P5_ALT[1:0] and.." "0: XTAL1 and XTAL2 are GPIO disable both LXT HXT..,1: HXT Enabled,?,?"
line.long 0x4 "CLK_AHBCLK,AHB Devices Clock Enable Control Register"
bitfld.long 0x4 4. "HDIVEN,Divider Clock Enable Control" "0: Divider clock Disabled,1: Divider clock Enabled"
bitfld.long 0x4 2. "ISPCKEN,Flash ISP Controller Clock Enable Control" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
line.long 0x8 "CLK_APBCLK,APB Devices Clock Enable Control Register"
bitfld.long 0x8 30. "ACMPCKEN,Analog Comparator Clock Enable Control" "0: Analog Comparator clock Disabled,1: Analog Comparator clock Enabled"
bitfld.long 0x8 28. "ADCCKEN,Analog-Digital-Converter (ADC) Clock Enable Control" "0: ADC peripheral clock Disabled,1: ADC peripheral clock Enabled"
newline
bitfld.long 0x8 22. "PWMCH45CKEN,PWM_45 Clock Enable Control" "0: PWM45 clock Disabled,1: PWM45 clock Enabled"
bitfld.long 0x8 21. "PWMCH23CKEN,PWM_23 Clock Enable Control" "0: PWM23 clock Disabled,1: PWM23 clock Enabled"
newline
bitfld.long 0x8 20. "PWMCH01CKEN,PWM_01 Clock Enable Control" "0: PWM01 clock Disabled,1: PWM01 clock Enabled"
bitfld.long 0x8 17. "UART1CKEN,UART1 Clock Enable Control" "0: UART1 clock Disabled,1: UART1 clock Enabled"
newline
bitfld.long 0x8 16. "UART0CKEN,UART0 Clock Enable Control" "0: UART0 clock Disabled,1: UART0 clock Enabled"
bitfld.long 0x8 12. "SPICKEN,SPI Peripheral Clock Enable Control" "0: SPI peripheral clock Disabled,1: SPI peripheral clock Enabled"
newline
bitfld.long 0x8 8. "I2CCKEN,I2C Clock Enable Control" "0: I2C clock Disabled,1: I2C clock Enabled"
bitfld.long 0x8 6. "CLKOCKEN,Frequency Divider Output Clock Enable Control" "0: FDIV clock Disabled,1: FDIV clock Enabled"
newline
bitfld.long 0x8 3. "TMR1CKEN,Timer1 Clock Enable Control" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
bitfld.long 0x8 2. "TMR0CKEN,Timer0 Clock Enable Control" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
newline
bitfld.long 0x8 0. "WDTCKEN,Watchdog Timer Clock Enable Control (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address.." "0: Watchdog Timer clock Disabled,1: Watchdog Timer clock Enabled"
line.long 0xC "CLK_STATUS,Clock Status Monitor Register"
bitfld.long 0xC 7. "CLKSFAIL,Clock Switch Fail Flag\nNote1: This bit is updated when software switches system clock source. If switch target clock is stable this bit will be set to 0. If switch target clock is not stable this bit will be set to 1.\nNote2: This bit is read.." "0: Clock switching success,1: This bit is updated when software switches.."
rbitfld.long 0xC 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: HIRC clock is not stable or disabled,1: HIRC clock is stable"
newline
rbitfld.long 0xC 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: LIRC clock is not stable or disabled,1: LIRC clock is stable"
bitfld.long 0xC 0. "XTLSTB,HXT Or LXT Clock Source Stable Flag" "0: HXT or LXT clock is not stable or disabled,1: HXT or LXT clock is stable"
line.long 0x10 "CLK_CLKSEL0,Clock Source Select Control Register 0"
bitfld.long 0x10 3.--5. "STCLKSEL,Cortex-M0 SysTick Clock Source Selection From Reference Clock (Write Protect)\nNote3: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Reserved,?,3: To set CLK_PWRCTL[1:0],?,?,?,?"
bitfld.long 0x10 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nNote1: Before clock switching the related clock sources (both pre-select and new-select) must be turn-on and stable.\nNote2: These bits are protected bit and programming them needs to write 0x59 .." "0: Clock source is from HXT or LXT,1: Before clock switching,2: These bits are protected bit,3: To set CLK_PWRCTL[1:0] to select HXT or LXT..,?,?,?,?"
line.long 0x14 "CLK_CLKSEL1,Clock Source Select Control Register 1"
bitfld.long 0x14 26.--27. "UART1SEL,UART1 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source from HXT or LXT crystal clock,1: Reserved,?,?"
bitfld.long 0x14 24.--25. "UART0SEL,UART0 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Reserved,?,?"
newline
bitfld.long 0x14 12.--14. "TMR1SEL,TIMER1 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from LIRC,?,?,?,?,?,?"
bitfld.long 0x14 8.--10. "TMR0SEL,TIMER0 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from LIRC,?,?,?,?,?,?"
newline
bitfld.long 0x14 4. "SPISEL,SPI Clock Source Selection\nNote: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from HCLK"
bitfld.long 0x14 2.--3. "ADCSEL,ADC Peripheral Clock Source Selection\nNote: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Reserved,?,?"
newline
bitfld.long 0x14 0.--1. "WDTSEL,WDT CLK Clock Source Selection (Write Protect)\nNote1: These bits are the protected bit and programming them needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address.." "0: Clock source is from HXT or LXT,1: These bits are the protected bit,2: To set CLK_PWRCTL[1:0],?"
line.long 0x18 "CLK_CLKDIV,Clock Divider Number Register"
hexmask.long.byte 0x18 16.--23. 1. "ADCDIV,ADC Peripheral Clock Divide Number From ADC Peripheral Clock Source"
hexmask.long.byte 0x18 12.--15. 1. "UART1DIV,UART1 Clock Divide Number From UART1 Clock Source"
newline
hexmask.long.byte 0x18 8.--11. 1. "UART0DIV,UART0 Clock Divide Number From UART0 Clock Source"
hexmask.long.byte 0x18 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source"
line.long 0x1C "CLK_CLKSEL2,Clock Source Select Control Register 2"
bitfld.long 0x1C 2.--3. "FDIVSEL,Clock Divider Clock Source Selection\nNote: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Reserved,?,?"
group.long 0x24++0x3
line.long 0x0 "CLK_CLKOCTL,Frequency Divider Control Register"
bitfld.long 0x0 5. "DIV1EN,Frequency Divider 1 Enable Control" "0: Divider output frequency is depended on FSEL value,1: Divider output frequency is the same as input.."
bitfld.long 0x0 4. "CLKOEN,Frequency Divider Enable Control" "0: Frequency Divider Disabled,1: Frequency Divider Enabled"
newline
hexmask.long.byte 0x0 0.--3. 1. "FSEL,Divider Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]."
endif
sif (cpuis("MINI5??DE"))
group.long 0x0++0x1F
line.long 0x0 "PWRCON,System Power-down Control Register"
bitfld.long 0x0 9. "PD_32K,Enable LXT In Power-down Mode\nThis bit controls the crystal oscillator active or not in Power-down mode.\n" "0: No effect to Power-down mode,1: If XTLCLK_EN[1:0] = 10 LXT is still active in.."
bitfld.long 0x0 7. "PWR_DOWN_EN,System Power-down Enable Bit (Write Protect)\nWhen chip wakes up from Power-down mode this bit is cleared by hardware. User needs to set this bit again for next Power-down.\nIn Power-down mode 4~24 MHz external high speed crystal oscillator.." "0: Chip operating normally or chip in Idle mode..,1: Chip enters Power-down mode instantly or waits.."
newline
bitfld.long 0x0 6. "PD_WU_STS,Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' which indicates that resume from Power-down mode'\nThe flag is set if the GPIO UART WDT I2C ACMP Timer or BOD wake-up occurred.\nNote: This bit works only if.." "0,1"
bitfld.long 0x0 5. "PD_WU_INT_EN,Power-down Mode Wake-up Interrupt Enable Control (Write Protect)\nNote: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 4. "PD_WU_DLY,Wake-up Delay Counter Enable Control (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
bitfld.long 0x0 3. "OSC10K_EN,10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protect)\n" "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).."
newline
bitfld.long 0x0 2. "OSC22M_EN,22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect)\nNote: The default of OSC22M_EN bit is 1." "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.."
bitfld.long 0x0 0.--1. "XTLCLK_EN,External Crystal HXT Or LXT Enable Control (Write Protect)\nThe default clock source is from HIRC. These two bits are default set to '00' and the XTAL1 and XTAL2 pins are GPIO.\nNote: To enable the external XTAL function the P5_ALT[1:0] and.." "0: XTAL1 and XTAL2 are GPIO disable both LXT HXT..,1: HXT Enabled,?,?"
line.long 0x4 "AHBCLK,AHB Devices Clock Enable Control Register"
bitfld.long 0x4 2. "ISP_EN,Flash ISP Controller Clock Enable Control\n" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
line.long 0x8 "APBCLK,APB Devices Clock Enable Control Register"
bitfld.long 0x8 30. "ACMP_EN,Analog Comparator Clock Enable Control\n" "0: Analog Comparator clock Disabled,1: Analog Comparator clock Enabled"
bitfld.long 0x8 28. "ADC_EN,Analog-digital-converter (ADC) Clock Enable Control\n" "0: ADC peripheral clock Disabled,1: ADC peripheral clock Enabled"
newline
bitfld.long 0x8 22. "PWM45_EN,PWM_45 Clock Enable Control\n" "0: PWM45 clock Disabled,1: PWM45 clock Enabled"
bitfld.long 0x8 21. "PWM23_EN,PWM_23 Clock Enable Control\n" "0: PWM23 clock Disabled,1: PWM23 clock Enabled"
newline
bitfld.long 0x8 20. "PWM01_EN,PWM_01 Clock Enable Control\n" "0: PWM01 clock Disabled,1: PWM01 clock Enabled"
bitfld.long 0x8 16. "UART_EN,UART Clock Enable Control\n" "0: UART clock Disabled,1: UART clock Enabled"
newline
bitfld.long 0x8 12. "SPI_EN,SPI Peripheral Clock Enable Control\n" "0: SPI peripheral clock Disabled,1: SPI peripheral clock Enabled"
bitfld.long 0x8 8. "I2C_EN,I2C Clock Enable Control\n" "0: I2C clock Disabled,1: I2C clock Enabled"
newline
bitfld.long 0x8 6. "FDIV_EN,Frequency Divider Output Clock Enable Control\n" "0: FDIV clock Disabled,1: FDIV clock Enabled"
bitfld.long 0x8 3. "TMR1_EN,Timer1 Clock Enable Control\n" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
newline
bitfld.long 0x8 2. "TMR0_EN,Timer0 Clock Enable Control\n" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
bitfld.long 0x8 0. "WDT_EN,Watchdog Timer Clock Enable Control (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address.." "0: Watchdog Timer clock Disabled,1: Watchdog Timer clock Enabled"
line.long 0xC "CLKSTATUS,Clock Status Monitor Register"
bitfld.long 0xC 7. "CLK_SW_FAIL,Clock Switch Fail Flag\nNote1: This bit is updated when software switches system clock source. If switch target clock is stable this bit will be set to 0. If switch target clock is not stable this bit will be set to 1.\nNote2: This bit is.." "0: Clock switching success,1: This bit is updated when software switches.."
rbitfld.long 0xC 4. "OSC22M_STB,HIRC Clock Source Stable Flag (Read Only)\n" "0: HIRC clock is not stable or disabled,1: HIRC clock is stable"
newline
rbitfld.long 0xC 3. "OSC10K_STB,LIRC Clock Source Stable Flag (Read Only)\n" "0: LIRC clock is not stable or disabled,1: LIRC clock is stable"
bitfld.long 0xC 0. "XTL_STB,HXT Or LXT Clock Source Stable Flag\n" "0: HXT or LXT clock is not stable or disabled,1: HXT or LXT clock is stable"
line.long 0x10 "CLKSEL0,Clock Source Select Control Register 0"
bitfld.long 0x10 3.--5. "STCLK_S,Cortex-M0 SysTick Clock Source Selection From Reference Clock (Write Protect)\nNote3: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Reserved,?,3: To set PWRCON[1:0],?,?,?,?"
bitfld.long 0x10 0.--2. "HCLK_S,HCLK Clock Source Selection (Write Protect)\nNote1: Before clock switching the related clock sources (both pre-select and new-select) must be turn-on and stable.\nNote2: These bits are protected bit and programming them needs to write 0x59 .." "0: Clock source is from HXT or LXT,1: Before clock switching,2: These bits are protected bit,3: To set PWRCON[1:0],?,?,?,?"
line.long 0x14 "CLKSEL1,Clock Source Select Control Register 1"
bitfld.long 0x14 24.--25. "UART_S,UART Clock Source Selection\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Reserved,?,?"
bitfld.long 0x14 12.--14. "TMR1_S,TIMER1 Clock Source Selection\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from LIRC,?,?,?,?,?,?"
newline
bitfld.long 0x14 8.--10. "TMR0_S,TIMER0 Clock Source Selection\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from LIRC,?,?,?,?,?,?"
bitfld.long 0x14 4. "SPI_S,SPI Clock Source Selection\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from HCLK"
newline
bitfld.long 0x14 2.--3. "ADC_S,ADC Peripheral Clock Source Selection\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Reserved,?,?"
bitfld.long 0x14 0.--1. "WDT_S,WDT CLK Clock Source Selection (Write Protect)\nNote1: These bits are the protected bit and programming them needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address.." "0: Clock source is from HXT or LXT,1: These bits are the protected bit,2: To set PWRCON[1:0],?"
line.long 0x18 "CLKDIV,Clock Divider Number Register"
hexmask.long.byte 0x18 16.--23. 1. "ADC_N,ADC Peripheral Clock Divide Number From ADC Peripheral Clock Source\n"
hexmask.long.byte 0x18 8.--11. 1. "UART_N,UART Clock Divide Number From UART Clock Source\n"
newline
hexmask.long.byte 0x18 0.--3. 1. "HCLK_N,HCLK Clock Divide Number From HCLK Clock Source\n"
line.long 0x1C "CLKSEL2,Clock Source Select Control Register 2"
bitfld.long 0x1C 2.--3. "FRQDIV_S,Clock Divider Clock Source Selection\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Reserved,?,?"
group.long 0x24++0x3
line.long 0x0 "FRQDIV,Frequency Divider Control Register"
bitfld.long 0x0 5. "DIVIDER1,Frequency Divider 1 Enable Control\n" "0: Divider output frequency is depended on FSEL value,1: Divider output frequency is the same as input.."
bitfld.long 0x0 4. "DIVIDER_EN,Frequency Divider Enable Control\n" "0: Frequency Divider Disabled,1: Frequency Divider Enabled"
newline
hexmask.long.byte 0x0 0.--3. 1. "FSEL,Divider Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]."
endif
sif (cpuis("MINI5?AN"))
group.long 0x0++0x1F
line.long 0x0 "PWRCON,System Power-down Control Register"
bitfld.long 0x0 9. "PD_32K,This bit controls the crystal oscillator active or not in Power-down mode.\n" "0: No effect to Power-down mode,1: If XTLCLK_EN[1:0] = 10 LXT is still active in.."
bitfld.long 0x0 7. "PWR_DOWN_EN,System Power-down Active or Enable Bit\nWhen chip waked up from power-down this bit is automatically cleared and user needs to set this bit again for the next power-down.\nIn Power-down mode the LDO external crystal and the HIRC will be.." "0: Chip operated in Normal mode or CPU enters into..,1: Chip entering the Power-down mode instantly or.."
newline
bitfld.long 0x0 6. "PD_WU_STS,Power-down Mode Wake-up Interrupt Status\nWhen set by 'power-down wake-up event' it indicates that resume from Power-down mode.\nThe flag is set if the GPIO UART WDT ACMP Timer or BOD wake-up occurred.\nSoftware can write 1 to clear the.." "0,1"
bitfld.long 0x0 5. "PD_WU_INT_EN,Power-down Mode Wake-up Interrupt Enable (Write-protected)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high." "0: Disabled,1: Enabled. The interrupt will occur when.."
newline
bitfld.long 0x0 4. "WU_DLY,Wake-up Delay Counter Enable (Write-protected)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at HXT 4096.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
bitfld.long 0x0 3. "OSC10K_EN,LIRC Control\n" "0: LIRC oscillator Disabled,1: LIRC oscillator Enabled"
newline
bitfld.long 0x0 2. "OSC22M_EN,HIRC Control\nNote: The default of OSC22M_EN bit is 1." "0: HIRC oscillator Disabled,1: HIRC oscillator Enabled"
bitfld.long 0x0 0.--1. "XTLCLK_EN,External HXT or LXT Crystal Oscillator Control\nThe default clock source is from HIRC. These two bits are default set to '00' and the XTAL1 and XTAL2 pins are GPIO.\nNote: To enable external XTAL function P5_ALT[1:0] and P5_MFP[1:0] bits must.." "0: XTAL1 and XTAL2 are GPIO disable both LXT HXT..,1: HXT Enabled,?,?"
line.long 0x4 "AHBCLK,AHB Device Clock Enable Control Register"
bitfld.long 0x4 2. "ISP_EN,Flash ISP Controller Clock Enable Control\n" "0: Flash ISP engine clock Disabled,1: Flash ISP engine clock Enabled"
line.long 0x8 "APBCLK,APB Device Clock Enable Control Register"
bitfld.long 0x8 30. "CMP_EN,Comparator Clock Enable\n" "0: Analog Comparator Clock Disabled,1: Analog Comparator Clock Enabled"
bitfld.long 0x8 28. "ADC_EN,Analog-Digital-Converter (ADC) Clock Enable Control\n" "0: Both the ADC's APB and the engine clock Disabled,1: Both the ADC's APB and the engine clock Enabled"
newline
bitfld.long 0x8 22. "PWM45_EN,PWM_45 Clock Enable Control\n" "0: Both the PWM45 APB and the engine clock Disabled,1: Both the PWM45 APB and the engine clock Enabled"
bitfld.long 0x8 21. "PWM23_EN,PWM_23 Clock Enable Control\n" "0: Both the PWM23 APB and the engine clock Disabled,1: Both the PWM23 APB and the engine clock Enabled"
newline
bitfld.long 0x8 20. "PWM01_EN,PWM_01 Clock Enable Control\n" "0: Both the PWM01 APB and the engine clock Disabled,1: Both the PWM01 APB and the engine clock Enabled"
bitfld.long 0x8 16. "UART_EN,UART Clock Enable Control\n" "0: Both the UART APB and the engine clock Disabled,1: Both the UART APB and the engine clock Enabled"
newline
bitfld.long 0x8 12. "SPI_EN,SPI Clock Enable Control\n" "0: Disabled,1: Enabled"
bitfld.long 0x8 8. "I2C_EN,I2C Clock Enable Control\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x8 6. "FDIV_EN,Clock Divider Clock Enable Control\n" "0: Disabled,1: Enabled"
bitfld.long 0x8 3. "TMR1_EN,Timer1 Clock Enable Control\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x8 2. "TMR0_EN,Timer0 Clock Enable Control\n" "0: Disabled,1: Enabled"
bitfld.long 0x8 0. "WDT_EN,Watchdog Clock Enable\nThis bit is the protected bit; programming this needs an open lock sequence write 0x59 0x16 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100.\n" "0: Disabled,1: Enabled"
line.long 0xC "CLKSTATUS,Clock Status Monitor Register"
bitfld.long 0xC 7. "CLK_SW_FAIL,Clock Switch Fail Flag\nThis bit will be set when target switch clock source is not stable.\nSoftware can write 1 to clear this bit to zero." "0: Clock switch success,1: Clock switch failed"
bitfld.long 0xC 4. "OSC22M_STB,HIRC Clock Source Stable Flag\n" "0: HIRC clock not stable or not enabled,1: HIRC clock stable"
newline
bitfld.long 0xC 3. "OSC10K_STB,LIRC Clock Source Stable Flag\n" "0: LIRC clock not stable or not enabled,1: LIRC clock stable"
bitfld.long 0xC 0. "XTL_STB,HXT or LXT Clock Source Stable Flag\n" "0: HXT or LXT clock not stable or not enabled,1: HXT or LXT clock stable"
line.long 0x10 "CLKSEL0,Clock Source Select Control Register 0"
bitfld.long 0x10 3.--5. "STCLK_S,Cortex-M0 CPU SysTick Clock Source Selection\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source from HXT or LXT crystal clock,1: Reserved,?,?,?,?,?,?"
bitfld.long 0x10 0.--2. "HCLK_S,HCLK Clock Source Selection\nNote: Before clock switch the related clock sources (pre-select and new-select) must be turned on.\nThese bits are protected bit; programming this needs an open lock sequence write 0x59 0x16 0x88 to address.." "0: Clock source from HXT or LXT crystal clock,1: Reserved,?,?,?,?,?,?"
line.long 0x14 "CLKSEL1,Clock Source Select Control Register 1"
bitfld.long 0x14 30.--31. "PWM23_S,PWM2 and PWM3 Clock Source Selection\nPWM2 and PWM3 use the same Engine clock source. They both have the same pre-scalar.\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Reserved,1: Reserved,?,?"
bitfld.long 0x14 28.--29. "PWM01_S,PWM0 and PWM1 Clock Source Selection\nPWM0 and PWM1 use the same Engine clock source. They both have the same pre-scalar.\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Reserved,1: Reserved,?,?"
newline
bitfld.long 0x14 24.--25. "UART_S,UART Clock Source Selection\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source from HXT or LXT crystal clock,1: Reserved,?,?"
bitfld.long 0x14 12.--14. "TMR1_S,TIMER1 Clock Source Selection\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source from HXT or LXT crystal clock,1: Clock source from LIRC oscillator clock,?,?,?,?,?,?"
newline
bitfld.long 0x14 8.--10. "TMR0_S,TIMER0 Clock Source Selection\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source from HXT or LXT crystal clock,1: Clock source from LIRC oscillator clock,?,?,?,?,?,?"
bitfld.long 0x14 2.--3. "ADC_S,ADC Clock Source Selection\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source from HXT or LXT crystal clock,1: Reserved,?,?"
newline
bitfld.long 0x14 0.--1. "WDT_S,WDT CLK Clock Source Selection\nThese bits are protected bit programming this needs an open lock sequence write 0x59 0x16 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100.\nNote: To.." "0: Clock source from HXT or LXT crystal clock,1: Reserved,?,?"
line.long 0x18 "CLKDIV,Clock Divider Number Register"
hexmask.long.byte 0x18 16.--23. 1. "ADC_N,ADC Clock Divide Number from ADC Clock Source\n"
hexmask.long.byte 0x18 8.--11. 1. "UART_N,UART Clock Divide Number from UART Clock Source\n"
newline
hexmask.long.byte 0x18 0.--3. 1. "HCLK_N,HCLK Clock Divide Number from HCLK Clock Source\n"
line.long 0x1C "CLKSEL2,Clock Source Select Control Register 2"
bitfld.long 0x1C 4.--5. "PWM45_S,PWM4 and PWM5 Clock Source Selection - PWM4 and PWM5 use the same Engine clock source. They both have the same pre-scalar.\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Reserved,1: Reserved,?,?"
bitfld.long 0x1C 2.--3. "FRQDIV_S,Clock Divider Clock Source Selection\nNote: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source from HXT or LXT crystal clock,1: Reserved,?,?"
group.long 0x24++0x3
line.long 0x0 "FRQDIV,Frequency Divider Control Register"
bitfld.long 0x0 4. "DIVIDER_EN,Frequency Divider Enable Bit\n" "0: Frequency Divider Disabled,1: Frequency Divider Enabled"
hexmask.long.byte 0x0 0.--3. 1. "FSEL,Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]."
endif
tree.end
tree "EPWM (Enhanced PWM Generator)"
base ad:0x40040000
sif (cpuis("MINI5?XAE"))
group.long 0x0++0x3B
line.long 0x0 "PWM_CLKPSC,PWM Pre-scale Register"
hexmask.long.byte 0x0 16.--23. 1. "CLKPSC45,Clock Prescaler 4 For PWM Counter 4 And 5\nClock input is divided by (CLKPSC45 + 1) before it is fed to the corresponding PWM counter."
hexmask.long.byte 0x0 8.--15. 1. "CLKPSC23,Clock Prescaler 2 For PWM Counter 2 And 3\nClock input is divided by (CLKPSC23 + 1) before it is fed to the corresponding PWM counter."
newline
hexmask.long.byte 0x0 0.--7. 1. "CLKPSC01,Clock Prescaler 0 For PWM Counter 0 And 1\nClock input is divided by (CLKPSC01 + 1) before it is fed to the corresponding PWM counter."
line.long 0x4 "PWM_CLKDIV,PWM Clock Select Register"
bitfld.long 0x4 20.--22. "CLKDIV5,Timer 5 Clock Source Selection\nSelect clock input for PWM timer." "0: 2 clock input/CLKPSC45/2,1: 4 clock input/CLKPSC45/4,?,?,?,?,?,?"
bitfld.long 0x4 16.--18. "CLKDIV4,Timer 4 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 12.--14. "CLKDIV3,Timer 3 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.)" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 8.--10. "CLKDIV2,Timer 2 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4.--6. "CLKDIV1,Timer 1 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.)" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "CLKDIV0,Timer 0 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.)" "0,1,2,3,4,5,6,7"
line.long 0x8 "PWM_CTL,PWM Control Register"
bitfld.long 0x8 31. "CNTTYPE,PWM Aligned Type Selection Bit" "0: Edge-aligned type,1: Center-aligned type"
bitfld.long 0x8 30. "GROUPEN,Group Bit" "0: The signals timing of all PWM channels are..,1: Unify the signals timing of PWM0 PWM2 and PWM4.."
newline
bitfld.long 0x8 28.--29. "MODE,PWM Operating Mode Selection" "0: Independent mode,1: Complementary mode,?,?"
bitfld.long 0x8 27. "CNTCLR,Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware." "0: Do not clear PWM counter,1: All 16-bit PWM counters cleared to 0x0000"
newline
bitfld.long 0x8 26. "DTCNT45,Dead-Zone 4 Generator Enable/Disable (PWM4 And PWM5 Pair For PWM Group)\nNote: When the dead-zone generator is enabled the pair of PWM4 and PWM5 becomes a complementary pair for PWM group." "0: Disabled,1: Enabled"
bitfld.long 0x8 25. "DTCNT23,Dead-Zone 2 Generator Enable/Disable (PWM2 And PWM3 Pair For PWM Group)\nNote: When the dead-zone generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group." "0: Disabled,1: Enabled"
newline
bitfld.long 0x8 24. "DTCNT01,Dead-Zone 0 Generator Enable/Disable (PWM0 And PWM1 Pair For PWM Group)\nNote: When the dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group." "0: Disabled,1: Enabled"
bitfld.long 0x8 23. "CNTMODE5,PWM-Timer 5 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause PWM_PERIOD5 and PWM_CMPDAT5 cleared." "0: One-shot mode,1: Auto-reload mode"
newline
bitfld.long 0x8 22. "PINV5,PWM-Timer 5 Output Inverter Enabled/Disabled" "0: Inverter Disabled,1: Inverter Enabled"
bitfld.long 0x8 21. "ASYMEN,Asymmetric Mode In Center-Aligned Type" "0: symmetric mode in center-aligned type,1: asymmetric mode in center-aligned type"
newline
bitfld.long 0x8 20. "CNTEN5,PWM-Timer 5 Enable/Disable Start Run" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
bitfld.long 0x8 19. "CNTMODE4,PWM-Timer 4 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause PWM_PERIOD4 and PWM_CMPDAT4 cleared." "0: One-shot mode,1: Auto-reload mode"
newline
bitfld.long 0x8 18. "PINV4,PWM-Timer 4 Output Inverter Enabled/Disabled" "0: Inverter Disabled,1: Inverter Enabled"
bitfld.long 0x8 16. "CNTEN4,PWM-Timer 4 Enable/Disable Start Run" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
newline
bitfld.long 0x8 15. "CNTMODE3,PWM-Timer 3 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause PWM_PERIOD3 and PWM_CMPDAT3 cleared." "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 14. "PINV3,PWM-Timer 3 Output Inverter Enabled/Disabled" "0: Inverter Disabled,1: Inverter Enabled"
newline
bitfld.long 0x8 12. "CNTEN3,PWM-Timer 3 Enable/Disable Start Run" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
bitfld.long 0x8 11. "CNTMODE2,PWM-Timer 2 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause PWM_PERIOD2 and PWM_CMPDAT2 cleared." "0: One-shot mode,1: Auto-reload mode"
newline
bitfld.long 0x8 10. "PINV2,PWM-Timer 2 Output Inverter Enabled/Disabled" "0: Inverter Disabled,1: Inverter Enabled"
bitfld.long 0x8 8. "CNTEN2,PWM-Timer 2 Enable/Disable Start Run" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
newline
bitfld.long 0x8 7. "CNTMODE1,PWM-Timer 1 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause PWM_PERIOD1 and PWM_CMPDAT1 cleared." "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 6. "PINV1,PWM-Timer 1 Output Inverter Enabled/Disabled" "0: Inverter Disabled,1: Inverter Enabled"
newline
bitfld.long 0x8 5. "HCUPDT,Half Cycle Update Enable For Center-Aligned Type" "0: disable half cycle update PERIOD CMP,1: enable half cycle update PERIOD CMP"
bitfld.long 0x8 4. "CNTEN1,PWM-Timer 1 Enable/Disable Start Run" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
newline
bitfld.long 0x8 3. "CNTMODE0,PWM-Timer 0 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause PWM_PERIOD0 and PWM_CMPDAT0 cleared." "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 2. "PINV0,PWM-Timer 0 Output Inverter Enabled/Disabled" "0: Inverter Disabled,1: Inverter Enabled"
newline
bitfld.long 0x8 1. "DBGTRIOFF,PWM Debug Mode Configuration Bit (Available In DEBUG Mode Only)" "0: Safe mode: The timer is frozen and PWM outputs..,1: Normal mode: The timer continues to operate.."
bitfld.long 0x8 0. "CNTEN0,PWM-Timer 0 Enable/Disable Start Run" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
line.long 0xC "PWM_PERIOD0,PWM Counter Register 0"
hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Counter/Timer Loaded Value\nPERIOD determines the PWM period.\nEdge-aligned mode:\nNote: Any write to PERIOD will take effect in next PWM cycle."
line.long 0x10 "PWM_PERIOD1,PWM Counter Register 1"
hexmask.long.word 0x10 0.--15. 1. "PERIOD,PWM Counter/Timer Loaded Value\nPERIOD determines the PWM period.\nEdge-aligned mode:\nNote: Any write to PERIOD will take effect in next PWM cycle."
line.long 0x14 "PWM_PERIOD2,PWM Counter Register 2"
hexmask.long.word 0x14 0.--15. 1. "PERIOD,PWM Counter/Timer Loaded Value\nPERIOD determines the PWM period.\nEdge-aligned mode:\nNote: Any write to PERIOD will take effect in next PWM cycle."
line.long 0x18 "PWM_PERIOD3,PWM Counter Register 3"
hexmask.long.word 0x18 0.--15. 1. "PERIOD,PWM Counter/Timer Loaded Value\nPERIOD determines the PWM period.\nEdge-aligned mode:\nNote: Any write to PERIOD will take effect in next PWM cycle."
line.long 0x1C "PWM_PERIOD4,PWM Counter Register 4"
hexmask.long.word 0x1C 0.--15. 1. "PERIOD,PWM Counter/Timer Loaded Value\nPERIOD determines the PWM period.\nEdge-aligned mode:\nNote: Any write to PERIOD will take effect in next PWM cycle."
line.long 0x20 "PWM_PERIOD5,PWM Counter Register 5"
hexmask.long.word 0x20 0.--15. 1. "PERIOD,PWM Counter/Timer Loaded Value\nPERIOD determines the PWM period.\nEdge-aligned mode:\nNote: Any write to PERIOD will take effect in next PWM cycle."
line.long 0x24 "PWM_CMPDAT0,PWM Comparator Register 0"
hexmask.long.word 0x24 16.--31. 1. "CMPD,PWM Comparator Register For Down Counter In Center-Aligned Asymmetric Mode\nOthers: PWM output is always high"
hexmask.long.word 0x24 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMP will take effect in next PWM cycle."
line.long 0x28 "PWM_CMPDAT1,PWM Comparator Register 1"
hexmask.long.word 0x28 16.--31. 1. "CMPD,PWM Comparator Register For Down Counter In Center-Aligned Asymmetric Mode\nOthers: PWM output is always high"
hexmask.long.word 0x28 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMP will take effect in next PWM cycle."
line.long 0x2C "PWM_CMPDAT2,PWM Comparator Register 2"
hexmask.long.word 0x2C 16.--31. 1. "CMPD,PWM Comparator Register For Down Counter In Center-Aligned Asymmetric Mode\nOthers: PWM output is always high"
hexmask.long.word 0x2C 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMP will take effect in next PWM cycle."
line.long 0x30 "PWM_CMPDAT3,PWM Comparator Register 3"
hexmask.long.word 0x30 16.--31. 1. "CMPD,PWM Comparator Register For Down Counter In Center-Aligned Asymmetric Mode\nOthers: PWM output is always high"
hexmask.long.word 0x30 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMP will take effect in next PWM cycle."
line.long 0x34 "PWM_CMPDAT4,PWM Comparator Register 4"
hexmask.long.word 0x34 16.--31. 1. "CMPD,PWM Comparator Register For Down Counter In Center-Aligned Asymmetric Mode\nOthers: PWM output is always high"
hexmask.long.word 0x34 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMP will take effect in next PWM cycle."
line.long 0x38 "PWM_CMPDAT5,PWM Comparator Register 5"
hexmask.long.word 0x38 16.--31. 1. "CMPD,PWM Comparator Register For Down Counter In Center-Aligned Asymmetric Mode\nOthers: PWM output is always high"
hexmask.long.word 0x38 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMP will take effect in next PWM cycle."
group.long 0x54++0x33
line.long 0x0 "PWM_INTEN,PWM Interrupt Enable Register"
bitfld.long 0x0 29. "CMPUIEN5,PWM Channel 5 Rising Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 28. "CMPUIEN4,PWM Channel 4 Rising Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 27. "CMPUIEN3,PWM Channel 3 Rising Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 26. "CMPUIEN2,PWM Channel 2 Rising Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 25. "CMPUIEN1,PWM Channel 1 Rising Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 24. "CMPUIEN0,PWM Channel 0 Rising Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 23. "PIEN5,PWM Channel 5 Central Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 22. "PIEN4,PWM Channel 4 Central Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 21. "PIEN3,PWM Channel 3 Central Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 20. "PIEN2,PWM Channel 2 Central Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 19. "PIEN1,PWM Channel 1 Central Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 18. "PIEN0,PWM Channel 0 Central Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 17. "PINTTYPE,PWM Period Interrupt Type Selection\nNote: This bit is effective when PWM in central align mode only." "0: ZIFn will be set if PWM counter underflows,1: ZIFn will be set if PWM counter matches PERIODn.."
bitfld.long 0x0 16. "BRKIEN,Enable Fault Brake0 And 1 Interrupt" "0: Disabling flags BRKIF0 and BRKIF1 to trigger PWM..,1: Enabling flags BRKIF0 and BRKIF1 can trigger PWM.."
newline
bitfld.long 0x0 13. "CMPDIEN5,PWM Channel 5 Duty Interrupt Enable" "0: Disabled. Rising for edge aligned mode. Falling..,1: Enabled"
bitfld.long 0x0 12. "CMPDIEN4,PWM Channel 4 Duty Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 11. "CMPDIEN3,PWM Channel 3 Duty Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "CMPDIEN2,PWM Channel 2 Duty Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 9. "CMPDIEN1,PWM Channel 1 Duty Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 8. "CMPDIEN0,PWM Channel 0 Duty Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "ZIEN5,PWM Channel 5 Period Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "ZIEN4,PWM Channel 4 Period Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 3. "ZIEN3,PWM Channel 3 Period Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 2. "ZIEN2,PWM Channel 2 Period Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "ZIEN1,PWM Channel 1 Period Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "ZIEN0,PWM Channel 0 Period Interrupt Enable" "0: Disabled,1: Enabled"
line.long 0x4 "PWM_INTSTS,PWM Interrupt Indication Register"
bitfld.long 0x4 29. "CMPUIF5,PWM Channel 5 Rise Interrupt Flag\nFlag is set by hardware when a channel 5 PWM rise counter reaches \nPWM_CNT0\n5. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 28. "CMPUIF4,PWM Channel 4 Rise Interrupt Flag\nFlag is set by hardware when a channel 4 PWM rise counter reaches PWM_CMPDAT4. Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 27. "CMPUIF3,PWM Channel 3 Rise Interrupt Flag\nFlag is set by hardware when a channel 3 PWM rise counter reaches PWM_CMPDAT3. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 26. "CMPUIF2,PWM Channel 2 Rise Interrupt Flag\nFlag is set by hardware when a channel 2 PWM rise counter reaches PWM_CMPDAT2. Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 25. "CMPUIF1,PWM Channel 1 Rise Interrupt Flag\nFlag is set by hardware when a channel 1 PWM rise counter reaches PWM_CMPDAT1. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 24. "CMPUIF0,PWM Channel 1 Rise Interrupt Flag\nFlag is set by hardware when a channel 0 PWM rise counter reaches PWM_CMPDAT0. Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 23. "PIF5,PWM Channel 5 Center Interrupt Flag\nFlag is set by hardware when a channel 5 PWM rise counter reaches CNT5. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 22. "PIF4,PWM Channel 4 Center Interrupt Flag\nFlag is set by hardware when a channel 4 PWM rise counter reaches CNT4. Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 21. "PIF3,PWM Channel 3 Center Interrupt Flag\nFlag is set by hardware when a channel 3 PWM rise counter reaches CNT3. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 20. "PIF2,PWM Channel 2 Center Interrupt Flag\nFlag is set by hardware when a channel 2 PWM rise counter reaches CNT2. Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 19. "PIF1,PWM Channel 1 Center Interrupt Flag\nFlag is set by hardware when a channel 1 PWM rise counter reaches CNT1. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 18. "PIF0,PWM Channel 0 Center Interrupt Flag\nFlag is set by hardware when a channel 0 PWM rise counter reaches CNT0. Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 17. "BRKIF1,PWM Brake1 Flag\nNote: Software can write 1 to clear this bit." "0: PWM Brake does not recognize a falling signal at..,1: When PWM Brake detects a falling signal at pin.."
bitfld.long 0x4 16. "BRKIF0,PWM Brake0 Flag\nNote: Software can write 1 to clear this bit." "0: PWM Brake does not recognize a falling signal at..,1: When PWM Brake detects a falling signal at pin.."
newline
bitfld.long 0x4 13. "CMPDIF5,PWM Channel 5 Duty Interrupt Flag\nFlag is set by hardware when a channel 5 PWM counter reaches PWM_CMPDAT5 in down-count direction. \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 12. "CMPDIF4,PWM Channel 4 Duty Interrupt Flag\nFlag is set by hardware when a channel 4 PWM counter reaches PWM_CMPDAT4 in down-count direction. \nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 11. "CMPDIF3,PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when a channel 3 PWM counter reaches PWM_CMPDAT3 in down-count direction. \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 10. "CMPDIF2,PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when a channel 2 PWM counter reaches PWM_CMPDAT2 in down-count direction. \nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 9. "CMPDIF1,PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when a channel 1 PWM counter reaches PWM_CMPDAT1 in down-count direction. \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 8. "CMPDIF0,PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when a channel 0 PWM counter reaches PWM_CMPDAT0 in down-count direction. \nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 5. "ZIF5,PWM Channel 5 Period Interrupt Flag\nFlag is set by hardware when PWM5 down counter reaches zero. \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 4. "ZIF4,PWM Channel 4 Period Interrupt Flag\nFlag is set by hardware when PWM4 down counter reaches zero. \nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 3. "ZIF3,PWM Channel 3 Period Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero. \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 2. "ZIF2,PWM Channel 2 Period Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero. \nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 1. "ZIF1,PWM Channel 1 Period Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero. \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 0. "ZIF0,PWM Channel 0 Period Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero. \nNote: Software can write 1 to clear this bit." "0,1"
line.long 0x8 "PWM_POEN,PWM Output Enable for Channel 0~5"
bitfld.long 0x8 5. "POEN5,PWM Channel 5 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 5 output to pin Disabled,1: PWM channel 5 output to pin Enabled"
bitfld.long 0x8 4. "POEN4,PWM Channel 4 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 4 output to pin Disabled,1: PWM channel 4 output to pin Enabled"
newline
bitfld.long 0x8 3. "POEN3,PWM Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 3 output to pin Disabled,1: PWM channel 3 output to pin Enabled"
bitfld.long 0x8 2. "POEN2,PWM Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 2 output to pin Disabled,1: PWM channel 2 output to pin Enabled"
newline
bitfld.long 0x8 1. "POEN1,PWM Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 1 output to pin Disabled,1: PWM channel 1 output to pin Enabled"
bitfld.long 0x8 0. "POEN0,PWM Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 0 output to pin Disabled,1: PWM channel 0 output to pin Enabled"
line.long 0xC "PWM_BRKCTL,PWM Fault Brake Control Register"
bitfld.long 0xC 31. "D7BKOD,D7 Brake Output Select Register" "0: D7 output low when fault brake conditions asserted,1: D7 output high when fault brake conditions.."
bitfld.long 0xC 30. "D6BKOD,D6 Brake Output Select Register" "0: D6 output low when fault brake conditions asserted,1: D6 output high when fault brake conditions.."
newline
bitfld.long 0xC 29. "BKOD5,PWM Channel 5 Brake Output Select Register" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
bitfld.long 0xC 28. "BKOD4,PWM Channel 4 Brake Output Select Register" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
newline
bitfld.long 0xC 27. "BKOD3,PWM Channel 3 Brake Output Select Register" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
bitfld.long 0xC 26. "BKOD2,PWM Channel 2 Brake Output Select Register" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
newline
bitfld.long 0xC 25. "BKOD1,PWM Channel 1 Brake Output Select Register" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
bitfld.long 0xC 24. "BKOD0,PWM Channel 0 Brake Output Select Register" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
newline
bitfld.long 0xC 9. "SWBRK,Software Brake" "0: Disable PWM Software brake and back to normal..,1: Assert PWM Brake immediately"
bitfld.long 0xC 8. "BRKACT,PWM Brake Type" "0: PWM counter stop when brake is asserted,1: PWM counter keep going when brake is asserted"
newline
bitfld.long 0xC 7. "BRKSTS,PWM Fault Brake Event Flag (Write 1 Clear)\nSoftware can write 1 to clear this bit and must clear this bit before restart PWM counter." "0: PWM output initial state when fault brake..,1: PWM output fault brake state when fault brake.."
bitfld.long 0xC 3. "BRK1SEL,BKP0 Fault Brake Function Source Selection" "0: EINT0 as one brake source in BKP0,1: CPO1 as one brake source in BKP0"
newline
bitfld.long 0xC 2. "BRK0SEL,BKP1 Fault Brake Function Source Selection" "0: EINT1 as one brake source in BKP1,1: CPO0 as one brake source in BKP1"
bitfld.long 0xC 1. "BRK1EN,Enable BKP1 Pin Trigger Fault Brake Function 1" "0: Disabling BKP1 pin can trigger brake function 1..,1: Enabling a falling at BKP1 pin can trigger brake.."
newline
bitfld.long 0xC 0. "BRK0EN,Enable BKP0 Pin Trigger Fault Brake Function 0" "0: Disabling BKP0 pin can trigger brake function 0..,1: Enabling a falling at BKP0 pin can trigger brake.."
line.long 0x10 "PWM_DTCTL,PWM Dead-zone Interval Register"
hexmask.long.byte 0x10 16.--23. 1. "DTCNT45,Dead-Zone Interval Register For Pair Of Channel4 And Channel5 (PWM4 And PWM5 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CLKDIV bits."
hexmask.long.byte 0x10 8.--15. 1. "DTCNT23,Dead-Zone Interval Register For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CLKDIV bits."
newline
hexmask.long.byte 0x10 0.--7. 1. "DTCNT01,Dead-Zone Interval Register For Pair Of Channel0 And Channel1 (PWM0 And PWM1 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CLKDIV bits."
line.long 0x14 "PWM_ADCTCTL0,PWM Trigger Control Register 0"
bitfld.long 0x14 27. "ZPTRGEN3,PWM Channel 3 Zero Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x14 26. "CDTRGEN3,PWM Channel 3 Compare Down Count Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 25. "CPTRGEN3,PWM Channel 3 Center Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
bitfld.long 0x14 24. "CUTRGEN3,PWM Channel 3 Compare Up Count Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 19. "ZPTRGEN2,PWM Channel 2 Zero Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x14 18. "CDTRGEN2,PWM Channel 2 Compare Down Count Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 17. "CPTRGEN2,PWM Channel 2 Center Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
bitfld.long 0x14 16. "CUTRGEN2,PWM Channel 2 Compare Up Count Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 11. "ZPTRGEN1,PWM Channel 1 Zero Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x14 10. "CDTRGEN1,PWM Channel 1 Compare Down Count Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 9. "CPTRGEN1,Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "?,1: Enabled"
bitfld.long 0x14 8. "CUTRGEN1,PWM Channel 1 Compare Up Count Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 3. "ZPTRGEN0,PWM Channel 0 Zero Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x14 2. "CDTRGEN0,PWM Channel 0 Compare Down Count Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 1. "CPTRGEN0,PWM Channel 0 Center Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
bitfld.long 0x14 0. "CUTRGEN0,PWM Channel 0 Compare Up Count Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
line.long 0x18 "PWM_ADCTCTL1,PWM Trigger Control Register 1"
bitfld.long 0x18 11. "ZPTRGEN5,PWM Channel 5 Zero Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x18 10. "CDTRGEN5,PWM Channel 5 Compare Down Count Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x18 9. "CPTRGEN5,PWM Channel 5 Center Point Trigger ADC Enable Bit\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
bitfld.long 0x18 8. "CUTRGEN5,PWM Channel 5 Compare Up Count Point Trigger ADC Enable Bit\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
newline
bitfld.long 0x18 3. "ZPTRGEN4,PWM Channel 4 Zero Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x18 2. "CDTRGEN4,PWM Channel 4 Compare Down Count Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x18 1. "CPTRGEN4,PWM Channel 4 Center Point Trigger ADC Enable Bit\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
bitfld.long 0x18 0. "CUTRGEN4,PWM Channel 4 Compare Up Count Point Trigger ADC Enable Bit\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
line.long 0x1C "PWM_ADCTSTS0,PWM Trigger Status Register 0"
bitfld.long 0x1C 27. "ZPTRGF3,PWM Channel 3 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 26. "CDTRGF3,PWM Channel 3 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 25. "CPTRGF3,PWM Channel 3 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 24. "CUTRGF3,PWM Channel 3 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 19. "ZPTRGF2,PWM Channel 2 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 18. "CDTRGF2,PWM Channel 2 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 17. "CPTRGF2,PWM Channel 2 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 16. "CUTRGF2,PWM Channel 3 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 11. "ZPTRGF1,PWM Channel 1 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 10. "CDTRGF1,PWM Channel 1 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 9. "CPTRGF1,PWM Channel 1 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 8. "CUTRGF1,PWM Channel 1 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 3. "ZPTRGF0,PWM Channel 0 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 2. "CDTRGF0,PWM Channel 0 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 1. "CPTRGF0,PWM Channel 0 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 0. "CUTRGF0,PWM Channel 0 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
line.long 0x20 "PWM_ADCTSTS1,PWM Trigger Status Register 1"
bitfld.long 0x20 11. "ZPTRGF5,PWM Channel 5 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x20 10. "CDTRGF5,PWM Channel 5 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x20 9. "CPTRGF5,PWM Channel 5 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x20 8. "CUTRGF5,PWM Channel 5 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x20 3. "ZPTRGF4,PWM Channel 4 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x20 2. "CDTRGF4,PWM Channel 4 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x20 1. "CPTRGF4,PWM Channel 4 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x20 0. "CUTRGF4,PWM Channel 4 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit." "0,1"
line.long 0x24 "PWM_PHCHG,Phase Changed Register"
bitfld.long 0x24 31. "ACMP0TEN,Enable ACMP0 Trigger Function\nNote: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set." "0: Disabled,1: Enabled"
bitfld.long 0x24 30. "T0,Enable Timer0 Trigger PWM Function\nWhen this bit is set timer0 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 28.--29. "A0POSSEL,A0POSSEL\nSelect the positive input source of ACMP0." "0: Select P1.5 as the input of ACMP0,1: Select P1.0 as the input of ACMP0,?,?"
bitfld.long 0x24 27. "OFFEN30,Setting This Bit Will Force MSKEN3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 26. "OFFEN20,Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
bitfld.long 0x24 25. "OFFEN10,Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 24. "OFFEN00,Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
bitfld.long 0x24 23. "ACMP1TEN,Enable ACMP1 Trigger Function\nNote: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 22. "TMR1TEN,Enable Timer1 Trigger PWM Function\nWhen this bit is set timer1 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register." "0: Disabled,1: Enabled"
bitfld.long 0x24 20.--21. "A1POSSEL,A1POSSEL\nSelect the positive input source of ACMP1." "0: Select P3.1 as the input of ACMP1,1: Select P3.2 as the input of ACMP1,?,?"
newline
bitfld.long 0x24 19. "OFFEN31,Setting This Bit Will Force MSKEN3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
bitfld.long 0x24 18. "OFFEN21,Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 17. "OFFEN11,Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
bitfld.long 0x24 16. "OFFEN01,Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 15. "AUTOCLR1,Hardware Auto Clear ACMP1TEN When ACMP1 Trigger It" "0: Enabled,1: Disabled"
bitfld.long 0x24 14. "AUTOCLR0,Hardware Auto Clear ACMP0TEN When ACMP0 Trigger It" "0: Enabled,1: Disabled"
newline
bitfld.long 0x24 13. "MSKEN5,MSKEN Channel 5 Output Enable Control" "0: Output MSKDAT5 specified in bit 5 of PWM_PHCHG..,1: Output the original channel 5 waveform"
bitfld.long 0x24 12. "MSKEN4,MSKEN Channel 4 Output Enable Control" "0: Output MSKDAT4 specified in bit 4 of PWM_PHCHG..,1: Output the original channel 4 waveform"
newline
bitfld.long 0x24 11. "MSKEN3,MSKEN Channel 3 Output Enable Control" "0: Output MSKDAT3 specified in bit 3 of PWM_PHCHG..,1: Output the original channel 3 waveform"
bitfld.long 0x24 10. "MSKEN2,MSKEN Channel 2 Output Enable Control" "0: Output MSKDAT2 specified in bit 2 of PWM_PHCHG..,1: Output the original channel 2 waveform"
newline
bitfld.long 0x24 9. "MSKEN1,MSKEN Channel 1 Output Enable Control" "0: Output MSKDAT1 specified in bit 1 of PWM_PHCHG..,1: Output the original channel 1 waveform"
bitfld.long 0x24 8. "MSKEN0,MSKEN Channel 0 Output Enable Control" "0: Output MSKDAT0 specified in bit 0 of PWM_PHCHG..,1: Output the original channel 0 waveform"
newline
bitfld.long 0x24 7. "MSKDAT7,MSKDAT7: When MSKEN7 Is 1 Channel 7's Output Waveform Is MSKDAT7" "0: Output low,1: Output high"
bitfld.long 0x24 6. "MSKDAT6,MSKDAT6: When MSKEN6 Is 1 Channel 6's Output Waveform Is MSKDAT6" "0: Output low,1: Output high"
newline
bitfld.long 0x24 5. "MSKDAT5,MSKDAT5: When MSKEN5 Is Zero Channel 5's Output Waveform Is MSKDAT5" "0: Output low,1: Output high"
bitfld.long 0x24 4. "MSKDAT4,MSKDAT4: When MSKEN4is Zero Channel 4's Output Waveform Is MSKDAT4" "0: Output low,1: Output high"
newline
bitfld.long 0x24 3. "MSKDAT3,MSKDAT3: When MSKEN3 Is Zero Channel 3's Output Waveform Is MSKDAT3" "0: Output low,1: Output high"
bitfld.long 0x24 2. "MSKDAT2,MSKDAT2: When MSKEN2 Is Zero Channel 2's Output Waveform Is MSKDAT2" "0: Output low,1: Output high"
newline
bitfld.long 0x24 1. "MSKDAT1,MSKDAT1: When MSKEN1is Zero Channel 1's Output Waveform Is MSKDAT1" "0: Output low,1: When MSKEN1is Zero"
bitfld.long 0x24 0. "MSKDAT0,MSKDAT0: When MSKEN0 Is Zero Channel 0's Output Waveform Is MSKDAT0" "0: When MSKEN0 Is Zero,1: Output high"
line.long 0x28 "PWM_PHCHGNXT,Next Phase Change Register"
bitfld.long 0x28 31. "ACMP0TEN,Enable ACMP0 Trigger Function\nNote: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set." "0: Disabled,1: Enabled"
bitfld.long 0x28 30. "TMR0TEN,Enable Timer0 Trigger PWM Function\nWhen this bit is set timer0 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 28.--29. "A0POSSEL,A0POSSEL\nSelect the positive input source of ACMP0." "0: Select P1.5 as the input of ACMP0,1: Select P1.0 as the input of ACMP0,?,?"
bitfld.long 0x28 27. "OFFEN30,Setting This Bit Will Force MSKEN3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 26. "OFFEN20,Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3.." "0: Disabled,1: Enabled"
bitfld.long 0x28 25. "OFFEN10,Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 24. "OFFEN00,Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
bitfld.long 0x28 23. "ACMP1TEN,Enable ACMP1 Trigger Function\nNote: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 22. "TMR1TEN,Enable Timer1 Trigger PWM Function\nWhen this bit is set timer1 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register." "0: Disabled,1: Enabled"
bitfld.long 0x28 20.--21. "A1POSSEL,A1POSSEL\nSelect the positive input source of ACMP1." "0: Select P3.1 as the input of ACMP1,1: Select P3.2 as the input of ACMP1,?,?"
newline
bitfld.long 0x28 19. "OFFEN31,Setting This Bit Will Force MSKEN3to Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
bitfld.long 0x28 18. "OFFEN21,Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 17. "OFFEN11,Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
bitfld.long 0x28 16. "OFFEN01,Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: only for MSKEN0 MSKEN3 MSKEN2 MSKEN3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 15. "AUTOCLR1,Hardware Auto Clear ACMP1TEN When ACMP1 Trigger It" "0: Enabled,1: Disabled"
bitfld.long 0x28 14. "AUTOCLR0,Hardware Auto Clear ACMP0TEN When ACMP0 Trigger It" "0: Enabled,1: Disabled"
newline
bitfld.long 0x28 13. "MSKEN5,MSKEN Channel 5 Output Enable Control" "0: Output MSKDAT5 specified in bit 5 of PWM_PHCHG..,1: Output the original channel 5 waveform"
bitfld.long 0x28 12. "MSKEN4,MSKEN Channel 4 Output Enable Control" "0: Output MSKDAT4 specified in bit 4 of PWM_PHCHG..,1: Output the original channel 4 waveform"
newline
bitfld.long 0x28 11. "MSKEN3,MSKEN Channel 3 Output Enable Control" "0: Output MSKDAT3 specified in bit 3 of PWM_PHCHG..,1: Output the original channel 3 waveform"
bitfld.long 0x28 10. "MSKEN2,MSKEN Channel 2 Output Enable Control" "0: Output MSKDAT2 specified in bit 2 of PWM_PHCHG..,1: Output the original channel 2 waveform"
newline
bitfld.long 0x28 9. "MSKEN1,MSKEN Channel 1 Output Enable Control" "0: Output MSKDAT1 specified in bit 1 of PWM_PHCHG..,1: Output the original channel 1 waveform"
bitfld.long 0x28 8. "MSKEN0,MSKEN Channel 0 Output Enable Control" "0: Output MSKDAT0 specified in bit 0 of PWM_PHCHG..,1: Output the original channel 0 waveform"
newline
bitfld.long 0x28 7. "MSKDAT7,MSKDAT7: When MSKEN7 Is 1 Channel 7's Output Waveform Is MSKDAT7" "0: Output low,1: Output high"
bitfld.long 0x28 6. "MSKDAT6,MSKDAT6: When MSKEN6 Is 1 Channel 6's Output Waveform Is MSKDAT6" "0: Output low,1: Output high"
newline
bitfld.long 0x28 5. "MSKDAT5,MSKDAT5: When MSKEN5 Is Zero Channel 5's Output Waveform Is MSKDAT5" "0: Output low,1: Output high"
bitfld.long 0x28 4. "MSKDAT4,MSKDAT4: When MSKEN4is Zero Channel 4's Output Waveform Is MSKDAT4" "0: Output low,1: Output high"
newline
bitfld.long 0x28 3. "MSKDAT3,MSKDAT3: When MSKEN3 Is Zero Channel 3's Output Waveform Is MSKDAT3" "0: Output low,1: Output high"
bitfld.long 0x28 2. "MSKDAT2,MSKDAT2: When MSKEN2 Is Zero Channel 2's Output Waveform Is MSKDAT2" "0: Output low,1: Output high"
newline
bitfld.long 0x28 1. "MSKDAT1,MSKDAT1: When MSKEN1is Zero Channel 1's Output Waveform Is MSKDAT1" "0: Output low,1: When MSKEN1is Zero"
bitfld.long 0x28 0. "MSKDAT0,MSKDAT0: When MSKEN0 Is Zero Channel 0's Output Waveform Is MSKDAT0" "0: When MSKEN0 Is Zero,1: Output high"
line.long 0x2C "PWM_PHCHGMSK,Phase Change MASK Register"
bitfld.long 0x2C 9. "POSCTL1,ACMP1 Positive Input Selection Control\nNote: Register CMP1CR is describe in Comparator Controller chapter" "0: The input of ACMP1 is controlled by CMP1CR,1: The input of ACMP1 is controlled by A1POSSEL of.."
bitfld.long 0x2C 8. "POSCTL0,ACMP0 Positive Input Selection Control \nNote: Register CMP0CR is describe in Comparator Controller chapter" "0: The input of ACMP0 is controlled by CMP0CR,1: The input of ACMP0 is controlled by A0POSSEL of.."
newline
bitfld.long 0x2C 7. "MASKEND7,MASK For D7" "0: Original GPIO P0.0,1: D7"
bitfld.long 0x2C 6. "MASKEND6,MASK For D6" "0: Original GPIO P0.1,1: D6"
line.long 0x30 "PWM_IFA,Period Interrupt Accumulation Control Register"
hexmask.long.byte 0x30 4.--7. 1. "IFCNT,Interrupt Accumulation Count\nWhen IFCNT is set IFCNT will decrease when every ZIF0 flag is set and when IFCNT reach to zero the PWM0 interrupt will occurred and IFCNT will reload itself."
bitfld.long 0x30 0. "IFAEN,Interrupt Accumulation Enable" "0: Disabled,1: Enabled"
endif
sif (cpuis("MINI5??DE"))
group.long 0x0++0x3B
line.long 0x0 "PPR,PWM Pre-scale Register"
hexmask.long.byte 0x0 16.--23. 1. "CP45,Clock Prescaler 4 For PWM Counter 4 And 5\nClock input is divided by (CP45 + 1) before it is fed to the corresponding PWM counter.\n"
hexmask.long.byte 0x0 8.--15. 1. "CP23,Clock Prescaler 2 For PWM Counter 2 And 3\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter.\n"
newline
hexmask.long.byte 0x0 0.--7. 1. "CP01,Clock Prescaler 0 For PWM Counter 0 And 1\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter.\n"
line.long 0x4 "CSR,PWM Clock Select Register"
bitfld.long 0x4 20.--22. "CSR5,Timer 5 Clock Source Selection\nSelect clock input for PWM timer.\n" "0: Input Clock Divided by 2,1: Input Clock Divided by 4,?,?,?,?,?,?"
bitfld.long 0x4 16.--18. "CSR4,Timer 4 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 12.--14. "CSR3,Timer 3 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 8.--10. "CSR2,Timer 2 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4.--6. "CSR1,Timer 1 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "CSR0,Timer 0 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7"
line.long 0x8 "PCR,PWM Control Register"
bitfld.long 0x8 31. "PWMTYPE,PWM Aligned Type Selection Bit\n" "0: Edge-aligned type,1: Center-aligned type"
bitfld.long 0x8 30. "GRP,Group Bit\n" "0: The signals timing of all PWM channels are..,1: Unify the signals timing of PWM0 PWM2 and PWM4.."
newline
bitfld.long 0x8 28.--29. "PWMMOD,PWM Operating Mode Selection\n" "0: Independent mode,1: Complementary mode,?,?"
bitfld.long 0x8 27. "CLRPWM,Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware." "0: Do not clear PWM counter,1: All 16-bit PWM counters cleared to 0x0000"
newline
bitfld.long 0x8 26. "DZEN45,Dead-zone 4 Generator Enable Control (PWM4 And PWM5 Pair For PWM Group)\nNote: When the dead-zone generator is enabled the pair of PWM4 and PWM5 becomes a complementary pair for PWM group." "0: Disabled,1: Enabled"
bitfld.long 0x8 25. "DZEN23,Dead-zone 2 Generator Enable Control (PWM2 And PWM3 Pair For PWM Group)\nNote: When the dead-zone generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group." "0: Disabled,1: Enabled"
newline
bitfld.long 0x8 24. "DZEN01,Dead-zone 0 Generator Enable Control (PWM0 And PWM1 Pair For PWM Group)\nNote: When the dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group." "0: Disabled,1: Enabled"
bitfld.long 0x8 23. "CH5MOD,PWM-timer 5 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit it will cause CNR5 and CMR5 cleared." "0: One-shot mode,1: Auto-reload mode"
newline
bitfld.long 0x8 22. "CH5INV,PWM-timer 5 Output Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled"
bitfld.long 0x8 20. "CH5EN,PWM-timer 5 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
newline
bitfld.long 0x8 19. "CH4MOD,PWM-timer 4 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit it will cause CNR4 and CMR4 cleared." "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 18. "CH4INV,PWM-timer 4 Output Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled"
newline
bitfld.long 0x8 16. "CH4EN,PWM-timer 4 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
bitfld.long 0x8 15. "CH3MOD,PWM-timer 3 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit it will cause CNR3 and CMR3 cleared." "0: One-shot mode,1: Auto-reload mode"
newline
bitfld.long 0x8 14. "CH3INV,PWM-timer 3 Output Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled"
bitfld.long 0x8 12. "CH3EN,PWM-timer 3 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
newline
bitfld.long 0x8 11. "CH2MOD,PWM-timer 2 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit it will cause CNR2 and CMR2 cleared." "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 10. "CH2INV,PWM-timer 2 Output Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled"
newline
bitfld.long 0x8 8. "CH2EN,PWM-timer 2 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
bitfld.long 0x8 7. "CH1MOD,PWM-timer 1 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit it will cause CNR1 and CMR1 cleared." "0: One-shot mode,1: Auto-reload mode"
newline
bitfld.long 0x8 6. "CH1INV,PWM-timer 1 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
bitfld.long 0x8 4. "CH1EN,PWM-timer 1 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
newline
bitfld.long 0x8 3. "CH0MOD,PWM-timer 0 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit it will cause CNR0 and CMR0 cleared." "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 2. "CH0INV,PWM-timer 0 Output Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled"
newline
bitfld.long 0x8 1. "DB_MODE,PWM Debug Mode Configuration Bit (Available In DEBUG Mode Only)\n" "0: Safe mode: The timer is frozen and PWM outputs..,1: Normal mode: The timer continues to operate.."
bitfld.long 0x8 0. "CH0EN,PWM-timer 0 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
line.long 0xC "CNR0,PWM Counter Register 0"
hexmask.long.word 0xC 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value\nNote: Any write to CNRn will take effect in next PWM cycle."
line.long 0x10 "CNR1,PWM Counter Register 1"
hexmask.long.word 0x10 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value\nNote: Any write to CNRn will take effect in next PWM cycle."
line.long 0x14 "CNR2,PWM Counter Register 2"
hexmask.long.word 0x14 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value\nNote: Any write to CNRn will take effect in next PWM cycle."
line.long 0x18 "CNR3,PWM Counter Register 3"
hexmask.long.word 0x18 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value\nNote: Any write to CNRn will take effect in next PWM cycle."
line.long 0x1C "CNR4,PWM Counter Register 4"
hexmask.long.word 0x1C 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value\nNote: Any write to CNRn will take effect in next PWM cycle."
line.long 0x20 "CNR5,PWM Counter Register 5"
hexmask.long.word 0x20 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value\nNote: Any write to CNRn will take effect in next PWM cycle."
line.long 0x24 "CMR0,PWM Comparator Register 0"
hexmask.long.word 0x24 0.--15. 1. "CMRn,PWM Comparator Bits\nNote: Any write to CMRn will take effect in next PWM cycle."
line.long 0x28 "CMR1,PWM Comparator Register 1"
hexmask.long.word 0x28 0.--15. 1. "CMRn,PWM Comparator Bits\nNote: Any write to CMRn will take effect in next PWM cycle."
line.long 0x2C "CMR2,PWM Comparator Register 2"
hexmask.long.word 0x2C 0.--15. 1. "CMRn,PWM Comparator Bits\nNote: Any write to CMRn will take effect in next PWM cycle."
line.long 0x30 "CMR3,PWM Comparator Register 3"
hexmask.long.word 0x30 0.--15. 1. "CMRn,PWM Comparator Bits\nNote: Any write to CMRn will take effect in next PWM cycle."
line.long 0x34 "CMR4,PWM Comparator Register 4"
hexmask.long.word 0x34 0.--15. 1. "CMRn,PWM Comparator Bits\nNote: Any write to CMRn will take effect in next PWM cycle."
line.long 0x38 "CMR5,PWM Comparator Register 5"
hexmask.long.word 0x38 0.--15. 1. "CMRn,PWM Comparator Bits\nNote: Any write to CMRn will take effect in next PWM cycle."
group.long 0x54++0x33
line.long 0x0 "PIER,PWM Interrupt Enable Control Register"
bitfld.long 0x0 17. "INT_TYPE,PWM Interrupt Type Selection Bit\nNote: This bit is effective when PWM in central align mode only." "0: PWMPIFn will be set if PWM counter underflows,1: PWMPIFn will be set if PWM counter matches CNRn.."
bitfld.long 0x0 16. "BRKIE,Fault Brake0 And 1 Interrupt Enable Control\n" "0: Disabling flags BKF0 and BKF1 to trigger PWM..,1: Enabling flags BKF0 and BKF1 can trigger PWM.."
newline
bitfld.long 0x0 13. "PWMDIE5,PWM Channel 5 Duty Interrupt Enable Control\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 12. "PWMDIE4,PWM Channel 4 Duty Interrupt Enable Control\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 11. "PWMDIE3,PWM Channel 3 Duty Interrupt Enable Control\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "PWMDIE2,PWM Channel 2 Duty Interrupt Enable Control\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 9. "PWMDIE1,PWM Channel 1 Duty Interrupt Enable Control\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 8. "PWMDIE0,PWM Channel 0 Duty Interrupt Enable Control\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "PWMPIE5,PWM Channel 5 Period Interrupt Enable Control\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "PWMPIE4,PWM Channel 4 Period Interrupt Enable Control\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 3. "PWMPIE3,PWM Channel 3 Period Interrupt Enable Control\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 2. "PWMPIE2,PWM Channel 2 Period Interrupt Enable Control\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "PWMPIE1,PWM Channel 1 Period Interrupt Enable Control\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "PWMPIE0,PWM Channel 0 Period Interrupt Enable Control\n" "0: Disabled,1: Enabled"
line.long 0x4 "PIIR,PWM Interrupt Indication Register"
bitfld.long 0x4 17. "BKF1,PWM Brake1 Flag\nNote: Software can write 1 to clear this bit." "0: PWM Brake does not recognize a falling signal at..,1: When PWM Brake detects a falling signal at pin.."
bitfld.long 0x4 16. "BKF0,PWM Brake0 Flag\nNote: Software can write 1 to clear this bit." "0: PWM Brake does not recognize a falling signal at..,1: When PWM Brake detects a falling signal at pin.."
newline
bitfld.long 0x4 13. "PWMDIF5,PWM Channel 5 Duty Interrupt Flag\nFlag is set by hardware when a channel 5 PWM counter reaches CMR5 in down-count direction. \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 12. "PWMDIF4,PWM Channel 4 Duty Interrupt Flag\nFlag is set by hardware when a channel 4 PWM counter reaches CMR4 in down-count direction. \nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 11. "PWMDIF3,PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when a channel 3 PWM counter reaches CMR3 in down-count direction. \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 10. "PWMDIF2,PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when a channel 2 PWM counter reaches CMR2 in down-count direction. \nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 9. "PWMDIF1,PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when a channel 1 PWM counter reaches CMR1 in down-count direction. \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 8. "PWMDIF0,PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when a channel 0 PWM counter reaches CMR0 in down-count direction. \nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 5. "PWMPIF5,PWM Channel 5 Period Interrupt Flag\nFlag is set by hardware when PWM5 down counter reaches zero. \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 4. "PWMPIF4,PWM Channel 4 Period Interrupt Flag\nFlag is set by hardware when PWM4 down counter reaches zero. \nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 3. "PWMPIF3,PWM Channel 3 Period Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero. \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 2. "PWMPIF2,PWM Channel 2 Period Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero. \nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 1. "PWMPIF1,PWM Channel 1 Period Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero. \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 0. "PWMPIF0,PWM Channel 0 Period Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero. \nNote: Software can write 1 to clear this bit." "0,1"
line.long 0x8 "PWMPOE,PWM Output Enable for Channel 0~5"
bitfld.long 0x8 5. "PWM5,PWM Channel 5 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 5 output to pin Disabled,1: PWM channel 5 output to pin Enabled"
bitfld.long 0x8 4. "PWM4,PWM Channel 4 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 4 output to pin Disabled,1: PWM channel 4 output to pin Enabled"
newline
bitfld.long 0x8 3. "PWM3,PWM Channel 3 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 3 output to pin Disabled,1: PWM channel 3 output to pin Enabled"
bitfld.long 0x8 2. "PWM2,PWM Channel 2 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 2 output to pin Disabled,1: PWM channel 2 output to pin Enabled"
newline
bitfld.long 0x8 1. "PWM1,PWM Channel 1 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 1 output to pin Disabled,1: PWM channel 1 output to pin Enabled"
bitfld.long 0x8 0. "PWM0,PWM Channel 0 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 0 output to pin Disabled,1: PWM channel 0 output to pin Enabled"
line.long 0xC "PFBCON,PWM Fault Brake Control Register"
bitfld.long 0xC 31. "D7BKO7,D7 Brake Output Select Bit\n" "0: D7 output low when fault brake conditions asserted,1: D7 output high when fault brake conditions.."
bitfld.long 0xC 30. "D6BKO6,D6 Brake Output Select Bit\n" "0: D6 output low when fault brake conditions asserted,1: D6 output high when fault brake conditions.."
newline
bitfld.long 0xC 29. "PWMBKO5,PWM Channel 5 Brake Output Select Bit\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
bitfld.long 0xC 28. "PWMBKO4,PWM Channel 4 Brake Output Select Bit\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
newline
bitfld.long 0xC 27. "PWMBKO3,PWM Channel 3 Brake Output Select Bit\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
bitfld.long 0xC 26. "PWMBKO2,PWM Channel 2 Brake Output Select Bit\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
newline
bitfld.long 0xC 25. "PWMBKO1,PWM Channel 1 Brake Output Select Bit\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
bitfld.long 0xC 24. "PWMBKO0,PWM Channel 0 Brake Output Select Bit\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
newline
bitfld.long 0xC 7. "BKF,PWM Fault Brake Event Flag (Write 1 Clear)\nSoftware can write 1 to clear this bit and must clear this bit before restart PWM counter." "0: PWM output initial state when fault brake..,1: PWM output fault brake state when fault brake.."
bitfld.long 0xC 3. "CPO1BKEN,BKP0 Fault Brake Function Source Selection\n" "0: EINT0 as one brake source in BKP0,1: CPO1 as one brake source in BKP0"
newline
bitfld.long 0xC 2. "CPO0BKEN,BKP1 Fault Brake Function Source Selection\n" "0: EINT1 as one brake source in BKP1,1: CPO0 as one brake source in BKP1"
bitfld.long 0xC 1. "BKEN1,Enable BKP1 Pin Trigger Fault Brake Function 1\n" "0: Disabling BKP1 pin can trigger brake function 1..,1: Enabling a falling at BKP1 pin can trigger brake.."
newline
bitfld.long 0xC 0. "BKEN0,Enable BKP0 Pin Trigger Fault Brake Function 0\n" "0: Disabling BKP0 pin can trigger brake function 0..,1: Enabling a falling at BKP0 pin can trigger brake.."
line.long 0x10 "PDZIR,PWM Dead-zone Interval Register"
hexmask.long.byte 0x10 16.--23. 1. "DZI45,Dead-zone Interval Register For Pair Of Channel4 And Channel5 (PWM4 And PWM5 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits."
hexmask.long.byte 0x10 8.--15. 1. "DZI23,Dead-zone Interval Register For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits."
newline
hexmask.long.byte 0x10 0.--7. 1. "DZI01,Dead-zone Interval Register For Pair Of Channel0 And Channel1 (PWM0 And PWM1 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits."
line.long 0x14 "TRGCON0,PWM Trigger Control Register 0"
bitfld.long 0x14 27. "P3TRGEN,Enable PWM Trigger ADC Function While Channel3's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x14 26. "CM3TRGFEN,Enable PWM Trigger ADC Function While Channel3's Counter Matching CMR3 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 25. "CNT3TRGEN,Enable PWM Trigger ADC Function While Channel3's Counter Matching CNR3\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
bitfld.long 0x14 24. "CM3TRGREN,Enable PWM Trigger ADC Function While Channel3's Counter Matching CMR3 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 19. "P2TRGEN,Enable PWM Trigger ADC Function While Channel2's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x14 18. "CM2TRGFEN,Enable PWM Trigger ADC Function While Channel2's Counter Matching CMR2 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 17. "CNT2TRGEN,Enable PWM Trigger ADC Function While Channel2's Counter Matching CNR2\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
bitfld.long 0x14 16. "CM2TRGREN,Enable PWM Trigger ADC Function While Channel2's Counter Matching CMR2 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 11. "P1TRGEN,Enable PWM Trigger ADC Function While Channel1's Counter Matching 0 \nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x14 10. "CM1TRGFEN,Enable PWM Trigger ADC Function While Channel1's Counter Matching CMR1 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 9. "CNT1TRGEN,Enable PWM Trigger ADC Function While Channel1's Counter Matching CNR1\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
bitfld.long 0x14 8. "CM1TRGREN,Enable PWM Trigger ADC Function While Channel1's Counter Matching CMR1 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 3. "P0TRGEN,Enable PWM Trigger ADC Function While Channel0's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x14 2. "CM0TRGFEN,Enable PWM Trigger ADC Function While Channel0's Counter Matching CMR0 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 1. "CNT0TRGEN,Enable PWM Trigger ADC Function While Channel0's Counter Matching CNR0\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
bitfld.long 0x14 0. "CM0TRGREN,Enable PWM Trigger ADC Function While Channel0's Counter Matching CMR0 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled"
line.long 0x18 "TRGCON1,PWM Trigger Control Register 1"
bitfld.long 0x18 11. "P5TRGEN,Enable PWM Trigger ADC Function While Channel5's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x18 10. "CM5TRGFEN,Enable PWM Trigger ADC Function While Channel5's Counter Matching CMR5 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x18 9. "CNT5TRGEN,Enable PWM Trigger ADC Function While Channel5's Counter Matching CNR5\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
bitfld.long 0x18 8. "CM5TRGREN,Enable PWM Trigger ADC Function While Channel5's Counter Matching CMR5 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled"
newline
bitfld.long 0x18 3. "P4TRGEN,Enable PWM Trigger ADC Function While Channel4's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x18 2. "CM4TRGFEN,Enable PWM Trigger ADC Function While Channel4's Counter Matching CMR4 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x18 1. "CNT4TRGEN,Enable PWM Trigger ADC Function While Channel4's Counter Matching CNR4\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled"
bitfld.long 0x18 0. "CM4TRGREN,Enable PWM Trigger ADC Function While Channel4's Counter Matching CMR4 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled"
line.long 0x1C "TRGSTS0,PWM Trigger Status Register 0"
bitfld.long 0x1C 27. "PERID3FLAG,When Counter Counting To Period This Bit Will Be Set For Trigger ADC \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 26. "CMR3FLAG_F,When Counter Counting Down To CMR This Bit Will Be Set For Trigger ADC\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 25. "CNT3FLAG,When Counter Counting To CNR This Bit Will Be Set For Trigger ADC\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 24. "CMR3FLAG_R,When Counter Counting Up To CMR This Bit Will Be Set For Trigger ADC\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 19. "PERID2FLAG,ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 18. "CMR2FLAG_F,ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 17. "CNT2FLAG,ADC Trigger Flag By Counting To CNR\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 16. "CMR2FLAG_R,ADC Trigger Flag By Counting Up To CMR \nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 11. "PERID1FLAG,ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 10. "CMR1FLAG_F,ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 9. "CNT1FLAG,ADC Trigger Flag By Counting To CNR\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 8. "CMR1FLAG_R,ADC Trigger Flag By Counting Up To CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 3. "PERID0FLAG,ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 2. "CMR0FLAG_F,ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 1. "CNT0FLAG,ADC Trigger Flag By Counting To CNR\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 0. "CMR0FLAG_R,ADC Trigger Flag By Counting Up To CMR\nNote: Software can write 1 to clear this bit." "0,1"
line.long 0x20 "TRGSTS1,PWM Trigger Status Register 1"
bitfld.long 0x20 11. "PERID5FLAG,ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x20 10. "CMR5FLAG_F,ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x20 9. "CNT5FLAG,ADC Trigger Flag By Counting To CNR\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x20 8. "CMR5FLAG_R,ADC Trigger Flag By Counting Up To CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x20 3. "PERID4FLAG,ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x20 2. "CMR4FLAG_F,ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x20 1. "CNT4FLAG,ADC Trigger Flag By Counting To CNR\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x20 0. "CMR4FLAG_R,ADC Trigger Flag By Counting Up To CMR\nNote: Software can write 1 to clear this bit." "0,1"
line.long 0x24 "PHCHG,Phase Change Register"
bitfld.long 0x24 31. "CE0,ACMP0 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set." "0: Disabled,1: Enabled"
bitfld.long 0x24 30. "T0,Timer0 Trigger PWM Function Enable Control\nWhen this bit is set timer0 time-out event will update PHCHG with PHCHG_NXT register." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 28.--29. "CMP0SEL,CMP0SEL\nSelect the positive input source of ACMP0.\n" "0: Select P1.5 as the input of ACMP0,1: Select P1.0 as the input of ACMP0,?,?"
bitfld.long 0x24 27. "CH31TOFF0,Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 26. "CH21TOFF0,Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x24 25. "CH11TOFF0,Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 24. "CH01TOFF0,Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x24 23. "CE1,ACMP1 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 22. "T1,Timer1 Trigger PWM Function Enable Control\nWhen this bit is set timer1 time-out event will update PHCHG with PHCHG_NXT register." "0: Disabled,1: Enabled"
bitfld.long 0x24 20.--21. "CMP1SEL,CMP1SEL\nSelect the positive input source of ACMP1.\n" "0: Select P3.1 as the input of ACMP1,1: Select P3.2 as the input of ACMP1,?,?"
newline
bitfld.long 0x24 19. "CH31TOFF1,Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x24 18. "CH21TOFF1,Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 17. "CH11TOFF1,Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x24 16. "CH01TOFF1,Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 15. "ACCNT1,Hardware Auto Clear CE1 When ACMP1 Trigger It\n" "0: Enabled,1: Disabled"
bitfld.long 0x24 14. "ACCNT0,Hardware Auto Clear CE0 When ACMP0 Trigger It\n" "0: Enabled,1: Disabled"
newline
bitfld.long 0x24 13. "PWM5,PWM Channel 5 Output Enable Control\n" "0: Output D5 specified in bit 5 of PHCHG register,1: Output the original channel 5 waveform"
bitfld.long 0x24 12. "PWM4,PWM Channel 4 Output Enable Control\n" "0: Output D4 specified in bit 4 of PHCHG register,1: Output the original channel 4 waveform"
newline
bitfld.long 0x24 11. "PWM3,PWM Channel 3 Output Enable Control\n" "0: Output D3 specified in bit 3 of PHCHG register,1: Output the original channel 3 waveform"
bitfld.long 0x24 10. "PWM2,PWM Channel 2 Output Enable Control\n" "0: Output D2 specified in bit 2 of PHCHG register,1: Output the original channel 2 waveform"
newline
bitfld.long 0x24 9. "PWM1,PWM Channel 1 Output Enable Control\n" "0: Output D1 specified in bit 1 of PHCHG register,1: Output the original channel 1 waveform"
bitfld.long 0x24 8. "PWM0,PWM Channel 0 Output Enable Control\n" "0: Output D0 specified in bit 0 of PHCHG register,1: Output the original channel 0 waveform"
newline
bitfld.long 0x24 7. "D7,D7: When MASK7 Is 1 Channel 7's Output Waveform Is D7\n" "0: Output low,1: Output high"
bitfld.long 0x24 6. "D6,D6: When MASK6 Is 1 Channel 6's Output Waveform Is D6\n" "0: Output low,1: Output high"
newline
bitfld.long 0x24 5. "D5,D5: When PWM5 Is Zero Channel 5's Output Waveform Is D5\n" "0: Output low,1: Output high"
bitfld.long 0x24 4. "D4,D4: When PWM4 Is Zero Channel 4's Output Waveform Is D4\n" "0: Output low,1: Output high"
newline
bitfld.long 0x24 3. "D3,D3: When PWM3 Is Zero Channel 3's Output Waveform Is D3\n" "0: Output low,1: Output high"
bitfld.long 0x24 2. "D2,D2: When PWM2 Is Zero Channel 2's Output Waveform Is D2\n" "0: Output low,1: Output high"
newline
bitfld.long 0x24 1. "D1,D1: When PWM1 Is Zero Channel 1's Output Waveform Is D1\n" "0: Output low,1: When PWM1 Is Zero"
bitfld.long 0x24 0. "D0,D0: When PWM0 Is Zero Channel 0's Output Waveform Is D0\n" "0: When PWM0 Is Zero,1: Output high"
line.long 0x28 "PHCHGNXT,Next Phase Change Register"
bitfld.long 0x28 31. "CE0,ACMP0 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set." "0: Disabled,1: Enabled"
bitfld.long 0x28 30. "T0,Timer0 Trigger PWM Function Enable Control\nWhen this bit is set timer0 time-out event will update PHCHG with PHCHG_NXT register." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 28.--29. "CMP0SEL,CMP0SEL\nSelect the positive input source of ACMP0.\n" "0: Select P1.5 as the input of ACMP0,1: Select P1.0 as the input of ACMP0,?,?"
bitfld.long 0x28 27. "CH31TOFF0,Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 26. "CH21TOFF0,Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x28 25. "CH11TOFF0,Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 24. "CH01TOFF0,Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x28 23. "CE1,ACMP1 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 22. "T1,Timer1 Trigger PWM Function Enable Control\nWhen this bit is set timer1 time-out event will update PHCHG with PHCHG_NXT register." "0: Disabled,1: Enabled"
bitfld.long 0x28 20.--21. "CMP1SEL,CMP1SEL\nSelect the positive input source of ACMP1.\n" "0: Select P3.1 as the input of ACMP1,1: Select P3.2 as the input of ACMP1,?,?"
newline
bitfld.long 0x28 19. "CH31TOFF1,Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x28 18. "CH21TOFF1,Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 17. "CH11TOFF1,Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x28 16. "CH01TOFF1,Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application\nNote: only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 15. "ACCNT1,Hardware Auto Clear CE1 When ACMP1 Trigger It\n" "0: Enabled,1: Disabled"
bitfld.long 0x28 14. "ACCNT0,Hardware Auto Clear CE0 When ACMP0 Trigger It\n" "0: Enabled,1: Disabled"
newline
bitfld.long 0x28 13. "PWM5,PWM Channel 5 Output Enable Control\n" "0: Output D5 specified in bit 5 of PHCHG register,1: Output the original channel 5 waveform"
bitfld.long 0x28 12. "PWM4,PWM Channel 4 Output Enable Control\n" "0: Output D4 specified in bit 4 of PHCHG register,1: Output the original channel 4 waveform"
newline
bitfld.long 0x28 11. "PWM3,PWM Channel 3 Output Enable Control\n" "0: Output D3 specified in bit 3 of PHCHG register,1: Output the original channel 3 waveform"
bitfld.long 0x28 10. "PWM2,PWM Channel 2 Output Enable Control\n" "0: Output D2 specified in bit 2 of PHCHG register,1: Output the original channel 2 waveform"
newline
bitfld.long 0x28 9. "PWM1,PWM Channel 1 Output Enable Control\n" "0: Output D1 specified in bit 1 of PHCHG register,1: Output the original channel 1 waveform"
bitfld.long 0x28 8. "PWM0,PWM Channel 0 Output Enable Control\n" "0: Output D0 specified in bit 0 of PHCHG register,1: Output the original channel 0 waveform"
newline
bitfld.long 0x28 7. "D7,D7: When MASK7 Is 1 Channel 7's Output Waveform Is D7\n" "0: Output low,1: Output high"
bitfld.long 0x28 6. "D6,D6: When MASK6 Is 1 Channel 6's Output Waveform Is D6\n" "0: Output low,1: Output high"
newline
bitfld.long 0x28 5. "D5,D5: When PWM5 Is Zero Channel 5's Output Waveform Is D5\n" "0: Output low,1: Output high"
bitfld.long 0x28 4. "D4,D4: When PWM4 Is Zero Channel 4's Output Waveform Is D4\n" "0: Output low,1: Output high"
newline
bitfld.long 0x28 3. "D3,D3: When PWM3 Is Zero Channel 3's Output Waveform Is D3\n" "0: Output low,1: Output high"
bitfld.long 0x28 2. "D2,D2: When PWM2 Is Zero Channel 2's Output Waveform Is D2\n" "0: Output low,1: Output high"
newline
bitfld.long 0x28 1. "D1,D1: When PWM1 Is Zero Channel 1's Output Waveform Is D1\n" "0: Output low,1: When PWM1 Is Zero"
bitfld.long 0x28 0. "D0,D0: When PWM0 Is Zero Channel 0's Output Waveform Is D0\n" "0: When PWM0 Is Zero,1: Output high"
line.long 0x2C "PHCHGMASK,Phase Change MASK Register"
bitfld.long 0x2C 9. "CMPMASK1,MASK For ACMP1\nNote: Register CMP1CR is describe in Comparator Controller chapter" "0: The input of ACMP is controlled by CMP1CR,1: The input of ACMP is controlled by CMP1SEL of.."
bitfld.long 0x2C 8. "CMPMASK0,MASK For ACMP0 \nNote: Register CMP0CR is describe in Comparator Controller chapter" "0: The input of ACMP is controlled by CMP0CR,1: The input of ACMP is controlled by CMP0SEL of.."
newline
bitfld.long 0x2C 7. "MASK7,MASK For D7 \n" "0: Original GPIO P0.0,1: D7"
bitfld.long 0x2C 6. "MASK6,MASK For D6 \n" "0: Original GPIO P0.1,1: D6"
line.long 0x30 "INTACCUCTL,Period Interrupt Accumulation Control Register"
hexmask.long.byte 0x30 4.--7. 1. "PERIODCNT,Interrupt Accumulation Bits\nWhen INTACCUEN0 is set PERIODCNT will decrease when every PWMPIF0 flag is set and when PERIODCNT reach to zero the PWM0 interrupt will occurred and PERIODCNT will reload itself."
bitfld.long 0x30 0. "INTACCUEN0,Interrupt Accumulation Function Enable Control\n" "0: Disabled,1: Enabled"
endif
sif (cpuis("MINI5?AN"))
group.long 0x0++0x3B
line.long 0x0 "PPR,PWM Pre-scale Register"
hexmask.long.byte 0x0 16.--23. 1. "CP45,Clock Prescaler 4 (PWM Counter 4 5 for group)\nClock input is divided by (CP45 + 1) before it is fed to the corresponding PWM counter.\n"
hexmask.long.byte 0x0 8.--15. 1. "CP23,Clock Prescaler 2 (PWM Counter 2 3 for group)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter.\n"
newline
hexmask.long.byte 0x0 0.--7. 1. "CP01,Clock Prescaler 0 (PWM Counter 0 1 for group)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter.\n"
line.long 0x4 "CSR,PWM Clock Select Register"
bitfld.long 0x4 20.--22. "CSR5,Timer 5 Clock Source Selection\n" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 16.--18. "CSR4,Timer 4 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 12.--14. "CSR3,Timer 3 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 8.--10. "CSR2,Timer 2 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4.--6. "CSR1,Timer 1 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "CSR0,Timer 0 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7"
line.long 0x8 "PCR,PWM Control Register"
bitfld.long 0x8 31. "PWMTYPE,PWM Aligned Type Selection Bit\n" "0: Edge-aligned type,1: Center-aligned type"
bitfld.long 0x8 30. "GRP,Group bit\n" "0: The signals timing of PWM0 PWM2 and PWM4 are..,1: Unify the signals timing of PWM0 PWM2 and PWM4.."
newline
bitfld.long 0x8 28.--29. "PWMMOD,PWM Operating Mode Selection\n" "0,1,2,3"
bitfld.long 0x8 27. "CLRPWM,Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware." "0: Do not clear PWM counter,1: 16-bit PWM counter cleared to 0x000"
newline
bitfld.long 0x8 26. "DZEN45,Dead-zone 4 Generator Enable/Disable (PWM4 and PWM5 pair for PWM group)\nNote: When the dead-zone generator is enabled the pair of PWM4 and PWM5 becomes a complementary pair for PWM group." "0: Disabled,1: Enabled"
bitfld.long 0x8 25. "DZEN23,Dead-zone 2 Generator Enable/Disable (PWM2 and PWM3 pair for PWM group)\nNote: When the dead-zone generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group." "0: Disabled,1: Enabled"
newline
bitfld.long 0x8 24. "DZEN01,Dead-zone 0 Generator Enable/Disable (PWM0 and PWM1 pair for PWM group)\nNote: When the dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group." "0: Disabled,1: Enabled"
bitfld.long 0x8 23. "CH5MOD,PWM-Timer 5 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CNR5 and CMR5 cleared." "0: One-shot mode,1: Auto-reload mode"
newline
bitfld.long 0x8 22. "CH5INV,PWM-Timer 5 Output Inverter ON/OFF\nNote: Only even channels (PWM0 PWM2 and PWM4) can be set as inverter bit in independent mode." "0: Inverter OFF,1: Inverter ON"
bitfld.long 0x8 20. "CH5EN,PWM-Timer 5 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
newline
bitfld.long 0x8 19. "CH4MOD,PWM-Timer 4 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CNR4 and CMR4 cleared." "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 18. "CH4INV,PWM-Timer 4 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
newline
bitfld.long 0x8 16. "CH4EN,PWM-Timer 4 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
bitfld.long 0x8 15. "CH3MOD,PWM-Timer 3 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CNR3 and CMR3 cleared." "0: One-shot mode,1: Auto-reload mode"
newline
bitfld.long 0x8 14. "CH3INV,PWM-Timer 3 Output Inverter ON/OFF\nNote: Only even channels (PWM0 PWM2 and PWM4) can be set as inverter bit in independent mode." "0: Inverter OFF,1: Inverter ON"
bitfld.long 0x8 12. "CH3EN,PWM-Timer 3 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
newline
bitfld.long 0x8 11. "CH2MOD,PWM-Timer 2 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CNR2 and CMR2 cleared." "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 10. "CH2INV,PWM-Timer 2 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
newline
bitfld.long 0x8 8. "CH2EN,PWM-Timer 2 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
bitfld.long 0x8 7. "CH1MOD,PWM-Timer 1 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CNR1 and CMR1 cleared." "0: One-shot mode,1: Auto-reload mode"
newline
bitfld.long 0x8 6. "CH1INV,PWM-Timer 1 Output Inverter ON/OFF\nNote: Only even channels (PWM0 PWM2 and PWM4) can be set as inverter bit in independent mode." "0: Inverter OFF,1: Inverter ON"
bitfld.long 0x8 4. "CH1EN,PWM-Timer 1 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
newline
bitfld.long 0x8 3. "CH0MOD,PWM-Timer 0 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CNR0 and CMR0 cleared." "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 2. "CH0INV,PWM-Timer 0 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
newline
bitfld.long 0x8 1. "DB_MODE,PWM Debug Mode Configuration Bit (Available in DEBUG mode only)\n" "0: Safe mode: The timer is frozen and PWM outputs..,1: Normal mode: The timer continues to operate.."
bitfld.long 0x8 0. "CH0EN,PWM-Timer 0 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
line.long 0xC "CNR0,PWM Counter Register 0"
hexmask.long.word 0xC 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value\nCNRn determines the PWM period.\nEdge-aligned mode:\nNote: Any write to CNRn will take effect in next PWM cycle."
line.long 0x10 "CNR1,PWM Counter Register 1"
hexmask.long.word 0x10 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value\nCNRn determines the PWM period.\nEdge-aligned mode:\nNote: Any write to CNRn will take effect in next PWM cycle."
line.long 0x14 "CNR2,PWM Counter Register 2"
hexmask.long.word 0x14 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value\nCNRn determines the PWM period.\nEdge-aligned mode:\nNote: Any write to CNRn will take effect in next PWM cycle."
line.long 0x18 "CNR3,PWM Counter Register 3"
hexmask.long.word 0x18 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value\nCNRn determines the PWM period.\nEdge-aligned mode:\nNote: Any write to CNRn will take effect in next PWM cycle."
line.long 0x1C "CNR4,PWM Counter Register 4"
hexmask.long.word 0x1C 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value\nCNRn determines the PWM period.\nEdge-aligned mode:\nNote: Any write to CNRn will take effect in next PWM cycle."
line.long 0x20 "CNR5,PWM Counter Register 5"
hexmask.long.word 0x20 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value\nCNRn determines the PWM period.\nEdge-aligned mode:\nNote: Any write to CNRn will take effect in next PWM cycle."
line.long 0x24 "CMR0,PWM Comparator Register 0"
hexmask.long.word 0x24 0.--15. 1. "CMRn,PWM Comparator Register\nCMR determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMRn will take effect in next PWM cycle."
line.long 0x28 "CMR1,PWM Comparator Register 1"
hexmask.long.word 0x28 0.--15. 1. "CMRn,PWM Comparator Register\nCMR determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMRn will take effect in next PWM cycle."
line.long 0x2C "CMR2,PWM Comparator Register 2"
hexmask.long.word 0x2C 0.--15. 1. "CMRn,PWM Comparator Register\nCMR determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMRn will take effect in next PWM cycle."
line.long 0x30 "CMR3,PWM Comparator Register 3"
hexmask.long.word 0x30 0.--15. 1. "CMRn,PWM Comparator Register\nCMR determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMRn will take effect in next PWM cycle."
line.long 0x34 "CMR4,PWM Comparator Register 4"
hexmask.long.word 0x34 0.--15. 1. "CMRn,PWM Comparator Register\nCMR determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMRn will take effect in next PWM cycle."
line.long 0x38 "CMR5,PWM Comparator Register 5"
hexmask.long.word 0x38 0.--15. 1. "CMRn,PWM Comparator Register\nCMR determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMRn will take effect in next PWM cycle."
group.long 0x54++0x33
line.long 0x0 "PIER,PWM Interrupt Enable Register"
bitfld.long 0x0 17. "INT_TYPE,PWM Interrupt Type Selection Bit\nNote: This bit is effective when PWM in central align mode only." "0: PWMPIFn will be set if PWM counter underflows,1: PWMPIFn will be set if PWM counter matches CNRn.."
bitfld.long 0x0 16. "BRKIE,Enable Fault Brake0 and 1 Interrupt\n" "0: Disabling flags BKF0 and BKF1 to trigger PWM..,1: Enabling flags BKF0 and BKF1 can trigger PWM.."
newline
bitfld.long 0x0 13. "PWMDIE5,PWM Channel 5 Duty Interrupt Enable\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 12. "PWMDIE4,PWM Channel 4 Duty Interrupt Enable\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 11. "PWMDIE3,PWM Channel 3 Duty Interrupt Enable\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "PWMDIE2,PWM Channel 2 Duty Interrupt Enable\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 9. "PWMDIE1,PWM Channel 1 Duty Interrupt Enable\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 8. "PWMDIE0,PWM Channel 0 Duty Interrupt Enable\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "PWMPIE5,PWM Channel 5 Period Interrupt Enable\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "PWMPIE4,PWM Channel 4 Period Interrupt Enable\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 3. "PWMPIE3,PWM Channel 3 Period Interrupt Enable\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 2. "PWMPIE2,PWM Channel 2 Period Interrupt Enable\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "PWMPIE1,PWM Channel 1 Period Interrupt Enable\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "PWMPIE0,PWM Channel 0 Period Interrupt Enable\n" "0: Disabled,1: Enabled"
line.long 0x4 "PIIR,PWM Interrupt Indication Register"
bitfld.long 0x4 17. "BKF1,PWM Brake1 Flag\nNote: Software can write 1 to clear this bit." "0: PWM Brake does not recognize a falling signal at..,1: When PWM Brake detects a falling signal at pin.."
bitfld.long 0x4 16. "BKF0,PWM Brake0 Flag\nNote: Software can write 1 to clear this bit." "0: PWM Brake does not recognize a falling signal at..,1: When PWM Brake detects a falling signal at pin.."
newline
bitfld.long 0x4 13. "PWMDIF5,PWM channel 5 Duty Interrupt Flag\nFlag is set by hardware when a channel 5 PWM counter reaches CMR5. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 12. "PWMDIF4,PWM channel 4 Duty Interrupt Flag\nFlag is set by hardware when a channel 4 PWM counter reaches CMR4. Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 11. "PWMDIF3,PWM channel 3 Duty Interrupt Flag\nFlag is set by hardware when a channel 3 PWM counter reaches CMR3. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 10. "PWMDIF2,PWM channel 2 Duty Interrupt Flag\nFlag is set by hardware when a channel 2 PWM counter reaches CMR2. Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 9. "PWMDIF1,PWM channel 1 Duty Interrupt Flag\nFlag is set by hardware when a channel 1 PWM counter reaches CMR1. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 8. "PWMDIF0,PWM channel 0 Duty Interrupt Flag\nFlag is set by hardware when a channel 0 PWM counter reaches CMR0. Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 5. "PWMPIF5,PWM channel 5 Period Interrupt Flag\nFlag is set by hardware when CNR5 down counter reaches zero. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 4. "PWMPIF4,PWM channel 4 Period Interrupt Flag\nFlag is set by hardware when CNR4 down counter reaches zero. Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 3. "PWMPIF3,PWM channel 3 Period Interrupt Flag\nFlag is set by hardware when CNR3 down counter reaches zero. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 2. "PWMPIF2,PWM channel 2 Period Interrupt Flag\nFlag is set by hardware when CNR2 down counter reaches zero. Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x4 1. "PWMPIF1,PWM channel 1 Period Interrupt Flag\nFlag is set by hardware when CNR1 down counter reaches zero. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 0. "PWMPIF0,PWM channel 0 Period Interrupt Flag\nFlag is set by hardware when CNR0 down counter reaches zero. Software can write 1 to clear this bit." "0,1"
line.long 0x8 "PWMPOE,PWM Output Enable for Channel 0~5"
bitfld.long 0x8 5. "PWM5,PWM Channel 5 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function." "0: PWM channel 5 output to pin Disabled,1: PWM channel 5 output to pin Enabled"
bitfld.long 0x8 4. "PWM4,PWM Channel 4 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function." "0: PWM channel 4 output to pin Disabled,1: PWM channel 4 output to pin Enabled"
newline
bitfld.long 0x8 3. "PWM3,PWM Channel 3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function." "0: PWM channel 3 output to pin Disabled,1: PWM channel 3 output to pin Enabled"
bitfld.long 0x8 2. "PWM2,PWM Channel 2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function." "0: PWM channel 2 output to pin Disabled,1: PWM channel 2 output to pin Enabled"
newline
bitfld.long 0x8 1. "PWM1,PWM Channel 1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function." "0: PWM channel 1 output to pin Disabled,1: PWM channel 1 output to pin Enabled"
bitfld.long 0x8 0. "PWM0,PWM Channel 0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function." "0: PWM channel 0 output to pin Disabled,1: PWM channel 0 output to pin Enabled"
line.long 0xC "PFBCON,PWM Fault Brake Control Register"
bitfld.long 0xC 31. "D7BKO7,D7 Brake Output Select Register\n" "0: D7 output low when fault brake conditions asserted,1: D7 output high when fault brake conditions.."
bitfld.long 0xC 30. "D6BKO6,D6 Brake Output Select Register\n" "0: D6 output low when fault brake conditions asserted,1: D6 output high when fault brake conditions.."
newline
bitfld.long 0xC 29. "PWMBKO5,PWM Channel 5 Brake Output Select Register\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
bitfld.long 0xC 28. "PWMBKO4,PWM Channel 4 Brake Output Select Register\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
newline
bitfld.long 0xC 27. "PWMBKO3,PWM Channel 3 Brake Output Select Register\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
bitfld.long 0xC 26. "PWMBKO2,PWM Channel 2 Brake Output Select Register\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
newline
bitfld.long 0xC 25. "PWMBKO1,PWM Channel 1 Brake Output Select Register\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
bitfld.long 0xC 24. "PWMBKO0,PWM Channel 0 Brake Output Select Register\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
newline
bitfld.long 0xC 7. "BKF,PWM Fault Brake Event Flag (write 1 clear)\nSoftware can write 1 to clear this bit" "0: PWM output initial state when fault brake..,1: PWM output fault brake state when fault brake.."
bitfld.long 0xC 2. "CPO0BKEN,BKP1 Fault Brake Function Source Selection\n" "0: EINT1 as one brake source in BKP1,1: CPO0 as one brake source in BKP1"
newline
bitfld.long 0xC 1. "BKEN1,Enable BKP1 Pin Trigger Fault Brake Function 1\n" "0: Disabling BKP1 pin can trigger brake function 1..,1: Enabling a falling at BKP1 pin can trigger brake.."
bitfld.long 0xC 0. "BKEN0,Enable BKP0 Pin Trigger Fault Brake Function 0\n" "0: Disabling BKP0 pin can trigger brake function 0..,1: Enabling a falling at BKP0 pin can trigger brake.."
line.long 0x10 "PDZIR,PWM Dead-zone Interval Register"
hexmask.long.byte 0x10 16.--23. 1. "DZI45,Dead-zone Interval Register for Pair of Channel4 and Channel5 (PWM4 and PWM5 pair).\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits."
hexmask.long.byte 0x10 8.--15. 1. "DZI23,Dead-zone Interval Register for Pair of Channel2 and Channel3 (PWM2 and PWM3 pair).\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits."
newline
hexmask.long.byte 0x10 0.--7. 1. "DZI01,Dead-zone Interval Register for Pair of Channel0 and Channel1 (PWM0 and PWM1 pair).\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits."
line.long 0x14 "TRGCON0,PWM Trigger Control Register 0"
bitfld.long 0x14 27. "P3TRGEN,Enable PWM trigger ADC function while Channel1's counter matching 0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x14 26. "CM3TRGFEN,Enable PWM trigger ADC function while Channel3's counter matching CMR3 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 25. "CNT3TRGEN,Enable PWM trigger ADC function while Channel3's counter matching CNR3 in down-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take.." "0: Disabled,1: Enabled"
bitfld.long 0x14 24. "CM3TRGREN,Enable PWM trigger ADC function while Channel3's counter matching CMR3 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 19. "P2TRGEN,Enable PWM trigger ADC function while Channel2's counter matching 0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x14 18. "CM2TRGFEN,Enable PWM trigger ADC function while Channel2's counter matching CMR2 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 17. "CNT2TRGEN,Enable PWM trigger ADC function while Channel2's counter matching CNR2 in down-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take.." "0: Disabled,1: Enabled"
bitfld.long 0x14 16. "CM2TRGREN,Enable PWM trigger ADC function while Channel2's counter matching CMR2 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 11. "P1TRGEN,Enable PWM trigger ADC function while Channel1's counter matching 0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x14 10. "CM1TRGFEN,Enable PWM trigger ADC function while Channel1's counter matching CMR1 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 9. "CNT1TRGEN,Enable PWM trigger ADC function while Channel1's counter matching CNR1 in down-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take.." "0: Disabled,1: Enabled"
bitfld.long 0x14 8. "CM1TRGREN,Enable PWM trigger ADC function while Channel1's counter matching CMR1 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 3. "P0TRGEN,Enable PWM trigger ADC function while Channel0's counter matching 0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x14 2. "CM0TRGFEN,Enable PWM trigger ADC function while Channel0's counter matching CMR0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 1. "CNT0TRGEN,Enable PWM trigger ADC function while Channel0's counter matching CNR0 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled"
bitfld.long 0x14 0. "CM0TRGREN,Enable PWM trigger ADC function while Channel0's counter matching CMR0 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled"
line.long 0x18 "TRGCON1,PWM Trigger Control Register 1"
bitfld.long 0x18 11. "P5TRGEN,Enable PWM trigger ADC function while Channel5's counter matching 0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x18 10. "CM5TRGFEN,Enable PWM trigger ADC function while Channel5's counter matching CMR5 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x18 9. "CNT5TRGEN,Enable PWM trigger ADC function while Channel5's counter matching CNR5 in down-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take.." "0: Disabled,1: Enabled"
bitfld.long 0x18 8. "CM5TRGREN,Enable PWM trigger ADC function while Channel5's counter matching CMR5 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled"
newline
bitfld.long 0x18 3. "P4TRGEN,Enable PWM trigger ADC function while Channel4's counter matching 0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
bitfld.long 0x18 2. "CM4TRGFEN,Enable PWM trigger ADC function while Channel4's counter matching CMR4 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x18 1. "CNT4TRGEN,Enable PWM trigger ADC function while Channel4's counter matching CNR4 in down-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take.." "0: Disabled,1: Enabled"
bitfld.long 0x18 0. "CM4TRGREN,Enable PWM trigger ADC function while Channel4's counter matching CMR4 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled"
line.long 0x1C "TRGSTS0,PWM Trigger Status Register 0"
bitfld.long 0x1C 27. "PERID3FLAG,ADC trigger flag by period \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 26. "CMR3FLAG_F,ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 25. "CNT3FLAG,ADC trigger flag by counting to CNR\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 24. "CMR3FLAG_R,ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 19. "PERID2FLAG,ADC trigger flag by period \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 18. "CMR2FLAG_F,ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 17. "CNT2FLAG,ADC trigger flag by counting to CNR\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 16. "CMR2FLAG_R,ADC trigger flag by counting up to CMR \nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 11. "PERID1FLAG,ADC trigger flag by period \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 10. "CMR1FLAG_F,ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 9. "CNT1FLAG,ADC trigger flag by counting to CNR\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 8. "CMR1FLAG_R,ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 3. "PERID0FLAG,ADC trigger flag by period \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 2. "CMR0FLAG_F,ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x1C 1. "CNT0FLAG,ADC trigger flag by counting to CNR\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x1C 0. "CMR0FLAG_R,ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit." "0,1"
line.long 0x20 "TRGSTS1,PWM Trigger Status Register 1"
bitfld.long 0x20 11. "PERID5FLAG,ADC trigger flag by period \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x20 10. "CMR5FLAG_F,ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x20 9. "CNT5FLAG,ADC trigger flag by counting to CNR\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x20 8. "CMR5FLAG_R,ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x20 3. "PERID4FLAG,ADC trigger flag by period \nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x20 2. "CMR4FLAG_F,ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit." "0,1"
newline
bitfld.long 0x20 1. "CNT4FLAG,ADC trigger flag by counting to CNR\nNote: Software can write 1 to clear this bit." "0,1"
bitfld.long 0x20 0. "CMR4FLAG_R,ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit." "0,1"
line.long 0x24 "PHCHG,Phase Changed Register"
bitfld.long 0x24 31. "CE0,Enable ACPM0 Trigger Function\nNote: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set." "0: Disabled,1: Enabled"
bitfld.long 0x24 30. "T0,Enable Timer0 trigger PWM function\nWhen this bit is set timer0 time-out event will update PHCHG with PHCHG_NXT register." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 28.--29. "CMP0SEL,CMP0SEL\nSelect the input source of ACMP0.\n" "0: Select P1.5 as the input of ACMP0,1: Select P1.0 as the input of ACMP0,?,?"
bitfld.long 0x24 27. "CH31TOFF0,Setting this bit will Force PWM3 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application.\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 26. "CH21TOFF0,Setting this bit will Force PWM2 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x24 25. "CH11TOFF0,Setting this bit will Force PWM1 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application.\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 24. "CH01TOFF0,Setting this bit will Force PWM0 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application.\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x24 23. "CE1,Enable ACPM1 Trigger Function\nNote: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 22. "T1,Enable Timer1 Trigger PWM Function\nWhen this bit is set timer1 time-out event will update PHCHG with PHCHG_NXT register." "0: Disabled,1: Enabled"
bitfld.long 0x24 20.--21. "CMP1SEL,CMP1SEL\nSelect the input source of ACMP1.\n" "0: Select P3.1 as the input of ACMP1,1: Select P3.2 as the input of ACMP1,?,?"
newline
bitfld.long 0x24 19. "CH31TOFF1,Setting this bit will Force PWM3 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application.\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x24 18. "CH21TOFF1,Setting this bit will Force PWM2 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application.\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 17. "CH11TOFF1,Setting this bit will Force PWM1 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application.\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x24 16. "CH01TOFF1,Setting this bit will Force PWM0 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application.\nNote: only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x24 15. "ACCNT1,Hardware auto clear CE1 when ACMP1 trigger it.\n" "0: Enabled,1: Disabled"
bitfld.long 0x24 14. "ACCNT0,Hardware auto clear CE0 when ACMP0 trigger it.\n" "0: Enabled,1: Disabled"
newline
bitfld.long 0x24 13. "PWM5,PWM channel 5 output enable control.\n" "0: Output the original channel 5 waveform,1: Output D5 specified in bit 5 of PHCHG register"
bitfld.long 0x24 12. "PWM4,PWM channel 4 output enable control.\n" "0: Output the original channel 4 waveform,1: Output D4 specified in bit 4 of PHCHG register"
newline
bitfld.long 0x24 11. "PWM3,PWM channel 3 output enable control.\n" "0: Output the original channel 3 waveform,1: Output D3 specified in bit 3 of PHCHG register"
bitfld.long 0x24 10. "PWM2,PWM channel 2 output enable control.\n" "0: Output the original channel 2 waveform,1: Output D2 specified in bit 2 of PHCHG register"
newline
bitfld.long 0x24 9. "PWM1,PWM channel 1 output enable control.\n" "0: Output the original channel 1 waveform,1: Output D1 specified in bit 1 of PHCHG register"
bitfld.long 0x24 8. "PWM0,PWM channel 0 output enable control.\n" "0: Output the original channel 0 waveform,1: Output D0 specified in bit 0 of PHCHG register"
newline
bitfld.long 0x24 7. "D7,D7: when MASK1 is 1 channel 7's output waveform is D7.\n" "0: Output low,1: Output high"
bitfld.long 0x24 6. "D6,D6: when MASK6 is 1 channel 6's output waveform is D6.\n" "0: Output low,1: Output high"
newline
bitfld.long 0x24 5. "D5,D5: when PWM5 is zero channel 5's output waveform is D5.\n" "0: Output low,1: Output high"
bitfld.long 0x24 4. "D4,D4: when PWM4 is zero channel 4's output waveform is D4.\n" "0: Output low,1: Output high"
newline
bitfld.long 0x24 3. "D3,D3: when PWM3 is zero channel 3's output waveform is D3.\n" "0: Output low,1: Output high"
bitfld.long 0x24 2. "D2,D2: when PWM2 is zero channel 2's output waveform is D2.\n" "0: Output low,1: Output high"
newline
bitfld.long 0x24 1. "D1,D1: when PWM1 is zero channel 1's output waveform is D1.\n" "0: Output low,1: when PWM1 is zero"
bitfld.long 0x24 0. "D0,D0: when PWM0 is zero channel 0's output waveform is D0.\n" "0: when PWM0 is zero,1: Output high"
line.long 0x28 "PHCHGNXT,Next Phase Change Register"
bitfld.long 0x28 31. "CE0,Enable ACPM0 Trigger Function\nNote: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set." "0: Disabled,1: Enabled"
bitfld.long 0x28 30. "T0,Enable Timer0 trigger PWM function\nWhen this bit is set timer0 time-out event will update PHCHG with PHCHG_NXT register." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 28.--29. "CMP0SEL,CMP0SEL\nSelect the input source of ACMP0.\n" "0: Select P1.5 as the input of ACMP0,1: Select P1.0 as the input of ACMP0,?,?"
bitfld.long 0x28 27. "CH31TOFF0,Setting this bit will Force PWM3 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application.\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 26. "CH21TOFF0,Setting this bit will Force PWM2 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x28 25. "CH11TOFF0,Setting this bit will Force PWM1 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application.\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 24. "CH01TOFF0,Setting this bit will Force PWM0 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application.\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x28 23. "CE1,Enable ACPM1 Trigger Function\nNote: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 22. "T1,Enable Timer1 Trigger PWM Function\nWhen this bit is set timer1 time-out event will update PHCHG with PHCHG_NXT register." "0: Disabled,1: Enabled"
bitfld.long 0x28 20.--21. "CMP1SEL,CMP1SEL\nSelect the input source of ACMP1.\n" "0: Select P3.1 as the input of ACMP1,1: Select P3.2 as the input of ACMP1,?,?"
newline
bitfld.long 0x28 19. "CH31TOFF1,Setting this bit will Force PWM3 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application.\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x28 18. "CH21TOFF1,Setting this bit will Force PWM2 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application.\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 17. "CH11TOFF1,Setting this bit will Force PWM1 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application.\nNote: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
bitfld.long 0x28 16. "CH01TOFF1,Setting this bit will Force PWM0 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application.\nNote: only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled"
newline
bitfld.long 0x28 15. "ACCNT1,Hardware auto clear CE1 when ACMP1 trigger it.\n" "0: Enabled,1: Disabled"
bitfld.long 0x28 14. "ACCNT0,Hardware auto clear CE0 when ACMP0 trigger it.\n" "0: Enabled,1: Disabled"
newline
bitfld.long 0x28 13. "PWM5,PWM channel 5 output enable control.\n" "0: Output the original channel 5 waveform,1: Output D5 specified in bit 5 of PHCHG register"
bitfld.long 0x28 12. "PWM4,PWM channel 4 output enable control.\n" "0: Output the original channel 4 waveform,1: Output D4 specified in bit 4 of PHCHG register"
newline
bitfld.long 0x28 11. "PWM3,PWM channel 3 output enable control.\n" "0: Output the original channel 3 waveform,1: Output D3 specified in bit 3 of PHCHG register"
bitfld.long 0x28 10. "PWM2,PWM channel 2 output enable control.\n" "0: Output the original channel 2 waveform,1: Output D2 specified in bit 2 of PHCHG register"
newline
bitfld.long 0x28 9. "PWM1,PWM channel 1 output enable control.\n" "0: Output the original channel 1 waveform,1: Output D1 specified in bit 1 of PHCHG register"
bitfld.long 0x28 8. "PWM0,PWM channel 0 output enable control.\n" "0: Output the original channel 0 waveform,1: Output D0 specified in bit 0 of PHCHG register"
newline
bitfld.long 0x28 7. "D7,D7: when MASK1 is 1 channel 7's output waveform is D7.\n" "0: Output low,1: Output high"
bitfld.long 0x28 6. "D6,D6: when MASK6 is 1 channel 6's output waveform is D6.\n" "0: Output low,1: Output high"
newline
bitfld.long 0x28 5. "D5,D5: when PWM5 is zero channel 5's output waveform is D5.\n" "0: Output low,1: Output high"
bitfld.long 0x28 4. "D4,D4: when PWM4 is zero channel 4's output waveform is D4.\n" "0: Output low,1: Output high"
newline
bitfld.long 0x28 3. "D3,D3: when PWM3 is zero channel 3's output waveform is D3.\n" "0: Output low,1: Output high"
bitfld.long 0x28 2. "D2,D2: when PWM2 is zero channel 2's output waveform is D2.\n" "0: Output low,1: Output high"
newline
bitfld.long 0x28 1. "D1,D1: when PWM1 is zero channel 1's output waveform is D1.\n" "0: Output low,1: when PWM1 is zero"
bitfld.long 0x28 0. "D0,D0: when PWM0 is zero channel 0's output waveform is D0.\n" "0: when PWM0 is zero,1: Output high"
line.long 0x2C "PHCHGMASK,Phase Change MASK Register"
bitfld.long 0x2C 9. "CMPMASK1,MASK for ACMP1\n" "0: The input of ACMP is controlled by CMP1CR,1: The input of ACMP is controlled by CMP1SEL of.."
bitfld.long 0x2C 8. "CMPMASK0,MASK for ACMP0 \n" "0: The input of ACMP is controlled by CMP0CR,1: The input of ACMP is controlled by CMP0SEL of.."
newline
bitfld.long 0x2C 7. "MASK7,MASK for D7 \n" "0: Original GPIO P0.0,1: D7"
bitfld.long 0x2C 6. "MASK6,MASK for D6 \n" "0: Original GPIO P0.1,1: D6"
line.long 0x30 "INTACCUCTL,Period Interrupt Accumulation Control Register"
hexmask.long.byte 0x30 4.--7. 1. "PERIODCNT,Interrupt Accumulation Register\nWhen INTACCUEN0 is set PERIODCNT will decrease when every PWMPIF0 flag is set and when PERIODCNT reach to zero the PWM0 interrupt will occurred and PERIODCNT will reload itself."
bitfld.long 0x30 0. "INTACCUEN0,Enable Interrupt Accumulation Function\n" "0: Disabled,1: Enabled"
endif
tree.end
tree "FMC (Flash Memory Controller)"
base ad:0x5000C000
sif (cpuis("MINI5?XAE"))
group.long 0x0++0x13
line.long 0x0 "FMC_ISPCTL,ISP Control Register"
bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself. \n(3) Destination address is illegal such as over.." "0,1"
bitfld.long 0x0 5. "LDUEN,LDROM Update Enable Control (Write Protect)" "0: LDROM cannot be updated,1: LDROM can be updated when the MCU runs in APROM"
newline
bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable Control (Write Protect)\nWriting this bit to 1 enables software to update CONFIG value by ISP register control procedure regardless of program code is running in APROM or LDROM." "0: ISP update User Configuration Disabled,1: ISP update User Configuration Enabled"
bitfld.long 0x0 3. "APUEN,APROM Update Enable Control (Write Protect)" "0: APROM cannot be updated when chip runs in APROM,1: APROM can be updated when chip runs in APROM"
newline
bitfld.long 0x0 1. "BS,Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as chip booting status flag which can be used to check where chip booted from. This bit is initiated with the inversed.." "0: Boot from APROM,1: Boot from LDROM"
bitfld.long 0x0 0. "ISPEN,ISP Enable Control (Write Protect)\nSet this bit to enable ISP function." "0: ISP function Disabled,1: ISP function Enabled"
line.long 0x4 "FMC_ISPADDR,ISP Address Register"
hexmask.long 0x4 0.--31. 1. "ISPADR,ISP Address\nThe NuMicroTM MINI51X series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation."
line.long 0x8 "FMC_ISPDAT,ISP Data Register"
hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation."
line.long 0xC "FMC_ISPCMD,ISP Command Register"
hexmask.long.byte 0xC 0.--5. 1. "CMD,ISP Command \nISP commands are shown below:"
line.long 0x10 "FMC_ISPTRG,ISP Trigger Register"
bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished." "0: ISP operation is finished,1: ISP operation is progressed"
rgroup.long 0x14++0x3
line.long 0x0 "FMC_DFBA,Data Flash Start Address"
hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nThe data flash start address is defined by user. Since on chip flash erase unit is 512 bytes it is mandatory to keep bit 8-0 as 0."
group.long 0x40++0x3
line.long 0x0 "FMC_ISPSTS,ISP Status Register"
hexmask.long.word 0x0 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0] 9'h000} ~ {VECMAP[11:0] 9'h1FF}."
bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write-Protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is.." "0,1"
newline
rbitfld.long 0x0 1.--2. "CBS,Config Boot Selection (Read Only)\nThis is a mirror of CBS in CONFIG0." "0,1,2,3"
rbitfld.long 0x0 0. "ISPBUSY,ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same with FMC_ISPTRG bit 0." "0: ISP operation is finished,1: ISP operation is progressed"
endif
sif (cpuis("MINI5??DE"))
group.long 0x0++0x13
line.long 0x0 "ISPCON,ISP Control Register"
bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(3) User Configuration is erased/programmed when CFGUEN is 0.\n(4) Destination address is illegal such as over an available.." "0,1"
bitfld.long 0x0 5. "LDUEN,LDROM Update Enable Control (Write Protect)\n" "0: LDROM cannot be updated,1: LDROM can be updated when the MCU runs in APROM"
newline
bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable Control (Write Protect)\nWriting this bit to 1 enables software to update CONFIG value by ISP register control procedure regardless of program code is running in APROM or LDROM.\n" "0: ISP update User Configuration Disabled,1: ISP update User Configuration Enabled"
bitfld.long 0x0 3. "APUEN,APROM Update Enable Control (Write Protect)\n" "0: APROM cannot be updated when chip runs in APROM,1: APROM can be updated when chip runs in APROM"
newline
bitfld.long 0x0 1. "BS,Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as chip booting status flag which can be used to check where chip booted from. This bit is initiated with the inversed.." "0: Boot from APROM,1: Boot from LDROM"
bitfld.long 0x0 0. "ISPEN,ISP Enable Control (Write Protect)\nSet this bit to enable ISP function.\n" "0: ISP function Disabled,1: ISP function Enabled"
line.long 0x4 "ISPADR,ISP Address Register"
hexmask.long 0x4 0.--31. 1. "ISPADR,ISP Address\nThe NuMicro Mini51TM series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation."
line.long 0x8 "ISPDAT,ISP Data Register"
hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation."
line.long 0xC "ISPCMD,ISP Command Register"
hexmask.long.byte 0xC 0.--5. 1. "ISPCMD,ISP Command \nISP commands are shown below:\n"
line.long 0x10 "ISPTRG,ISP Trigger Register"
bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n" "0: ISP operation is finished,1: ISP operation is progressed"
rgroup.long 0x14++0x3
line.long 0x0 "DFBA,Data Flash Start Address"
hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash start address is defined by user. Since on chip flash erase unit is 512 bytes it is mandatory to keep bit 8-0 as 0."
group.long 0x40++0x3
line.long 0x0 "ISPSTA,ISP Status Register"
hexmask.long.word 0x0 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0] 9'h000} ~ {VECMAP[11:0] 9'h1FF}."
bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(3) User Configuration is erased/programmed when CFGUEN is 0.\n(4) Destination address is illegal such as over an available.." "0,1"
newline
rbitfld.long 0x0 1.--2. "CBS,Config Boot Selection (Read Only)\nThis is a mirror of CBS in CONFIG0." "0,1,2,3"
rbitfld.long 0x0 0. "ISPGO,ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same with ISPTRG bit 0." "0: ISP operation is finished,1: ISP operation is progressed"
endif
sif (cpuis("MINI5?AN"))
group.long 0x0++0x13
line.long 0x0 "ISPCON,ISP Control Register"
bitfld.long 0x0 12.--14. "ET,Flash Erase Time\n" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 8.--10. "PT,Flash Program Time\n" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7. "SWRST,Software Reset\nWriting 1 to this bit to start software reset.\nIt is cleared by hardware after reset is finished." "0,1"
bitfld.long 0x0 6. "ISPFF,ISP Fail Flag\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself.\n(2) LDROM writes to itself.\n(3) CONFIG is erased/programmed when the MCU is running in APROM.\n(4) Destination.." "0,1"
newline
bitfld.long 0x0 5. "LDUEN,LDROM Update Enable\n" "0: LDROM cannot be updated,1: LDROM can be updated when the MCU runs in APROM"
bitfld.long 0x0 4. "CFGUEN,Enable Config-bits Update by ISP\n" "0: Disable ISP can update config-bits,1: Enable ISP can update config-bits"
newline
bitfld.long 0x0 1. "BS,Boot Selection\nSet/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as MCU booting status flag which can be used to check where MCU booted from. This bit is initiated with the inversed value of CBS in.." "0: Boot from APROM,1: Boot from LDROM"
bitfld.long 0x0 0. "ISPEN,ISP Enable\nISP function enable bit. Set this bit to enable ISP function.\n" "0: ISP function Disabled,1: ISP function Enabled"
line.long 0x4 "ISPADR,ISP Address Register"
hexmask.long 0x4 0.--31. 1. "ISPADR,ISP Address\nThe NuMicro Mini51TM series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation."
line.long 0x8 "ISPDAT,ISP Data Register"
hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation."
line.long 0xC "ISPCMD,ISP Command Register"
hexmask.long.byte 0xC 0.--5. 1. "FOEN_FCEN_FCTRL,ISP Command\n"
line.long 0x10 "ISPTRG,ISP Trigger Register"
bitfld.long 0x10 0. "ISPGO,ISP Start Trigger\nWrite 1 to start ISP operation; this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n" "0: ISP operation finished,1: ISP on going"
rgroup.long 0x14++0x3
line.long 0x0 "DFBA,Data Flash Start Address"
hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nThe data flash start address is defined by user. Since on chip flash erase unit is 512 bytes it is mandatory to keep bit 8-0 as 0."
endif
tree.end
tree "GCR (System Global Control Registers)"
base ad:0x50000000
sif (cpuis("MINI5?XAE"))
rgroup.long 0x0++0x3
line.long 0x0 "SYS_PDID,Part Device Identification Number Register"
hexmask.long 0x0 0.--31. 1. "PDID,Product Device Identification Number\nThis register reflects the device part number code. Software can read this register to identify which device is used."
group.long 0x4++0xB
line.long 0x0 "SYS_RSTSTS,System Reset Source Register"
bitfld.long 0x0 7. "CPURF,CPU Reset Flag\nThe CPURF flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC).\nNote: Software can write 1 to clear this bit to zero." "0: No reset from CPU,1: Cortex-M0 core and FMC are reset by software.."
bitfld.long 0x0 5. "SYSRF,MCU Reset Flag\nThe SYSRF flag is set by the 'reset signal' from the Cortex-M0 core to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to zero." "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.."
newline
bitfld.long 0x0 4. "BODRF,Brown-Out Detector Reset Flag\nThe BODRF flag is set by the 'reset signal' from the Brown-out Detector to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to zero." "0: No reset from BOD,1: The BOD had issued the reset signal to reset the.."
bitfld.long 0x0 2. "WDTRF,Watchdog Reset Flag\nThe RSTS_WDT flag is set by the 'reset signal' from the Watchdog timer to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to zero." "0: No reset from Watchdog timer,1: The Watchdog timer had issued the reset signal.."
newline
bitfld.long 0x0 1. "PINRF,Reset Pin Reset Flag\nThe PINRF flag is set by the 'reset signal' from the /RESET pin to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to zero." "0: No reset from pin /RESET pin,1: The /RESET pin had issued the reset signal to.."
bitfld.long 0x0 0. "PORF,Power-On Reset Flag\nThe PORF flag is set by the 'reset signal' which is from the Power-On Reset (POR) controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to zero." "0: No reset from POR or CHIPRST,1: The Power-on-Reset (POR) or CHIPRST had issued.."
line.long 0x4 "SYS_IPRST0,Peripheral Reset Control Resister 1"
bitfld.long 0x4 2. "CPUWS,CPU Wait-State Control For Flash Memory Access\n0: Insert one wait-state when access Flash\n1: Non-insert wait-state when access Flash\nNote: When HCLK frequency is faster than 44MHz insert one wait state is necessary." "0: Insert one wait-state when access Flash\n1:..,?"
bitfld.long 0x4 1. "CPURST,CPU Kernel One Shot Reset\nSetting this bit will reset the CPU kernel and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is the protected bit and programming it needs to write 0x59 0x16 and 0x88 to address.." "0: Normal,1: Reset CPU"
newline
bitfld.long 0x4 0. "CHIPRST,CHIP One-Shot Reset (Write Protect)\nSetting this bit will reset the CHIP including CPU kernel and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is the same as the POR reset and all the chip.." "0: Chip normal operation,1: CHIP one-shot reset"
line.long 0x8 "SYS_IPRST1,Peripheral Reset Control Resister 2"
bitfld.long 0x8 28. "ADCRST,ADC Controller Reset" "0: ADC block normal operation,1: ADC block reset"
bitfld.long 0x8 22. "ACMPRST,ACMP Controller Reset" "0: ACMP block normal operation,1: ACMP block reset"
newline
bitfld.long 0x8 20. "PWMRST,PWM Controller Reset" "0: PWM block normal operation,1: PWM block reset"
bitfld.long 0x8 17. "UART1RST,UART1 Controller Reset" "0: UART1 normal operation,1: UART1 block reset"
newline
bitfld.long 0x8 16. "UART0RST,UART0 Controller Reset" "0: UART0 normal operation,1: UART0 block reset"
bitfld.long 0x8 12. "SPIRST,SPI Controller Reset" "0: SPI block normal operation,1: SPI block reset"
newline
bitfld.long 0x8 8. "I2C_RST,I2C Controller Reset" "0: I2C normal operation,1: I2C block reset"
bitfld.long 0x8 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 normal operation,1: Timer1 block reset"
newline
bitfld.long 0x8 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 normal operation,1: Timer0 block reset"
bitfld.long 0x8 1. "GPIORST,GPIO (P0~P5) Controller Reset" "0: GPIO normal operation,1: GPIO reset"
group.long 0x18++0x3
line.long 0x0 "SYS_BODCTL,Brown-out Detector Control Register"
bitfld.long 0x0 8. "BOREN,Brown-Out Reset Enable\nThe bit will enable BOR reset function. When VDD5V lower than 1.7v BOR will reset whole chip.\n0: Disable\n1: Enable" "0: Disable\n1: Enable,?"
bitfld.long 0x0 7. "BODVL2,Brown-Out Detector Threshold Voltage Selection (Initiated Write-Protected Bit)\nThe default value is set by flash controller user configuration register config0 bit[19]." "0,1"
newline
bitfld.long 0x0 6. "BODOUT,Brown-Out Detector Output State" "0: Brown-out Detector status output is 0 the..,1: Brown-out Detector status output is 1 the.."
bitfld.long 0x0 5. "BODLPM,Brown-Out Detector Low Power Mode (Write-Protected)\nThe BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1/10 but slow the BOD response." "0: BOD operate in normal mode (default),1: Enable the BOD low power mode"
newline
bitfld.long 0x0 4. "BODIF,Brown-Out Detector Interrupt Flag" "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the VDD is.."
bitfld.long 0x0 3. "BODRSTEN,Brown-Out Reset Enable (Initiated And Write-Protected Bit)\nThe default value is set by flash controller user configuration register config0 bit[20].\nWhen the BOREN is enabled and the interrupt is asserted the interrupt will be kept till the.." "0: Brown-out 'INTERRUPT' function Enabled; when the..,1: Brown-out 'RESET' function Enabled; when the.."
newline
bitfld.long 0x0 1.--2. "BODVL1_0,Brown-Out Detector Threshold Voltage Selection (Initiated Write-Protected Bit)" "0,1,2,3"
bitfld.long 0x0 0. "BODVL_EXT,Brown-Out Detector Selection Extension (Initiated Write-Protected Bit)" "0: Brown-out detector threshold voltage is selected..,1: Brown-out detector threshold voltage is selected.."
group.long 0x30++0x1B
line.long 0x0 "SYS_P0_MFP,P0 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x0 24.--31. 1. "HS,P0[7:0] Slew Rate Control"
hexmask.long.byte 0x0 16.--23. 1. "TYPE,P0[7:0] Input Schmitt Trigger Function Enable"
newline
bitfld.long 0x0 15. "ALT7,P0.7 Alternate Function Selection" "0,1"
bitfld.long 0x0 14. "ALT6,P0.6 Alternate Function Selection" "0,1"
newline
bitfld.long 0x0 13. "ALT5,P0.5 Alternate Function Selection" "0,1"
bitfld.long 0x0 12. "ALT4,P0.4 Alternate Function Selection" "0,1"
newline
bitfld.long 0x0 9. "ALT1,P0.1 Alternate Function Selection" "0,1"
bitfld.long 0x0 8. "ALT0,P0.0 Alternate Function Selection" "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "MFP,P0 Multiple Function Selection\nThe pin function of P0 depends on P0_MFP and ALT.\nRefer to ALT Description for details."
line.long 0x4 "SYS_P1_MFP,P1 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x4 24.--31. 1. "HS,P1[7:0] Slew Rate Control"
hexmask.long.byte 0x4 16.--23. 1. "TYPE,P1[7:0] Input Schmitt Trigger Function Enable"
newline
bitfld.long 0x4 14. "ALT6,P1.6 Alternate Function Selection" "0,1"
bitfld.long 0x4 13. "ALT5,P1.5 Alternate Function Selection" "0,1"
newline
bitfld.long 0x4 12. "ALT4,P1.4 Alternate Function Selection" "0,1"
bitfld.long 0x4 11. "ALT3,P1.3 Alternate Function Selection" "0,1"
newline
bitfld.long 0x4 10. "ALT2,P1.2 Alternate Function Selection" "0,1"
bitfld.long 0x4 8. "ALT0,P1.0 Alternate Function Selection" "0,1"
newline
hexmask.long.byte 0x4 0.--7. 1. "MFP,P1 Multiple Function Selection\nThe pin function of P1 depends on MFP and ALT.\nRefer to P1_ALT Description for details."
line.long 0x8 "SYS_P2_MFP,P2 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x8 24.--31. 1. "HS,P2[7:0] Slew Rate Control"
hexmask.long.byte 0x8 16.--23. 1. "TYPE,P2[7:0] Input Schmitt Trigger Function Enable"
newline
bitfld.long 0x8 15. "ALT7,P2.7 Alternate Function Selection" "0,1"
bitfld.long 0x8 14. "ALT6,P2.6 Alternate Function Selection" "0,1"
newline
bitfld.long 0x8 13. "ALT5,P2.5 Alternate Function Selection" "0,1"
bitfld.long 0x8 12. "ALT4,P2.4 Alternate Function Selection" "0,1"
newline
bitfld.long 0x8 11. "ALT3,P2.3 Alternate Function Selection" "0,1"
bitfld.long 0x8 10. "ALT2,P2.2 Alternate Function Selection" "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "MFP,P2 Multiple Function Selection\nThe pin function of P2 depends on P2_MFP and ALT.\nRefer to ALT Description for details."
line.long 0xC "SYS_P3_MFP,P3 Multiple Function and Input Type Control Register"
hexmask.long.byte 0xC 25.--31. 1. "HS,P3[6:0] Slew Rate Control"
bitfld.long 0xC 24. "P32CTL,P3.2 Alternate Function Selection Extension" "0: P3.2 is set by ALT[2] and MFP[2],1: P3.2 is set to CPP1 of ACMP1"
newline
hexmask.long.byte 0xC 16.--23. 1. "TYPE,P3[7:0] Input Schmitt Trigger Function Enable"
bitfld.long 0xC 15. "ALT7,P3.7 Alternate Function Selection" "0,1"
newline
bitfld.long 0xC 14. "ALT6,P3.6 Alternate Function Selection" "0,1"
bitfld.long 0xC 13. "ALT5,P3.5 Alternate Function Selection" "0,1"
newline
bitfld.long 0xC 12. "ALT4,P3.4 Alternate Function Selection" "0,1"
bitfld.long 0xC 10. "ALT2,P3.2 Alternate Function Selection" "0,1"
newline
bitfld.long 0xC 9. "ALT1,P3.1 Alternate Function Selection" "0,1"
bitfld.long 0xC 8. "ALT0,P3.0 Alternate Function Selection" "0,1"
newline
hexmask.long.byte 0xC 0.--7. 1. "MFP,P3 Multiple Function Selection\nThe pin function of P3 depends on MFP and ALT.\nRefer to ALT Description for details."
line.long 0x10 "SYS_P4_MFP,P4 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x10 24.--31. 1. "HS,P4[7:0] Slew Rate Control"
hexmask.long.byte 0x10 16.--23. 1. "TYPE,P4[7:0] Input Schmitt Trigger Function Enable"
newline
bitfld.long 0x10 15. "ALT7,P4.7 Alternate Function Selection" "0,1"
bitfld.long 0x10 14. "ALT6,P4.6 Alternate Function Selection" "0,1"
newline
hexmask.long.byte 0x10 0.--7. 1. "MFP,P4 Multiple Function Selection\nThe pin function of P4 depends on MFP and P4_ALT.\nRefer to ALT Description for details."
line.long 0x14 "SYS_P5_MFP,P5 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x14 24.--31. 1. "HS,P5[7:0] Slew Rate Control"
hexmask.long.byte 0x14 16.--23. 1. "TYPE,P5[7:0] Input Schmitt Trigger Function Enable"
newline
bitfld.long 0x14 13. "ALT5,P5.5 Alternate Function Selection" "0,1"
bitfld.long 0x14 12. "ALT4,P5.4 Alternate Function Selection" "0,1"
newline
bitfld.long 0x14 11. "ALT3,P5.3 Alternate Function Selection" "0,1"
bitfld.long 0x14 10. "ALT2,P5.2 Alternate Function Selection" "0,1"
newline
bitfld.long 0x14 9. "ALT1,P5.1 Alternate Function Selection" "0,1"
bitfld.long 0x14 8. "ALT0,P5.0 Alternate Function Selection" "0,1"
newline
hexmask.long.byte 0x14 0.--7. 1. "MFP,P5 Multiple Function Selection\nThe pin function of P5 depends on MFP and ALT.\nRefer to ALT Description for details."
line.long 0x18 "SYS_EINT0SEL,PIN selection"
bitfld.long 0x18 0. "SEL,INT0 SEL GPB3" "0: INT0 source is P3.2,1: INT0 source is P1.3"
group.long 0x80++0xB
line.long 0x0 "SYS_IRCTCTL,HFIRC Trim Control Register"
bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop\nThis field defines trim value calculation based on the number of LXT clock.\nFor example if LOOPSEL is set as '00' auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
bitfld.long 0x0 0. "FREQSEL,Trim Frequency Selection\nThis bit is to enable the HFIRC auto trim.\nWhen setting this bit to 1 the HFIRC auto trim function will trim HFIRC to 22.1184 MHz automatically based on the LXT reference clock.\nDuring auto trim operation if LXT.." "0: HFIRC auto trim function Disabled,1: HFIRC auto trim function Enabled and HFIRC.."
line.long 0x4 "SYS_IRCTIEN,HFIRC Trim Interrupt Enable Register"
bitfld.long 0x4 2. "CLKEIEN,LXT Clock Error Interrupt Enable\nThis bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation.\nIf this bit is high and CLKERRIF is set during auto trim operation an interrupt will be triggered to.." "0: CLKERRIF status Disabled to trigger an interrupt..,1: CLKERRIF status Enabled to trigger an interrupt.."
bitfld.long 0x4 1. "TFAILIEN,Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HFIRC trim value update limitation count is reached and HFIRC frequency is still not locked on target frequency set by FREQSEL.\nIf this bit is high and.." "0: TFAILIF status Disabled to trigger an interrupt..,1: TFAILIF status Enabled to trigger an interrupt.."
line.long 0x8 "SYS_IRCTISTS,HFIRC Trim Interrupt Status Register"
bitfld.long 0x8 2. "CLKERRIF,LXT Clock Error Interrupt Status\nThis bit indicates that LXT clock frequency is inaccuracy. Once this bit is set the auto trim operation stopped and FREQSEL will be cleared to 0 by hardware automatically.\nIf this bit is set and CLKEIEN is.." "0: LXT clock frequency is accuracy,1: LXT clock frequency is inaccuracy"
bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HFIRC trim value update limitation count reached and HFIRC clock frequency still doesn't lock. Once this bit is set the auto trim operation stopped and FREQSEL will be cleared to 0 by.." "0: Trim value update limitation count is not reached,1: Trim value update limitation count is reached.."
newline
bitfld.long 0x8 0. "FREQLOCK,HFIRC Frequency Lock Status\nThis bit indicates the HFIRC frequency locked in 22.1184 MHz.\nThis is a read only status bit and doesn't trigger any interrupt." "0,1"
group.long 0x100++0x3
line.long 0x0 "SYS_REGLCTL,Register Write-Protection Control Register"
rbitfld.long 0x0 0. "REGWRPROT,Register Write-Protection Disable Index (Read Only)" "0: Write-protection Enabled for writing protected..,1: Write-protection Disabled for writing protected.."
hexmask.long.byte 0x0 0.--7. 1. "REGPROTDIS,Register Write-Protection Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59 0x16 0x88 to this field. After this sequence is.."
endif
sif (cpuis("MINI5??DE"))
rgroup.long 0x0++0x3
line.long 0x0 "PDID,Part Device Identification Number Register"
hexmask.long 0x0 0.--31. 1. "PDID,Product Device Identification Number\nThis register reflects the device part number code. Software can read this register to identify which device is used.\nFor example the MINI51LDE PDID code is '0x20205100'."
group.long 0x4++0xB
line.long 0x0 "RSTSRC,System Reset Source Register"
bitfld.long 0x0 7. "RSTS_CPU,CPU Reset Flag\nThe RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC).\nNote: Software can write 1 to clear this bit to 0." "0: No reset from CPU,1: Cortex-M0 core and FMC are reset by software.."
bitfld.long 0x0 5. "RSTS_MCU,MCU Reset Flag\nThe RSTS_MCU flag is set by the 'reset signal' from the Cortex-M0 core to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to 0." "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.."
newline
bitfld.long 0x0 4. "RSTS_BOD,Brown-out Detector Reset Flag\nThe RSTS_BOD flag is set by the 'reset signal' from the Brown-out Detector to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to 0." "0: No reset from BOD,1: The BOD had issued the reset signal to reset the.."
bitfld.long 0x0 2. "RSTS_WDT,Watchdog Reset Flag\nThe RSTS_WDT flag is set by the 'reset signal' from the Watchdog timer to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to 0." "0: No reset from Watchdog timer,1: The Watchdog timer had issued the reset signal.."
newline
bitfld.long 0x0 1. "RSTS_RESET,Reset Pin Reset Flag\nThe RSTS_RESET flag is set by the 'reset signal' from the /RESET pin to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to 0." "0: No reset from pin /RESET pin,1: The /RESET pin had issued the reset signal to.."
bitfld.long 0x0 0. "RSTS_POR,Power-on Reset Flag\nThe RSTS_POR flag is set by the 'reset signal' which is from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to 0." "0: No reset from POR or CHIP_RST,1: Power-on-Reset (POR) or CHIP_RST had issued the.."
line.long 0x4 "IPRSTC1,Peripheral Reset Control Resister 1"
bitfld.long 0x4 1. "CPU_RST,CPU Kernel Reset\nSetting this bit will reset the CPU kernel and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is the protected bit and programming it needs to write 0x59 0x16 and 0x88 to address.." "0: CPU normal operation,1: Reset CPU Kernel"
bitfld.long 0x4 0. "CHIP_RST,CHIP One-shot Reset (Write Protect)\nSetting this bit will reset the CHIP including CPU kernel and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset and all the.." "0: Chip normal operation,1: CHIP one-shot reset"
line.long 0x8 "IPRSTC2,Peripheral Reset Control Resister 2"
bitfld.long 0x8 28. "ADC_RST,ADC Controller Reset\n" "0: ADC module normal operation,1: ADC module reset"
bitfld.long 0x8 22. "ACMP_RST,ACMP Controller Reset\n" "0: ACMP module normal operation,1: ACMP module reset"
newline
bitfld.long 0x8 20. "PWM_RST,PWM Controller Reset\n" "0: PWM module normal operation,1: PWM module reset"
bitfld.long 0x8 16. "UART_RST,UART Controller Reset\n" "0: UART module normal operation,1: UART module reset"
newline
bitfld.long 0x8 12. "SPI_RST,SPI Controller Reset\n" "0: SPI module normal operation,1: SPI module reset"
bitfld.long 0x8 8. "I2C_RST,I2C Controller Reset\n" "0: I2C module normal operation,1: I2C module reset"
newline
bitfld.long 0x8 3. "TMR1_RST,Timer1 Controller Reset\n" "0: Timer1 module normal operation,1: Timer1 module reset"
bitfld.long 0x8 2. "TMR0_RST,Timer0 Controller Reset\n" "0: Timer0 module normal operation,1: Timer0 module reset"
newline
bitfld.long 0x8 1. "GPIO_RST,GPIO (P0~P5) Controller Reset\n" "0: GPIO module normal operation,1: GPIO module reset"
group.long 0x18++0x3
line.long 0x0 "BODCR,Brown-out Detector Control Register"
bitfld.long 0x0 6. "BOD_OUT,Brown-out Detector Output State\n" "0: Brown-out Detector status output is 0 the..,1: Brown-out Detector status output is 1 the.."
bitfld.long 0x0 5. "BOD_LPM,Brown-out Detector Low Power Mode (Write Protect)\nThe BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1uA but slow the BOD response." "0: BOD operate in normal mode (default),1: Enable the BOD low power mode"
newline
bitfld.long 0x0 4. "BOD_INTF,Brown-out Detector Interrupt Flag\n" "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the AVDD is.."
bitfld.long 0x0 3. "BOD_RSTEN,Brown-out Reset Enable Control (Initiated And Write-protected Bit)\nThe default value is set by flash controller user configuration register config0 bit[20].\nWhen the BOD_EN is enabled and the interrupt is asserted the interrupt will be kept.." "0: Brown-out 'INTERRUPT' function Enabled; when the..,1: Brown-out 'RESET' function Enabled; when the.."
newline
bitfld.long 0x0 1.--2. "BOD_VL,Brown-out Detector Threshold Voltage Selection (Initiated Write-protected Bit)\n" "0,1,2,3"
bitfld.long 0x0 0. "BOD_VL_EXT,Brown-out Detector Selection Extension (Initiated Write-protected Bit)\n" "0: Brown-out detector threshold voltage is selected..,1: Brown-out detector threshold voltage is selected.."
group.long 0x30++0x17
line.long 0x0 "P0_MFP,P0 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x0 16.--23. 1. "P0_TYPE,P0[7:0] TTL Or Schmitt Trigger Function Enable Control\n"
bitfld.long 0x0 15. "P0_ALT7,P0.7 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x0 14. "P0_ALT6,P0.6 Alternate Function Selection\n" "0,1"
bitfld.long 0x0 13. "P0_ALT5,P0.5 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x0 12. "P0_ALT4,P0.4 Alternate Function Selection\n" "0,1"
bitfld.long 0x0 9. "P0_ALT1,P0.1 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x0 8. "P0_ALT0,P0.0 Alternate Function Selection\n" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "P0_MFP,P0 Multiple Function Selection\nThe pin function of P0 depends on P0_MFP and P0_ALT.\nRefer to P0_ALT Description for details."
line.long 0x4 "P1_MFP,P1 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x4 16.--23. 1. "P1_TYPE,P1[7:0] TTL Or Schmitt Trigger Function Enable Control\n"
bitfld.long 0x4 13. "P1_ALT5,P1.5 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x4 12. "P1_ALT4,P1.4 Alternate Function Selection\n" "0,1"
bitfld.long 0x4 11. "P1_ALT3,P1.3 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x4 10. "P1_ALT2,P1.2 Alternate Function Selection\n" "0,1"
bitfld.long 0x4 8. "P1_ALT0,P1.0 Alternate Function Selection\n" "0,1"
newline
hexmask.long.byte 0x4 0.--7. 1. "P1_MFP,P1 Multiple Function Selection\nThe pin function of P1 depends on P1_MFP and P1_ALT.\nRefer to P1_ALT Description for details."
line.long 0x8 "P2_MFP,P2 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x8 16.--23. 1. "P2_TYPE,P2[7:0] TTL Or Schmitt Trigger Function Enable Control\n"
bitfld.long 0x8 14. "P2_ALT6,P2.6 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x8 13. "P2_ALT5,P2.5 Alternate Function Selection\n" "0,1"
bitfld.long 0x8 12. "P2_ALT4,P2.4 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x8 11. "P2_ALT3,P2.3 Alternate Function Selection\n" "0,1"
bitfld.long 0x8 10. "P2_ALT2,P2.2 Alternate Function Selection\n" "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "P2_MFP,P2 Multiple Function Selection\nThe pin function of P2 depends on P2_MFP and P2_ALT.\nRefer to P2_ALT Description for details."
line.long 0xC "P3_MFP,P3 Multiple Function and Input Type Control Register"
bitfld.long 0xC 24. "P32CPP1,P3.2 Alternate Function Selection Extension\n" "0: P3.2 is set by P3_ALT[2] and P3_MFP[2],1: P3.2 is set to CPP1 of ACMP1"
hexmask.long.byte 0xC 16.--23. 1. "P3_TYPE,P3[7:0] TTL Or Schmitt Trigger Function Enable Control\n"
newline
bitfld.long 0xC 14. "P3_ALT6,P3.6 Alternate Function Selection\n" "0,1"
bitfld.long 0xC 13. "P3_ALT5,P3.5 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0xC 12. "P3_ALT4,P3.4 Alternate Function Selection\n" "0,1"
bitfld.long 0xC 10. "P3_ALT2,P3.2 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0xC 9. "P3_ALT1,P3.1 Alternate Function Selection\n" "0,1"
bitfld.long 0xC 8. "P3_ALT0,P3.0 Alternate Function Selection\n" "0,1"
newline
hexmask.long.byte 0xC 0.--7. 1. "P3_MFP,P3 Multiple Function Selection\nThe pin function of P3 depends on P3_MFP and P3_ALT.\nRefer to P3_ALT Description for details."
line.long 0x10 "P4_MFP,P4 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x10 16.--23. 1. "P4_TYPE,P4[7:0] TTL Or Schmitt Trigger Function Enable Control\n"
bitfld.long 0x10 15. "P4_ALT7,P4.7 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x10 14. "P4_ALT6,P4.6 Alternate Function Selection\n" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "P4_MFP,P4 Multiple Function Selection\nThe pin function of P4 depends on P4_MFP and P4_ALT.\nRefer to P4_ALT Description for details."
line.long 0x14 "P5_MFP,P5 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x14 16.--23. 1. "P5_TYPE,P5[7:0] TTL Or Schmitt Trigger Function Enable Control\n"
bitfld.long 0x14 13. "P5_ALT5,P5.5 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x14 12. "P5_ALT4,P5.4 Alternate Function Selection\n" "0,1"
bitfld.long 0x14 11. "P5_ALT3,P5.3 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x14 10. "P5_ALT2,P5.2 Alternate Function Selection\n" "0,1"
bitfld.long 0x14 9. "P5_ALT1,P5.1 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x14 8. "P5_ALT0,P5.0 Alternate Function Selection\n" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "P5_MFP,P5 Multiple Function Selection\nThe pin function of P5 depends on P5_MFP and P5_ALT.\nRefer to P5_ALT Description for details."
group.long 0x80++0xB
line.long 0x0 "IRCTRIMCTL,HIRC Trim Control Register"
bitfld.long 0x0 6.--7. "TRIM_RETRY_CNT,Trim Value Update Limitation Count\n" "0,1,2,3"
bitfld.long 0x0 4.--5. "TRIM_LOOP,Trim Calculation Loop\nThis field defines that trim value calculation is based on how many LXT clocks in.\nFor example if TRIM_LOOP is set as 00 auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
newline
bitfld.long 0x0 0. "TRIM_SEL,Trim Frequency Selection\nThis bit is to enable the HIRC auto trim.\nWhen setting this bit to 1 the HIRC auto trim function will trim HIRC to 22.1184 MHz automatically based on the LXT reference clock.\nDuring auto trim operation if LXT clock.." "0: HIRC auto trim function Disabled,1: HIRC auto trim function Enabled and HIRC trimmed.."
line.long 0x4 "IRCTRIMIEN,HIRC Trim Interrupt Enable Control Register"
bitfld.long 0x4 2. "_32K_ERR_IEN,LXT Clock Error Interrupt Enable Control\nThis bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation.\nIf this bit is high and 32K_ERR_INT is set during auto trim operation an interrupt will be.." "0: 32K_ERR_INT status Disabled to trigger an..,1: 32K_ERR_INT status Enabled to trigger an.."
bitfld.long 0x4 1. "TRIM_FAIL_IEN,Trim Failure Interrupt Enable Control\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count is reached and HIRC frequency is still not locked on target frequency set by TRIM_SEL.\nIf this bit is.." "0: TRIM_FAIL_INT status Disabled to trigger an..,1: TRIM_FAIL_INT status Enabled to trigger an.."
line.long 0x8 "IRCTRIMINT,HIRC Trim Interrupt Status Register"
bitfld.long 0x8 2. "_32K_ERR_INT,LXT Clock Error Interrupt Status\nThis bit indicates that LXT clock frequency is inaccuracy. Once this bit is set the auto trim operation stopped and TRIM_SEL will be cleared to 0 by hardware automatically.\nIf this bit is set and.." "0: LXT clock frequency is accuracy,1: LXT clock frequency is inaccuracy"
bitfld.long 0x8 1. "TRIM_FAIL_INT,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set the auto trim operation stopped and TRIM_SEL will be cleared to 0 by.." "0: Trim value update limitation count is not reached,1: Trim value update limitation count is reached.."
newline
bitfld.long 0x8 0. "FREQ_LOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency locked in 22.1184 MHz.\nThis is a read only status bit and doesn't trigger any interrupt." "0,1"
group.long 0x100++0x3
line.long 0x0 "REGWRPROT,Register Write-protection Control Register"
rbitfld.long 0x0 0. "REGPROTDIS,Register Write-protection Disable Index (Read Only)\n" "0: Write-protection Enabled for writing protected..,1: Write-protection Disabled for writing protected.."
hexmask.long.byte 0x0 0.--7. 1. "REGWRPROT,Register Write-protection Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59 0x16 0x88 to this field. After this sequence is.."
endif
sif (cpuis("MINI5?AN"))
rgroup.long 0x0++0x3
line.long 0x0 "PDID,Part Device Identification Number Register"
hexmask.long 0x0 0.--31. 1. "PDID,Product Device Identification Number\nThis register reflects the device part number code. Software can read this register to identify which device is used.\nFor example the MINI51LBN PDID code is '0x10205100'."
group.long 0x4++0xB
line.long 0x0 "RSTSRC,System Reset Source Register"
bitfld.long 0x0 7. "RSTS_CPU,The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) with 1 to reset the Cortex-M0 CPU kernel and Flash Memory Controller (FMC).\nSoftware can write 1 to clear this bit to zero." "0: No reset from CPU,1: The Cortex-M0 CPU kernel and FMC are reset by.."
bitfld.long 0x0 5. "RSTS_MCU,The RSTS_MCU flag is set by the 'reset signal' from the Cortex-M0 kernel to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero." "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.."
newline
bitfld.long 0x0 4. "RSTS_BOD,The RSTS_BOD flag is set by the 'reset signal' from the Brown-out Detected module to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero." "0: No reset from BOD,1: The Brown-out Detected module had issued the.."
bitfld.long 0x0 2. "RSTS_WDT,The RSTS_WDT flag is set by the 'reset signal' from the Watchdog module to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero." "0: No reset from Watchdog,1: The Watchdog module had issued the reset signal.."
newline
bitfld.long 0x0 1. "RSTS_RESET,The RSTS_RESET flag is set by the 'reset signal' from the /RESET pin to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero." "0: No reset from pin /RESET,1: The pin /RESET had issued the reset signal to.."
bitfld.long 0x0 0. "RSTS_POR,The RSTS_POR flag is set by the 'reset signal' which is from the Power-On Reset (POR) module or bit CHIP_RST (IPRSTC1[0]) set to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero." "0: No reset from POR,1: The Power-On-Reset (POR) or CHIP_RST=1 had.."
line.long 0x4 "IPRSTC1,IP Reset Control Resister 1"
bitfld.long 0x4 1. "CPU_RST,CPU Kernel One Shot Reset\nSetting this bit will reset the CPU kernel and this bit will automatically return to 0 after the 2 clock cycles.\nThis bit is the protected bit programming this needs an open lock sequence write 0x59 0x16 0x88 to.." "0: Normal,1: Reset CPU"
bitfld.long 0x4 0. "CHIP_RST,CHIP One Shot Reset\nSetting this bit will reset the CHIP including CPU kernel and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset and all the chip module is.." "0: Normal,1: Reset CHIP"
line.long 0x8 "IPRSTC2,IP Reset Control Resister 2"
bitfld.long 0x8 28. "ADC_RST,ADC Controller Reset\n" "0: ADC block normal operation,1: ADC block reset"
bitfld.long 0x8 22. "ACMP_RST,ACMP Controller Reset\n" "0: ACMP block normal operation,1: ACMP block reset"
newline
bitfld.long 0x8 20. "PWM_RST,PWM Controller Reset\n" "0: PWM block normal operation,1: PWM block reset"
bitfld.long 0x8 16. "UART_RST,UART Controller Reset\n" "0: UART normal operation,1: UART block reset"
newline
bitfld.long 0x8 12. "SPI_RST,SPI Controller Reset\n" "0: SPI block normal operation,1: SPI block reset"
bitfld.long 0x8 8. "I2C_RST,I2C Controller Reset\n" "0: I2C normal operation,1: I2C block reset"
newline
bitfld.long 0x8 3. "TMR1_RST,Timer1 Controller Reset\n" "0: Timer1 normal operation,1: Timer1 block reset"
bitfld.long 0x8 2. "TMR0_RST,Timer0 Controller Reset\n" "0: Timer0 normal operation,1: Timer0 block reset"
newline
bitfld.long 0x8 1. "GPIO_RST,GPIO (P0~P5) Controller Reset\n" "0: GPIO normal operation,1: GPIO reset"
group.long 0x18++0xF
line.long 0x0 "BODCR,Brown-out Detector Control Register"
bitfld.long 0x0 6. "BOD_OUT,Brown-out Detector Output State\n" "0: Brown-out Detector status output is 0 the..,1: Brown-out Detector status output is 1 the.."
bitfld.long 0x0 4. "BOD_INTF,Brown-out Detector Interrupt Flag\n" "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the VDD is.."
newline
bitfld.long 0x0 3. "BOD_RSTEN,Brown-out Reset Enable (Initiated and Write-protected bit)\nWhen the BOD_EN is enabled and the interrupt is asserted the interrupt will be kept till the BOD_EN is set to 0. The interrupt for CPU can be blocked by disabling the NVIC in CPU for.." "0: Brown-out 'INTERRUPT' function Enabled; when the..,1: Brown-out 'RESET' function Enabled; when the.."
bitfld.long 0x0 1.--2. "BOD_VL,Brown-out Detector Threshold Voltage Selection (Initiated Write-protected bit)\n" "0,1,2,3"
line.long 0x4 "LDOCR,LDO Control Register"
line.long 0x8 "LDOBPCR,LDO Bypass Control Register"
line.long 0xC "PORCR,Power-On-Reset Control Register"
group.long 0x30++0x17
line.long 0x0 "P0_MFP,P0 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x0 16.--23. 1. "P0_TYPE,P0[7:0] Input Schmitt Trigger Function Enable\n"
bitfld.long 0x0 15. "P0_ALT7,P0.7 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x0 14. "P0_ALT6,P0.6 Alternate Function Selection\n" "0,1"
bitfld.long 0x0 13. "P0_ALT5,P0.5 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x0 12. "P0_ALT4,P0.4 Alternate Function Selection\n" "0,1"
bitfld.long 0x0 9. "P0_ALT1,P0.1 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x0 8. "P0_ALT0,P0.0 Alternate Function Selection\n" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "P0_MFP,P0 Multiple Function Selection\nThe pin function of P0 depends on P0_MFP and P0_ALT.\nRefer to P0_ALT Description for details."
line.long 0x4 "P1_MFP,P1 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x4 16.--23. 1. "P1_TYPE,P1[7:0] Input Schmitt Trigger Function Enable\n"
bitfld.long 0x4 13. "P1_ALT5,P1.5 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x4 12. "P1_ALT4,P1.4 Alternate Function Selection\n" "0,1"
bitfld.long 0x4 11. "P1_ALT3,P1.3 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x4 10. "P1_ALT2,P1.2 Alternate Function Selection\n" "0,1"
bitfld.long 0x4 8. "P1_ALT0,P1.0 Alternate Function Selection\n" "0,1"
newline
hexmask.long.byte 0x4 0.--7. 1. "P1_MFP,P1 Multiple Function Selection\nThe pin function of P1 depends on P1_MFP and P1_ALT.\nRefer to P1_ALT Description for details."
line.long 0x8 "P2_MFP,P2 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x8 16.--23. 1. "P2_TYPE,P2[7:0] Input Schmitt Trigger Function Enable\n"
bitfld.long 0x8 14. "P2_ALT6,P2.6 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x8 13. "P2_ALT5,P2.5 Alternate Function Selection\n" "0,1"
bitfld.long 0x8 12. "P2_ALT4,P2.4 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x8 11. "P2_ALT3,P2.3 Alternate Function Selection\n" "0,1"
bitfld.long 0x8 10. "P2_ALT2,P2.2 Alternate Function Selection\n" "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "P2_MFP,P2 Multiple Function Selection\nThe pin function of P2 depends on P2_MFP and P2_ALT.\nRefer to P2_ALT Description for details."
line.long 0xC "P3_MFP,P3 Multiple Function and Input Type Control Register"
bitfld.long 0xC 24. "P32CPP1,P3.2 Alternate Function Selection Extension\n" "0: P3.2 is set by P3_ALT[2] and P3_MFP[2],1: P3.2 is set to CPP1 of ACMP1"
hexmask.long.byte 0xC 16.--23. 1. "P3_TYPE,P3[7:0] Input Schmitt Trigger Function Enable\n"
newline
bitfld.long 0xC 14. "P3_ALT6,P3.6 Alternate Function Selection\n" "0,1"
bitfld.long 0xC 13. "P3_ALT5,P3.5 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0xC 12. "P3_ALT4,P3.4 Alternate Function Selection\n" "0,1"
bitfld.long 0xC 10. "P3_ALT2,P3.2 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0xC 9. "P3_ALT1,P3.1 Alternate Function Selection\n" "0,1"
bitfld.long 0xC 8. "P3_ALT0,P3.0 Alternate Function Selection\n" "0,1"
newline
hexmask.long.byte 0xC 0.--7. 1. "P3_MFP,P3 Multiple Function Selection\nThe pin function of P3 depends on P3_MFP and P3_ALT.\nRefer to P3_ALT Description for details."
line.long 0x10 "P4_MFP,P4 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x10 16.--23. 1. "P4_TYPE,P4[7:0] Input Schmitt Trigger Function Enable\n"
bitfld.long 0x10 15. "P4_ALT7,P4.7 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x10 14. "P4_ALT6,P4.6 Alternate Function Selection\n" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "P4_MFP,P4 Multiple Function Selection\nThe pin function of P4 depends on P4_MFP and P4_ALT.\nRefer to P4_ALT Description for details."
line.long 0x14 "P5_MFP,P5 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x14 16.--23. 1. "P5_TYPE,P5[7:0] Input Schmitt Trigger Function Enable\n"
bitfld.long 0x14 13. "P5_ALT5,P5.5 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x14 12. "P5_ALT4,P5.4 Alternate Function Selection\n" "0,1"
bitfld.long 0x14 11. "P5_ALT3,P5.3 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x14 10. "P5_ALT2,P5.2 Alternate Function Selection\n" "0,1"
bitfld.long 0x14 9. "P5_ALT1,P5.1 Alternate Function Selection\n" "0,1"
newline
bitfld.long 0x14 8. "P5_ALT0,P5.0 Alternate Function Selection\n" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "P5_MFP,P5 Multiple Function Selection\nThe pin function of P5 depends on P5_MFP and P5_ALT.\nRefer to P5_ALT Description for details."
group.long 0x80++0xB
line.long 0x0 "IRCTRIMCTL,HIRC Trim Control Register"
bitfld.long 0x0 4.--5. "TRIM_LOOP,Trim Calculation Loop\nThis field defines trim value calculation based on the number of LXT clock.\nFor example if TRIM_LOOP is set as '00' auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
bitfld.long 0x0 0. "TRIM_SEL,Trim Frequency Selection\nThis bit is to enable the HFIRC auto trim.\nWhen setting this bit to 1 the HFIRC auto trim function will trim HFIRC to 22.1184 MHz automatically based on the LXT reference clock.\nDuring auto trim operation if LXT.." "0: HFIRC auto trim function Disabled,1: HFIRC auto trim function Enabled and HFIRC.."
line.long 0x4 "IRCTRIMIEN,HIRC Trim Interrupt Enable Register"
bitfld.long 0x4 2. "_32K_ERR_IEN,LXT Clock Error Interrupt Enable\nThis bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation.\nIf this bit is high and 32K_ERR_INT is set during auto trim operation an interrupt will be.." "0: 32K_ERR_INT status Disabled to trigger an..,1: 32K_ERR_INT status Enabled to trigger an.."
bitfld.long 0x4 1. "TRIM_FAIL_IEN,Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HFIRC trim value update limitation count is reached and HFIRC frequency is still not locked on target frequency set by TRIM_SEL.\nIf this bit is high.." "0: TRIM_FAIL_INT status Disabled to trigger an..,1: TRIM_FAIL_INT status Enabled to trigger an.."
line.long 0x8 "IRCTRIMINT,HIRC Trim Interrupt Status Register"
bitfld.long 0x8 2. "_32K_ERR_INT,LXT Clock Error Interrupt Status\nThis bit indicates that LXT clock frequency is inaccuracy. Once this bit is set the auto trim operation stopped and TRIM_SEL will be cleared to 0 by hardware automatically.\nIf this bit is set and.." "0: LXT clock frequency is accuracy,1: LXT clock frequency is inaccuracy"
bitfld.long 0x8 1. "TRIM_FAIL_INT,Trim Failure Interrupt Status\nThis bit indicates that HFIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set the auto trim operation stopped and TRIM_SEL will be cleared to 0 by.." "0: Trim value update limitation count is not reached,1: Trim value update limitation count is reached.."
newline
bitfld.long 0x8 0. "FREQ_LOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency lock.\nThis is a status bit and doesn't trigger any interrupt." "0,1"
group.long 0x100++0x3
line.long 0x0 "RegLockAddr,Register Lock Key Address Register"
bitfld.long 0x0 0. "RegUnLock,The Protected registers are:\nIPRSTC1 - address 0x5000_0008 (IP reset control register 1)\nBODCR - address 0x5000_0018 (Brown-out detector control register)\nLDOCR - address 0x5000_001C (LDO control register)\nPORCR - address 0x5000_0024.." "0: address 0x5000_0210,1: address 0x5000_0008"
endif
tree.end
tree "GPIO (General Purpose I/O)"
base ad:0x50004000
sif (cpuis("MINI5?XAE"))
group.long 0x0++0x7
line.long 0x0 "P0_MODE,P0 I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "MODE3,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "MODE1,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
line.long 0x4 "P0_DINOFF,P0 Digital Input Path Disable Control"
hexmask.long.byte 0x4 16.--23. 1. "DINOFF,Port 0-5 Pin [N] Digital Input Path Disable Control"
group.long 0xC++0x3
line.long 0x0 "P0_DATMSK,P0 Data Output Write Mask"
hexmask.long.byte 0x0 0.--7. 1. "DATMSK,Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DATMSK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.."
group.long 0x18++0xB
line.long 0x0 "P0_INTTYPE,P0 Interrupt Mode Control"
hexmask.long.byte 0x0 0.--7. 1. "INTTYPE,Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nINTTYPE[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by.."
line.long 0x4 "P0_INTEN,P0 Interrupt Enable Control"
hexmask.long.byte 0x4 16.--23. 1. "RHIEN,Port 0-5 Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRHIEN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN[n] bit.."
bitfld.long 0x4 0. "FLIEN,Port 0-5 Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFLIEN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: Px.n low level or high to low interrupt Enabled"
line.long 0x8 "P0_INTSRC,P0 Interrupt Source Flag"
hexmask.long.byte 0x8 0.--7. 1. "INTSRC,Port 0-5 Pin [N] Interrupt Source Flag\nWrite :"
group.long 0x40++0x7
line.long 0x0 "P1_MODE,P1 I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "MODE3,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "MODE1,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
line.long 0x4 "P1_DINOFF,P1 Digital Input Path Disable Control"
hexmask.long.byte 0x4 16.--23. 1. "DINOFF,Port 0-5 Pin [N] Digital Input Path Disable Control"
group.long 0x4C++0x3
line.long 0x0 "P1_DATMSK,P1 Data Output Write Mask"
hexmask.long.byte 0x0 0.--7. 1. "DATMSK,Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DATMSK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.."
group.long 0x58++0xB
line.long 0x0 "P1_INTTYPE,P1 Interrupt Mode Control"
hexmask.long.byte 0x0 0.--7. 1. "INTTYPE,Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nINTTYPE[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by.."
line.long 0x4 "P1_INTEN,P1 Interrupt Enable Control"
hexmask.long.byte 0x4 16.--23. 1. "RHIEN,Port 0-5 Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRHIEN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN[n] bit.."
bitfld.long 0x4 0. "FLIEN,Port 0-5 Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFLIEN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: Px.n low level or high to low interrupt Enabled"
line.long 0x8 "P1_INTSRC,P1 Interrupt Source Flag"
hexmask.long.byte 0x8 0.--7. 1. "INTSRC,Port 0-5 Pin [N] Interrupt Source Flag\nWrite :"
group.long 0x80++0x7
line.long 0x0 "P2_MODE,P2 I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "MODE3,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "MODE1,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
line.long 0x4 "P2_DINOFF,P2 Digital Input Path Disable Control"
hexmask.long.byte 0x4 16.--23. 1. "DINOFF,Port 0-5 Pin [N] Digital Input Path Disable Control"
group.long 0x8C++0x3
line.long 0x0 "P2_DATMSK,P2 Data Output Write Mask"
hexmask.long.byte 0x0 0.--7. 1. "DATMSK,Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DATMSK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.."
group.long 0x98++0xB
line.long 0x0 "P2_INTTYPE,P2 Interrupt Mode Control"
hexmask.long.byte 0x0 0.--7. 1. "INTTYPE,Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nINTTYPE[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by.."
line.long 0x4 "P2_INTEN,P2 Interrupt Enable Control"
hexmask.long.byte 0x4 16.--23. 1. "RHIEN,Port 0-5 Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRHIEN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN[n] bit.."
bitfld.long 0x4 0. "FLIEN,Port 0-5 Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFLIEN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: Px.n low level or high to low interrupt Enabled"
line.long 0x8 "P2_INTSRC,P2 Interrupt Source Flag"
hexmask.long.byte 0x8 0.--7. 1. "INTSRC,Port 0-5 Pin [N] Interrupt Source Flag\nWrite :"
group.long 0xC0++0x7
line.long 0x0 "P3_MODE,P3 I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "MODE3,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "MODE1,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
line.long 0x4 "P3_DINOFF,P3 Digital Input Path Disable Control"
hexmask.long.byte 0x4 16.--23. 1. "DINOFF,Port 0-5 Pin [N] Digital Input Path Disable Control"
group.long 0xCC++0x3
line.long 0x0 "P3_DATMSK,P3 Data Output Write Mask"
hexmask.long.byte 0x0 0.--7. 1. "DATMSK,Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DATMSK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.."
group.long 0xD8++0xB
line.long 0x0 "P3_INTTYPE,P3 Interrupt Mode Control"
hexmask.long.byte 0x0 0.--7. 1. "INTTYPE,Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nINTTYPE[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by.."
line.long 0x4 "P3_INTEN,P3 Interrupt Enable Control"
hexmask.long.byte 0x4 16.--23. 1. "RHIEN,Port 0-5 Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRHIEN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN[n] bit.."
bitfld.long 0x4 0. "FLIEN,Port 0-5 Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFLIEN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: Px.n low level or high to low interrupt Enabled"
line.long 0x8 "P3_INTSRC,P3 Interrupt Source Flag"
hexmask.long.byte 0x8 0.--7. 1. "INTSRC,Port 0-5 Pin [N] Interrupt Source Flag\nWrite :"
group.long 0x100++0x7
line.long 0x0 "P4_MODE,P4 I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "MODE3,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "MODE1,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
line.long 0x4 "P4_DINOFF,P4 Digital Input Path Disable Control"
hexmask.long.byte 0x4 16.--23. 1. "DINOFF,Port 0-5 Pin [N] Digital Input Path Disable Control"
group.long 0x10C++0x3
line.long 0x0 "P4_DATMSK,P4 Data Output Write Mask"
hexmask.long.byte 0x0 0.--7. 1. "DATMSK,Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DATMSK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.."
group.long 0x118++0xB
line.long 0x0 "P4_INTTYPE,P4 Interrupt Mode Control"
hexmask.long.byte 0x0 0.--7. 1. "INTTYPE,Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nINTTYPE[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by.."
line.long 0x4 "P4_INTEN,P4 Interrupt Enable Control"
hexmask.long.byte 0x4 16.--23. 1. "RHIEN,Port 0-5 Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRHIEN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN[n] bit.."
bitfld.long 0x4 0. "FLIEN,Port 0-5 Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFLIEN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: Px.n low level or high to low interrupt Enabled"
line.long 0x8 "P4_INTSRC,P4 Interrupt Source Flag"
hexmask.long.byte 0x8 0.--7. 1. "INTSRC,Port 0-5 Pin [N] Interrupt Source Flag\nWrite :"
group.long 0x140++0x7
line.long 0x0 "P5_MODE,P5 I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "MODE3,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "MODE1,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Port 0-5 I/O Pin [N] Mode Control" "0,1,2,3"
line.long 0x4 "P5_DINOFF,P5 Digital Input Path Disable Control"
hexmask.long.byte 0x4 16.--23. 1. "DINOFF,Port 0-5 Pin [N] Digital Input Path Disable Control"
group.long 0x14C++0x3
line.long 0x0 "P5_DATMSK,P5 Data Output Write Mask"
hexmask.long.byte 0x0 0.--7. 1. "DATMSK,Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DATMSK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.."
group.long 0x158++0xB
line.long 0x0 "P5_INTTYPE,P5 Interrupt Mode Control"
hexmask.long.byte 0x0 0.--7. 1. "INTTYPE,Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nINTTYPE[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by.."
line.long 0x4 "P5_INTEN,P5 Interrupt Enable Control"
hexmask.long.byte 0x4 16.--23. 1. "RHIEN,Port 0-5 Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRHIEN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN[n] bit.."
bitfld.long 0x4 0. "FLIEN,Port 0-5 Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFLIEN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: Px.n low level or high to low interrupt Enabled"
line.long 0x8 "P5_INTSRC,P5 Interrupt Source Flag"
hexmask.long.byte 0x8 0.--7. 1. "INTSRC,Port 0-5 Pin [N] Interrupt Source Flag\nWrite :"
group.long 0x238++0x3
line.long 0x0 "P16_PDIO,GPIO P1.6 Pin Data Input/Output"
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
group.long 0x25C++0x3
line.long 0x0 "P27_PDIO,GPIO P2.7 Pin Data Input/Output"
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
group.long 0x27C++0x3
line.long 0x0 "P37_PDIO,GPIO P3.7 Pin Data Input/Output"
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
group.long 0x0++0x7
line.long 0x0 "P0_PMD,P0 I/O Mode Control"
bitfld.long 0x0 14.--15. "PMD7,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "PMD6,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 10.--11. "PMD5,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "PMD4,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 6.--7. "PMD3,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "PMD2,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 2.--3. "PMD1,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "PMD0,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "P0_OFFD,P0 Digital Input Path Disable Control"
hexmask.long.byte 0x4 16.--23. 1. "OFFD,Port 0-5 Pin [N] Digital Input Path Disable Control\n"
group.long 0xC++0x3
line.long 0x0 "P0_DMASK,P0 Data Output Write Mask"
hexmask.long.byte 0x0 0.--7. 1. "DMASK,Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.."
group.long 0x18++0xB
line.long 0x0 "P0_IMD,P0 Interrupt Mode Control"
hexmask.long.byte 0x0 0.--7. 1. "IMD,Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If.."
line.long 0x4 "P0_IEN,P0 Interrupt Enable Control"
hexmask.long.byte 0x4 16.--23. 1. "IR_EN,Port 0-5 Pin [N] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n].."
bitfld.long 0x4 0. "IF_EN,Port 0-5 Pin [N] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EB[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: Px.n low level or high to low interrupt Enabled"
line.long 0x8 "P0_ISRC,P0 Interrupt Source Flag"
hexmask.long.byte 0x8 0.--7. 1. "ISRC,Port 0-5 Pin [N] Interrupt Source Flag\nWrite :\nNote2:\nP0_ISRC[3:2] are reserved.\nP1_ISRC[7:6] [1] are reserved.\nP2_ISRC[7] [1:0] are reserved.\nP3_ISRC[7] [3] are reserved.\nP4_ISRC[5:0] are reserved.\nP5_ISRC[7:6] are reserved."
group.long 0x40++0x7
line.long 0x0 "P1_PMD,P1 I/O Mode Control"
bitfld.long 0x0 14.--15. "PMD7,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "PMD6,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 10.--11. "PMD5,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "PMD4,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 6.--7. "PMD3,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "PMD2,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 2.--3. "PMD1,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "PMD0,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "P1_OFFD,P1 Digital Input Path Disable Control"
hexmask.long.byte 0x4 16.--23. 1. "OFFD,Port 0-5 Pin [N] Digital Input Path Disable Control\n"
group.long 0x4C++0x3
line.long 0x0 "P1_DMASK,P1 Data Output Write Mask"
hexmask.long.byte 0x0 0.--7. 1. "DMASK,Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.."
group.long 0x58++0xB
line.long 0x0 "P1_IMD,P1 Interrupt Mode Control"
hexmask.long.byte 0x0 0.--7. 1. "IMD,Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If.."
line.long 0x4 "P1_IEN,P1 Interrupt Enable Control"
hexmask.long.byte 0x4 16.--23. 1. "IR_EN,Port 0-5 Pin [N] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n].."
bitfld.long 0x4 0. "IF_EN,Port 0-5 Pin [N] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EB[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: Px.n low level or high to low interrupt Enabled"
line.long 0x8 "P1_ISRC,P1 Interrupt Source Flag"
hexmask.long.byte 0x8 0.--7. 1. "ISRC,Port 0-5 Pin [N] Interrupt Source Flag\nWrite :\nNote2:\nP0_ISRC[3:2] are reserved.\nP1_ISRC[7:6] [1] are reserved.\nP2_ISRC[7] [1:0] are reserved.\nP3_ISRC[7] [3] are reserved.\nP4_ISRC[5:0] are reserved.\nP5_ISRC[7:6] are reserved."
group.long 0x80++0x7
line.long 0x0 "P2_PMD,P2 I/O Mode Control"
bitfld.long 0x0 14.--15. "PMD7,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "PMD6,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 10.--11. "PMD5,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "PMD4,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 6.--7. "PMD3,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "PMD2,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 2.--3. "PMD1,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "PMD0,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "P2_OFFD,P2 Digital Input Path Disable Control"
hexmask.long.byte 0x4 16.--23. 1. "OFFD,Port 0-5 Pin [N] Digital Input Path Disable Control\n"
group.long 0x8C++0x3
line.long 0x0 "P2_DMASK,P2 Data Output Write Mask"
hexmask.long.byte 0x0 0.--7. 1. "DMASK,Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.."
group.long 0x98++0xB
line.long 0x0 "P2_IMD,P2 Interrupt Mode Control"
hexmask.long.byte 0x0 0.--7. 1. "IMD,Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If.."
line.long 0x4 "P2_IEN,P2 Interrupt Enable Control"
hexmask.long.byte 0x4 16.--23. 1. "IR_EN,Port 0-5 Pin [N] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n].."
bitfld.long 0x4 0. "IF_EN,Port 0-5 Pin [N] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EB[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: Px.n low level or high to low interrupt Enabled"
line.long 0x8 "P2_ISRC,P2 Interrupt Source Flag"
hexmask.long.byte 0x8 0.--7. 1. "ISRC,Port 0-5 Pin [N] Interrupt Source Flag\nWrite :\nNote2:\nP0_ISRC[3:2] are reserved.\nP1_ISRC[7:6] [1] are reserved.\nP2_ISRC[7] [1:0] are reserved.\nP3_ISRC[7] [3] are reserved.\nP4_ISRC[5:0] are reserved.\nP5_ISRC[7:6] are reserved."
group.long 0xC0++0x7
line.long 0x0 "P3_PMD,P3 I/O Mode Control"
bitfld.long 0x0 14.--15. "PMD7,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "PMD6,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 10.--11. "PMD5,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "PMD4,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 6.--7. "PMD3,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "PMD2,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 2.--3. "PMD1,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "PMD0,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "P3_OFFD,P3 Digital Input Path Disable Control"
hexmask.long.byte 0x4 16.--23. 1. "OFFD,Port 0-5 Pin [N] Digital Input Path Disable Control\n"
group.long 0xCC++0x3
line.long 0x0 "P3_DMASK,P3 Data Output Write Mask"
hexmask.long.byte 0x0 0.--7. 1. "DMASK,Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.."
group.long 0xD8++0xB
line.long 0x0 "P3_IMD,P3 Interrupt Mode Control"
hexmask.long.byte 0x0 0.--7. 1. "IMD,Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If.."
line.long 0x4 "P3_IEN,P3 Interrupt Enable Control"
hexmask.long.byte 0x4 16.--23. 1. "IR_EN,Port 0-5 Pin [N] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n].."
bitfld.long 0x4 0. "IF_EN,Port 0-5 Pin [N] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EB[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: Px.n low level or high to low interrupt Enabled"
line.long 0x8 "P3_ISRC,P3 Interrupt Source Flag"
hexmask.long.byte 0x8 0.--7. 1. "ISRC,Port 0-5 Pin [N] Interrupt Source Flag\nWrite :\nNote2:\nP0_ISRC[3:2] are reserved.\nP1_ISRC[7:6] [1] are reserved.\nP2_ISRC[7] [1:0] are reserved.\nP3_ISRC[7] [3] are reserved.\nP4_ISRC[5:0] are reserved.\nP5_ISRC[7:6] are reserved."
group.long 0x100++0x7
line.long 0x0 "P4_PMD,P4 I/O Mode Control"
bitfld.long 0x0 14.--15. "PMD7,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "PMD6,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 10.--11. "PMD5,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "PMD4,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 6.--7. "PMD3,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "PMD2,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 2.--3. "PMD1,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "PMD0,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "P4_OFFD,P4 Digital Input Path Disable Control"
hexmask.long.byte 0x4 16.--23. 1. "OFFD,Port 0-5 Pin [N] Digital Input Path Disable Control\n"
group.long 0x10C++0x3
line.long 0x0 "P4_DMASK,P4 Data Output Write Mask"
hexmask.long.byte 0x0 0.--7. 1. "DMASK,Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.."
group.long 0x118++0xB
line.long 0x0 "P4_IMD,P4 Interrupt Mode Control"
hexmask.long.byte 0x0 0.--7. 1. "IMD,Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If.."
line.long 0x4 "P4_IEN,P4 Interrupt Enable Control"
hexmask.long.byte 0x4 16.--23. 1. "IR_EN,Port 0-5 Pin [N] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n].."
bitfld.long 0x4 0. "IF_EN,Port 0-5 Pin [N] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EB[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: Px.n low level or high to low interrupt Enabled"
line.long 0x8 "P4_ISRC,P4 Interrupt Source Flag"
hexmask.long.byte 0x8 0.--7. 1. "ISRC,Port 0-5 Pin [N] Interrupt Source Flag\nWrite :\nNote2:\nP0_ISRC[3:2] are reserved.\nP1_ISRC[7:6] [1] are reserved.\nP2_ISRC[7] [1:0] are reserved.\nP3_ISRC[7] [3] are reserved.\nP4_ISRC[5:0] are reserved.\nP5_ISRC[7:6] are reserved."
group.long 0x140++0x7
line.long 0x0 "P5_PMD,P5 I/O Mode Control"
bitfld.long 0x0 14.--15. "PMD7,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "PMD6,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 10.--11. "PMD5,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "PMD4,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 6.--7. "PMD3,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "PMD2,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
newline
bitfld.long 0x0 2.--3. "PMD1,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "PMD0,Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12] [3:2] are reserved.\nP2_PMD[15:14] [3:0] are reserved.\nP3_PMD[15:14] .." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "P5_OFFD,P5 Digital Input Path Disable Control"
hexmask.long.byte 0x4 16.--23. 1. "OFFD,Port 0-5 Pin [N] Digital Input Path Disable Control\n"
group.long 0x14C++0x3
line.long 0x0 "P5_DMASK,P5 Data Output Write Mask"
hexmask.long.byte 0x0 0.--7. 1. "DMASK,Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.."
group.long 0x158++0xB
line.long 0x0 "P5_IMD,P5 Interrupt Mode Control"
hexmask.long.byte 0x0 0.--7. 1. "IMD,Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If.."
line.long 0x4 "P5_IEN,P5 Interrupt Enable Control"
hexmask.long.byte 0x4 16.--23. 1. "IR_EN,Port 0-5 Pin [N] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n].."
bitfld.long 0x4 0. "IF_EN,Port 0-5 Pin [N] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EB[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: Px.n low level or high to low interrupt Enabled"
line.long 0x8 "P5_ISRC,P5 Interrupt Source Flag"
hexmask.long.byte 0x8 0.--7. 1. "ISRC,Port 0-5 Pin [N] Interrupt Source Flag\nWrite :\nNote2:\nP0_ISRC[3:2] are reserved.\nP1_ISRC[7:6] [1] are reserved.\nP2_ISRC[7] [1:0] are reserved.\nP3_ISRC[7] [3] are reserved.\nP4_ISRC[5:0] are reserved.\nP5_ISRC[7:6] are reserved."
endif
sif (cpuis("MINI5?AN"))
group.long 0x0++0x7
line.long 0x0 "P0_PMD,P0 Pin I/O Mode Control"
bitfld.long 0x0 14.--15. "PMD7,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 12.--13. "PMD6,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "PMD5,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 8.--9. "PMD4,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PMD3,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 4.--5. "PMD2,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PMD1,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 0.--1. "PMD0,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
line.long 0x4 "P0_OFFD,P0 Pin OFF Digital Enable"
hexmask.long.byte 0x4 16.--23. 1. "OFFD,OFFD: Px Pin[n] OFF Digital Input Path Enable\n"
group.long 0xC++0x3
line.long 0x0 "P0_DMASK,P0 Data Output Write Mask"
bitfld.long 0x0 0. "DMASK,Px Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT pin[n]. When the DMASK bit[n] is set to 1 the corresponding DOUTn pin is protected. The write signal is masked and writing data to the protect pin is.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
group.long 0x18++0xB
line.long 0x0 "P0_IMD,P0 Interrupt Mode Control"
bitfld.long 0x0 0. "IMD,Port 0-5 Interrupt Mode Control\nIMD[n] is used to control the interrupt by level trigger or edge trigger. If the interrupt is by edge trigger the trigger source is control de-bounced. If the interrupt is by level trigger the input source is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x4 "P0_IEN,P0 Interrupt Enable"
bitfld.long 0x4 16. "IR_EN,Port 0-5 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.\nWhen the IR_EN[n] bit is set to 1:\nIf.." "0: The Px[n] level-high or low-to-high interrupt..,1: The Px[n] level-high or low-to-high interrupt.."
bitfld.long 0x4 0. "IF_EN,Port 0-5 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.\nWhen the IF_EB[n] bit is set to 1:\nIf.." "0: The Px[n] state low-level or high-to-low change..,1: The Px[n] state low-level or high-to-low change.."
line.long 0x8 "P0_ISRC,P0 Interrupt Trigger Source Indicator"
bitfld.long 0x8 0. "ISRC,Port 0-5 Interrupt Trigger Source Indicator\nRead :\n" "0: No interrupt at Px[n].\nNo action,1: Indicates Px[n] generate an interrupt.\nClear.."
group.long 0x40++0x7
line.long 0x0 "P1_PMD,P1 Pin I/O Mode Control"
bitfld.long 0x0 14.--15. "PMD7,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 12.--13. "PMD6,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "PMD5,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 8.--9. "PMD4,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PMD3,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 4.--5. "PMD2,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PMD1,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 0.--1. "PMD0,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
line.long 0x4 "P1_OFFD,P1 Pin OFF Digital Enable"
hexmask.long.byte 0x4 16.--23. 1. "OFFD,OFFD: Px Pin[n] OFF Digital Input Path Enable\n"
group.long 0x4C++0x3
line.long 0x0 "P1_DMASK,P1 Data Output Write Mask"
bitfld.long 0x0 0. "DMASK,Px Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT pin[n]. When the DMASK bit[n] is set to 1 the corresponding DOUTn pin is protected. The write signal is masked and writing data to the protect pin is.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
group.long 0x58++0xB
line.long 0x0 "P1_IMD,P1 Interrupt Mode Control"
bitfld.long 0x0 0. "IMD,Port 0-5 Interrupt Mode Control\nIMD[n] is used to control the interrupt by level trigger or edge trigger. If the interrupt is by edge trigger the trigger source is control de-bounced. If the interrupt is by level trigger the input source is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x4 "P1_IEN,P1 Interrupt Enable"
bitfld.long 0x4 16. "IR_EN,Port 0-5 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.\nWhen the IR_EN[n] bit is set to 1:\nIf.." "0: The Px[n] level-high or low-to-high interrupt..,1: The Px[n] level-high or low-to-high interrupt.."
bitfld.long 0x4 0. "IF_EN,Port 0-5 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.\nWhen the IF_EB[n] bit is set to 1:\nIf.." "0: The Px[n] state low-level or high-to-low change..,1: The Px[n] state low-level or high-to-low change.."
line.long 0x8 "P1_ISRC,P1 Interrupt Trigger Source Indicator"
bitfld.long 0x8 0. "ISRC,Port 0-5 Interrupt Trigger Source Indicator\nRead :\n" "0: No interrupt at Px[n].\nNo action,1: Indicates Px[n] generate an interrupt.\nClear.."
group.long 0x80++0x7
line.long 0x0 "P2_PMD,P2 Pin I/O Mode Control"
bitfld.long 0x0 14.--15. "PMD7,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 12.--13. "PMD6,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "PMD5,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 8.--9. "PMD4,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PMD3,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 4.--5. "PMD2,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PMD1,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 0.--1. "PMD0,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
line.long 0x4 "P2_OFFD,P2 Pin OFF Digital Enable"
hexmask.long.byte 0x4 16.--23. 1. "OFFD,OFFD: Px Pin[n] OFF Digital Input Path Enable\n"
group.long 0x8C++0x3
line.long 0x0 "P2_DMASK,P2 Data Output Write Mask"
bitfld.long 0x0 0. "DMASK,Px Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT pin[n]. When the DMASK bit[n] is set to 1 the corresponding DOUTn pin is protected. The write signal is masked and writing data to the protect pin is.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
group.long 0x98++0xB
line.long 0x0 "P2_IMD,P2 Interrupt Mode Control"
bitfld.long 0x0 0. "IMD,Port 0-5 Interrupt Mode Control\nIMD[n] is used to control the interrupt by level trigger or edge trigger. If the interrupt is by edge trigger the trigger source is control de-bounced. If the interrupt is by level trigger the input source is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x4 "P2_IEN,P2 Interrupt Enable"
bitfld.long 0x4 16. "IR_EN,Port 0-5 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.\nWhen the IR_EN[n] bit is set to 1:\nIf.." "0: The Px[n] level-high or low-to-high interrupt..,1: The Px[n] level-high or low-to-high interrupt.."
bitfld.long 0x4 0. "IF_EN,Port 0-5 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.\nWhen the IF_EB[n] bit is set to 1:\nIf.." "0: The Px[n] state low-level or high-to-low change..,1: The Px[n] state low-level or high-to-low change.."
line.long 0x8 "P2_ISRC,P2 Interrupt Trigger Source Indicator"
bitfld.long 0x8 0. "ISRC,Port 0-5 Interrupt Trigger Source Indicator\nRead :\n" "0: No interrupt at Px[n].\nNo action,1: Indicates Px[n] generate an interrupt.\nClear.."
group.long 0xC0++0x7
line.long 0x0 "P3_PMD,P3 Pin I/O Mode Control"
bitfld.long 0x0 14.--15. "PMD7,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 12.--13. "PMD6,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "PMD5,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 8.--9. "PMD4,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PMD3,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 4.--5. "PMD2,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PMD1,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 0.--1. "PMD0,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
line.long 0x4 "P3_OFFD,P3 Pin OFF Digital Enable"
hexmask.long.byte 0x4 16.--23. 1. "OFFD,OFFD: Px Pin[n] OFF Digital Input Path Enable\n"
group.long 0xCC++0x3
line.long 0x0 "P3_DMASK,P3 Data Output Write Mask"
bitfld.long 0x0 0. "DMASK,Px Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT pin[n]. When the DMASK bit[n] is set to 1 the corresponding DOUTn pin is protected. The write signal is masked and writing data to the protect pin is.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
group.long 0xD8++0xB
line.long 0x0 "P3_IMD,P3 Interrupt Mode Control"
bitfld.long 0x0 0. "IMD,Port 0-5 Interrupt Mode Control\nIMD[n] is used to control the interrupt by level trigger or edge trigger. If the interrupt is by edge trigger the trigger source is control de-bounced. If the interrupt is by level trigger the input source is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x4 "P3_IEN,P3 Interrupt Enable"
bitfld.long 0x4 16. "IR_EN,Port 0-5 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.\nWhen the IR_EN[n] bit is set to 1:\nIf.." "0: The Px[n] level-high or low-to-high interrupt..,1: The Px[n] level-high or low-to-high interrupt.."
bitfld.long 0x4 0. "IF_EN,Port 0-5 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.\nWhen the IF_EB[n] bit is set to 1:\nIf.." "0: The Px[n] state low-level or high-to-low change..,1: The Px[n] state low-level or high-to-low change.."
line.long 0x8 "P3_ISRC,P3 Interrupt Trigger Source Indicator"
bitfld.long 0x8 0. "ISRC,Port 0-5 Interrupt Trigger Source Indicator\nRead :\n" "0: No interrupt at Px[n].\nNo action,1: Indicates Px[n] generate an interrupt.\nClear.."
group.long 0x100++0x7
line.long 0x0 "P4_PMD,P4 Pin I/O Mode Control"
bitfld.long 0x0 14.--15. "PMD7,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 12.--13. "PMD6,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "PMD5,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 8.--9. "PMD4,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PMD3,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 4.--5. "PMD2,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PMD1,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 0.--1. "PMD0,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
line.long 0x4 "P4_OFFD,P4 Pin OFF Digital Enable"
hexmask.long.byte 0x4 16.--23. 1. "OFFD,OFFD: Px Pin[n] OFF Digital Input Path Enable\n"
group.long 0x10C++0x3
line.long 0x0 "P4_DMASK,P4 Data Output Write Mask"
bitfld.long 0x0 0. "DMASK,Px Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT pin[n]. When the DMASK bit[n] is set to 1 the corresponding DOUTn pin is protected. The write signal is masked and writing data to the protect pin is.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
group.long 0x118++0xB
line.long 0x0 "P4_IMD,P4 Interrupt Mode Control"
bitfld.long 0x0 0. "IMD,Port 0-5 Interrupt Mode Control\nIMD[n] is used to control the interrupt by level trigger or edge trigger. If the interrupt is by edge trigger the trigger source is control de-bounced. If the interrupt is by level trigger the input source is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x4 "P4_IEN,P4 Interrupt Enable"
bitfld.long 0x4 16. "IR_EN,Port 0-5 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.\nWhen the IR_EN[n] bit is set to 1:\nIf.." "0: The Px[n] level-high or low-to-high interrupt..,1: The Px[n] level-high or low-to-high interrupt.."
bitfld.long 0x4 0. "IF_EN,Port 0-5 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.\nWhen the IF_EB[n] bit is set to 1:\nIf.." "0: The Px[n] state low-level or high-to-low change..,1: The Px[n] state low-level or high-to-low change.."
line.long 0x8 "P4_ISRC,P4 Interrupt Trigger Source Indicator"
bitfld.long 0x8 0. "ISRC,Port 0-5 Interrupt Trigger Source Indicator\nRead :\n" "0: No interrupt at Px[n].\nNo action,1: Indicates Px[n] generate an interrupt.\nClear.."
group.long 0x140++0x7
line.long 0x0 "P5_PMD,P5 Pin I/O Mode Control"
bitfld.long 0x0 14.--15. "PMD7,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 12.--13. "PMD6,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "PMD5,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 8.--9. "PMD4,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PMD3,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 4.--5. "PMD2,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PMD1,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
bitfld.long 0x0 0.--1. "PMD0,Px Pin[n] I/O Mode Control\n" "0,1,2,3"
line.long 0x4 "P5_OFFD,P5 Pin OFF Digital Enable"
hexmask.long.byte 0x4 16.--23. 1. "OFFD,OFFD: Px Pin[n] OFF Digital Input Path Enable\n"
group.long 0x14C++0x3
line.long 0x0 "P5_DMASK,P5 Data Output Write Mask"
bitfld.long 0x0 0. "DMASK,Px Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT pin[n]. When the DMASK bit[n] is set to 1 the corresponding DOUTn pin is protected. The write signal is masked and writing data to the protect pin is.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
group.long 0x158++0xB
line.long 0x0 "P5_IMD,P5 Interrupt Mode Control"
bitfld.long 0x0 0. "IMD,Port 0-5 Interrupt Mode Control\nIMD[n] is used to control the interrupt by level trigger or edge trigger. If the interrupt is by edge trigger the trigger source is control de-bounced. If the interrupt is by level trigger the input source is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x4 "P5_IEN,P5 Interrupt Enable"
bitfld.long 0x4 16. "IR_EN,Port 0-5 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.\nWhen the IR_EN[n] bit is set to 1:\nIf.." "0: The Px[n] level-high or low-to-high interrupt..,1: The Px[n] level-high or low-to-high interrupt.."
bitfld.long 0x4 0. "IF_EN,Port 0-5 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.\nWhen the IF_EB[n] bit is set to 1:\nIf.." "0: The Px[n] state low-level or high-to-low change..,1: The Px[n] state low-level or high-to-low change.."
line.long 0x8 "P5_ISRC,P5 Interrupt Trigger Source Indicator"
bitfld.long 0x8 0. "ISRC,Port 0-5 Interrupt Trigger Source Indicator\nRead :\n" "0: No interrupt at Px[n].\nNo action,1: Indicates Px[n] generate an interrupt.\nClear.."
group.long 0x200++0x7
line.long 0x0 "P00_DOUT,P0.0 Data Output Value"
bitfld.long 0x0 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x4 "P01_DOUT,P0.1 Data Output Value"
bitfld.long 0x4 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
group.long 0x210++0x13
line.long 0x0 "P04_DOUT,P0.4 Data Output Value"
bitfld.long 0x0 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x4 "P05_DOUT,P0.5 Data Output Value"
bitfld.long 0x4 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x8 "P06_DOUT,P0.6 Data Output Value"
bitfld.long 0x8 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0xC "P07_DOUT,P0.7 Data Output Value"
bitfld.long 0xC 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x10 "P10_DOUT,P1.0 Data Output Value"
bitfld.long 0x10 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
group.long 0x228++0xF
line.long 0x0 "P12_DOUT,P1.2 Data Output Value"
bitfld.long 0x0 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x4 "P13_DOUT,P1.3 Data Output Value"
bitfld.long 0x4 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x8 "P14_DOUT,P1.4 Data Output Value"
bitfld.long 0x8 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0xC "P15_DOUT,P1.5 Data Output Value"
bitfld.long 0xC 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
group.long 0x248++0x13
line.long 0x0 "P22_DOUT,P2.2 Data Output Value"
bitfld.long 0x0 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x4 "P23_DOUT,P2.3 Data Output Value"
bitfld.long 0x4 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x8 "P24_DOUT,P2.4 Data Output Value"
bitfld.long 0x8 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0xC "P25_DOUT,P2.5 Data Output Value"
bitfld.long 0xC 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x10 "P26_DOUT,P2.6 Data Output Value"
bitfld.long 0x10 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
group.long 0x260++0xB
line.long 0x0 "P30_DOUT,P3.0 Data Output Value"
bitfld.long 0x0 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x4 "P31_DOUT,P3.1 Data Output Value"
bitfld.long 0x4 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x8 "P32_DOUT,P3.2 Data Output Value"
bitfld.long 0x8 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
group.long 0x270++0xB
line.long 0x0 "P34_DOUT,P3.4 Data Output Value"
bitfld.long 0x0 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x4 "P35_DOUT,P3.5 Data Output Value"
bitfld.long 0x4 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x8 "P36_DOUT,P3.6 Data Output Value"
bitfld.long 0x8 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
group.long 0x298++0x1B
line.long 0x0 "P46_DOUT,P4.6 Data Output Value"
bitfld.long 0x0 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x4 "P47_DOUT,P4.7 Data Output Value"
bitfld.long 0x4 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x8 "P50_DOUT,P5.0 Data Output Value"
bitfld.long 0x8 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0xC "P51_DOUT,P5.1 Data Output Value"
bitfld.long 0xC 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x10 "P52_DOUT,P5.2 Data Output Value"
bitfld.long 0x10 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x14 "P53_DOUT,P5.3 Data Output Value"
bitfld.long 0x14 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
line.long 0x18 "P54_DOUT,P5.4 Data Output Value"
bitfld.long 0x18 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
endif
group.long 0x8++0x3
line.long 0x0 "P0_DOUT,P0 Data Output Value"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "DOUT,Port 0-5 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output and Quasi-bidirectional mode."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "DOUT,Px Pin[n] Output Value\nEach of these bits controls the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px pin[n] will drive Low if the corresponding..,1: Px pin[n] will drive High if the corresponding.."
endif
rgroup.long 0x10++0x3
line.long 0x0 "P0_PIN,P0 Pin Value"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "PIN,Port 0-5 Pin [N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "PIN,Px Pin[n] Value\n" "0,1"
endif
group.long 0x14++0x3
line.long 0x0 "P0_DBEN,P0 De-bounce Enable Control"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Port 0-5 Pin [N] Input Signal De-Bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "DBEN,Px Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle the input signal transition is regarded as the.." "0: The pin[n] de-bounce function disabled,1: The pin[n] de-bounce function enabled"
endif
group.long 0x48++0x3
line.long 0x0 "P1_DOUT,P1 Data Output Value"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "DOUT,Port 0-5 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output and Quasi-bidirectional mode."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "DOUT,Px Pin[n] Output Value\nEach of these bits controls the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px pin[n] will drive Low if the corresponding..,1: Px pin[n] will drive High if the corresponding.."
endif
rgroup.long 0x50++0x3
line.long 0x0 "P1_PIN,P1 Pin Value"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "PIN,Port 0-5 Pin [N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "PIN,Px Pin[n] Value\n" "0,1"
endif
group.long 0x54++0x3
line.long 0x0 "P1_DBEN,P1 De-bounce Enable Control"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Port 0-5 Pin [N] Input Signal De-Bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "DBEN,Px Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle the input signal transition is regarded as the.." "0: The pin[n] de-bounce function disabled,1: The pin[n] de-bounce function enabled"
endif
group.long 0x88++0x3
line.long 0x0 "P2_DOUT,P2 Data Output Value"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "DOUT,Port 0-5 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output and Quasi-bidirectional mode."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "DOUT,Px Pin[n] Output Value\nEach of these bits controls the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px pin[n] will drive Low if the corresponding..,1: Px pin[n] will drive High if the corresponding.."
endif
rgroup.long 0x90++0x3
line.long 0x0 "P2_PIN,P2 Pin Value"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "PIN,Port 0-5 Pin [N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "PIN,Px Pin[n] Value\n" "0,1"
endif
group.long 0x94++0x3
line.long 0x0 "P2_DBEN,P2 De-bounce Enable Control"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Port 0-5 Pin [N] Input Signal De-Bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "DBEN,Px Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle the input signal transition is regarded as the.." "0: The pin[n] de-bounce function disabled,1: The pin[n] de-bounce function enabled"
endif
group.long 0xC8++0x3
line.long 0x0 "P3_DOUT,P3 Data Output Value"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "DOUT,Port 0-5 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output and Quasi-bidirectional mode."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "DOUT,Px Pin[n] Output Value\nEach of these bits controls the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px pin[n] will drive Low if the corresponding..,1: Px pin[n] will drive High if the corresponding.."
endif
rgroup.long 0xD0++0x3
line.long 0x0 "P3_PIN,P3 Pin Value"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "PIN,Port 0-5 Pin [N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "PIN,Px Pin[n] Value\n" "0,1"
endif
group.long 0xD4++0x3
line.long 0x0 "P3_DBEN,P3 De-bounce Enable Control"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Port 0-5 Pin [N] Input Signal De-Bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "DBEN,Px Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle the input signal transition is regarded as the.." "0: The pin[n] de-bounce function disabled,1: The pin[n] de-bounce function enabled"
endif
group.long 0x108++0x3
line.long 0x0 "P4_DOUT,P4 Data Output Value"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "DOUT,Port 0-5 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output and Quasi-bidirectional mode."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "DOUT,Px Pin[n] Output Value\nEach of these bits controls the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px pin[n] will drive Low if the corresponding..,1: Px pin[n] will drive High if the corresponding.."
endif
rgroup.long 0x110++0x3
line.long 0x0 "P4_PIN,P4 Pin Value"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "PIN,Port 0-5 Pin [N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "PIN,Px Pin[n] Value\n" "0,1"
endif
group.long 0x114++0x3
line.long 0x0 "P4_DBEN,P4 De-bounce Enable Control"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Port 0-5 Pin [N] Input Signal De-Bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "DBEN,Px Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle the input signal transition is regarded as the.." "0: The pin[n] de-bounce function disabled,1: The pin[n] de-bounce function enabled"
endif
group.long 0x148++0x3
line.long 0x0 "P5_DOUT,P5 Data Output Value"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "DOUT,Port 0-5 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output and Quasi-bidirectional mode."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "DOUT,Px Pin[n] Output Value\nEach of these bits controls the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px pin[n] will drive Low if the corresponding..,1: Px pin[n] will drive High if the corresponding.."
endif
rgroup.long 0x150++0x3
line.long 0x0 "P5_PIN,P5 Pin Value"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "PIN,Port 0-5 Pin [N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "PIN,Px Pin[n] Value\n" "0,1"
endif
group.long 0x154++0x3
line.long 0x0 "P5_DBEN,P5 De-bounce Enable Control"
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Port 0-5 Pin [N] Input Signal De-Bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 0. "DBEN,Px Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle the input signal transition is regarded as the.." "0: The pin[n] de-bounce function disabled,1: The pin[n] de-bounce function enabled"
endif
group.long 0x180++0x3
line.long 0x0 "DBNCECON,Interrupt De-bounce Control"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x0 5. "ICLKON,Interrupt Clock On Mode\nNote: It is recommended to turn off this bit to save system power if no special application concern." "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
hexmask.long.byte 0x0 0.--3. 1. "DBCLKSEL,De-Bounce Sampling Cycle Selection"
newline
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x0 5. "ICLK_ON,Interrupt Clock On Mode\nNote: It is recommended to turn off this bit to save system power if no special application concern." "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 5. "ICLK_ON,Interrupt Clock On Mode\nSetting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled.\n" "0: The clock Disabled if the P0/1/2/3/4[n]..,1: Interrupt generated circuit clock always Enabled"
newline
endif
bitfld.long 0x0 4. "DBCLKSRC,De-Bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
sif (cpuis("MINI5?AN"))
hexmask.long.byte 0x0 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection\n"
endif
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
group.long 0x200++0x7
line.long 0x0 "P00_PDIO,GPIO P0.0 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x0 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x4 "P01_PDIO,GPIO P0.1 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x4 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
group.long 0x210++0x13
line.long 0x0 "P04_PDIO,GPIO P0.4 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x0 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x4 "P05_PDIO,GPIO P0.5 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x4 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x8 "P06_PDIO,GPIO P0.6 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x8 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0xC "P07_PDIO,GPIO P0.7 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0xC 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x10 "P10_PDIO,GPIO P1.0 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x10 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
group.long 0x228++0xF
line.long 0x0 "P12_PDIO,GPIO P1.2 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x0 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x4 "P13_PDIO,GPIO P1.3 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x4 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x8 "P14_PDIO,GPIO P1.4 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x8 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0xC "P15_PDIO,GPIO P1.5 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0xC 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
group.long 0x248++0x13
line.long 0x0 "P22_PDIO,GPIO P2.2 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x0 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x4 "P23_PDIO,GPIO P2.3 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x4 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x8 "P24_PDIO,GPIO P2.4 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x8 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0xC "P25_PDIO,GPIO P2.5 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0xC 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x10 "P26_PDIO,GPIO P2.6 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x10 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
group.long 0x260++0xB
line.long 0x0 "P30_PDIO,GPIO P3.0 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x0 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x4 "P31_PDIO,GPIO P3.1 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x4 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x8 "P32_PDIO,GPIO P3.2 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x8 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
group.long 0x270++0xB
line.long 0x0 "P34_PDIO,GPIO P3.4 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x0 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x4 "P35_PDIO,GPIO P3.5 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x4 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x8 "P36_PDIO,GPIO P3.6 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x8 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
group.long 0x298++0x1F
line.long 0x0 "P46_PDIO,GPIO P4.6 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x0 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x4 "P47_PDIO,GPIO P4.7 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x4 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x8 "P50_PDIO,GPIO P5.0 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x8 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0xC "P51_PDIO,GPIO P5.1 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0xC 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x10 "P52_PDIO,GPIO P5.2 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x10 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x14 "P53_PDIO,GPIO P5.3 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x14 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x18 "P54_PDIO,GPIO P5.4 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x18 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
line.long 0x1C "P55_PDIO,GPIO P5.5 Pin Data Input/Output"
sif (cpuis("MINI5?XAE"))
bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example writing P01_PDIO will reflect the written value to bit P0_DOUT[1] reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing.." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x1C 0. "P_PDIO,GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.."
endif
endif
sif (cpuis("MINI5?AN"))
group.long 0x2B4++0x3
line.long 0x0 "P55_DOUT,P5.5 Data Output Value"
bitfld.long 0x0 0. "P_DOUT,P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n" "0: The corresponding GPIO pin set to..,1: The corresponding GPIO pin set to.."
endif
tree.end
sif (cpuis("MINI5?XAE"))
tree "HDIV (Hardware Divider)"
base ad:0x50014000
group.long 0x0++0xF
line.long 0x0 "HDIV_DIVIDEND,Dividend Source Register"
hexmask.long 0x0 0.--31. 1. "DIVIDEND,Dividend Source\nThis register is given the dividend of divider before calculation starting."
line.long 0x4 "HDIV_DIVISOR,Divisor Source Resister"
hexmask.long.word 0x4 0.--15. 1. "DIVISOR,Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written hardware divider will start calculate."
line.long 0x8 "HDIV_QUOTIENT,Quotient Result Resister"
hexmask.long 0x8 0.--31. 1. "QUOTIENT,Quotient Result\nThis register holds the quotient result of divider after calculation complete."
line.long 0xC "HDIV_REM,Remainder Result Register"
hexmask.long 0xC 0.--31. 1. "REM,Remainder Result\nThe remainder of hardware divider is 16-bit sign integer (REM[15:0]) with sign extension (REM[31:16]) to 32-bit integer."
rgroup.long 0x10++0x3
line.long 0x0 "HDIV_STATUS,Divider Status Register"
bitfld.long 0x0 1. "DIVBYZERO,Divisor Zero Warning\nNote: The DIVBYZERO flag is used to indicate divide-by-zero situation and updated whenever HDIV_DIVISOR is written. This register is read only." "0: The divisor is not 0,1: The divisor is 0"
tree.end
endif
tree "I2C (I2C Serial Interface Controller)"
base ad:0x40020000
sif (cpuis("MINI5?XAE"))
group.long 0x0++0xB
line.long 0x0 "I2C_CTL,I2C Control Register"
bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C Controller Disabled,1: I2C Controller Enabled"
newline
bitfld.long 0x0 5. "STA,I2C START Control Bit\nSetting STA to logic 1 to enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free." "0,1"
bitfld.long 0x0 4. "STO,I2C STOP Control Bit\nIn Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode setting STO resets.." "0,1"
newline
bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register the SI flag is set by hardware and if bit INTEN (I2C_CTL[7]) is set the I2C interrupt is requested. SI must be cleared by software. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x0 2. "AA,Assert Acknowledge Control Bit" "0,1"
line.long 0x4 "I2C_ADDR0,I2C Slave Address Register 0"
hexmask.long.byte 0x4 1.--7. 1. "ADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x8 "I2C_DAT,I2C Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of the I2C serial port."
rgroup.long 0xC++0x3
line.long 0x0 "I2C_STATUS,I2C Status Register"
hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status Register"
group.long 0x10++0x23
line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
hexmask.long.byte 0x0 0.--7. 1. "DIVIDER,I2C Clock Divided Register\nNote: The minimum value of DIVIDER is 4."
line.long 0x4 "I2C_TOCTL,I2C Time-Out Counter Register"
bitfld.long 0x4 2. "TOCEN,Time-Out Counter Enabled\nNote: When the 14-bit time-out counter is enabled it will start counting when SI is clear. Setting 1to the SI flag will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x4 1. "TOCDIV4,Time-Out Counter Input Clock Divided By 4\nNote: When enabled the time-out period is extended 4 times." "0: Time-out counter input clock divided by 4 Disabled,1: Time-out counter input clock divided by 4 Enabled"
newline
bitfld.long 0x4 0. "TOIF,Time-Out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit." "0,1"
line.long 0x8 "I2C_ADDR1,I2C Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "ADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0xC "I2C_ADDR2,I2C Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "ADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x10 "I2C_ADDR3,I2C Slave Address Register 3"
hexmask.long.byte 0x10 1.--7. 1. "ADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register 0"
hexmask.long.byte 0x14 1.--7. 1. "ADDRMSK,I2C Address Mask Register"
line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register 1"
hexmask.long.byte 0x18 1.--7. 1. "ADDRMSK,I2C Address Mask Register"
line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register 2"
hexmask.long.byte 0x1C 1.--7. 1. "ADDRMSK,I2C Address Mask Register"
line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register 3"
hexmask.long.byte 0x20 1.--7. 1. "ADDRMSK,I2C Address Mask Register"
group.long 0x3C++0x7
line.long 0x0 "I2C_CTL1,I2C Control Register 1"
bitfld.long 0x0 4. "URIEN,I2C UNDER RUN Interrupt Control Bit\nSetting URIEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted FIFO." "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "OVIEN,I2C OVER RUN Interrupt Control Bit\nSetting OVIEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received FIFO." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "NSTRETCH,NO STRETCH The I2C BUS" "0: The I2C SCL bus is stretched by hardware if the..,1: The I2C SCL bus is not stretched by hardware if.."
bitfld.long 0x0 1. "FIFOEN,FIFO Mode Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 0. "WKEN,Wake-Up Enable\nThe system can be wake up by I2C bus when the system is set into power mode and the received data matched one of the addresses in Address Register." "0: I2C wake up function Disabled,1: I2C wake up function Enabled"
line.long 0x4 "I2C_STATUS1,I2C Status Register 1"
bitfld.long 0x4 4. "URIF,I2C UNDER RUN Status Bit" "0,1"
bitfld.long 0x4 3. "OVIF,I2C OVER RUN Status Bit" "0,1"
newline
bitfld.long 0x4 2. "EMPTY,I2C TWO LEVEL FIFO EMPTY" "0,1"
bitfld.long 0x4 1. "FULL,I2C TWO LEVEL FIFO FULL" "0,1"
newline
bitfld.long 0x4 0. "WKIF,I2C Wake-Up Interrupt Flag\nWhen chip is woken up from Power-Down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
endif
sif (cpuis("MINI5??DE"))
group.long 0x0++0x7
line.long 0x0 "I2CON,I2C Control Register"
bitfld.long 0x0 7. "EI,Interrupt Enable Control\n" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
bitfld.long 0x0 6. "ENS1,I2C Controller Enable Control\n" "0: I2C Controller Disabled,1: I2C Controller Enabled"
newline
bitfld.long 0x0 5. "STA,I2C START Control Bit\nSetting STA to logic 1 to enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free." "0,1"
bitfld.long 0x0 4. "STO,I2C STOP Control Bit\nIn Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode setting STO resets.." "0,1"
newline
bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON[7]) is set the I2C interrupt is requested. SI must be cleared by software. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x0 2. "AA,Assert Acknowledge Control Bit\n" "0,1"
line.long 0x4 "I2CADRR0,I2C Slave Address Register 0"
endif
sif (cpuis("MINI5??DE"))
group.long 0x4++0x7
line.long 0x0 "I2CADDR0,I2C Slave Address Register 0"
hexmask.long.byte 0x0 1.--7. 1. "I2CADDR,I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x0 0. "GC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x4 "I2CDAT,I2C DATA Register"
hexmask.long.byte 0x4 0.--7. 1. "I2CDAT,I2C Data Bits\nBit [7:0] is located with the 8-bit transferred data of the I2C serial port."
rgroup.long 0xC++0x3
line.long 0x0 "I2CSTATUS,I2C Status Register"
hexmask.long.byte 0x0 0.--7. 1. "I2CSTATUS,I2C Status Bits\n"
group.long 0x10++0x23
line.long 0x0 "I2CLK,I2C Clock Divided Register"
hexmask.long.byte 0x0 0.--7. 1. "I2CLK,I2C Clock Divided Bits\nNote: The minimum value of I2CLK is 4."
line.long 0x4 "I2CTOC,I2C Time-out Counter Register"
bitfld.long 0x4 2. "ENTI,Time-out Counter Enable Control\nNote: When the 14-bit time-out counter is enabled it will start counting when SI is clear. Setting 1to the SI flag will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x4 1. "DIV4,Time-out Counter Input Clock Divided By 4\nNote: When enabled the time-out period is extended 4 times." "0: Time-out counter input clock divided by 4 Disabled,1: Time-out counter input clock divided by 4 Enabled"
newline
bitfld.long 0x4 0. "TIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nNote: Software can write 1 to clear this bit." "0,1"
line.long 0x8 "I2CADDR1,I2C Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "I2CADDR,I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x8 0. "GC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0xC "I2CADDR2,I2C Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "I2CADDR,I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0xC 0. "GC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x10 "I2CADDR3,I2C Slave Address Register 3"
hexmask.long.byte 0x10 1.--7. 1. "I2CADDR,I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x10 0. "GC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x14 "I2CADM0,I2C Slave Address Mask Register 0"
hexmask.long.byte 0x14 1.--7. 1. "I2CADM,I2C Address Mask Bits\n"
line.long 0x18 "I2CADM1,I2C Slave Address Mask Register 1"
hexmask.long.byte 0x18 1.--7. 1. "I2CADM,I2C Address Mask Bits\n"
line.long 0x1C "I2CADM2,I2C Slave Address Mask Register 2"
hexmask.long.byte 0x1C 1.--7. 1. "I2CADM,I2C Address Mask Bits\n"
line.long 0x20 "I2CADM3,I2C Slave Address Mask Register 3"
hexmask.long.byte 0x20 1.--7. 1. "I2CADM,I2C Address Mask Bits\n"
group.long 0x3C++0x7
line.long 0x0 "I2CCON2,I2C Control Register 2"
bitfld.long 0x0 4. "UNDER_INTEN,I2C UNDER RUN Interrupt Control Bit\nSetting UNDER_INTEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted FIFO.\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "OVER_INTEN,I2C OVER RUN Interrupt Control Bit\nSetting OVER_INTEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received FIFO.\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "NOSTRETCH,NO STRETCH The I2C BUS\n" "0: The I2C SCL bus is stretched by hardware if the..,1: The I2C SCL bus is not stretched by hardware if.."
bitfld.long 0x0 1. "TWOFF_EN,TWO LEVEL FIFO Enable Control\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 0. "WAKEUPEN,Wake-up Enable Control\nThe system can be wake-up by I2C bus when the system is set into power mode and the received data matched one of the addresses in Address Register." "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
line.long 0x4 "I2CSTATUS2,I2C Status Register 2"
bitfld.long 0x4 4. "UNDERUN,I2C UNDER RUN Status Bit\n" "0,1"
bitfld.long 0x4 3. "OVERUN,I2C OVER RUN Status Bit\n" "0,1"
newline
bitfld.long 0x4 2. "EMPTY,I2C TWO LEVEL FIFO EMPTY\n" "0,1"
bitfld.long 0x4 1. "FULL,I2C TWO LEVEL FIFO FULL\n" "0,1"
newline
bitfld.long 0x4 0. "WAKEUPIF,I2C Wake-up Interrupt Flag\nWhen chip is woken up from Power-Down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
endif
sif (cpuis("MINI5?AN"))
group.long 0x0++0x7
line.long 0x0 "I2CON,I2C Control Register"
bitfld.long 0x0 7. "EI,Enable Interrupt\n" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
bitfld.long 0x0 6. "ENSI,I2C Controller Enable Bit\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "STA,I2C START Control Bit\nSetting STA to logic 1 will enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free." "0,1"
bitfld.long 0x0 4. "STO,I2C STOP Control Bit\nIn Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode setting STO resets.." "0,1"
newline
bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON[7]) is set the I2C interrupt is requested. SI must be cleared by software. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x0 2. "AA,Assert Acknowledge Control Bit\n" "0,1"
line.long 0x4 "I2CADRR0,I2C Slave Address Register 0"
endif
sif (cpuis("MINI5?AN"))
group.long 0x4++0x7
line.long 0x0 "I2CADDR0,I2C Slave Address Register 0"
hexmask.long.byte 0x0 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x0 0. "GC,General Call Function\n" "0: Disable General Call Function,1: Enable General Call Function"
line.long 0x4 "I2CDAT,I2C DATA Register"
hexmask.long.byte 0x4 0.--7. 1. "I2CDAT,I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of the I2C serial port."
rgroup.long 0xC++0x3
line.long 0x0 "I2CSTATUS,I2C Status Register"
hexmask.long.byte 0x0 0.--7. 1. "I2CSTATUS,I2C Status Register\nThe status register of I2C controller:\n"
group.long 0x10++0x23
line.long 0x0 "I2CLK,I2C Clock Divided Register"
hexmask.long.byte 0x0 0.--7. 1. "I2CLK,I2C Clock Divided Register\n"
line.long 0x4 "I2CTOC,I2C Time-out Counter Register"
bitfld.long 0x4 2. "ENTI,Time-out Counter Enabled\nWhen enabled the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared." "0: Disabled,1: Enabled"
bitfld.long 0x4 1. "DIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is prolong 4 times." "0: Disabled,1: Enabled"
newline
bitfld.long 0x4 0. "TIF,Time-out Flag\n" "0: Software can clear the flag by writing 1 to this..,1: Time-out flag is set by hardware. It can.."
line.long 0x8 "I2CADDR1,I2C Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x8 0. "GC,General Call Function\n" "0: Disable General Call Function,1: Enable General Call Function"
line.long 0xC "I2CADDR2,I2C Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0xC 0. "GC,General Call Function\n" "0: Disable General Call Function,1: Enable General Call Function"
line.long 0x10 "I2CADDR3,I2C Slave Address Register 3"
hexmask.long.byte 0x10 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x10 0. "GC,General Call Function\n" "0: Disable General Call Function,1: Enable General Call Function"
line.long 0x14 "I2CADM0,I2C Slave Address Mask Register 0"
hexmask.long.byte 0x14 1.--7. 1. "I2CADMx,I2C Address Mask register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to 1 the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x18 "I2CADM1,I2C Slave Address Mask Register 1"
hexmask.long.byte 0x18 1.--7. 1. "I2CADMx,I2C Address Mask register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to 1 the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x1C "I2CADM2,I2C Slave Address Mask Register 2"
hexmask.long.byte 0x1C 1.--7. 1. "I2CADMx,I2C Address Mask register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to 1 the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x20 "I2CADM3,I2C Slave Address Mask Register 3"
hexmask.long.byte 0x20 1.--7. 1. "I2CADMx,I2C Address Mask register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to 1 the received corresponding address bit is don't-care. If the bit is set.."
group.long 0x3C++0x7
line.long 0x0 "I2CON2,I2C Control Register 2"
bitfld.long 0x0 4. "UNDER_INTEN,I2C UNDER RUN Interrupt Control Bit\nSetting UNDER_INTEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted fifo." "0,1"
bitfld.long 0x0 3. "OVER_INTEN,I2C OVER RUN Interrupt Control Bit\nSetting OVER_INTEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received fifo." "0,1"
newline
bitfld.long 0x0 2. "NOSTRETCH,NO STRETCH the I2C BUS\n" "0: The I2C SCL bus is stretched by hardware if the..,1: The I2C SCL bus is not stretched by hardware if.."
bitfld.long 0x0 1. "TWOFF_EN,TWO LEVEL FIFO Enable\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 0. "WAKEUPEN,Wake-Up Enable\nThe system can be wake up by I2C bus when the system is set into power mode and the received data matched one of the addresses in Address Register." "0: Disabled,1: Enabled"
line.long 0x4 "I2CSTATUS2,I2C Status Register 2"
bitfld.long 0x4 4. "UNDERUN,I2C UNDER RUN Status Bit\n" "0,1"
bitfld.long 0x4 3. "OVERUN,I2C OVER RUN Status Bit\n" "0,1"
newline
bitfld.long 0x4 2. "EMPTY,TWO LEVEL FIFO EMPTY\nThis bit is set when RX_POINTER is equal to 0." "0,1"
bitfld.long 0x4 1. "FULL,TWO LEVEL FIFO FULL\nThis bit is set when TX_POINTER is equal to 2" "0,1"
newline
bitfld.long 0x4 0. "WAKEUP,Wake Up\nThis bit indicates the wake-up function is done." "0,1"
endif
tree.end
tree "INT (Interrupt Multiplexer Control Registers)"
base ad:0x50000300
sif (cpuis("MINI5?XAE"))
rgroup.long 0x0++0x27
line.long 0x0 "IRQ0SRC,IRQ0 (BOD) Interrupt Source Identity"
bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0x4 "IRQ1SRC,IRQ1 (BOD) Interrupt Source Identity"
bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0x8 "IRQ2SRC,IRQ2 (BOD) Interrupt Source Identity"
bitfld.long 0x8 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0xC "IRQ3SRC,IRQ3 (BOD) Interrupt Source Identity"
bitfld.long 0xC 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0x10 "IRQ4SRC,IRQ4 (BOD) Interrupt Source Identity"
bitfld.long 0x10 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0x14 "IRQ5SRC,IRQ5 (BOD) Interrupt Source Identity"
bitfld.long 0x14 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0x18 "IRQ6SRC,IRQ6 (BOD) Interrupt Source Identity"
bitfld.long 0x18 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0x1C "IRQ7SRC,IRQ7 (BOD) Interrupt Source Identity"
bitfld.long 0x1C 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0x20 "IRQ8SRC,IRQ8 (BOD) Interrupt Source Identity"
bitfld.long 0x20 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0x24 "IRQ9SRC,IRQ9 (BOD) Interrupt Source Identity"
bitfld.long 0x24 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
rgroup.long 0x30++0xB
line.long 0x0 "IRQ12SRC,IRQ12 (BOD) Interrupt Source Identity"
bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0x4 "IRQ13SRC,IRQ13 (BOD) Interrupt Source Identity"
bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0x8 "IRQ14SRC,IRQ14 (BOD) Interrupt Source Identity"
bitfld.long 0x8 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
rgroup.long 0x40++0xB
line.long 0x0 "IRQ16SRC,IRQ16 (BOD) Interrupt Source Identity"
bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0x4 "IRQ17SRC,IRQ17 (BOD) Interrupt Source Identity"
bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0x8 "IRQ18SRC,IRQ18 (BOD) Interrupt Source Identity"
bitfld.long 0x8 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
rgroup.long 0x64++0x3
line.long 0x0 "IRQ25SRC,IRQ25 (BOD) Interrupt Source Identity"
bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
rgroup.long 0x70++0x7
line.long 0x0 "IRQ28SRC,IRQ28 (BOD) Interrupt Source Identity"
bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
line.long 0x4 "IRQ29SRC,IRQ29 (BOD) Interrupt Source Identity"
bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source" "0,1,2,3,4,5,6,7"
group.long 0x80++0x7
line.long 0x0 "NMICTL,NMI Source Interrupt Select Control Register"
bitfld.long 0x0 8. "NMISELEN,NMI Interrupt Enable Control (Write Protected)\nNote: This bit is the protected bit and programming it needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address.." "0: NMI interrupt Disabled,1: NMI interrupt Enabled"
hexmask.long.byte 0x0 0.--4. 1. "NMTSEL,NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMTSEL."
line.long 0x4 "IRQSTS,MCU IRQ Number Identity Register"
hexmask.long 0x4 0.--31. 1. "IRQ,MCU IRQ Source Register\nThe IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There are two modes to generate interrupt to Cortex-M0 - the normal mode and test mode.\nThe IRQ collects all.."
endif
sif (cpuis("MINI5??DE"))
rgroup.long 0x0++0x7F
line.long 0x0 "IRQ0_SRC,IRQ0 (BOD) Interrupt Source Identity"
bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x4 "IRQ1_SRC,IRQ1 (WDT) Interrupt Source Identity"
bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x8 "IRQ2_SRC,IRQ2 (EINT0) Interrupt Source Identity"
bitfld.long 0x8 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0xC "IRQ3_SRC,IRQ3 (EINT1) Interrupt Source Identity"
bitfld.long 0xC 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x10 "IRQ4_SRC,IRQ4 (GP0/1) Interrupt Source Identity"
bitfld.long 0x10 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x14 "IRQ5_SRC,IRQ5 (GP2/3/4) Interrupt Source Identity"
bitfld.long 0x14 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x18 "IRQ6_SRC,IRQ6 (PWM) Interrupt Source Identity"
bitfld.long 0x18 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x1C "IRQ7_SRC,IRQ7 (BRAKE) Interrupt Source Identity"
bitfld.long 0x1C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x20 "IRQ8_SRC,IRQ8 (TMR0) Interrupt Source Identity"
bitfld.long 0x20 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x24 "IRQ9_SRC,IRQ9 (TMR1) Interrupt Source Identity"
bitfld.long 0x24 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x28 "IRQ10_SRC,Reserved"
bitfld.long 0x28 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x2C "IRQ11_SRC,Reserved"
bitfld.long 0x2C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x30 "IRQ12_SRC,IRQ12 (UART) Interrupt Source Identity"
bitfld.long 0x30 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x34 "IRQ13_SRC,Reserved"
bitfld.long 0x34 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x38 "IRQ14_SRC,IRQ14 (SPI) Interrupt Source Identity"
bitfld.long 0x38 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x3C "IRQ15_SRC,Reserved"
bitfld.long 0x3C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x40 "IRQ16_SRC,IRQ16 (GP5) Interrupt Source Identity"
bitfld.long 0x40 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x44 "IRQ17_SRC,IRQ17 (HIRC Trim) Interrupt Source Identity"
bitfld.long 0x44 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x48 "IRQ18_SRC,IRQ18 (I2C) Interrupt Source Identity"
bitfld.long 0x48 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x4C "IRQ19_SRC,Reserved"
bitfld.long 0x4C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x50 "IRQ20_SRC,Reserved"
bitfld.long 0x50 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x54 "IRQ21_SRC,Reserved"
bitfld.long 0x54 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x58 "IRQ22_SRC,Reserved"
bitfld.long 0x58 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x5C "IRQ23_SRC,Reserved"
bitfld.long 0x5C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x60 "IRQ24_SRC,Reserved"
bitfld.long 0x60 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x64 "IRQ25_SRC,IRQ25 (ACMP) Interrupt Source Identity"
bitfld.long 0x64 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x68 "IRQ26_SRC,Reserved"
bitfld.long 0x68 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x6C "IRQ27_SRC,Reserved"
bitfld.long 0x6C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x70 "IRQ28_SRC,IRQ28 (PWRWU) Interrupt Source Identity"
bitfld.long 0x70 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x74 "IRQ29_SRC,IRQ29 (ADC) Interrupt Source Identity"
bitfld.long 0x74 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x78 "IRQ30_SRC,Reserved"
bitfld.long 0x78 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x7C "IRQ31_SRC,Reserved"
bitfld.long 0x7C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
group.long 0x80++0x7
line.long 0x0 "NMI_CON,NMI Source Interrupt Select Control Register"
bitfld.long 0x0 8. "NMI_SEL_EN,NMI Interrupt Enable Control (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address.." "0: NMI interrupt Disabled,1: NMI interrupt Enabled"
hexmask.long.byte 0x0 0.--4. 1. "NMI_SEL,NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL."
line.long 0x4 "MCU_IRQ,MCU IRQ Number Identity Register"
hexmask.long 0x4 0.--31. 1. "MCU_IRQ,MCU IRQ Source\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. This modes to generate interrupt to Cortex-M0 - the normal mode.\nThe MCU_IRQ collects all interrupts from.."
endif
sif (cpuis("MINI5?AN"))
rgroup.long 0x0++0x7F
line.long 0x0 "IRQ0_SRC,IRQ0 (Brown-out) Interrupt Source Identity"
bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x4 "IRQ1_SRC,IRQ1 (WDT) Interrupt Source Identity"
bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x8 "IRQ2_SRC,IRQ2 (EINT0) Interrupt Source Identity"
bitfld.long 0x8 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0xC "IRQ3_SRC,IRQ3 (EINT1) Interrupt Source Identity"
bitfld.long 0xC 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x10 "IRQ4_SRC,IRQ4 (GP0/1) Interrupt Source Identity"
bitfld.long 0x10 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x14 "IRQ5_SRC,IRQ5 (GP2/3/4) Interrupt Source Identity"
bitfld.long 0x14 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x18 "IRQ6_SRC,IRQ6 (PWM) Interrupt Source Identity"
bitfld.long 0x18 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x1C "IRQ7_SRC,IRQ7 (BRAKE) Interrupt Source Identity"
bitfld.long 0x1C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x20 "IRQ8_SRC,IRQ8 (TMR0) Interrupt Source Identity"
bitfld.long 0x20 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x24 "IRQ9_SRC,IRQ9 (TMR1) Interrupt Source Identity"
bitfld.long 0x24 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x28 "IRQ10_SRC,Reserved"
bitfld.long 0x28 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x2C "IRQ11_SRC,Reserved"
bitfld.long 0x2C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x30 "IRQ12_SRC,IRQ12 (UART) Interrupt Source Identity"
bitfld.long 0x30 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x34 "IRQ13_SRC,Reserved"
bitfld.long 0x34 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x38 "IRQ14_SRC,IRQ14 (SPI) Interrupt Source Identity"
bitfld.long 0x38 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x3C "IRQ15_SRC,Reserved"
bitfld.long 0x3C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x40 "IRQ16_SRC,IRQ16 (GP5) Interrupt Source Identity"
bitfld.long 0x40 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x44 "IRQ17_SRC,IRQ17 (HFIRC Trim) Interrupt Source Identity"
bitfld.long 0x44 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x48 "IRQ18_SRC,IRQ18 (I2C) Interrupt Source Identity"
bitfld.long 0x48 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x4C "IRQ19_SRC,Reserved"
bitfld.long 0x4C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x50 "IRQ20_SRC,Reserved"
bitfld.long 0x50 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x54 "IRQ21_SRC,Reserved"
bitfld.long 0x54 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x58 "IRQ22_SRC,Reserved"
bitfld.long 0x58 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x5C "IRQ23_SRC,Reserved"
bitfld.long 0x5C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x60 "IRQ24_SRC,Reserved"
bitfld.long 0x60 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x64 "IRQ25_SRC,IRQ25 (ACMP) Interrupt Source Identity"
bitfld.long 0x64 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x68 "IRQ26_SRC,Reserved"
bitfld.long 0x68 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x6C "IRQ27_SRC,Reserved"
bitfld.long 0x6C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x70 "IRQ28_SRC,IRQ28 (PWRWU) Interrupt Source Identity"
bitfld.long 0x70 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x74 "IRQ29_SRC,IRQ29 (ADC) Interrupt Source Identity"
bitfld.long 0x74 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x78 "IRQ30_SRC,Reserved"
bitfld.long 0x78 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
line.long 0x7C "IRQ31_SRC,Reserved"
bitfld.long 0x7C 0.--2. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7"
group.long 0x80++0x7
line.long 0x0 "NMI_CON,NMI Source Interrupt Select Control Register"
bitfld.long 0x0 8. "NMI_SEL_EN,NMI Interrupt Source Enable (Write-protected)\nSetting this bit will enable NMI_SEL to generate NMI interrupt source of Cortex-M0." "0,1"
hexmask.long.byte 0x0 0.--4. 1. "NMI_SEL,NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 CPU can be selected from one of the interrupt[31:0].\nThe NMI_SEL[4:0] is used to select the NMI interrupt source."
line.long 0x4 "MCU_IRQ,MCU IRQ Number Identity Register"
hexmask.long 0x4 0.--31. 1. "MCU_IRQ,MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There are two modes to generate interrupt to Cortex-M0 - the normal mode and test mode.\nThe MCU_IRQ.."
endif
tree.end
tree "SCS (System Controllers Space)"
base ad:0xE000E000
group.long 0x10++0xB
line.long 0x0 "SYST_CSR,SysTick Control and Status Register"
bitfld.long 0x0 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register." "0,1"
bitfld.long 0x0 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is optional refer to STCLK_S,1: Core clock used for SysTick timer"
newline
bitfld.long 0x0 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
bitfld.long 0x0 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter Enabled and will operate in a multi-shot.."
line.long 0x4 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0."
line.long 0x8 "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the.."
group.long 0x100++0x3
line.long 0x0 "NVIC_ISER,IRQ0 ~ IRQ31 Set-Enable Control Register"
hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Enable Register \nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite:\nRead value indicates the current enable status."
group.long 0x180++0x3
line.long 0x0 "NVIC_ICER,IRQ0 ~ IRQ31 Clear-Enable Control Register"
hexmask.long 0x0 0.--31. 1. "CLRENA,Interrupt Disable Register\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite:\nRead value indicates the current enable status."
group.long 0x200++0x3
line.long 0x0 "NVIC_ISPR,IRQ0 ~ IRQ31 Set-Pending Control Register"
hexmask.long 0x0 0.--31. 1. "SETPEND,Set Interrupt Pending Register\nWrite:\nRead value indicates the current pending status."
group.long 0x280++0x3
line.long 0x0 "NVIC_ICPR,IRQ0 ~ IRQ31 Clear-Pending Control Register"
hexmask.long 0x0 0.--31. 1. "CLRPEND,Clear Interrupt Pending Register\nWrite:\nRead value indicates the current pending status."
group.long 0x400++0x1F
line.long 0x0 "NVIC_IPR0,IRQ0 ~ IRQ3 Interrupt Priority Control Register"
bitfld.long 0x0 30.--31. "PRI_3,Priority Of IRQ3\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x0 22.--23. "PRI_2,Priority Of IRQ2\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "PRI_1,Priority Of IRQ1\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x0 6.--7. "PRI_0,Priority Of IRQ0\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x4 "NVIC_IPR1,IRQ4 ~ IRQ7 Interrupt Priority Control Register"
bitfld.long 0x4 30.--31. "PRI_7,Priority Of IRQ7\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x4 22.--23. "PRI_6,Priority Of IRQ6\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
newline
bitfld.long 0x4 14.--15. "PRI_5,Priority Of IRQ5\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x4 6.--7. "PRI_4,Priority Of IRQ4\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x8 "NVIC_IPR2,IRQ8 ~ IRQ11 Interrupt Priority Control Register"
bitfld.long 0x8 30.--31. "PRI_11,Priority Of IRQ11\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x8 22.--23. "PRI_10,Priority Of IRQ10\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
newline
bitfld.long 0x8 14.--15. "PRI_9,Priority Of IRQ9\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x8 6.--7. "PRI_8,Priority Of IRQ8\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0xC "NVIC_IPR3,IRQ12 ~ IRQ15 Interrupt Priority Control Register"
bitfld.long 0xC 30.--31. "PRI_15,Priority Of IRQ15\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0xC 22.--23. "PRI_14,Priority Of IRQ14\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
newline
bitfld.long 0xC 14.--15. "PRI_13,Priority Of IRQ13\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0xC 6.--7. "PRI_12,Priority Of IRQ12\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x10 "NVIC_IPR4,IRQ16 ~ IRQ19 Interrupt Priority Control Register"
bitfld.long 0x10 30.--31. "PRI_19,Priority Of IRQ19\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x10 22.--23. "PRI_18,Priority Of IRQ18\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
newline
bitfld.long 0x10 14.--15. "PRI_17,Priority Of IRQ17\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x10 6.--7. "PRI_16,Priority Of IRQ16\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x14 "NVIC_IPR5,IRQ20 ~ IRQ23 Interrupt Priority Control Register"
bitfld.long 0x14 30.--31. "PRI_23,Priority Of IRQ23\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x14 22.--23. "PRI_22,Priority Of IRQ22\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
newline
bitfld.long 0x14 14.--15. "PRI_21,Priority Of IRQ21\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x14 6.--7. "PRI_20,Priority Of IRQ20\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x18 "NVIC_IPR6,IRQ24 ~ IRQ27 Interrupt Priority Control Register"
bitfld.long 0x18 30.--31. "PRI_27,Priority Of IRQ27\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x18 22.--23. "PRI_26,Priority Of IRQ26\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
newline
bitfld.long 0x18 14.--15. "PRI_25,Priority Of IRQ25\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x18 6.--7. "PRI_24,Priority Of IRQ24\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x1C "NVIC_IPR7,IRQ28 ~ IRQ31 Interrupt Priority Control Register"
bitfld.long 0x1C 30.--31. "PRI_31,Priority Of IRQ31\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x1C 22.--23. "PRI_30,Priority Of IRQ30\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
newline
bitfld.long 0x1C 14.--15. "PRI_29,Priority Of IRQ29\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x1C 6.--7. "PRI_28,Priority Of IRQ28\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
rgroup.long 0xD00++0x3
line.long 0x0 "CPUID,CPUID Register"
hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,Implementer Code"
hexmask.long.byte 0x0 16.--19. 1. "PART,Architecture Of The Processor\nRead as 0xC for ARMv6-M parts."
newline
hexmask.long.word 0x0 4.--15. 1. "PARTNO,Part Number Of The Processor\nRead as 0xC20."
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Revision Number\nRead as 0x0."
group.long 0xD04++0x3
line.long 0x0 "ICSR,Interrupt Control State Register"
bitfld.long 0x0 31. "NMIPENDSET,NMI Set-Pending Bit\nWrite:\nNote: Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This.." "0: No effect.\nNMI exception not pending,1: Changes NMI exception state to pending.\nNMI.."
bitfld.long 0x0 28. "PENDSVSET,PendSV Set-Pending Bit\nWrite:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending." "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
newline
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
bitfld.long 0x0 27. "PENDSVCLR,PendSV Clear-Pending Bit\nWrite:\nNote: This bit is write-only. To clear the PENDSV bit you must 'write 0 to PENDSVSET and write 1 to PENDSVCLR' at the same time." "0: No effect,1: Removes the pending state from the PendSV.."
bitfld.long 0x0 25. "PENDSTCLR,SysTick Exception Clear-Pending Bit\nWrite:\nNote: This bit is write-only. When you want to clear PENDST bit you must 'write 0 to PENDSTSET and write 1 to PENDSTCLR' at the same time." "0: No effect,1: Removes the pending state from the SysTick.."
newline
bitfld.long 0x0 23. "ISRPREEMPT,Interrupt Preemption Bit\nIf set a pending exception will be serviced on exit from the debug halt state.\nThis bit is read only." "0,1"
bitfld.long 0x0 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI And Faults\nThis bit is read only." "0: Interrupt not pending,1: Interrupt pending"
newline
hexmask.long.word 0x0 12.--20. 1. "VECTPENDING,Exception Number Of The Highest Priority Pending Enabled Exception\nThis bit is read only."
hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Contains The Active Exception Number\nThis bit is read only."
newline
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 27. "PENDSVCLR,PendSV Clear-pending Bit (Write Only)\nWrite:\n" "0: No effect,1: The pending state removed from the PendSV.."
endif
bitfld.long 0x0 26. "PENDSTSET,SysTick Exception Set-Pending Bit\nWrite:" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.."
newline
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 25. "PENDSTCLR,SysTick Exception Clear-pending Bit (Write Only)\nWrite:\n" "0: No effect,1: The pending state removed from the SysTick.."
endif
sif (cpuis("MINI5?AN"))
rbitfld.long 0x0 23. "ISRPREEMPT,Interrupt Preemption (Read Only)\nIf set a pending exception will be serviced on exit from the debug halt state." "0,1"
newline
rbitfld.long 0x0 22. "ISRPENDING,Interrupt Pending Flag (Read Only)\nExcluding NMI and Faults.\n" "0: Interrupt not pending,1: Interrupt pending"
endif
sif (cpuis("MINI5?AN"))
hexmask.long.word 0x0 12.--20. 1. "VECTPENDING,Vector Pending Indicator (Read Only)\nThis field indicates the exception number of the highest priority pending enabled exception:\n"
newline
endif
sif (cpuis("MINI5?AN"))
hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Vector Active Indicator (Read Only)\nThis field contains the active exception number:\n"
endif
group.long 0xD0C++0x7
line.long 0x0 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x0 16.--31. 1. "VECTORKEY,Register Access Key\nWrite:\nWhen writing to this register the VECTORKEY field need to be set to 0x05FA otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting.."
bitfld.long 0x0 2. "SYSRESETREQ,System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence." "0,1"
newline
bitfld.long 0x0 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nReserved for debug use. When writing to the register user must write 0 to this bit otherwise behavior is unpredictable." "0,1"
line.long 0x4 "SCR,System Control Register"
bitfld.long 0x4 4. "SEVONPEND,Send Event On Pending Bit\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE. If the processor is not waiting for an event the event is registered and affects next WFE.\nThe processor also wakes.." "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.."
bitfld.long 0x4 2. "SLEEPDEEP,Processor Deep Sleep And Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:" "0: Sleep mode,1: Deep Sleep mode"
newline
bitfld.long 0x4 1. "SLEEPONEXIT,Sleep-On-Exit Enable\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application." "0: Do not sleep when returning to Thread mode,1: Enter Sleep or Deep Sleep on return from ISR to.."
group.long 0xD1C++0x7
line.long 0x0 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x0 30.--31. "PRI_11,Priority Of System Handler 11 - SVCall\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x4 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x4 30.--31. "PRI_15,Priority Of System Handler 15 - SysTick\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x4 22.--23. "PRI_14,Priority Of System Handler 14 - PendSV\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x40030000
sif (cpuis("MINI5?XAE"))
group.long 0x0++0xB
line.long 0x0 "SPI_CTL,SPI Control and Status Register"
rbitfld.long 0x0 27. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[27]." "0: The transmit FIFO buffer is not full,1: The transmit FIFO buffer is full"
rbitfld.long 0x0 26. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STAUTS[26]." "0: The transmit FIFO buffer is not empty,1: The transmit FIFO buffer is empty"
newline
rbitfld.long 0x0 25. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[25]" "0: The receive FIFO buffer is not full,1: The receive FIFO buffer is full"
rbitfld.long 0x0 24. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CTL[24]." "0: The receive FIFO buffer is not empty,1: The receive FIFO buffer is empty"
newline
bitfld.long 0x0 21. "FIFOEN,FIFO Mode Enable Control\nNote 1: Before enabling FIFO mode the other related settings should be set in advance.\nNote 2: In Master mode if the FIFO mode is enabled the SPIEN bit will be set to 1 automatically after writing data into the.." "0: FIFO Mode Disabled,1: Before enabling FIFO mode"
bitfld.long 0x0 19. "REORDER,Byte Reorder Function\nNote: This setting is only available if DWIDTH is defined as 16 24 and 32 bits." "0: Byte reorder function Disabled,1: Byte reorder function Enabled"
newline
bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
bitfld.long 0x0 17. "UNITIEN,Unit-Transfer Interrupt Enable Control" "0: SPI unit-transfer interrupt Disabled,1: SPI unit-transfer interrupt Enabled"
newline
bitfld.long 0x0 16. "UNITIF,Unit-Transfer Interrupt Flag\nNote 1: This bit will be cleared by writing 1 to itself.\nNote 2: . It's a mutual mirror bit of SPI_STATUS[16]." "0: The transfer does not finish yet,1: This bit will be cleared by writing 1 to itself"
hexmask.long.byte 0x0 12.--15. 1. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
newline
bitfld.long 0x0 11. "CLKPOL,Clock Polarity" "0: SPICLK idle low,1: SPICLK idle high"
bitfld.long 0x0 10. "LSB,LSB First" "0: The MSB is transmitted/received first,1: The LSB is transmitted/received first"
newline
hexmask.long.byte 0x0 3.--7. 1. "DWIDTH,Transmit Bit Length\nThis field specifies how many bits are transmitted in one transmit/receive. The minimum bit length is 8 bits and can up to 32 bits."
bitfld.long 0x0 2. "TXNEG,Transmit On Negative Edge" "0: The transmitted data output signal is driven on..,1: The transmitted data output signal is driven on.."
newline
bitfld.long 0x0 1. "RXNEG,Receive On Negative Edge" "0: The received data input signal latched on the..,1: The received data input signal latched on the.."
bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Bit And Busy Status\nIf FIFO mode is enabled this bit will be controlled by hardware and its Read only.\nIf FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit.." "0: Writing 0 to this bit to stop data transfer if..,1: When FIFO mode is disabled"
line.long 0x4 "SPI_CLKDIV,SPI Divider Register"
hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider Register (Master Only)\nThe value in this field is the frequency divider to determine the SPI peripheral clock frequency fspi and the SPI master's bus clock frequency on the SPICLK output pin. The frequency is obtained according to.."
line.long 0x8 "SPI_SSCTL,SPI Slave Select Register"
rbitfld.long 0x8 5. "LTF,Level Trigger Flag (Read Only Slave Only)\nWhen the SSLTEN bit is set in Slave mode this bit can be read to indicate the received bit number is met the requirement or not." "0: The transaction number or the transferred bit..,1: The transaction number and the transferred bit.."
bitfld.long 0x8 4. "SSLTEN,Slave Select Level Trigger Enable Bit (Slave Only)" "0: The input slave select signal is edge-trigger,1: The input slave select signal is level-trigger"
newline
bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: SPISS pin signal will be asserted/de-asserted by..,1: SPISS pin signal will be generated automatically.."
bitfld.long 0x8 2. "SSACTPOL,Slave Select Active Level (Slave Only)\nIt defines the active status of slave select signal (SPISS).\nIf SSLTEN bit is 1:" "0: The slave select signal SPISS is active at..,1: The slave select signal SPISS is active at.."
newline
bitfld.long 0x8 0. "SS,Slave Select Control Bits (Master Only)\nIf AUTOSS bit is 0 " "0: Set the SPISS line to inactive state.\nKeep the..,1: Set the proper SPISS line to active.."
group.long 0x3C++0x7
line.long 0x0 "SPI_SLVCTL,SPI Slave Mode Control Register"
bitfld.long 0x0 31. "DIVMOD,Clock Configuration Backward Compatible Option\nNote: Refer to the description of SPI_CLKDIV register for details." "0: The clock configuration is backward compatible,1: The clock configuration is not backward compatible"
bitfld.long 0x0 16. "SSINAIEN,Slave Select Inactive Interrupt Option (Slave Only)\nNote: This setting is only available if the SPI controller is configured as level trigger in slave device." "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.."
newline
bitfld.long 0x0 11. "SLVSTIF,Slave 3-Wire Mode Start Interrupt Status (Slave Only)\nThis bit dedicates if a transaction has started in Slave 3-wire mode. \nNote 1: It will be cleared automatically when a transaction is done or by writing 1 to this bit.\nNote 2: It is a.." "0: Slave does not detect any SPI bus clock transfer..,1: It will be cleared automatically when a.."
bitfld.long 0x0 10. "SLVSTIEN,Slave 3-Wire Mode Start Interrupt Enable (Slave Only)\nIt is used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer.." "0: Transaction start interrupt Disabled,1: It will be cleared to 0 as the current transfer.."
newline
bitfld.long 0x0 9. "SLVABT,Slave 3-Wire Mode Abort Control Bit (Slave Only)\nIn normal operation there is an interrupt event when the number of received bits meets the requirement which defined in DWIDTH.\nIf the number of received bits is less than the requirement and.." "0: No force the transfer done when the SLV3WIRE bit..,1: Force the transfer done when the SLV3WIRE bit is.."
bitfld.long 0x0 8. "SLV3WIRE,Slave 3-Wire Mode Enable Bit (Slave Only)\nThe SPI controller work with 3-wire interface including SPICLK SPI_MISO and SPI_MOSI.\nNote: In Slave 3-wire mode the SSLTEN bit (SPI_SSCTL[4]) shall be set as 1." "0: The controller is 4-wire bi-direction interface,1: The controller is 3-wire bi-direction interface.."
line.long 0x4 "SPI_FIFOCTL,SPI FIFO Control Register"
bitfld.long 0x4 28.--29. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
bitfld.long 0x4 24.--25. "RXTH,Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0." "0,1,2,3"
newline
bitfld.long 0x4 21. "RXTOIEN,Receive FIFO Time-Out Interrupt Enable Control" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled"
bitfld.long 0x4 6. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Control" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
newline
bitfld.long 0x4 3. "TXTHIEN,Transmit Threshold Interrupt Enable" "0: Transmit threshold interrupt Disabled,1: Transmit threshold interrupt Enabled"
bitfld.long 0x4 2. "RXTHIEN,Receive Threshold Interrupt Enable Control" "0: Receive threshold interrupt Disabled,1: Receive threshold interrupt Enabled"
newline
bitfld.long 0x4 1. "TXRST,Clear Transmit FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared." "0: No effect,1: Clear transmit FIFO buffer"
bitfld.long 0x4 0. "RXRST,Clear Receive FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared." "0: No effect,1: Clear receive FIFO buffer"
endif
sif (cpuis("MINI5??DE"))
group.long 0x0++0xB
line.long 0x0 "SPI_CNTRL,SPI Control and Status Register"
rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[27]." "0: The transmit FIFO buffer is not full,1: The transmit FIFO buffer is full"
rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STAUTS[26]." "0: The transmit FIFO buffer is not empty,1: The transmit FIFO buffer is empty"
newline
rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[25]" "0: The receive FIFO buffer is not full,1: The receive FIFO buffer is full"
rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CNTRL[24]." "0: The receive FIFO buffer is not empty,1: The receive FIFO buffer is empty"
newline
bitfld.long 0x0 21. "FIFO,FIFO Mode Enable Control\nNote 1: Before enabling FIFO mode the other related settings should be set in advance.\nNote 2: In Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data into the.." "0: FIFO Mode Disabled,1: Before enabling FIFO mode"
bitfld.long 0x0 19. "REORDER,Byte Reorder Function\nNote: This setting is only available if TX_BIT_LEN is defined as 16 24 and 32 bits." "0: Byte reorder function Disabled,1: Byte reorder function Enabled"
newline
bitfld.long 0x0 18. "SLAVE,Slave Mode Control\n" "0: Master mode,1: Slave mode"
bitfld.long 0x0 17. "IE,Unit-transfer Interrupt Enable Control\n" "0: SPI unit-transfer interrupt Disabled,1: SPI unit-transfer interrupt Enabled"
newline
bitfld.long 0x0 16. "IF,Unit-transfer Interrupt Flag\nNote 1: This bit will be cleared by writing 1 to itself.\nNote 2: It's a mutual mirror bit of SPI_STATUS[16]." "0: The transfer does not finish yet,1: This bit will be cleared by writing 1 to itself"
hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
newline
bitfld.long 0x0 11. "CLKP,Clock Polarity\n" "0: SPICLK idle low,1: SPICLK idle high"
bitfld.long 0x0 10. "LSB,LSB First\n" "0: The MSB is transmitted/received first,1: The LSB is transmitted/received first"
newline
hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length\nThis field specifies how many bits are transmitted in one transmit/receive. The minimum bit length is 8 bits and can up to 32 bits.\n"
bitfld.long 0x0 2. "TX_NEG,Transmit On Negative Edge\n" "0: The transmitted data output signal is driven on..,1: The transmitted data output signal is driven on.."
newline
bitfld.long 0x0 1. "RX_NEG,Receive On Negative Edge\n" "0: The received data input signal latched on the..,1: The received data input signal latched on the.."
bitfld.long 0x0 0. "GO_BUSY,SPI Transfer Control Bit And Busy Status\nIf FIFO mode is enabled this bit will be controlled by hardware and is Read only.\nIf FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit.." "0: Writing 0 to this bit to stop data transfer if..,1: When FIFO mode is disabled"
line.long 0x4 "SPI_DIVIDER,SPI Clock Divider Register"
hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider Bits (Master Only)\nThe value in this field is the frequency divider to determine the SPI peripheral clock frequency fspi and the SPI master's bus clock frequency on the SPICLK output pin. The frequency is obtained according to the.."
line.long 0x8 "SPI_SSR,SPI Slave Select Register"
rbitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Flag (Read Only Slave Only)\nWhen the SS_LTRIG bit is set in Slave mode this bit can be read to indicate the received bit number is met the requirement or not.\n" "0: The transaction number or the transferred bit..,1: The transaction number and the transferred bit.."
bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger Enable Bit (Slave Only)\n" "0: The input slave select signal is edge-trigger,1: The input slave select signal is level-trigger"
newline
bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)\n" "0: SPISS pin signal will be asserted/de-asserted by..,1: SPISS pin signal will be generated automatically.."
bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level (Slave Only)\nIt defines the active status of slave select signal (SPISS).\nIf SS_LTRIG bit is 1:\n" "0: The slave select signal SPISS is active at..,1: The slave select signal SPISS is active at.."
newline
bitfld.long 0x8 0. "SSR,Slave Select Control Bit (Master Only)\nIf AUTOSS bit is 0 \n" "0: Set the SPISS line to inactive state.\nKeep the..,1: Set the proper SPISS line to active.."
group.long 0x3C++0x7
line.long 0x0 "SPI_CNTRL2,SPI Control and Status Register 2"
bitfld.long 0x0 31. "BCn,Clock Configuration Backward Compatible Option\nNote: Refer to the description of SPI_DIVIDER register for details." "0: The clock configuration is backward compatible,1: The clock configuration is not backward compatible"
bitfld.long 0x0 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option (Slave Only)\nNote: This setting is only available if the SPI controller is configured as level trigger in slave device." "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.."
newline
bitfld.long 0x0 11. "SLV_START_INTSTS,Slave 3-wire Mode Start Interrupt Status (Slave Only)\nThis bit dedicates if a transaction has started in slave 3-wire mode. \nNote 1: It will be cleared automatically when a transaction is done or by writing 1 to this bit.\nNote 2: It.." "0: Slave does not detect any SPI bus clock transfer..,1: It will be cleared automatically when a.."
bitfld.long 0x0 10. "SSTA_INTEN,Slave 3-wire Mode Start Interrupt Enable Control (Slave Only)\nIt is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the.." "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled"
newline
bitfld.long 0x0 9. "SLV_ABORT,Slave 3-wire Mode Abort Control Bit (Slave Only)\nIn normal operation there is an interrupt event when the number of received bits meets the requirement which defined in TX_BIT_LEN.\nIf the number of received bits is less than the requirement.." "0: No force the transfer done when the NOSLVSEL bit..,1: Force the transfer done when the NOSLVSEL bit is.."
bitfld.long 0x0 8. "NOSLVSEL,Slave 3-wire Mode Enable Control (Slave Only)\nThe SPI controller work with 3-wire interface including SPICLK SPI_MISO and SPI_MOSI \nNote: In Slave 3-wire mode the SS_LTRIG bit (SPI_SSR[4]) shall be set as 1." "0: The controller is 4-wire bi-direction interface,1: The controller is 3-wire bi-direction interface.."
line.long 0x4 "SPI_FIFO_CTL,SPI FIFO Control Register"
bitfld.long 0x4 28.--29. "TX_THRESHOLD,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0." "0,1,2,3"
bitfld.long 0x4 24.--25. "RX_THRESHOLD,Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0." "0,1,2,3"
newline
bitfld.long 0x4 21. "TIMEOUT_INTEN,Receive FIFO Time-out Interrupt Enable Control\n" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled"
bitfld.long 0x4 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable Control\n" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
newline
bitfld.long 0x4 3. "TX_INTEN,Transmit Threshold Interrupt Enable Control\n" "0: Transmit threshold interrupt Disabled,1: Transmit threshold interrupt Enabled"
bitfld.long 0x4 2. "RX_INTEN,Receive Threshold Interrupt Enable Control\n" "0: Receive threshold interrupt Disabled,1: Receive threshold interrupt Enabled"
newline
bitfld.long 0x4 1. "TX_CLR,Clear Transmit FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared." "0: No effect,1: Clear transmit FIFO buffer"
bitfld.long 0x4 0. "RX_CLR,Clear Receive FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared." "0: No effect,1: Clear receive FIFO buffer"
endif
sif (cpuis("MINI5?AN"))
group.long 0x0++0xB
line.long 0x0 "SPI_CNTRL,Control and Status Register"
rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[27].\n" "0: Indicates that the transmit FIFO buffer is not..,1: Indicates that the transmit FIFO buffer is full"
rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_STAUTS[26].\n" "0: Indicates that the transmit FIFO buffer is not..,1: Indicates that the transmit FIFO buffer is empty"
newline
rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[25].\n" "0: Indicates that the receive FIFO buffer is not full,1: Indicates that the receive FIFO buffer is full"
rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24].\n" "0: Indicates that the receive FIFO buffer is not..,1: Indicates that the receive FIFO buffer is empty"
newline
bitfld.long 0x0 21. "FIFO,FIFO Mode\nNote:\nBefore enabling FIFO mode the other related settings should be set in advance.\nIn Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data into the 8-depth FIFO. It means all.." "0: Disable FIFO Mode,1: Enable FIFO Mode"
bitfld.long 0x0 19. "REORDER,Byte Reorder Function\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits." "0: Disable the byte reorder function,1: Enable byte reorder function"
newline
bitfld.long 0x0 18. "SLAVE,Slave Mode Enable Bit\n" "0: Master mode,1: Slave mode"
bitfld.long 0x0 17. "IE,SPI Unit Transfer Interrupt Enable Bit\n" "0: Disable SPI unit transfer interrupt,1: Enable SPI unit transfer interrupt"
newline
bitfld.long 0x0 16. "IF,SPI Unit Transfer Interrupt Flag\nNote: Software can write 1 to clear this bit." "0: It indicates that the transfer does not finish yet,1: It indicates that the SPI controller has.."
hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.."
newline
bitfld.long 0x0 11. "CLKP,Clock Polarity\n" "0: SPICLK idle low,1: SPICLK idle high"
bitfld.long 0x0 10. "LSB,LSB First\n" "0: The MSB which bit of SPI_TX0/SPI_RX0 register..,1: The LSB bit 0 of the SPI_TX0 register is sent.."
newline
hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length\nThis field specifies how many bits are transmitted in one transmit/receive. The minimum bit length is 8 bits and can up to 32 bits.\n"
bitfld.long 0x0 2. "TX_NEG,Transmit At Negative Edge\n" "0: The transmitted data output signal changed at..,1: The transmitted data output signal changed at.."
newline
bitfld.long 0x0 1. "RX_NEG,Receive At Negative Edge\n" "0: The received data input signal latched at the..,1: The received data input signal latched at the.."
bitfld.long 0x0 0. "GO_BUSY,SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit will be cleared automatically.\nIn FIFO mode this bit will be controlled by.." "0: Writing 0 to this bit to stop data transfer if..,1: In Master mode writing 1 to this bit to start.."
line.long 0x4 "SPI_DIVIDER,Clock Divider Register"
hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider Register (Master Only)\nThe value in this field is the frequency divider for generating the SPI engine clock and its SPI clock. The frequency is obtained according to the following equation:\nIf the bit of BCn SPI_CNTRL2[31] is.."
line.long 0x8 "SPI_SSR,Slave Select Register"
bitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Accomplish Flag\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only." "0: The transferred bit length of one transaction..,1: The transferred bit length meets the specified.."
bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger Enable Bit (Slave only)\n" "0: The slave select signal is edge-trigger. This is..,1: The slave select signal will be level-trigger."
newline
bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)\n" "0: If this bit is cleared slave select signal is..,1: If this bit is set SPISS signal are generated.."
bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level\nIt defines the active status of slave select signal (SPISS).\n" "0: The slave select signal SPISS is active at..,1: The slave select signal SPISS is active at.."
newline
bitfld.long 0x8 0. "SSR,Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared writing 1 to this field sets the SPISS line to active state and writing 0 sets the line back to inactive state.\nIf AUTOSS bit is set writing 0 to this field will keep the SPISS line.." "0,1"
rgroup.long 0x10++0x3
line.long 0x0 "SPI_RX0,Data Receive Register 0"
hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit .."
wgroup.long 0x20++0x3
line.long 0x0 "SPI_TX0,Data Transmit Register 0"
hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe Data Transmit Register holds the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example if TX_BIT_LEN is set to.."
group.long 0x3C++0x7
line.long 0x0 "SPI_CNTRL2,Control and Status Register 2"
bitfld.long 0x0 31. "BCn,SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details." "0: Backward compatible clock configuration,1: The clock configuration is not backward compatible"
bitfld.long 0x0 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n" "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.."
newline
bitfld.long 0x0 11. "SLV_START_INTSTS,Slave 3-Wire Mode Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode.\n" "0: It indicates that the SPI transfer is not active,1: It indicates that the transfer has started in.."
bitfld.long 0x0 10. "SSTA_INTEN,Slave 3-Wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start the.." "0: Disable the transfer start interrupt,1: Enable the transaction start interrupt. It is.."
newline
bitfld.long 0x0 9. "SLV_ABORT,Slave 3-Wire Mode Abort Control Bit\nIn normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial.." "0,1"
bitfld.long 0x0 8. "NOSLVSEL,Slave 3-Wire Mode Enable Bit\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3-wire interface including SPICLK SPI_MISO and SPI_MOSI.\nNote: In 3-wire mode the SS_LTRIG SPI_SSR[4] shall be set.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
line.long 0x4 "SPI_FIFO_CTL,FIFO Control Register"
bitfld.long 0x4 28.--29. "TX_THRESHOLD,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0." "0,1,2,3"
bitfld.long 0x4 24.--25. "RX_THRESHOLD,Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0." "0,1,2,3"
newline
bitfld.long 0x4 21. "TIMEOUT_INTEN,Receive FIFO Time-out Interrupt Enable\n" "0: Disable time-out interrupt,1: Enable time-out interrupt"
bitfld.long 0x4 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable\n" "0: Disable Receive FIFO overrun interrupt,1: Enable Receive FIFO overrun interrupt"
newline
bitfld.long 0x4 3. "TX_INTEN,Transmit Threshold Interrupt Enable\n" "0: Disable transmit threshold interrupt,1: Enable transmit threshold interrupt"
bitfld.long 0x4 2. "RX_INTEN,Receive Threshold Interrupt Enable\n" "0: Disable receive threshold interrupt,1: Enable receive threshold interrupt"
newline
bitfld.long 0x4 1. "TX_CLR,Clear Transmit FIFO Buffer\n" "0: No effect,1: Clear transmit FIFO buffer. The TX_FULL flag.."
bitfld.long 0x4 0. "RX_CLR,Clear Receive FIFO Buffer\n" "0: No effect,1: Clear receive FIFO buffer. The RX_FULL flag will.."
endif
sif (cpuis("MINI5??DE")||cpuis("MINI5?XAE"))
rgroup.long 0x10++0x3
line.long 0x0 "SPI_RX,SPI Data Receive Register"
hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register (Read Only)\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CTL register.\nFor example if DWIDTH is set to 0x08 bit.."
wgroup.long 0x20++0x3
line.long 0x0 "SPI_TX,SPI Data Transmit Register"
hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register.\nFor example if DWIDTH is set to 0x08 the bit TX0[7:0] will be.."
endif
group.long 0x44++0x3
line.long 0x0 "SPI_STATUS,SPI Status Register"
sif (cpuis("MINI5?XAE"))
hexmask.long.byte 0x0 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer."
rbitfld.long 0x0 27. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CTL[27]." "0: The transmit FIFO buffer is not full,1: The transmit FIFO buffer is full"
newline
rbitfld.long 0x0 26. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CTL[26]." "0: The transmit FIFO buffer is not empty,1: The transmit FIFO buffer is empty"
rbitfld.long 0x0 25. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CTL[25]." "0: The receive FIFO buffer is not full,1: The receive FIFO buffer is full"
newline
rbitfld.long 0x0 24. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CTL[24]." "0: The receive FIFO buffer is not empty,1: The receive FIFO buffer is empty"
bitfld.long 0x0 20. "SLVTOIF,Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: The receive FIFO buffer is not empty and it does.."
newline
bitfld.long 0x0 16. "UNITIF,SPI Unit-Transfer Interrupt Flag\nNote 1: This bit will be cleared by writing 1 to itself.\nNote 2: It's a mutual mirror bit of SPI_CTL[16]." "0: The transfer does not finish yet,1: This bit will be cleared by writing 1 to itself"
hexmask.long.byte 0x0 12.--15. 1. "RXCNT,Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer."
newline
bitfld.long 0x0 11. "SLVSTIF,Slave Start Interrupt Status (Slave Only)\nIt is used to dedicate that the transfer has started in slave 3-wire mode. \nNote 1: It will be cleared as transfer done or by writing one to this bit.\nNote 2: It's a mutual mirror bit of SPI_SLVCTL[11]." "0: Slave does not detect any SPI bus clock transfer..,1: It will be cleared as transfer done or by.."
rbitfld.long 0x0 4. "TXTHIF,Transmit FIFO Threshold Interrupt Status (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
newline
bitfld.long 0x0 2. "RXOVIF,Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself." "0: No overrun in receive FIFO,1: Overrun in receive FIFO"
rbitfld.long 0x0 0. "RXTHIF,Receive FIFO Threshold Interrupt Status (Read Only)" "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.."
newline
endif
sif (cpuis("MINI5??DE"))
hexmask.long.byte 0x0 28.--31. 1. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer."
rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CNTRL[27]." "0: The transmit FIFO buffer is not full,1: The transmit FIFO buffer is full"
newline
rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CNTRL[26]." "0: The transmit FIFO buffer is not empty,1: The transmit FIFO buffer is empty"
rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CNTRL[25]." "0: The receive FIFO buffer is not full,1: The receive FIFO buffer is full"
newline
rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CNTRL[24]." "0: The receive FIFO buffer is not empty,1: The receive FIFO buffer is empty"
endif
sif (cpuis("MINI5?AN"))
hexmask.long.byte 0x0 28.--31. 1. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer."
newline
rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[27].\n" "0: Indicates that the transmit FIFO buffer is not..,1: Indicates that the transmit FIFO buffer is full"
rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only) \nIt's a mutual mirror bit of SPI_CNTRL[26].\n" "0: Indicates that the transmit FIFO buffer is not..,1: Indicates that the transmit FIFO buffer is empty"
newline
rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only) \nIt's a mutual mirror bit of SPI_CNTRL[25].\n" "0: Indicates that the receive FIFO buffer is not full,1: Indicates that the receive FIFO buffer is full"
rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[24].\n" "0: Indicates that the receive FIFO buffer is not..,1: Indicates that the receive FIFO buffer is empty"
newline
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x0 20. "TIMEOUT,Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: The receive FIFO buffer is not empty and it does.."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 20. "TIMEOUT,Time-out Interrupt Flag\nNote: Software can write 1 to clear this bit." "0: No receive FIFO time-out event,1: It indicates that the receive FIFO buffer is not.."
newline
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x0 16. "IF,SPI Unit-transfer Interrupt Flag\nNote 1: This bit will be cleared by writing 1 to itself.\nNote 2: It's a mutual mirror bit of SPI_CNTRL[16]." "0: The transfer does not finish yet,1: This bit will be cleared by writing 1 to itself"
hexmask.long.byte 0x0 12.--15. 1. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer."
newline
bitfld.long 0x0 11. "SLV_START_INTSTS,Slave Start Interrupt Status (Slave Only)\nIt is used to dedicate that the transfer has started in slave 3-wire mode. \nNote 1: It will be cleared as transfer done or by writing one to this bit.\nNote 2: It's a mutual mirror bit of.." "0: Slave does not detect any SPI bus clock transfer..,1: It will be cleared as transfer done or by.."
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 16. "IF,SPI Unit Transfer Interrupt Flag\nIt's a mutual mirror bit of SPI_CNTRL[16].\nNote: Software can write 1 to clear this bit." "0: It indicates that the transfer does not finish yet,1: It indicates that the SPI controller has.."
newline
hexmask.long.byte 0x0 12.--15. 1. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer."
bitfld.long 0x0 11. "SLV_START_INTSTS,Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11].\n" "0: It indicates that the transfer is not started,1: It indicates that the transfer has started in.."
newline
endif
sif (cpuis("MINI5??DE"))
rbitfld.long 0x0 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
endif
sif (cpuis("MINI5?AN"))
rbitfld.long 0x0 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (read only)\n" "0: It indicates that the valid data count within..,1: It indicates that the valid data count within.."
newline
endif
sif (cpuis("MINI5??DE"))
bitfld.long 0x0 2. "RX_OVERRUN,Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself." "0: No overrun in receive FIFO,1: Overrun in receive FIFO"
endif
sif (cpuis("MINI5?AN"))
bitfld.long 0x0 2. "RX_OVERRUN,Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: Software can write 1 to clear this bit." "0,1"
newline
endif
sif (cpuis("MINI5??DE"))
rbitfld.long 0x0 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.."
endif
sif (cpuis("MINI5?AN"))
rbitfld.long 0x0 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)\n" "0: It indicates that the valid data count within..,1: It indicates that the valid data count within.."
endif
tree.end
tree "TMR (Timer Controller)"
base ad:0x40010000
sif (cpuis("MINI5?XAE"))
group.long 0x0++0xB
line.long 0x0 "TIMER0_CTL,Timer0 Control and Status Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CNTEN,Timer Enable Control" "0: Stops/Suspends counting,1: Starts counting"
newline
bitfld.long 0x0 29. "INTEN,Interrupt Enable Control\nIf this bit is enabled when the timer interrupt flag (TIF) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode" "0: The timer is operating in the One-shot OPMODE.,1: The timer is operating in Periodic OPMODE. The..,?,?"
newline
bitfld.long 0x0 26. "RSTCNT,Timer Reset" "0: No effect,1: Reset 8-bit PSC counter 24-bit up counter value.."
rbitfld.long 0x0 25. "ACTSTS,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
newline
bitfld.long 0x0 24. "EXTCNTEN,Counter Mode Enable Control\nThis bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 6.12.5.3 for detail.." "0: External event counter mode Disabled,1: External event counter mode Enabled"
bitfld.long 0x0 23. "WKEN,Wake-Up Enable\nWhen WKEN is set and the TIF or CAPIF is set the timer controller will generator a wake-up trigger event to CPU." "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
newline
bitfld.long 0x0 19. "CAPPINSEL,Capture Pin Source Selection" "0: Capture Function source is from TxEX pin,1: Capture Function source is from ACMPx output.."
bitfld.long 0x0 18. "TGLPINSEL,Toggle Out Pin Selection\nWhen Timer is set to toggle mode " "0: Time0/1 toggle output pin is T0/T1 pin,1: Time0/1 toggle output pin is T0EX/T1EX pin"
newline
bitfld.long 0x0 17. "CMPCTL,TIMERx_CMP Mode Control" "0: In One-shot or Periodic mode when write new..,1: In One-shot or Periodic mode when write new.."
bitfld.long 0x0 16. "CNTDATEN,Data Load Enable Control\nWhen CNTDATEN is set CNT (TIMERx_CNT[23:0]) (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting." "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.."
newline
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter"
line.long 0x4 "TIMER0_CMP,Timer0 Compare Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field or the core will run into unknown.."
line.long 0x8 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
bitfld.long 0x8 1. "TWKF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
rgroup.long 0xC++0x7
line.long 0x0 "TIMER0_CNT,Timer0 Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register\nIf CNTDATEN is set to 1 CNT register value will be updated continuously to monitor 24-bit up counter value."
line.long 0x4 "TIMER0_CAP,Timer0 Capture Data Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPIF flag is set to 1 the current CNT (TIMERx_CNT[23:0]) value will be auto-loaded into this TCAP filed immediately."
group.long 0x14++0x7
line.long 0x0 "TIMER0_EXTCTL,Timer0 External Control Register"
bitfld.long 0x0 8. "CAPMODE,Capture Mode Selection" "0: Timer counter reset function or free-counting..,1: Trigger-counting mode of timer capture function"
bitfld.long 0x0 7. "ECNTDBEN,Timer External Counter Input Pin De-Bounce Enable Control" "0: Tx (x = 0~1) pin de-bounce Disabled,1: Tx (x = 0~1) pin de-bounce Enabled"
newline
bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Input Pin De-Bounce Enable Control" "0: TxEX (x = 0~1) pin de-bounce Disabled,1: TxEX (x = 0~1) pin de-bounce Enabled"
bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Control\nIf CAPIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while CAPIF flag is set to 1." "0: TxEX (x = 0~1) pin detection Interrupt Disabled,1: TxEX (x = 0~1) pin detection Interrupt Enabled"
newline
bitfld.long 0x0 4. "CAPFUNCS,Timer External Reset Counter / Timer External Capture Mode Selection" "0: Transition on TxEX (x = 0~1) pin is using to..,1: Transition on TxEX (x = 0~1) pin is using to.."
bitfld.long 0x0 3. "CAPEN,Timer External Pin Function Enable" "0: CAPFUNCS function of TxEX (x = 0~1) pin will be..,1: CAPFUNCS function of TxEX (x = 0~1) pin is active"
newline
bitfld.long 0x0 1.--2. "CAPEDGE,Timer External Pin Edge Detection" "0: A 1 to 0 transition on TxEX (x = 0~1) will be..,1: A 0 to 1 transition on TxEX (x = 0~1) will be..,?,?"
bitfld.long 0x0 0. "CNTPHASE,Timer External Count Pin Phase Detect Selection" "0: A falling edge of Tx (x = 0~1) pin will be counted,1: A rising edge of Tx (x = 0~1) pin will be counted"
line.long 0x4 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
bitfld.long 0x4 0. "CAPIF,Timer External Interrupt Flag\nThis bit indicates the external capture interrupt flag status\nNote: This bit is cleared by writing 1 to it" "0: TxEX (x = 0~1) pin interrupt did not occur,1: TxEX (x = 0~1) pin interrupt occurred"
group.long 0x20++0xB
line.long 0x0 "TIMER1_CTL,Timer1 Control and Status Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CNTEN,Timer Enable Control" "0: Stops/Suspends counting,1: Starts counting"
newline
bitfld.long 0x0 29. "INTEN,Interrupt Enable Control\nIf this bit is enabled when the timer interrupt flag (TIF) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode" "0: The timer is operating in the One-shot OPMODE.,1: The timer is operating in Periodic OPMODE. The..,?,?"
newline
bitfld.long 0x0 26. "RSTCNT,Timer Reset" "0: No effect,1: Reset 8-bit PSC counter 24-bit up counter value.."
rbitfld.long 0x0 25. "ACTSTS,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
newline
bitfld.long 0x0 24. "EXTCNTEN,Counter Mode Enable Control\nThis bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 6.12.5.3 for detail.." "0: External event counter mode Disabled,1: External event counter mode Enabled"
bitfld.long 0x0 23. "WKEN,Wake-Up Enable\nWhen WKEN is set and the TIF or CAPIF is set the timer controller will generator a wake-up trigger event to CPU." "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
newline
bitfld.long 0x0 19. "CAPPINSEL,Capture Pin Source Selection" "0: Capture Function source is from TxEX pin,1: Capture Function source is from ACMPx output.."
bitfld.long 0x0 18. "TGLPINSEL,Toggle Out Pin Selection\nWhen Timer is set to toggle mode " "0: Time0/1 toggle output pin is T0/T1 pin,1: Time0/1 toggle output pin is T0EX/T1EX pin"
newline
bitfld.long 0x0 17. "CMPCTL,TIMERx_CMP Mode Control" "0: In One-shot or Periodic mode when write new..,1: In One-shot or Periodic mode when write new.."
bitfld.long 0x0 16. "CNTDATEN,Data Load Enable Control\nWhen CNTDATEN is set CNT (TIMERx_CNT[23:0]) (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting." "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.."
newline
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter"
line.long 0x4 "TIMER1_CMP,Timer1 Compare Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field or the core will run into unknown.."
line.long 0x8 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
bitfld.long 0x8 1. "TWKF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
rgroup.long 0x2C++0x7
line.long 0x0 "TIMER1_CNT,Timer1 Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register\nIf CNTDATEN is set to 1 CNT register value will be updated continuously to monitor 24-bit up counter value."
line.long 0x4 "TIMER1_CAP,Timer1 Capture Data Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPIF flag is set to 1 the current CNT (TIMERx_CNT[23:0]) value will be auto-loaded into this TCAP filed immediately."
group.long 0x34++0x7
line.long 0x0 "TIMER1_EXTCTL,Timer1 External Control Register"
bitfld.long 0x0 8. "CAPMODE,Capture Mode Selection" "0: Timer counter reset function or free-counting..,1: Trigger-counting mode of timer capture function"
bitfld.long 0x0 7. "ECNTDBEN,Timer External Counter Input Pin De-Bounce Enable Control" "0: Tx (x = 0~1) pin de-bounce Disabled,1: Tx (x = 0~1) pin de-bounce Enabled"
newline
bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Input Pin De-Bounce Enable Control" "0: TxEX (x = 0~1) pin de-bounce Disabled,1: TxEX (x = 0~1) pin de-bounce Enabled"
bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Control\nIf CAPIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while CAPIF flag is set to 1." "0: TxEX (x = 0~1) pin detection Interrupt Disabled,1: TxEX (x = 0~1) pin detection Interrupt Enabled"
newline
bitfld.long 0x0 4. "CAPFUNCS,Timer External Reset Counter / Timer External Capture Mode Selection" "0: Transition on TxEX (x = 0~1) pin is using to..,1: Transition on TxEX (x = 0~1) pin is using to.."
bitfld.long 0x0 3. "CAPEN,Timer External Pin Function Enable" "0: CAPFUNCS function of TxEX (x = 0~1) pin will be..,1: CAPFUNCS function of TxEX (x = 0~1) pin is active"
newline
bitfld.long 0x0 1.--2. "CAPEDGE,Timer External Pin Edge Detection" "0: A 1 to 0 transition on TxEX (x = 0~1) will be..,1: A 0 to 1 transition on TxEX (x = 0~1) will be..,?,?"
bitfld.long 0x0 0. "CNTPHASE,Timer External Count Pin Phase Detect Selection" "0: A falling edge of Tx (x = 0~1) pin will be counted,1: A rising edge of Tx (x = 0~1) pin will be counted"
line.long 0x4 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
bitfld.long 0x4 0. "CAPIF,Timer External Interrupt Flag\nThis bit indicates the external capture interrupt flag status\nNote: This bit is cleared by writing 1 to it" "0: TxEX (x = 0~1) pin interrupt did not occur,1: TxEX (x = 0~1) pin interrupt occurred"
group.long 0x40++0x3
line.long 0x0 "TIMER_CCAPCTL,Timer Continuous Capture Control Register"
bitfld.long 0x0 11. "CAPF2F,Capture Falling Edge 2 Flag\nSecond falling edge already captured this bit will be set to 1.\nNote: This bit is cleared by H/W automatically when write CCAPEN to 1 or writing 1 to it" "0: None,1: TIMER0_CAP or TIMER1_CAP data is ready for read"
bitfld.long 0x0 10. "CAPR2F,Capture Rising Edge 2 Flag\nSecond rising edge already captured this bit will be set to 1.\nNote: This bit is cleared by H/W automatically when write CCAPEN to 1 or writing 1 to it" "0: None,1: TIMER_CCAP2 data is ready for read"
newline
bitfld.long 0x0 9. "CAPF1F,Capture Falling Edge 1 Flag\nFirst falling edge already captured this bit will be set to 1.\nNote: This bit is cleared by H/W automatically when write CCAPEN to 1 or writing 1 to it" "0: None,1: TIMER_CCAP1 data is ready for read"
bitfld.long 0x0 8. "CAPR1F,Capture Rising Edge 1 Flag\nFirst rising edge already captured this bit will be set to 1.\nNote: This bit is cleared by H/W automatically when write CCAPEN to 1 or writing 1 to it" "0: None,1: TIMER_CCAP0 data is ready for read"
newline
bitfld.long 0x0 3.--5. "CAPCHSEL,Capture Channel Selection\nSelect the input channel to be captured." "0: P0.0,1: P0.4,?,?,?,?,?,?"
bitfld.long 0x0 2. "TMRSEL,Capture Timer Selection\nSelect the timer to capture the input signal." "0: Timer 0,1: Timer 1"
newline
bitfld.long 0x0 1. "INV,Input Signal Inverse\nInvert the input signal which be captured." "0: None,1: Inverse"
bitfld.long 0x0 0. "CCAPEN,Continuous Capture Enable\nThis bit enables the advanced capture function.\nNote: This bit is cleared by H/W automatically when capture operation finish or writing 0 to it" "0: Enable,1: Disable"
rgroup.long 0x44++0xB
line.long 0x0 "TIMER_CCAP0,Timer Continuous Capture Data Register 0"
hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Continuous Capture Data Register X\nTIMER_CCAP0 store the timer count value of first rising edge.\nTIMER_CCAP1 store the timer count value of first falling edge.\nTIMER_CCAP2 store the timer count value of second rising edge."
line.long 0x4 "TIMER_CCAP1,Timer Continuous Capture Data Register 1"
hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Continuous Capture Data Register X\nTIMER_CCAP0 store the timer count value of first rising edge.\nTIMER_CCAP1 store the timer count value of first falling edge.\nTIMER_CCAP2 store the timer count value of second rising edge."
line.long 0x8 "TIMER_CCAP2,Timer Continuous Capture Data Register 2"
hexmask.long.tbyte 0x8 0.--23. 1. "CAPDAT,Timer Continuous Capture Data Register X\nTIMER_CCAP0 store the timer count value of first rising edge.\nTIMER_CCAP1 store the timer count value of first falling edge.\nTIMER_CCAP2 store the timer count value of second rising edge."
endif
sif (cpuis("MINI5??DE"))
group.long 0x0++0xB
line.long 0x0 "TCSR0,Timer0 Control and Status Register"
bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Control (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CEN,Timer Enable Control\n" "0: Stops/Suspends counting,1: Starts counting"
newline
bitfld.long 0x0 29. "IE,Interrupt Enable Control\nIf this bit is enabled when the timer interrupt flag (TIF) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode\n" "0,1,2,3"
newline
bitfld.long 0x0 26. "CRST,Timer Reset\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.."
rbitfld.long 0x0 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
newline
bitfld.long 0x0 24. "CTB,Counter Mode Enable Control\nThis bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 6.12.5.3 for detail description.\n" "0: External event counter mode Disabled,1: External event counter mode Enabled"
bitfld.long 0x0 23. "WAKE_EN,Wake-up Enable Control\nWhen WAKE_EN (UA_IER[6]) is set and the TIF or TEXIF (TEXISR[0]) is set the timer controller will generator a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
newline
bitfld.long 0x0 19. "CAP_SRC,Capture Pin Source Selection\n" "0: Capture Function source is from TxEX pin,1: Capture Function source is from ACMPx output.."
bitfld.long 0x0 18. "TOUT_PIN,Toggle Out Pin Selection\nWhen Timer is set to toggle mode \n" "0: Time0/1 toggle output pin is T0/T1 pin,1: Time0/1 toggle output pin is T0EX/T1EX pin"
newline
bitfld.long 0x0 17. "PERIODIC_SEL,Periodic Mode Behavior Selection\n" "0: In One-shot or Periodic mode when write new TCMP..,1: In One-shot or Periodic mode when write new TCMP.."
bitfld.long 0x0 16. "TDR_EN,Data Load Enable Control\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.."
newline
hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter\n"
line.long 0x4 "TCMPR0,Timer0 Compare Register"
hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field or the core will run into unknown state."
line.long 0x8 "TISR0,Timer0 Interrupt Status Register"
bitfld.long 0x8 1. "TWF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: TDR value matches the TCMP value"
rgroup.long 0xC++0x7
line.long 0x0 "TDR0,Timer0 Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSRx[16]) is set to 1 TDR register value will be updated continuously to monitor 24-bit up counter value."
line.long 0x4 "TCAP0,Timer0 Capture Data Register"
hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF flag is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately."
group.long 0x14++0x7
line.long 0x0 "TEXCON0,Timer0 External Control Register"
bitfld.long 0x0 8. "CAP_MODE,Capture Mode Selection\n" "0: Timer counter reset function or free-counting..,1: Trigger-counting mode of timer capture function"
bitfld.long 0x0 7. "TCDB,Timer External Counter Input Pin De-bounce Enable Control\n" "0: Tx (x = 0~1) pin de-bounce Disabled,1: Tx (x = 0~1) pin de-bounce Enabled"
newline
bitfld.long 0x0 6. "TEXDB,Timer External Capture Input Pin De-bounce Enable Control\n" "0: TxEX (x = 0~1) pin de-bounce Disabled,1: TxEX (x = 0~1) pin de-bounce Enabled"
bitfld.long 0x0 5. "TEXIEN,Timer External Capture Interrupt Enable Control\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1." "0: TxEX (x = 0~1) pin detection Interrupt Disabled,1: TxEX (x = 0~1) pin detection Interrupt Enabled"
newline
bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection\n" "0: Transition on TxEX (x = 0~1) pin is using to..,1: Transition on TxEX (x = 0~1) pin is using to.."
bitfld.long 0x0 3. "TEXEN,Timer External Pin Function Enable Control\n" "0: RSTCAPSEL function of TxEX (x = 0~1) pin will be..,1: RSTCAPSEL function of TxEX (x = 0~1) pin is active"
newline
bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detection\n" "0: A 1 to 0 transition on TxEX (x = 0~1) will be..,1: A 0 to 1 transition on TxEX (x = 0~1) will be..,?,?"
bitfld.long 0x0 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\n" "0: A falling edge of Tx (x = 0~1) pin will be counted,1: A rising edge of Tx (x = 0~1) pin will be counted"
line.long 0x4 "TEXISR0,Timer0 External Interrupt Status Register"
bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag\nThis bit indicates the external capture interrupt flag status\nNote: This bit is cleared by writing 1 to it" "0: TxEX (x = 0 1) pin interrupt did not occur,1: TxEX (x = 0 1) pin interrupt occurred"
group.long 0x20++0xB
line.long 0x0 "TCSR1,Timer1 Control and Status Register"
bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Control (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CEN,Timer Enable Control\n" "0: Stops/Suspends counting,1: Starts counting"
newline
bitfld.long 0x0 29. "IE,Interrupt Enable Control\nIf this bit is enabled when the timer interrupt flag (TIF) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode\n" "0,1,2,3"
newline
bitfld.long 0x0 26. "CRST,Timer Reset\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.."
rbitfld.long 0x0 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
newline
bitfld.long 0x0 24. "CTB,Counter Mode Enable Control\nThis bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 6.12.5.3 for detail description.\n" "0: External event counter mode Disabled,1: External event counter mode Enabled"
bitfld.long 0x0 23. "WAKE_EN,Wake-up Enable Control\nWhen WAKE_EN (UA_IER[6]) is set and the TIF or TEXIF (TEXISR[0]) is set the timer controller will generator a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
newline
bitfld.long 0x0 19. "CAP_SRC,Capture Pin Source Selection\n" "0: Capture Function source is from TxEX pin,1: Capture Function source is from ACMPx output.."
bitfld.long 0x0 18. "TOUT_PIN,Toggle Out Pin Selection\nWhen Timer is set to toggle mode \n" "0: Time0/1 toggle output pin is T0/T1 pin,1: Time0/1 toggle output pin is T0EX/T1EX pin"
newline
bitfld.long 0x0 17. "PERIODIC_SEL,Periodic Mode Behavior Selection\n" "0: In One-shot or Periodic mode when write new TCMP..,1: In One-shot or Periodic mode when write new TCMP.."
bitfld.long 0x0 16. "TDR_EN,Data Load Enable Control\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.."
newline
hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter\n"
line.long 0x4 "TCMPR1,Timer1 Compare Register"
hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field or the core will run into unknown state."
line.long 0x8 "TISR1,Timer1 Interrupt Status Register"
bitfld.long 0x8 1. "TWF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: TDR value matches the TCMP value"
rgroup.long 0x2C++0x7
line.long 0x0 "TDR1,Timer1 Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSRx[16]) is set to 1 TDR register value will be updated continuously to monitor 24-bit up counter value."
line.long 0x4 "TCAP1,Timer1 Capture Data Register"
hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF flag is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately."
group.long 0x34++0x7
line.long 0x0 "TEXCON1,Timer1 External Control Register"
bitfld.long 0x0 8. "CAP_MODE,Capture Mode Selection\n" "0: Timer counter reset function or free-counting..,1: Trigger-counting mode of timer capture function"
bitfld.long 0x0 7. "TCDB,Timer External Counter Input Pin De-bounce Enable Control\n" "0: Tx (x = 0~1) pin de-bounce Disabled,1: Tx (x = 0~1) pin de-bounce Enabled"
newline
bitfld.long 0x0 6. "TEXDB,Timer External Capture Input Pin De-bounce Enable Control\n" "0: TxEX (x = 0~1) pin de-bounce Disabled,1: TxEX (x = 0~1) pin de-bounce Enabled"
bitfld.long 0x0 5. "TEXIEN,Timer External Capture Interrupt Enable Control\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1." "0: TxEX (x = 0~1) pin detection Interrupt Disabled,1: TxEX (x = 0~1) pin detection Interrupt Enabled"
newline
bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection\n" "0: Transition on TxEX (x = 0~1) pin is using to..,1: Transition on TxEX (x = 0~1) pin is using to.."
bitfld.long 0x0 3. "TEXEN,Timer External Pin Function Enable Control\n" "0: RSTCAPSEL function of TxEX (x = 0~1) pin will be..,1: RSTCAPSEL function of TxEX (x = 0~1) pin is active"
newline
bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detection\n" "0: A 1 to 0 transition on TxEX (x = 0~1) will be..,1: A 0 to 1 transition on TxEX (x = 0~1) will be..,?,?"
bitfld.long 0x0 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\n" "0: A falling edge of Tx (x = 0~1) pin will be counted,1: A rising edge of Tx (x = 0~1) pin will be counted"
line.long 0x4 "TEXISR1,Timer1 External Interrupt Status Register"
bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag\nThis bit indicates the external capture interrupt flag status\nNote: This bit is cleared by writing 1 to it" "0: TxEX (x = 0 1) pin interrupt did not occur,1: TxEX (x = 0 1) pin interrupt occurred"
endif
sif (cpuis("MINI5?AN"))
group.long 0x0++0xB
line.long 0x0 "TCSR0,Timer0 Control and Status Register"
bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nThe TIMER counter will be held while ICE Debug mode acknowledged." "0: ICE Debug mode acknowledgement effects TIMER..,1: ICE Debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CEN,Timer Enable Bit\n" "0: Counting stopped/suspended,1: Counting started"
newline
bitfld.long 0x0 29. "IE,Interrupt Enable Bit\nIf timer interrupt is enabled the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode\n" "0,1,2,3"
newline
bitfld.long 0x0 26. "CRST,Timer Reset Bit\nSet this bit will reset the 24-bit up-timer 8-bit pre-scale counter and also force CEN to 0.\n" "0: No effect,1: Timer's 8-bit pre-scale counter internal 24-bit.."
rbitfld.long 0x0 25. "CACT,Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n" "0: Timer not active,1: Timer active"
newline
bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit\nThis bit is the counter mode enable bit. When Timer is used as an event counter this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external.." "0: Counter mode Disabled,1: Counter mode Enabled"
bitfld.long 0x0 23. "WAKE_EN,Wake-Up Enable\nWhen WAKE_EN is set and the TIF or TEXIF is set the timer controller will generator a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
newline
bitfld.long 0x0 19. "CAPS,Capture Trigger Source Selection\n" "0: Time0/1 capture mode trigger input source is..,1: Time0/1 capture mode trigger input source is.."
bitfld.long 0x0 18. "TOUT,Toggle Out Pin Selection\nWhen Timer is set to toggle mode \n" "0: Time0/1 toggle output pin is T0/T1 pin,1: Time0/1 toggle output pin is T0EX/T1EX pin"
newline
bitfld.long 0x0 17. "PERIOD2,PERIOD2 Enable Bit\n" "0: In One-shout or Periodic mode when write new..,1: In One-shout or Periodic mode when write new TCMP"
bitfld.long 0x0 16. "TDR_EN,Data Load Enable\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled"
newline
hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Pre-Scale Counter\n"
line.long 0x4 "TCMPR0,Timer0 Compare Register"
hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value\nNote1: Never write 0 or 1 in TCMP or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode the 24-bit up-timer will count continuously if software writes a new value into TCMP. If.."
line.long 0x8 "TISR0,Timer0 Interrupt Status Register"
bitfld.long 0x8 1. "TWF,Timer Wake-up Flag\nIf timer causes CPU wakes up from power-down mode this bit will be set to high.\nSoftware can write 1 to clear this bit.\n" "0: Timer does not cause CPU wake-up,1: CPU wakes up from sleep or power-down mode by.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt status of timer.\n" "0,1"
rgroup.long 0xC++0x7
line.long 0x0 "TDR0,Timer0 Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register\nThis field indicates the current count value."
line.long 0x4 "TCAP0,Timer0 Capture Data Register"
hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set RSTCAPN (TEXCON[4]) is 0 and the transition on the TEX pins associated TEX_EDGE (TEXCON[2:1]) setting is occurred the internal 24-bit up-timer value will be loaded into TCAP. User can.."
group.long 0x14++0x7
line.long 0x0 "TEXCON0,Timer0 External Control Register"
bitfld.long 0x0 8. "CAP_MODE,Capture Mode Selection\n" "0: Timer counter reset function or free-counting..,1: Trigger-counting mode of timer capture function"
bitfld.long 0x0 7. "TCDB,Timer Counter Pin De-bounce Enable Bit\nIf this bit is enabled the edge of T0~T1 pin is detected with de-bounce circuit." "0: De-bounce Disabled,1: De-bounce Enabled"
newline
bitfld.long 0x0 6. "TEXDB,Timer External Capture Pin De-bounce Enable Bit\nIf this bit is enabled the edge of TEX pin is detected with de-bounce circuit." "0: De-bounce Disabled,1: De-bounce Enabled"
bitfld.long 0x0 5. "TEXIEN,Timer External Interrupt Enable Bit\n" "0: Timer External Interrupt Disabled,1: Timer External Interrupt Enabled"
newline
bitfld.long 0x0 4. "RSTCAPN,Timer External Reset Counter / Capture Mode Selection\n" "0: TEX transition is used as the timer capture..,1: TEX transition is used as the timer counter.."
bitfld.long 0x0 3. "TEXEN,Timer External Pin Enable\nThis bit enables the reset/capture function on the TEX pin.\n" "0: The TEX pin will be ignored,1: The transition detected on the TEX pin will.."
newline
bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detection\n" "0,1,2,3"
bitfld.long 0x0 0. "TX_PHASE,Timer External Count Phase\nThis bit indicates the external count pin phase.\n" "0: A falling edge of external count pin will be..,1: A rising edge of external count pin will be.."
line.long 0x4 "TEXISR0,Timer0 External Interrupt Status Register"
bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag\nThis bit indicates the external interrupt status of the timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1 and the transition on the TEX pins associated with TEX_EDGE (TEXCON[2:1]) setting occurred." "0,1"
group.long 0x20++0xB
line.long 0x0 "TCSR1,Timer1 Control and Status Register"
bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nThe TIMER counter will be held while ICE Debug mode acknowledged." "0: ICE Debug mode acknowledgement effects TIMER..,1: ICE Debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CEN,Timer Enable Bit\n" "0: Counting stopped/suspended,1: Counting started"
newline
bitfld.long 0x0 29. "IE,Interrupt Enable Bit\nIf timer interrupt is enabled the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode\n" "0,1,2,3"
newline
bitfld.long 0x0 26. "CRST,Timer Reset Bit\nSet this bit will reset the 24-bit up-timer 8-bit pre-scale counter and also force CEN to 0.\n" "0: No effect,1: Timer's 8-bit pre-scale counter internal 24-bit.."
rbitfld.long 0x0 25. "CACT,Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n" "0: Timer not active,1: Timer active"
newline
bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit\nThis bit is the counter mode enable bit. When Timer is used as an event counter this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external.." "0: Counter mode Disabled,1: Counter mode Enabled"
bitfld.long 0x0 23. "WAKE_EN,Wake-Up Enable\nWhen WAKE_EN is set and the TIF or TEXIF is set the timer controller will generator a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
newline
bitfld.long 0x0 19. "CAPS,Capture Trigger Source Selection\n" "0: Time0/1 capture mode trigger input source is..,1: Time0/1 capture mode trigger input source is.."
bitfld.long 0x0 18. "TOUT,Toggle Out Pin Selection\nWhen Timer is set to toggle mode \n" "0: Time0/1 toggle output pin is T0/T1 pin,1: Time0/1 toggle output pin is T0EX/T1EX pin"
newline
bitfld.long 0x0 17. "PERIOD2,PERIOD2 Enable Bit\n" "0: In One-shout or Periodic mode when write new..,1: In One-shout or Periodic mode when write new TCMP"
bitfld.long 0x0 16. "TDR_EN,Data Load Enable\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled"
newline
hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Pre-Scale Counter\n"
line.long 0x4 "TCMPR1,Timer1 Compare Register"
hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value\nNote1: Never write 0 or 1 in TCMP or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode the 24-bit up-timer will count continuously if software writes a new value into TCMP. If.."
line.long 0x8 "TISR1,Timer1 Interrupt Status Register"
bitfld.long 0x8 1. "TWF,Timer Wake-up Flag\nIf timer causes CPU wakes up from power-down mode this bit will be set to high.\nSoftware can write 1 to clear this bit.\n" "0: Timer does not cause CPU wake-up,1: CPU wakes up from sleep or power-down mode by.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt status of timer.\n" "0,1"
rgroup.long 0x2C++0x7
line.long 0x0 "TDR1,Timer1 Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register\nThis field indicates the current count value."
line.long 0x4 "TCAP1,Timer1 Capture Data Register"
hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set RSTCAPN (TEXCON[4]) is 0 and the transition on the TEX pins associated TEX_EDGE (TEXCON[2:1]) setting is occurred the internal 24-bit up-timer value will be loaded into TCAP. User can.."
group.long 0x34++0x7
line.long 0x0 "TEXCON1,Timer1 External Control Register"
bitfld.long 0x0 8. "CAP_MODE,Capture Mode Selection\n" "0: Timer counter reset function or free-counting..,1: Trigger-counting mode of timer capture function"
bitfld.long 0x0 7. "TCDB,Timer Counter Pin De-bounce Enable Bit\nIf this bit is enabled the edge of T0~T1 pin is detected with de-bounce circuit." "0: De-bounce Disabled,1: De-bounce Enabled"
newline
bitfld.long 0x0 6. "TEXDB,Timer External Capture Pin De-bounce Enable Bit\nIf this bit is enabled the edge of TEX pin is detected with de-bounce circuit." "0: De-bounce Disabled,1: De-bounce Enabled"
bitfld.long 0x0 5. "TEXIEN,Timer External Interrupt Enable Bit\n" "0: Timer External Interrupt Disabled,1: Timer External Interrupt Enabled"
newline
bitfld.long 0x0 4. "RSTCAPN,Timer External Reset Counter / Capture Mode Selection\n" "0: TEX transition is used as the timer capture..,1: TEX transition is used as the timer counter.."
bitfld.long 0x0 3. "TEXEN,Timer External Pin Enable\nThis bit enables the reset/capture function on the TEX pin.\n" "0: The TEX pin will be ignored,1: The transition detected on the TEX pin will.."
newline
bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detection\n" "0,1,2,3"
bitfld.long 0x0 0. "TX_PHASE,Timer External Count Phase\nThis bit indicates the external count pin phase.\n" "0: A falling edge of external count pin will be..,1: A rising edge of external count pin will be.."
line.long 0x4 "TEXISR1,Timer1 External Interrupt Status Register"
bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag\nThis bit indicates the external interrupt status of the timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1 and the transition on the TEX pins associated with TEX_EDGE (TEXCON[2:1]) setting occurred." "0,1"
endif
tree.end
tree "UART (Universal Asynchronous Receiver/Transmitter)"
base ad:0x0
sif (cpuis("MINI5?XAE"))
tree "UART0"
base ad:0x40050000
group.long 0x0++0x1B
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Receiving/Transmit Buffer\nWrite Operation:\nBy writing to this register the UART sends out an 8-bit data through the TX pin (LSB first). \nBy reading this register the UART Controller will return an 8-bit data received from RX pin (LSB first)."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 13. "ATOCTSEN,CTS Auto Flow Control Enable Control\nNote: When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled"
bitfld.long 0x4 12. "ATORTSEN,RTS Auto Flow Control Enable Control\nNote: When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled"
newline
bitfld.long 0x4 11. "TOCNTEN,Time-Out Counter Enable Control" "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x4 6. "WKCTSIEN,Wake-Up CPU Function Enable Control\nNote: when the chip is in Power-down mode an external CTS change will wake-up chip from Power-down mode." "0: UART wake-up function Disabled,1: UART Wake-up function Enabled"
newline
bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Control" "0: BUFERRINT Masked Disabled,1: BUFERRINT Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-Out Interrupt Enable Control" "0: RXTOINT Masked off,1: RXTOINT Enabled"
newline
bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Control" "0: MODEMINT Masked off,1: MODEMINT Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Control" "0: RLSINT Masked off,1: RLSINT Enabled"
newline
bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Control" "0: THREINT Masked off,1: THREINT Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Control" "0: RDAINT Masked off,1: RDAINT Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,RTS Trigger Level (for Auto-flow Control Use)\nNote: This field is used for RTS auto-flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Register\nThe receiver is disabled or not (setting 1 to disable the receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
newline
hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt (RDAINT) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set (if RDAIEN in UART_INTEN register is enable an interrupt will generated)."
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles." "0: No effect,1: The TX internal state machine and pointers reset"
newline
bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles." "0: No effect,1: The RX internal state machine and pointers reset"
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0: Break control Disabled,1: Break control Enabled"
bitfld.long 0xC 5. "SPE,Stick Parity Enable Control" "0: Stick parity Disabled,1: If PBE (UART_LINE[3]) and EBE (UART_LINE[4]) are.."
newline
bitfld.long 0xC 4. "EPE,Even Parity Enable Control\nThis bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
bitfld.long 0xC 3. "PBE,Parity Bit Enable Control" "0: No parity bit,1: Parity bit is generated on each outgoing.."
newline
bitfld.long 0xC 2. "NSB,Number Of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
bitfld.long 0xC 0.--1. "WLS,Word Length Selection" "0: Word length is 5-bit,1: Word length is 6-bit,?,?"
line.long 0x10 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x10 13. "RTSSTS,RTS Pin State (Read Only)\nThis bit mirror from RTS pin output of voltage logic status." "0: RTS pin output is low level voltage logic state,1: RTS pin output is high level voltage logic state"
bitfld.long 0x10 9. "RTSACTLV,RTS Pin Active Level\nThis bit defines the active level state of RTS pin output." "0: RTS pin output is high level active,1: RTS pin output is low level active"
newline
bitfld.long 0x10 1. "RTS,RTS (Request-To-Send) Signal Control\nThis bit is direct control internal RTS signal active or not and then drive the RTS pin output with RTSACTLV bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is.." "0: RTS signal is active,1: This RTS signal control bit is not effective.."
line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x14 8. "CTSACTLV,CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 6.1410" "0: CTS pin input is high level active,1: CTS pin input is low level active"
rbitfld.long 0x14 4. "CTSSTS,CTS Pin Status (Read Only)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled and CTS multi-function port is selected." "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state"
newline
bitfld.long 0x14 0. "CTSDETF,Detect CTS State Change Flag\nThis bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: CTS input has not change state,1: CTS input has change state"
line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty"
bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
newline
rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into DAT (TX.." "0: TX FIFO is not empty,1: TX FIFO is empty"
newline
hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware.." "0: RX FIFO is not full,1: RX FIFO is full"
newline
rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
newline
rbitfld.long 0x18 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated"
rbitfld.long 0x18 5. "FEF,Framing Error Flag (Read Only)\nNote: This bit is read only but can be cleared by writing '1' to it ." "?,1: Framing error is generated"
newline
rbitfld.long 0x18 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'." "0: No parity error is generated,1: Parity error is generated.Note: This bit is read.."
bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detection Flag \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it." "?,1: This field is used for RS-485 function mode"
newline
bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
rgroup.long 0x1C++0x3
line.long 0x0 "UART_INTSTS,UART Interrupt Status Register"
bitfld.long 0x0 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and BUFERRIF are both set to 1." "0: No buffer error interrupt is generated,1: buffer error interrupt is generated"
bitfld.long 0x0 12. "RXTOINT,Time-Out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN and RXTOIF are both set to 1." "0: No Time-out interrupt is generated,1: Time-out interrupt is generated"
newline
bitfld.long 0x0 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN and MODENIF are both set to 1." "0: No Modem interrupt is generated,1: Modem interrupt is generated"
bitfld.long 0x0 10. "RLSINT,Receive Line Status Interrupt (Read Only)\nThis bit is set if RLSIEN and RLSIF are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
newline
bitfld.long 0x0 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN and THREIF are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
bitfld.long 0x0 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN and RDAIF are both set to 1.\nThis bit is set if RDAIEN and RDAIF are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
newline
bitfld.long 0x0 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TXOVIF or RXOVIF) is set. \nWhen BUFERRIF is set the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled the buffer error interrupt will.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
bitfld.long 0x0 4. "RXTOIF,Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RXTOIEN (UART_INTEN [4]) is enabled the Tout interrupt will be.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
newline
bitfld.long 0x0 3. "MODENIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
bitfld.long 0x0 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error framing error or break error (at least one of 3 bits BIF FEF and PEF is set). If RLSIEN (UART_INTEN [2]) is enabled the RLS interrupt will be.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
newline
bitfld.long 0x0 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN [1]) is enabled the THRE interrupt will be generated.\nNote: This bit.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
bitfld.long 0x0 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated. \nNote: This bit is read only and it.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x13
line.long 0x0 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value\nThis field is used to program the transfer delay time between the last stop bit and next start bit."
hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-Out Interrupt Comparator"
line.long 0x4 "UART_BAUD,UART Baud Rate Divisor Register"
bitfld.long 0x4 29. "BAUDM1,Divider X Enable\nRefer to the table below for more information.\nNote: When in IrDA mode this bit must be disabled." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.."
bitfld.long 0x4 28. "BAUDM0,Divider X Equal 1\nUART Controller Baud Rate Generator\nRefer to section 'UART Controller Baud Rate Generator' for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
newline
hexmask.long.byte 0x4 24.--27. 1. "EDIVM1,Divider X"
hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider."
line.long 0x8 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x8 6. "RXINV,RXINV" "0: No inversion,1: Inverse RX input signal"
bitfld.long 0x8 5. "TXINV,TXINV" "0: No inversion,1: Inverse TX output signal"
newline
bitfld.long 0x8 1. "TXEN,TXEN" "0: IrDA receiver Enabled,1: IrDA transmitter Enabled"
line.long 0xC "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0xC 24.--31. 1. "ADDRMV,Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0xC 15. "ADDRDEN,RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 Address Detection mode.\nNote: This field is used for RS-485 any operation mode." "0: RS-485 address detection mode Disabled,1: RS-485 address detection mode Enabled"
newline
bitfld.long 0xC 10. "RS485AUD,RS-485 Auto Direction Mode (AUD) Control\nNote: It can be active with RS485ADD or RS485NMM operation mode." "0: RS-485 Auto Direction Mode (AUD) Disabled,1: RS-485 Auto Direction Mode (AUD) Enabled"
bitfld.long 0xC 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS485NMM operation mode." "0: RS-485 Auto Address Detection Operation Mode..,1: RS-485 Auto Address Detection Operation Mode.."
newline
bitfld.long 0xC 8. "RS485NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) Control\nNote: It cannot be active with RS485AAD operation mode." "0: RS-485 Normal Multi-drop Operation Mode (NMM)..,1: RS-485 Normal Multi-drop Operation Mode (NMM).."
line.long 0x10 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x10 0.--1. "FUNCSEL,Function Select" "0: UART function mode,1: Reserved,?,?"
tree.end
tree "UART1"
base ad:0x40150000
group.long 0x0++0x1B
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Receiving/Transmit Buffer\nWrite Operation:\nBy writing to this register the UART sends out an 8-bit data through the TX pin (LSB first). \nBy reading this register the UART Controller will return an 8-bit data received from RX pin (LSB first)."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 13. "ATOCTSEN,CTS Auto Flow Control Enable Control\nNote: When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled"
bitfld.long 0x4 12. "ATORTSEN,RTS Auto Flow Control Enable Control\nNote: When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled"
newline
bitfld.long 0x4 11. "TOCNTEN,Time-Out Counter Enable Control" "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x4 6. "WKCTSIEN,Wake-Up CPU Function Enable Control\nNote: when the chip is in Power-down mode an external CTS change will wake-up chip from Power-down mode." "0: UART wake-up function Disabled,1: UART Wake-up function Enabled"
newline
bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Control" "0: BUFERRINT Masked Disabled,1: BUFERRINT Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-Out Interrupt Enable Control" "0: RXTOINT Masked off,1: RXTOINT Enabled"
newline
bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Control" "0: MODEMINT Masked off,1: MODEMINT Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Control" "0: RLSINT Masked off,1: RLSINT Enabled"
newline
bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Control" "0: THREINT Masked off,1: THREINT Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Control" "0: RDAINT Masked off,1: RDAINT Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,RTS Trigger Level (for Auto-flow Control Use)\nNote: This field is used for RTS auto-flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Register\nThe receiver is disabled or not (setting 1 to disable the receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
newline
hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt (RDAINT) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set (if RDAIEN in UART_INTEN register is enable an interrupt will generated)."
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles." "0: No effect,1: The TX internal state machine and pointers reset"
newline
bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles." "0: No effect,1: The RX internal state machine and pointers reset"
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0: Break control Disabled,1: Break control Enabled"
bitfld.long 0xC 5. "SPE,Stick Parity Enable Control" "0: Stick parity Disabled,1: If PBE (UART_LINE[3]) and EBE (UART_LINE[4]) are.."
newline
bitfld.long 0xC 4. "EPE,Even Parity Enable Control\nThis bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
bitfld.long 0xC 3. "PBE,Parity Bit Enable Control" "0: No parity bit,1: Parity bit is generated on each outgoing.."
newline
bitfld.long 0xC 2. "NSB,Number Of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
bitfld.long 0xC 0.--1. "WLS,Word Length Selection" "0: Word length is 5-bit,1: Word length is 6-bit,?,?"
line.long 0x10 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x10 13. "RTSSTS,RTS Pin State (Read Only)\nThis bit mirror from RTS pin output of voltage logic status." "0: RTS pin output is low level voltage logic state,1: RTS pin output is high level voltage logic state"
bitfld.long 0x10 9. "RTSACTLV,RTS Pin Active Level\nThis bit defines the active level state of RTS pin output." "0: RTS pin output is high level active,1: RTS pin output is low level active"
newline
bitfld.long 0x10 1. "RTS,RTS (Request-To-Send) Signal Control\nThis bit is direct control internal RTS signal active or not and then drive the RTS pin output with RTSACTLV bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is.." "0: RTS signal is active,1: This RTS signal control bit is not effective.."
line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x14 8. "CTSACTLV,CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 6.1410" "0: CTS pin input is high level active,1: CTS pin input is low level active"
rbitfld.long 0x14 4. "CTSSTS,CTS Pin Status (Read Only)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled and CTS multi-function port is selected." "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state"
newline
bitfld.long 0x14 0. "CTSDETF,Detect CTS State Change Flag\nThis bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: CTS input has not change state,1: CTS input has change state"
line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty"
bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
newline
rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into DAT (TX.." "0: TX FIFO is not empty,1: TX FIFO is empty"
newline
hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware.." "0: RX FIFO is not full,1: RX FIFO is full"
newline
rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
newline
rbitfld.long 0x18 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated"
rbitfld.long 0x18 5. "FEF,Framing Error Flag (Read Only)\nNote: This bit is read only but can be cleared by writing '1' to it ." "?,1: Framing error is generated"
newline
rbitfld.long 0x18 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'." "0: No parity error is generated,1: Parity error is generated.Note: This bit is read.."
bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detection Flag \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it." "?,1: This field is used for RS-485 function mode"
newline
bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
rgroup.long 0x1C++0x3
line.long 0x0 "UART_INTSTS,UART Interrupt Status Register"
bitfld.long 0x0 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and BUFERRIF are both set to 1." "0: No buffer error interrupt is generated,1: buffer error interrupt is generated"
bitfld.long 0x0 12. "RXTOINT,Time-Out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN and RXTOIF are both set to 1." "0: No Time-out interrupt is generated,1: Time-out interrupt is generated"
newline
bitfld.long 0x0 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN and MODENIF are both set to 1." "0: No Modem interrupt is generated,1: Modem interrupt is generated"
bitfld.long 0x0 10. "RLSINT,Receive Line Status Interrupt (Read Only)\nThis bit is set if RLSIEN and RLSIF are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
newline
bitfld.long 0x0 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN and THREIF are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
bitfld.long 0x0 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN and RDAIF are both set to 1.\nThis bit is set if RDAIEN and RDAIF are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
newline
bitfld.long 0x0 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TXOVIF or RXOVIF) is set. \nWhen BUFERRIF is set the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled the buffer error interrupt will.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
bitfld.long 0x0 4. "RXTOIF,Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RXTOIEN (UART_INTEN [4]) is enabled the Tout interrupt will be.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
newline
bitfld.long 0x0 3. "MODENIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
bitfld.long 0x0 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error framing error or break error (at least one of 3 bits BIF FEF and PEF is set). If RLSIEN (UART_INTEN [2]) is enabled the RLS interrupt will be.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
newline
bitfld.long 0x0 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN [1]) is enabled the THRE interrupt will be generated.\nNote: This bit.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
bitfld.long 0x0 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated. \nNote: This bit is read only and it.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x13
line.long 0x0 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value\nThis field is used to program the transfer delay time between the last stop bit and next start bit."
hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-Out Interrupt Comparator"
line.long 0x4 "UART_BAUD,UART Baud Rate Divisor Register"
bitfld.long 0x4 29. "BAUDM1,Divider X Enable\nRefer to the table below for more information.\nNote: When in IrDA mode this bit must be disabled." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.."
bitfld.long 0x4 28. "BAUDM0,Divider X Equal 1\nUART Controller Baud Rate Generator\nRefer to section 'UART Controller Baud Rate Generator' for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
newline
hexmask.long.byte 0x4 24.--27. 1. "EDIVM1,Divider X"
hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider."
line.long 0x8 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x8 6. "RXINV,RXINV" "0: No inversion,1: Inverse RX input signal"
bitfld.long 0x8 5. "TXINV,TXINV" "0: No inversion,1: Inverse TX output signal"
newline
bitfld.long 0x8 1. "TXEN,TXEN" "0: IrDA receiver Enabled,1: IrDA transmitter Enabled"
line.long 0xC "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0xC 24.--31. 1. "ADDRMV,Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0xC 15. "ADDRDEN,RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 Address Detection mode.\nNote: This field is used for RS-485 any operation mode." "0: RS-485 address detection mode Disabled,1: RS-485 address detection mode Enabled"
newline
bitfld.long 0xC 10. "RS485AUD,RS-485 Auto Direction Mode (AUD) Control\nNote: It can be active with RS485ADD or RS485NMM operation mode." "0: RS-485 Auto Direction Mode (AUD) Disabled,1: RS-485 Auto Direction Mode (AUD) Enabled"
bitfld.long 0xC 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS485NMM operation mode." "0: RS-485 Auto Address Detection Operation Mode..,1: RS-485 Auto Address Detection Operation Mode.."
newline
bitfld.long 0xC 8. "RS485NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) Control\nNote: It cannot be active with RS485AAD operation mode." "0: RS-485 Normal Multi-drop Operation Mode (NMM)..,1: RS-485 Normal Multi-drop Operation Mode (NMM).."
line.long 0x10 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x10 0.--1. "FUNCSEL,Function Select" "0: UART function mode,1: Reserved,?,?"
tree.end
endif
sif (cpuis("MINI5??DE"))
tree "UART"
base ad:0x40050000
rgroup.long 0x0++0x3
line.long 0x0 "UA_RBR,UART Receive Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Bits (Read Only)\nBy reading this register the UART Controller will return an 8-bit data received from RX pin (LSB first)."
wgroup.long 0x0++0x3
line.long 0x0 "UA_THR,UART Transmit Holding Register"
hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Bits\nBy writing to this register the UART sends out an 8-bit data through the TX pin (LSB first)."
group.long 0x4++0x17
line.long 0x0 "UA_IER,UART Interrupt Enable Control Register"
bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Control\nNote: When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled"
bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Control\nNote: When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled"
newline
bitfld.long 0x0 11. "TIME_OUT_EN,Time-out Counter Enable Control\n" "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x0 6. "WAKE_EN,Wake-up CPU Function Enable Control\nNote: when the chip is in Power-down mode an external CTS change will wake-up chip from Power-down mode." "0: UART wake-up function Disabled,1: UART Wake-up function Enabled"
newline
bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Control\n" "0: INT_BUF_ERR Masked Disabled,1: INT_BUF_ERR Enabled"
bitfld.long 0x0 4. "RTO_IEN,RX Time-out Interrupt Enable Control\n" "0: TOUT_INT Masked off,1: TOUT_INT Enabled"
newline
bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable Control\n" "0: MODEM_INT Masked off,1: MODEM_INT Enabled"
bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable Control\n" "0: RLS_INT Masked off,1: RLS_INT Enabled"
newline
bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Control\n" "0: THRE_INT Masked off,1: THRE_INT Enabled"
bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable Control\n" "0: RDA_INT Masked off,1: RDA_INT Enabled"
line.long 0x4 "UA_FCR,UART FIFO Control Register"
hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTS Trigger Level (For Auto-flow Control Use)\nNote: This field is used for RTS auto-flow control."
bitfld.long 0x4 8. "RX_DIS,Receiver Disable Control\nThe receiver is disabled or not (setting 1 to disable the receiver).\nNote1: This field is only used for RS-485 Normal Multi-drop mode. It should be programmed firstly to avoid receiving unknown data before RS-485_NMM.." "0: Receiver Enabled,1: This field is only used for RS-485 Normal.."
newline
hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (RDA_INT) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDA_IF will be set (if RDA_IEN in UA_IER register is enable an interrupt will generated).\n"
bitfld.long 0x4 2. "TFR,TX Field Software Reset\nWhen TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles." "0: No effect,1: The TX internal state machine and pointers reset"
newline
bitfld.long 0x4 1. "RFR,RX Field Software Reset\nWhen RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles." "0: No effect,1: The RX internal state machine and pointers reset"
line.long 0x8 "UA_LCR,UART Line Control Register"
bitfld.long 0x8 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.\n" "0: Break control Disabled,1: Break control Enabled"
bitfld.long 0x8 5. "SPE,Stick Parity Enable Control\n" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.."
newline
bitfld.long 0x8 4. "EPE,Even Parity Enable Control\nThis bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
bitfld.long 0x8 3. "PBE,Parity Bit Enable Control\n" "0: No parity bit,1: Parity bit is generated on each outgoing.."
newline
bitfld.long 0x8 2. "NSB,Number Of 'STOP Bit'\n" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
bitfld.long 0x8 0.--1. "WLS,Word Length Selection\n" "0: Word length is 5-bit,1: Word length is 6-bit,?,?"
line.long 0xC "UA_MCR,UART Modem Control Register"
rbitfld.long 0xC 13. "RTS_ST,RTS Pin State (Read Only)\nThis bit mirror from RTS pin output of voltage logic status.\n" "0: RTS pin output is low level voltage logic state,1: RTS pin output is high level voltage logic state"
bitfld.long 0xC 9. "LEV_RTS,RTS Pin Active Level\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to and UART function mode.\nNote2: Refer to and for RS-485 function mode." "0: RTS pin output is high level active,1: Refer to and UART function mode"
newline
bitfld.long 0xC 1. "RTSn,RTS (Request-to-send) Signal Control\nThis bit is direct control internal RTS signal active or not and then drive the RTS pin output with LEV_RTS bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control.." "0: RTS signal is active,1: This RTS signal control bit is not effective.."
line.long 0x10 "UA_MSR,UART Modem Status Register"
bitfld.long 0x10 8. "LEV_CTS,CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to" "0: CTS pin input is high level active,1: CTS pin input is low level active"
rbitfld.long 0x10 4. "CTS_ST,CTS Pin Status (Read Only)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled and CTS multi-function port is selected." "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state"
newline
bitfld.long 0x10 0. "DCTSF,Detect CTS State Change Flag\nThis bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: CTS input has not change state,1: CTS input has change state"
line.long 0x14 "UA_FSR,UART FIFO Status Register"
rbitfld.long 0x14 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x14 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
newline
rbitfld.long 0x14 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x14 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR.." "0: TX FIFO is not empty,1: TX FIFO is empty"
newline
hexmask.long.byte 0x14 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TX_POINTER decreases one.\nThe.."
rbitfld.long 0x14 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
newline
rbitfld.long 0x14 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x14 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RX_POINTER increases one. When one byte of RX FIFO is read by CPU RX_POINTER decreases one.\nThe Maximum value.."
newline
rbitfld.long 0x14 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated"
rbitfld.long 0x14 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit follows the last data bit or parity bit is detected as as logic 0). \nNote: This bit is read only but.." "0: No framing error is generated,1: Framing error is generated"
newline
rbitfld.long 0x14 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\n" "0: No parity error is generated,1: Parity error is generated.Note: This bit is read.."
bitfld.long 0x14 3. "RS_485_ADD_DETF,RS-485 Address Byte Detection Flag \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it." "?,1: This field is used for RS-485 function mode"
newline
bitfld.long 0x14 0. "RX_OVER_IF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
rgroup.long 0x1C++0x3
line.long 0x0 "UA_ISR,UART Interrupt Status Register"
bitfld.long 0x0 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n" "0: No buffer error interrupt is generated,1: buffer error interrupt is generated"
bitfld.long 0x0 12. "TOUT_INT,Time-out Interrupt Indicator (Read Only)\nThis bit is set if RTO_IEN and TOUT_IF are both set to 1.\n" "0: No Time-out interrupt is generated,1: Time-out interrupt is generated"
newline
bitfld.long 0x0 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
bitfld.long 0x0 10. "RLS_INT,Receive Line Status Interrupt (Read Only)\nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
newline
bitfld.long 0x0 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
bitfld.long 0x0 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
newline
bitfld.long 0x0 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TX_OVER_IF or RX_OVER_IF) is set. \nWhen BUF_ERR_IF is set the transfer is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled the buffer error.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
bitfld.long 0x0 4. "TOUT_IF,Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RTO_IEN (UA_IER [4]) is enabled the Tout interrupt will be generated.\nNote:.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
newline
bitfld.long 0x0 3. "MODEM_IF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
bitfld.long 0x0 2. "RLS_IF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error framing error or break error (at least one of 3 bits BIF FEF and PEF is set). If RLS_IEN (UA_IER [2]) is enabled the RLS interrupt will be.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
newline
bitfld.long 0x0 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER [1]) is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
bitfld.long 0x0 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If RDA_IEN (UA_IER [0]) is enabled the RDA interrupt will be generated. \nNote: This bit is read only and it.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x13
line.long 0x0 "UA_TOR,UART Time-out Register"
hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value\nThis field is used to program the transfer delay time between the last stop bit and next start bit."
hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator\n"
line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register"
bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable Control\nNote: When in IrDA mode this bit must be disabled." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.."
bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal 1\n\nRefer to section 'UART Controller Baud Rate Generator' for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
newline
hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X\n"
hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider."
line.long 0x8 "UA_IRCR,UART IrDA Control Register"
bitfld.long 0x8 6. "INV_RX,INV_RX\n" "0: No inversion,1: Inverse RX input signal"
bitfld.long 0x8 5. "INV_TX,INV_TX\n" "0: No inversion,1: Inverse TX output signal"
newline
bitfld.long 0x8 1. "TX_SELECT,TX_SELECT\n" "0: IrDA receiver Enabled,1: IrDA transmitter Enabled"
line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register"
hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 Address Detection mode.\nNote: This field is used for RS-485 any operation mode." "0: RS-485 address detection mode Disabled,1: RS-485 address detection mode Enabled"
newline
bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) Control\nNote: This bit cannot be active with RS485_NMM operation mode." "0: RS-485 Auto Address Detection Operation Mode..,1: RS-485 Auto Address Detection Operation Mode.."
bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: This bit cannot be active with RS485_NMM operation mode." "0: RS-485 Auto Address Detection Operation Mode..,1: RS-485 Auto Address Detection Operation Mode.."
newline
bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-drop Operation Mode (NMM) Control\nNote: This bit cannot be active with RS485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation Mode (NMM)..,1: RS-485 Normal Multi-drop Operation Mode (NMM).."
line.long 0x10 "UA_FUN_SEL,UART Function Select Register"
bitfld.long 0x10 0.--1. "FUN_SEL,Function Selection\n" "0: UART function mode,1: Reserved,?,?"
tree.end
endif
sif (cpuis("MINI5?AN"))
tree "UART"
base ad:0x40050000
rgroup.long 0x0++0x3
line.long 0x0 "UA_RBR,UART Receive Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only)\nBy reading this register the UART will return an 8-bit data received from RX pin (LSB first)."
wgroup.long 0x0++0x3
line.long 0x0 "UA_THR,UART Transmit Holding Register"
hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register\nBy writing to this register the UART sends out an 8-bit data through the TX pin (LSB first)."
group.long 0x4++0x13
line.long 0x0 "UA_IER,UART Interrupt Enable Register"
bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable\nNote: When CTSn auto-flow is enabled the UART will send data to external device when CTSn input assert (UART will not send data to device until CTSn is asserted)." "0: CTSn auto flow control Disabled,1: CTSn auto flow control Enabled"
bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable\nNote: When RTSn auto-flow is enabled if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV] the UART will de-assert RTSn signal." "0: RTSn auto flow control Disabled,1: RTSn auto flow control Enabled"
newline
bitfld.long 0x0 11. "TIME_OUT_EN,Time-out Counter Enable\n" "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x0 6. "WAKE_EN,Wake-up CPU Function Enable\n" "0: UART wake-up CPU function Disabled,1: Wake-up function Enabled; when the system is in.."
newline
bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable\n" "0: INT_BUF_ERR Masked off,1: INT_BUF_ERR Enabled"
bitfld.long 0x0 4. "RTO_IEN,RX Time-out Interrupt Enable\n" "0: INT_TOUT Masked off,1: INT_TOUT Enabled"
newline
bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable\n" "0: INT_MODEM Masked off,1: INT_MODEM Enabled"
bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable\n" "0: INT_RLS Masked off,1: INT_RLS Enabled"
newline
bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable\n" "0: INT_THRE Masked off,1: INT_THRE Enabled"
bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable\n" "0: INT_RDA Masked off,1: INT_RDA Enabled"
line.long 0x4 "UA_FCR,UART FIFO Control Register"
hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTSn Trigger Level (for Auto-flow Control Use)\n"
bitfld.long 0x4 8. "RX_DIS,Receiver Disable register\nThe receiver is disabled or not (setting 1 to disable the receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR[RS-485_NMM] is programmed." "0: Receiver Enabled,1: Receiver Disabled"
newline
hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level\n"
bitfld.long 0x4 2. "TFR,TX Field Software Reset\nWhen TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles." "0: No effect,1: The TX internal state machine and pointers reset"
newline
bitfld.long 0x4 1. "RFR,RX Field Software Reset\nWhen RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles." "0: No effect,1: The RX internal state machine and pointers reset"
line.long 0x8 "UA_LCR,UART Line Control Register"
bitfld.long 0x8 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1"
bitfld.long 0x8 5. "SPE,Stick Parity Enable\n" "0: Stick parity Disabled,1: When bits PBE EPE and SPE are set the parity bit.."
newline
bitfld.long 0x8 4. "EPE,Even Parity Enable\nNote: This bit has effect only when bit 3 (parity bit enable) is set." "0: Odd number of logic 1 transmitted or checked in..,1: Even number of logic 1 transmitted or checked in.."
bitfld.long 0x8 3. "PBE,Parity Bit Enable\n" "0: Parity bit not generated (transmit data) or..,1: Parity bit generated or checked between the last.."
newline
bitfld.long 0x8 2. "NSB,Number of 'STOP bit'\n" "0: One 'STOP bit' is generated in the transmitted..,1: One and a half 'STOP bit' is generated in the.."
bitfld.long 0x8 0.--1. "WLS,Word Length Selection\n" "0,1,2,3"
line.long 0xC "UA_MCR,UART Modem Control Register"
rbitfld.long 0xC 13. "RTS_ST,RTSn Pin State (Read Only)\nThis bit is the output pin status of RTSn." "0,1"
bitfld.long 0xC 9. "LEV_RTS,RTSn Trigger Level\nThis bit can change the RTSn trigger level.\n" "0: Low level triggered,1: High level triggered"
newline
bitfld.long 0xC 1. "RTSn,RTSn (Request-to-Send) Signal\n" "0,1"
line.long 0x10 "UA_MSR,UART Modem Status Register"
bitfld.long 0x10 8. "LEV_CTS,CTSn Trigger Level\nThis bit can change the CTSn trigger level.\n" "0: Low level triggered,1: High level triggered"
rbitfld.long 0x10 4. "CTS_ST,CTSn Pin Status (Read Only)\nThis bit is the pin status of CTSn." "0,1"
newline
rbitfld.long 0x10 0. "DCTSF,Detect CTSn State Change Flag (Read Only)\nThis bit is set whenever CTSn input has change state and it will generate Modem interrupt to CPU when UA_IER[MODEM_IEN].\nNote: This bit is read only but software can write 1 to clear it." "0,1"
rgroup.long 0x18++0x7
line.long 0x0 "UA_FSR,UART FIFO Status Register"
bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not.." "0,1"
bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only but software can write 1 to clear it." "0,1"
newline
bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to 16 otherwise is cleared by hardware." "0,1"
bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates whether TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR.." "0,1"
newline
hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TX_POINTER decreases one."
bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is equal to 16; otherwise it is cleared by hardware." "0,1"
newline
bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiates RX FIFO empty (or not).\nWhen the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0,1"
hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When the UART receives one byte from an external device RX_POINTER increases one. When one byte of RX FIFO is read by CPU RX_POINTER decreases one."
newline
bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to a logic 1 when the received data input(RX) is held in the 'spacing state' (logic 0) for the time longer than a full word transmission time (that is the total time of 'start bit' + data bits +.." "0,1"
bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 when the received character does not have a valid 'stop bit' (that is the stop bit follows the last data bit or parity bit is detected as a logic 0) and is reset when the CPU writes 1 to.." "0,1"
newline
bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 when the received character does not have a valid 'parity bit' and is reset when the CPU writes 1 to this bit.\nNote: This bit is read only but software can write 1 to clear it." "0,1"
bitfld.long 0x0 3. "RS_485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only but software can write 1 to clear it." "0,1"
newline
bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 16 bytes of UART this bit will be set.\nNote: This bit is read only but software can.." "0,1"
line.long 0x4 "UA_ISR,UART Interrupt Status Register"
bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator To Interrupt Controller (Read Only)\nAn AND output with inputs of BUF_ERR_IEN and BUF_ERR_IF." "0,1"
bitfld.long 0x4 12. "TOUT_INT,Time-out Interrupt Indicator to Interrupt Controller (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n" "0: No Tout interrupt generated,1: The Tout interrupt generated"
newline
bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator to Interrupt Controller (Read Only)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n" "0: No Modem interrupt generated,1: The Modem interrupt generated"
bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator to Interrupt Controller (Read Only)\nThis bit is set if RLS_IEN and RLS_IF .are both set to 1.\n" "0: No RLS interrupt generated,1: The RLS interrupt generated"
newline
bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n" "0: No THRE interrupt generated,1: The THRE interrupt generated"
bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator to Interrupt Controller (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n" "0: No RDA interrupt generated,1: The RDA interrupt generated"
newline
bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows or Break Interrupt Flag or Parity Error Flag or Frame Error Flag (TX_OVER_IF or RX_OVER_IF or BIF or PEF or FEF ) is set. When BUF_ERR_IF is set the.." "0,1"
bitfld.long 0x4 4. "TOUT_IF,Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER[TOUT_IEN] is enabled the Tout interrupt will be generated.\nNote: This.." "0,1"
newline
bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF." "0,1"
bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error framing error or break error (at least one of 3 bits BIF FEF and PEF is set). If UA_IER[RLS_IEN] is enabled the RLS interrupt will be.." "0,1"
newline
bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled the THRE interrupt will be generated.\nNote: This bit is read.." "0,1"
bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER[RDA_IEN] is enabled the RDA interrupt will be generated.\nNote: This bit is read only and it will.." "0,1"
group.long 0x20++0x13
line.long 0x0 "UA_TOR,UART Time-out Register"
hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value\nThis field is used to program the transfer delay time between the last stop bit and next start bit."
hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator\n"
line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register"
bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable\nRefer to the table below for more information.\nNote: When in IrDA mode this bit must be disabled." "0: The divider X Disabled (the equation of M = 16),1: The divider X Enabled (the equation of M = X+1.."
bitfld.long 0x4 28. "DIV_X_ONE,Divider X equal 1\nRefer to the table below for more information." "0: Divider M = 'any value' (the equation of M = X+1..,1: Divider M = 1 (the equation of M = 1 but BRD.."
newline
hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X\n"
hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider."
line.long 0x8 "UA_IRCR,UART IrDA Control Register"
bitfld.long 0x8 6. "INV_RX,INV_RX\n" "0: No inversion,1: RX input signal inversed"
bitfld.long 0x8 5. "INV_TX,INV_TX\n" "0: No inversion,1: TX output signal inversed"
newline
bitfld.long 0x8 1. "TX_SELECT,TX_SELECT\nNote: When in IrDA mode the UA_BAUD[DIV_X_EN] register must be disabled (the baud equation must be Clock / 16 * (BRD)." "0: IrDA receiver Enabled,1: IrDA transmitter Enabled"
line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register"
hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for Auto RS-485 Address Detection mode."
bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable\nThis bit is used to enable RS-485 Address Detection mode.\nNote: This field is used for any RS-485 Operation mode." "0: Address Detection mode Disabled,1: Address Detection mode Enabled"
newline
bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD)\nNote: It is able to be active in RS-485_AAD or RS-485_NMM Operation mode." "0: RS-485 Auto Direction Operation mode (AUD)..,1: RS-485 Auto Direction Operation mode (AUD) Enabled"
bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It is unable to be active with RS-485_NMM Operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
newline
bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It is unable to be active in RS-485_AAD Operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
line.long 0x10 "UA_FUN_SEL,UART Function Select Register"
bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable\n" "0,1,2,3"
tree.end
endif
tree.end
tree "WDT (Watchdog Timer)"
base ad:0x40004000
sif (cpuis("MINI5?XAE"))
group.long 0x0++0x3
line.long 0x0 "WDT_CTL,Watchdog Timer Control Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Control (Write Protect)\nWDT up counter will keep going no matter CPU is hanging by ICE or not." "0: ICE debug mode acknowledgement effects WDT..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 8.--10. "TOUTSEL,Watchdog Timer Interval Selection\nThese three bits select the time-out interval for the Watchdog Timer." "0: 24 * TWDT,1: 26 * TWDT,?,?,?,?,?,?"
newline
bitfld.long 0x0 7. "WDTEN,Watchdog Timer Enable Control (Write Protect)" "0: WDT Disabled. (This action will reset the..,1: WDT Enabled"
bitfld.long 0x0 6. "INTEN,Watchdog Timer Time-Out Interrupt Enable Control (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU." "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
newline
bitfld.long 0x0 5. "WKF,Watchdog Timer Time-Out Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it." "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if WDT.."
bitfld.long 0x0 4. "WKEN,Watchdog Timer Time-Out Wake-Up Function Control (Write Protect)\nIf this bit is set to 1 while IF is generated to 1 and INTEN enabled the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by.." "0: Wake-up trigger event Disabled if WDT time-out..,1: Wake-up trigger event Enabled if WDT time-out.."
newline
bitfld.long 0x0 3. "IF,Watchdog Timer Time-Out Interrupt Flag\nThis bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
bitfld.long 0x0 2. "RSTF,Watchdog Timer Time-Out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
newline
bitfld.long 0x0 1. "RSTEN,Watchdog Timer Time-Out Reset Enable Control (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period (1024 * TWDT) expires." "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
bitfld.long 0x0 0. "RSTCNT,Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware." "0: No effect,1: Reset the internal 18-bit WDT up counter value"
endif
sif (cpuis("MINI5??DE"))
group.long 0x0++0x3
line.long 0x0 "WTCR,Watchdog Timer Control Register"
bitfld.long 0x0 31. "DBGACK_WDT,ICE Debug Mode Acknowledge Disable Control (Write Protect)\nWDT up counter will keep going no matter CPU is hanging by ICE or not." "0: ICE debug mode acknowledgement effects WDT..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 8.--10. "WTIS,Watchdog Timer Interval Selection\nThese three bits select the time-out interval for the Watchdog Timer.\n" "0: 24 * TWDT,1: 26 * TWDT,?,?,?,?,?,?"
newline
bitfld.long 0x0 7. "WTE,Watchdog Timer Enable Control (Write Protect)\n" "0: WDT Disabled. (This action will reset the..,1: WDT Enabled"
bitfld.long 0x0 6. "WTIE,Watchdog Timer Time-out Interrupt Enable Control (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU.\n" "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
newline
bitfld.long 0x0 5. "WTWKF,Watchdog Timer Time-out Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it." "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if WDT.."
bitfld.long 0x0 4. "WTWKE,Watchdog Timer Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WTIF is generated to 1 and WTIE enabled the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up.." "0: Wake-up trigger event Disabled if WDT time-out..,1: Wake-up trigger event Enabled if WDT time-out.."
newline
bitfld.long 0x0 3. "WTIF,Watchdog Timer Time-out Interrupt Flag\nThis bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
bitfld.long 0x0 2. "WTRF,Watchdog Timer Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
newline
bitfld.long 0x0 1. "WTRE,Watchdog Timer Time-out Reset Enable Control (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period (1024 * TWDT) expires.\n" "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
bitfld.long 0x0 0. "WTR,Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware." "0: No effect,1: Reset the internal 18-bit WDT up counter value"
endif
sif (cpuis("MINI5?AN"))
group.long 0x0++0x3
line.long 0x0 "WTCR,Watchdog Timer Control Register"
bitfld.long 0x0 31. "DBGACK_WDT,ICE Debug Mode Acknowledge Disable (write-protection bit)\nThe Watchdog Timer counter will be held while ICE Debug mode is acknowledged." "0: ICE Debug mode acknowledgement affects Watchdog..,1: ICE Debug mode acknowledgement Disabled"
bitfld.long 0x0 8.--10. "WTIS,Watchdog Timer Interval Selection\n" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7. "WTE,Watchdog Timer Enable\n" "0: Watchdog Timer Disabled (this action will reset..,1: Watchdog Timer Enabled"
bitfld.long 0x0 6. "WTIE,Watchdog Timer Interrupt Enable\n" "0: Watchdog Timer interrupt Disabled,1: Watchdog Timer interrupt Enabled"
newline
bitfld.long 0x0 5. "WTWKF,Watchdog Timer Wake-up Flag\nIf Watchdog Timer causes CPU wakes up from Power-down mode this bit will be set to high. Software can write 1 to clear this bit.\n" "0: Watchdog Timer does not cause CPU wake-up,1: CPU wake-up from sleep or Power-down mode by.."
bitfld.long 0x0 4. "WTWKE,Watchdog Timer Wake-up Function Enable bit\n" "0: Watchdog Timer Wake-up CPU function Disabled,1: Wake-up function Enabled so that Watchdog Timer.."
newline
bitfld.long 0x0 3. "WTIF,Watchdog Timer Interrupt Flag\nIf the Watchdog Timer interrupt is Enabled hardware will set this bit to indicate that the Watchdog Timer interrupt has occurred.\nNote: Software can write 1 to clear this bit." "0: Watchdog Timer interrupt does not occur,1: Watchdog Timer interrupt occurs"
bitfld.long 0x0 2. "WTRF,Watchdog Timer Reset Flag\nWhen the Watchdog Timer initiates a reset the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is.." "0: Watchdog Timer reset does not occur,1: Watchdog Timer reset occurs"
newline
bitfld.long 0x0 1. "WTRE,Watchdog Timer Reset Enable\nSetting this bit will enable the Watchdog Timer Reset function.\n" "0: Watchdog Timer reset function Disabled,1: Watchdog Timer reset function Enabled"
bitfld.long 0x0 0. "WTR,Clear Watchdog Timer\nSet this bit will clear the Watchdog Timer.\nNote: This bit will be automatically cleared after a few clock cycles." "0: No effect,1: The contents of the Watchdog Timer Reset"
endif
tree.end
AUTOINDENT.OFF
Reference in New Issue View Git Blame Copy Permalink