40087 lines
2.8 MiB
40087 lines
2.8 MiB
; --------------------------------------------------------------------------------
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; @Title: MB9D560 On-Chip Peripherals
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; @Props: Released
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; @Author: LOS, DPS, MHM
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; @Changelog: 2018-01-02 MHM
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; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
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; @Doc: mb9d560_mn708-00002-e.pdf (rev. 4.00, 2015-03-06)
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; mb9d560-ds708-00001-e-from-web.pdf (rev. 3.00, 2015-05-15)
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; @Core: Cortex-R5MPCore
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; @Chip: MB9DF564MAE, MB9DF564MGE, MB9DF564MLE, MB9DF564MQE,
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; MB9DF564LAE, MB9DF564LGE, MB9DF564LLE, MB9DF564LQE,
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; MB9DF565MAE, MB9DF565MGE, MB9DF565MLE, MB9DF565MQE,
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; MB9DF565LAE, MB9DF565LGE, MB9DF565LLE, MB9DF565LQE,
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; MB9DF566MAE, MB9DF566MGE, MB9DF566MLE, MB9DF566MQE,
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; MB9DF566LAE, MB9DF566LGE, MB9DF566LLE, MB9DF566LQE,
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: permb9d560.per 9611 2018-08-31 08:39:10Z psurmacki $
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; Known problems:
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; Module Register Description
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; --------------------------------------------------------------------------------
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; CSIO SACSR difference between register diagram and register description on bits 8-9
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; R/D - module not implemented, documentation is missing
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config 16. 8.
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tree "Core Registers (Cortex-R5MPCore)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup.long c15:0x00++0x00
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line.long 0x00 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x100++0x00
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line.long 0x00 "CTR,Cache Type Register"
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bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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textline " "
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup.long c15:0x400--0x400
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line.long 0x0 "MPUIR,MPU type register"
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hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions"
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bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated"
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rgroup.long c15:0x500++0x00
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system"
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textline " "
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hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2"
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hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1"
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hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0"
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textline " "
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rgroup.long c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..."
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bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
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rgroup.long c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
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rgroup.long c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup.long c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
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bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
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rgroup.long c15:0x020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attributes Register 4"
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bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..."
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bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup.long c15:0x0520++0x00
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line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
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rgroup.long c15:0x0620++0x00
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line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
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rgroup.long c15:0x0720++0x00
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line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
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rgroup.long c15:0x010++0x00
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup.long c15:0x110++0x00
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line.long 0x00 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
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textline " "
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rgroup.long c15:0x210++0x00
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line.long 0x00 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
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rgroup.long c15:0x310++0x00
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line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long c15:0x02f++0x00
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line.long 0x00 "BO1R,Build Options 1 Register"
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hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM"
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bitfld.long 0x00 1. " FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented"
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textline " "
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bitfld.long 0x00 0. " PP_BUS_ECC ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented"
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group.long c15:0x12f++0x00
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line.long 0x00 "BO2R,Build Options 2 Register"
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bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2"
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bitfld.long 0x00 30. " LOCK_STEP ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included"
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textline " "
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bitfld.long 0x00 29. " NO_ICACHE ,Indicate whether the CPU contains instruction cache" "Yes,No"
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bitfld.long 0x00 28. " NO_DCACHE ,Indicate whether the CPU contains data cache" "Yes,No"
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textline " "
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bitfld.long 0x00 26.--27. " ATCM_ES ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection"
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bitfld.long 0x00 23.--25. " BTCM_ES ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..."
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textline " "
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bitfld.long 0x00 23. " NO_IE ,Indicate whether the processor supports big-endian instructions" "Yes,No"
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bitfld.long 0x00 22. " NO_FPU ,Indicate whether the CPU contains a floating point unit" "Yes,No"
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textline " "
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bitfld.long 0x00 20.--21. " MPU_REGIONS ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions"
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bitfld.long 0x00 17.--19. " BREAK_POINTS ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 14.--16. " WATCH_POINTS ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 13. " NO_A_TCM_INF ,Indicate whether the CPUs contain ATCM ports" "Yes,No"
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textline " "
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bitfld.long 0x00 12. " NO_B0_TCM_INF ,Indicate whether the CPUs contain B0TCM ports" "Yes,No"
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bitfld.long 0x00 11. " NO_B1_TCM_INF ,Indicate whether the CPUs contain B1TCM ports" "Yes,No"
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textline " "
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bitfld.long 0x00 10. " TCMBUSPARITY ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes"
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bitfld.long 0x00 9. " NO_SLAVE ,Indicate whether the CPU contains an AXI slave port" "Yes,No"
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textline " "
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bitfld.long 0x00 7.--8. " ICACHE_ES ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC"
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bitfld.long 0x00 5.--6. " DCACHE_ES ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..."
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textline " "
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bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No"
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bitfld.long 0x00 3. " AXI_BUS_ECC ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes"
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textline " "
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bitfld.long 0x00 2. " SL ,Indicate whether the processor has been built with split/lock logic" "No,Yes"
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bitfld.long 0x00 1. " AHB_PP ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes"
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textline " "
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bitfld.long 0x00 0. " MICRO_SCU ,Indicate whether the processor contain an ACP interface" "No,Yes"
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group.long c15:0x72f++0x00
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line.long 0x00 "POR,Pin Options Register"
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bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High"
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bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High"
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textline " "
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bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High"
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bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High"
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textline " "
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bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High"
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group.long c15:0x01++0x00
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line.long 0x00 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
|
|
bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x101++0x00
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Enable,Disable"
|
|
bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Enable,Disable"
|
|
bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable"
|
|
bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable"
|
|
bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable"
|
|
bitfld.long 0x00 13. " DLFO ,Disable linefill optimization in the AXI master" "Enable,Disable"
|
|
bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DNCH ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable"
|
|
bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
|
|
bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
|
|
bitfld.long 0x00 7. " SMOV ,sMOV disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable"
|
|
bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "Disable,Enable"
|
|
bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x0f++0x00
|
|
line.long 0x00 "SACTLR,Secondary Auxiliary Control Register"
|
|
bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable"
|
|
bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable"
|
|
bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable"
|
|
bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable"
|
|
bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable"
|
|
bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x201++0x00
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
group.long c15:0x000b++0x00
|
|
line.long 0x00 "SPCR,Slave Port Control Register"
|
|
bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only"
|
|
bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled"
|
|
tree.end
|
|
width 0x8
|
|
tree "MPU Control and Configuration"
|
|
group.long c15:0x01++0x00
|
|
line.long 0x00 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
|
|
bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x05++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x15++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable"
|
|
bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register"
|
|
group.long c15:0x06++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
textline " "
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x115++0x00
|
|
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
|
|
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable"
|
|
bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register"
|
|
group.long c15:0x206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
textline " "
|
|
group.long c15:0x0016++0x00
|
|
line.long 0x00 "RBAR,Region Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group.long c15:0x0216++0x00
|
|
line.long 0x00 "RSER,Region Size and Enable Register"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group.long c15:0x0416++0x00
|
|
line.long 0x00 "RACR,Region Access Control Register"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
group.long c15:0x0026++0x00
|
|
line.long 0x00 "MRNR,Memory Region Number Register"
|
|
bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group.long c15:0x010d++0x00
|
|
line.long 0x00 "CIDR,Context ID Register"
|
|
group.long c15:0x20d++0x00
|
|
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
|
|
group.long c15:0x30d++0x00
|
|
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
|
|
group.long c15:0x40d++0x00
|
|
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
|
|
width 0x08
|
|
tree "MPU regions"
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RBAR0,Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RSER0,Region Size and Enable Register 0"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RACR0,Region Access Control Register 0"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RBAR1,Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RSER1,Region Size and Enable Register 1"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RACR1,Region Access Control Register 1"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RBAR2,Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RSER2,Region Size and Enable Register 2"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RACR2,Region Access Control Register 2"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RBAR3,Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RSER3,Region Size and Enable Register 3"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RACR3,Region Access Control Register 3"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RBAR4,Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RSER4,Region Size and Enable Register 4"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RACR4,Region Access Control Register 4"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RBAR5,Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RSER5,Region Size and Enable Register 5"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RACR5,Region Access Control Register 5"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RBAR6,Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RSER6,Region Size and Enable Register 6"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RACR6,Region Access Control Register 6"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RBAR7,Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RSER7,Region Size and Enable Register 7"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RACR7,Region Access Control Register 7"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RBAR8,Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RSER8,Region Size and Enable Register 8"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RACR8,Region Access Control Register 8"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RBAR9,Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RSER9,Region Size and Enable Register 9"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RACR9,Region Access Control Register 9"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RBAR10,Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RSER10,Region Size and Enable Register 10"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RACR10,Region Access Control Register 10"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RBAR11,Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RSER11,Region Size and Enable Register 11"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RACR11,Region Access Control Register 11"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RBAR12,Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RSER12,Region Size and Enable Register 12"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RACR12,Region Access Control Register 12"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RBAR13,Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RSER13,Region Size and Enable Register 13"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RACR13,Region Access Control Register 13"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RBAR14,Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RSER14,Region Size and Enable Register 14"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RACR14,Region Access Control Register 14"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RBAR15,Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RSER15,Region Size and Enable Register 15"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RACR15,Region Access Control Register 15"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
tree.end
|
|
tree.end
|
|
width 0x9
|
|
tree "TCM Control and Configuration"
|
|
rgroup.long c15:0x200++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x019++0x00
|
|
line.long 0x00 "BTCMRR,BTCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
group.long c15:0x119++0x00
|
|
line.long 0x00 "ATCMRR,ATCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
rgroup.long c15:0x29++0x00
|
|
line.long 0x00 "TCMSEL,TCM Selection Register"
|
|
textline " "
|
|
group.long c15:0x10f++0x00
|
|
line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled"
|
|
group.long c15:0x20f++0x00
|
|
line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled"
|
|
group.long c15:0x30f++0x00
|
|
line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100++0x00
|
|
line.long 0x00 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
|
|
rgroup.long c15:0x1700++0x00
|
|
line.long 0x00 "AIDR,Auxiliary ID Register"
|
|
rgroup.long c15:0x1000++0x00
|
|
line.long 0x00 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x2000++0x00
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction"
|
|
group.long c15:0x03f++0x00
|
|
line.long 0x00 "CFLR,Correctable Fault Location Register"
|
|
bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
|
|
group.long c15:0x5f++0x00
|
|
line.long 0x00 "IADCR,Invalidate All Data Cache Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
group.long c15:0xef++0x00
|
|
line.long 0x00 "CSOR,Cache Size Override Register"
|
|
bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
|
|
bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group.long c15:0xc9++0x00
|
|
line.long 0x00 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable PMCCNTR when prohibited" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Enable" "Disabled,Enabled"
|
|
group.long c15:0x1c9++0x00
|
|
line.long 0x00 "PMCNTENSET,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group.long c15:0x2c9++0x00
|
|
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group.long c15:0x3c9++0x00
|
|
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group.long c15:0x4c9++0x00
|
|
line.long 0x0 "PMSWINC,Software Increment Register"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group.long c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Type Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected"
|
|
group.long c15:0x02d9++0x00
|
|
line.long 0x00 "PMXEVCNTR,Event Count Register"
|
|
group.long c15:0x5c9++0x00
|
|
line.long 0x00 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..."
|
|
group.long c15:0xd9++0x00
|
|
line.long 0x00 "PMCCNTR,Cycle Count Register"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "ESR0,Event Selection Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "ESR1,Event Selection Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "ESR2,Event Selection Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0xe9++0x00
|
|
line.long 0x00 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed"
|
|
group.long c15:0x1e9++0x00
|
|
line.long 0x00 "PMINTENSET,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
group.long c15:0x2e9++0x00
|
|
line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
tree "Validation Registers"
|
|
group.long c15:0x01f++0x00
|
|
line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
|
|
group.long c15:0x11f++0x00
|
|
line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
|
|
group.long c15:0x21f++0x00
|
|
line.long 0x00 "RESR,nVAL Reset Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
|
|
group.long c15:0x31f++0x00
|
|
line.long 0x00 "RESR,VAL Debug Request Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
|
|
group.long c15:0x41f++0x00
|
|
line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
|
|
group.long c15:0x51f++0x00
|
|
line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
|
|
group.long c15:0x61f++0x00
|
|
line.long 0x00 "RECR,nVAL Reset Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
|
|
group.long c15:0x71f++0x00
|
|
line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
|
|
tree.end
|
|
tree.end
|
|
width 11.
|
|
width 18.
|
|
tree "Debug Registers"
|
|
tree "Processor Identifier Registers"
|
|
rgroup.long c14:832.++0x00
|
|
line.long 0x00 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup.long c14:833.++0x00
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup.long c14:834.++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
group.long c14:835.++0x00
|
|
line.long 0x00 "AMIDR,Alias of MIDR"
|
|
rgroup.long c14:836.++0x00
|
|
line.long 0x00 "MPUTR,MPU Type Register"
|
|
rgroup.long c14:837.++0x00
|
|
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
|
|
group.long c14:838.++0x00
|
|
line.long 0x00 "AMIDR0,Alias of MIDR"
|
|
group.long c14:839.++0x00
|
|
line.long 0x00 "AMIDR1,Alias of MIDR"
|
|
rgroup.long c14:840.++0x00
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:841.++0x00
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:842.++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup.long c14:843.++0x00
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long c14:844.++0x00
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup.long c14:845.++0x00
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup.long c14:846.++0x00
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup.long c14:847.++0x00
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:848.++0x00
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:849.++0x00
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:850.++0x00
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:851.++0x00
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:852.++0x00
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup.long c14:853.++0x00
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
|
width 15.
|
|
tree "Coresight Management Registers"
|
|
group.long c14:960.++0x00
|
|
line.long 0x00 "DBGITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration"
|
|
group.long c14:1000.++0x00
|
|
line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set"
|
|
group.long c14:1001.++0x00
|
|
line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear"
|
|
wgroup.long c14:1004.++0x00
|
|
line.long 0x00 "DBGLAR,Lock Access Register"
|
|
rgroup.long c14:1005.++0x00
|
|
line.long 0x00 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " 32BA ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked"
|
|
rgroup.long c14:1006.++0x00
|
|
line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "Disabled,Enabled"
|
|
rgroup.long c14:1011.++0x00
|
|
line.long 0x00 "DBGDEVTYPE,Device Type Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class"
|
|
tree.end
|
|
textline " "
|
|
width 12.
|
|
rgroup.long c14:0.++0x0
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version"
|
|
textline " "
|
|
bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High"
|
|
bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High"
|
|
bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number"
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
group.long c14:0x7++0x0
|
|
line.long 0x00 "DBGVCR,Debug Vector Catch register"
|
|
bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "Disabled,Enabled"
|
|
hgroup.long c14:32.++0x0
|
|
hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register"
|
|
in
|
|
group.long c14:35.++0x00
|
|
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data"
|
|
group.long c14:10.++0x0
|
|
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Write through disable" "No,Yes"
|
|
bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NDL ,L1 data cache line-fills disable" "No,Yes"
|
|
wgroup.long c14:33.++0x0
|
|
line.long 0x00 "DBGITR,Instruction Transfer Register"
|
|
wgroup.long c14:36.++0x0
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt"
|
|
textline " "
|
|
rgroup.long c14:193.++0x0
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented"
|
|
group.long c14:196.++0x0
|
|
line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate"
|
|
rgroup.long c14:197.++0x0
|
|
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
|
|
bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset"
|
|
bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset"
|
|
bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up"
|
|
tree.end
|
|
width 7.
|
|
tree "Breakpoint Registers"
|
|
group.long c14:64.++0x0
|
|
line.long 0x00 "BVR0,Breakpoint Value 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
|
|
group.long c14:80.++0x0
|
|
line.long 0x00 "BCR0,Breakpoint Control 0 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:65.++0x0
|
|
line.long 0x00 "BVR1,Breakpoint Value 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
|
|
group.long c14:81.++0x0
|
|
line.long 0x00 "BCR1,Breakpoint Control 1 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:66.++0x0
|
|
line.long 0x00 "BVR2,Breakpoint Value 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
|
|
group.long c14:82.++0x0
|
|
line.long 0x00 "BCR2,Breakpoint Control 2 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:67.++0x0
|
|
line.long 0x00 "BVR3,Breakpoint Value 3 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
|
|
group.long c14:83.++0x0
|
|
line.long 0x00 "BCR3,Breakpoint Control 3 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:68.++0x0
|
|
line.long 0x00 "BVR4,Breakpoint Value 4 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
|
|
group.long c14:84.++0x0
|
|
line.long 0x00 "BCR4,Breakpoint Control 4 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:69.++0x0
|
|
line.long 0x00 "BVR5,Breakpoint Value 5 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
|
|
group.long c14:85.++0x0
|
|
line.long 0x00 "BCR5,Breakpoint Control 5 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:70.++0x0
|
|
line.long 0x00 "BVR6,Breakpoint Value 6 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
|
|
group.long c14:86.++0x0
|
|
line.long 0x00 "BCR6,Breakpoint Control 6 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:71.++0x0
|
|
line.long 0x00 "BVR7,Breakpoint Value 7 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
|
|
group.long c14:87.++0x0
|
|
line.long 0x00 "BCR7,Breakpoint Control 7 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Watchpoint Control Registers"
|
|
group.long c14:96.++0x0
|
|
line.long 0x00 "WVR0,Watchpoint Value 0 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:112.++0x0
|
|
line.long 0x00 "WCR0,Watchpoint Control 0 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:97.++0x0
|
|
line.long 0x00 "WVR1,Watchpoint Value 1 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:113.++0x0
|
|
line.long 0x00 "WCR1,Watchpoint Control 1 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:98.++0x0
|
|
line.long 0x00 "WVR2,Watchpoint Value 2 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:114.++0x0
|
|
line.long 0x00 "WCR2,Watchpoint Control 2 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:99.++0x0
|
|
line.long 0x00 "WVR3,Watchpoint Value 3 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:115.++0x0
|
|
line.long 0x00 "WCR3,Watchpoint Control 3 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:100.++0x0
|
|
line.long 0x00 "WVR4,Watchpoint Value 4 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:116.++0x0
|
|
line.long 0x00 "WCR4,Watchpoint Control 4 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:101.++0x0
|
|
line.long 0x00 "WVR5,Watchpoint Value 5 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:117.++0x0
|
|
line.long 0x00 "WCR5,Watchpoint Control 5 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:102.++0x0
|
|
line.long 0x00 "WVR6,Watchpoint Value 6 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:118.++0x0
|
|
line.long 0x00 "WCR6,Watchpoint Control 6 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:103.++0x0
|
|
line.long 0x00 "WVR7,Watchpoint Value 7 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:119.++0x0
|
|
line.long 0x00 "WCR7,Watchpoint Control 7 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:6.++0x0
|
|
line.long 0x00 "WFAR ,Watchpoint Fault Address Register"
|
|
hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
width 11.
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "MODEC (Operation Mode)"
|
|
base ad:0xB0600800
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "MODEC_MODER,Mode Register"
|
|
bitfld.long 0x00 31. " USERMODE ,User mode bit" ",User mode"
|
|
bitfld.long 0x00 30. " BOARDMODE ,Board mode bit" "Not board,Board"
|
|
bitfld.long 0x00 13. " MD1 ,Mode 1 bit" "0,1"
|
|
bitfld.long 0x00 12. " MD0 ,Mode 0 bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CPUMD ,CPU operation mode" "2CPU Mode,,,,1CPU0 Mode,1CPU1 Mode,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "Reset (Reset)"
|
|
base ad:0xB0600380
|
|
width 22.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SYSC_RSTCNTR0,Reset Control Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DBGR0 ,Software debugger reset register bits of CPU0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SWHRST0 ,Software trigger hardware reset register bits of CPU0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SWRST0 ,Software reset register bits of CPU0"
|
|
line.long 0x04 "SYSC_RSTCNTR1,Reset Control Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DBGR1 ,Software debugger reset register bits of CPU1"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SWHRST1 ,Software trigger hardware reset register bits of CPU1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SWRST1 ,Software reset register bits of CPU1"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "SYSC_RSTCAUSEUR,User Reset Factor Register"
|
|
bitfld.long 0x00 26. " CSVPR ,Clock supervisor reset (PLL clock) detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " CSVMOR ,Clock supervisor reset (main clock) detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 21. " SHRST1 ,Software trigger hardware reset detection bit of CPU1" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " SHRST0 ,Software trigger hardware reset detection bit of CPU0" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SRST1 ,Software reset detection bit of CPU1" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " SRST0 ,Software reset detection bit of CPU0" "Not detected,Detected"
|
|
bitfld.long 0x00 13. " SWDR1 ,Software watchdog reset detection bit of CPU1" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " SWDR0 ,Software watchdog reset detection bit of CPU0" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " HWDR ,Hardware watchdog reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " PRFERR ,Profile error reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " SRSTX ,nSRST pin reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " LVD50R ,External power supply (5.0V) low-voltage detection reset detection bit" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RSTX ,RSTX pin input reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " CKTOR ,Clock stop wait timeout reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " INITX ,INITX pin input reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " LVD12R ,Internal power supply low-voltage detection reset detection bit" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PONR ,Power-on reset detection bit" "Not detected,Detected"
|
|
line.long 0x04 "SYSC_EXCSVRSTCAUSEUR,User Extended CSV Reset Factor Register"
|
|
bitfld.long 0x04 0. " CSVSSR[0] ,Detection bit of PLL for FlexRay/RDC clock supervisor reset" "Not detected,Detected"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "SYSC_RSTCAUSEBT,BootROM Reset Factor Register"
|
|
bitfld.long 0x00 26. " CSVPR ,Clock supervisor reset (PLL clock) detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " CSVMOR ,Clock supervisor reset (main clock) detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 21. " SHRST1 ,Software trigger hardware reset detection bit of CPU1" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " SHRST0 ,Software trigger hardware reset detection bit of CPU0" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SRST1 ,Software reset detection bit of CPU1" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " SRST0 ,Software reset detection bit of CPU0" "Not detected,Detected"
|
|
bitfld.long 0x00 13. " SWDR1 ,Software watchdog reset detection bit of CPU1" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " SWDR0 ,Software watchdog reset detection bit of CPU0" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " HWDR ,Hardware watchdog reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " PRFERR ,Profile error reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " SRSTX ,nSRST pin reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " LVD50R ,External power supply (5.0V) low-voltage detection reset detection bit" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RSTX ,RSTX pin input reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " CKTOR ,Clock stop wait timeout reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " INITX ,INITX pin input reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " LVD12R ,Internal power supply low-voltage detection reset detection bit" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PONR ,Power-on reset detection bit" "Not detected,Detected"
|
|
line.long 0x04 "SYSC_EXCSVRSTCAUSEBT,BootROM Extended CSV Reset Factor Register"
|
|
bitfld.long 0x04 0. " CSVSSR[0] ,Detection bit of PLL for FlexRay/RDC clock supervisor reset" "Not detected,Detected"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SYSC_WRBOOTCPUSEL,Watchdog Reset Boot CPU Selection Register"
|
|
bitfld.long 0x00 22. " CPUBS ,CPU activation selection bit" "CPU0,CPU1"
|
|
bitfld.long 0x00 17. " HWRCLR ,Hardware watchdog reset counter clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 16. " SWRCLR ,Software watchdog reset counter clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 12.--15. " HWRCC ,Hardware watchdog reset count compare bits" "No compare,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " HWRCS ,Hardware watchdog reset count display bits" "No occurrence,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " SWRCC ,Software watchdog 0 reset count compare bits" "No compare,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " SWRCS ,Software watchdog 0 reset count display bits" "No occurrence,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Clock (Clock System)"
|
|
base ad:0xB0600600
|
|
width 16.
|
|
group.long 0x00++0x07 "Common Configuration Registers"
|
|
line.long 0x00 "SYSC_CRCNTR,Fast-CR Clock Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CRTRM ,Fast-CR oscillation trimming bits"
|
|
line.long 0x04 "SYSC_MOSCCNTR,Main Oscillator Control Register"
|
|
bitfld.long 0x04 8. " DIV2SEL ,Main clock 2 division select bit" "Not divided,/2"
|
|
if (((per.l(ad:0xB0600000+0x84))&0x010)==0x010)||(((per.l(ad:0xB0600000+0x104))&0x010)==0x010)||(((per.l(ad:0xB0600000+0x184))&0x010)==0x010)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SYSC_PLLSTCNTR,PLL Stabilization Time Control Register"
|
|
bitfld.long 0x00 3. " PLLSTABS[3] ,PLL stabilization wait time selection bits" "0,1"
|
|
bitfld.long 0x00 0.--2. " PLLSTABS[2:0] ,PLL stabilization wait time selection bits" "512,1024,2048,4096,8192,16384,32768,65536"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SYSC_PLLCGCNTR,PLL Clock Gear Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLLCGLP ,PLL clock gear loop count setting bits"
|
|
rbitfld.long 0x00 14.--15. " PLLCGSTP ,PLL clock gear step width setting bits" "1,2,3,4"
|
|
rbitfld.long 0x00 8.--13. " PLLCGSSN ,PLL clock gear start step setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status flag bits" "Stopped in the low-speed,Gear up,Stopped in the high-speed,Gear down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLCGSTR ,PLL clock gear operation start bit" "No effect,Start"
|
|
rbitfld.long 0x00 0. " PLLCGEN ,PLL clock gear operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SYSC_PLLSTCNTR,PLL Stabilization Time Control Register"
|
|
rbitfld.long 0x00 3. " PLLSTABS[3] ,PLL stabilization wait time selection bits" "0,1"
|
|
bitfld.long 0x00 0.--2. " PLLSTABS[2:0] ,PLL stabilization wait time selection bits" "512,1024,2048,4096,8192,16384,32768,65536"
|
|
line.long 0x04 "SYSC_PLLCGCNTR,PLL Clock Gear Control Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PLLCGLP ,PLL clock gear loop count setting bits"
|
|
bitfld.long 0x04 14.--15. " PLLCGSTP ,PLL clock gear step width setting bits" "1,2,3,4"
|
|
bitfld.long 0x04 8.--13. " PLLCGSSN ,PLL clock gear start step setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 6.--7. " PLLCGSTS ,PLL clock gear status flag bits" "Stopped in the low-speed,Gear up,Stopped in the high-speed,Gear down"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PLLCGSTR ,PLL clock gear operation start bit" "No effect,Start"
|
|
bitfld.long 0x04 0. " PLLCGEN ,PLL clock gear operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x020++0x03 "Clock Output Function Register"
|
|
line.long 0x00 "SYSC_CKOTCNTR,Clock Output Function Control Register"
|
|
bitfld.long 0x00 24. " ENCLKO ,Output enable bit of an external output clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " CKOUTDIV ,Division setting bits of an external output clock" "None,2,4,8,16,32,64,128"
|
|
bitfld.long 0x00 0.--2. " CKSEL ,External output clock select bits" "Fast-CR,Slow-CR,Main/Main clock /2,Fixed at L,PLL,Fixed at L,Fixed at L,Fixed at L"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LPC (Low-power Consumption)"
|
|
base ad:0xB0600000
|
|
width 18.
|
|
group.long 0x00++0x03 "Protection Register Group"
|
|
line.long 0x00 "SYSC_PROTKEYR,Protection Key Setting Register"
|
|
group.long 0x84++0x07 "Run Profile Register Group"
|
|
line.long 0x00 "SYSC_RUNCKSRER,RUN Clock Source Enable Register"
|
|
bitfld.long 0x00 4. " PLLEN ,PLL clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " SCROSCEN ,Slow-CR clock oscillation enable bit" ",Enabled"
|
|
rbitfld.long 0x00 0. " CROSCEN ,Fast-CR clock oscillation enable bit" ",Enabled"
|
|
line.long 0x04 "SYSC_RUNCKSELR0,RUN Clock Selection Register 0"
|
|
bitfld.long 0x04 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "Fast-CR,Slow-CR,Main/Main /2,Fixed at L,PLL clock,Fixed at L,Fixed at L,Fixed at L"
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "SYSC_RUNCKER,RUN Clock Enable Register"
|
|
rbitfld.long 0x00 31. " ENCLKTRC ,TRC internal clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENCLKPERI7 ,PERI7 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ENCLKPERI6 ,PERI6 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENCLKPERI5 ,PERI5 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " ENCLKPERI4 ,PERI4 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENCLKPERI1 ,PERI1 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENCLKPERI0 ,PERI0 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " ENCLKSYSCPD1 ,SYSCPD1 internal operation clock oscillation enable bit" ",Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENCLKEXTBUS ,EXTBUS internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENCLKMEMC ,MEMC internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENCLKDMA ,DMA internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " ENCLKHPMPD2 ,HPMPD2 internal operation clock oscillation enable bit" ",Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENCLKATB ,ATB internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENCLKDBG ,DBG internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " ENCLKCPU1 ,CPU1 internal operation clock oscillation enable bit" ",Enabled"
|
|
rbitfld.long 0x00 0. " ENCLKCPU0 ,CPU0 internal operation clock oscillation enable bit" ",Enabled"
|
|
line.long 0x04 "SYSC_RUNCKDIVR0,RUN Clock Divider Register 0"
|
|
bitfld.long 0x04 28.--29. " HPMDIV ,HPM clock divider setting bits" "None,/2,/4,/8"
|
|
bitfld.long 0x04 24.--25. " TRCDIV ,TRC clock divider setting bits" "None,/2,/4,/8"
|
|
rbitfld.long 0x04 20.--21. " ATBDIV ,ATB clock divider setting bits" "None,/2,/4,/8"
|
|
rbitfld.long 0x04 16.--17. " DBGDIV ,DBG clock divider setting bits" ",/2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,18,/19/,20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x08 "SYSC_RUNCKDIVR1,RUN Clock Divider Register 1"
|
|
bitfld.long 0x08 24.--27. " SYSCPD1DIV ,SYSC_PD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 12.--14. " EXTBUSDIV ,EXTBUS clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x0C "SYSC_RUNCKDIVR2,RUN Clock Divider Register 2"
|
|
bitfld.long 0x0C 20.--23. " PERI7DIV ,PERI7 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 16.--19. " PERI6DIV ,PERI6 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 12.--15. " PERI5DIV ,PERI5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 8.--11. " PERI4DIV ,PERI4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--7. " PERI1DIV ,PERI1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 0.--3. " PERI0DIV ,PERI0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "SYSC_RUNPLLCNTR,RUN PLL Control Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " PLLDIVN ,PLL clock N-multiplier setting bits"
|
|
bitfld.long 0x00 8.--11. " PLLDIVM ,PLL clock M-divider setting bits" ",/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30"
|
|
bitfld.long 0x00 0.--1. " PLLDIVL ,PLL input clock divider setting bits" "No division,/2,/4,/6"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "SYSC_RUNLVDCFGR,RUN Low-voltage Detection Configuration Register"
|
|
rbitfld.long 0x00 17.--19. " SV12 ,1.2V reference voltage setting bits" ",,,,0.9V,?..."
|
|
rbitfld.long 0x00 16. " LVDE12 ,1.2V low-voltage detection operation enable bit" ",Enabled"
|
|
bitfld.long 0x00 6. " LVDS50 ,Low-voltage detection (5.0V) operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 1.--3. " SV50 ,5.0V reference voltage setting" ",,,,,3.9V,4.1V,4.3V"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LVDE50 ,5.0V low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "SYSC_RUNCSVCFGR,RUN Clock Supervisor Configuration Register"
|
|
bitfld.long 0x00 2. " PLLCSVE ,PLL clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "SYSC_TRGRUNCNTR,RUN Profile Update Trigger Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " APPLY_RUN ,RUN profile update trigger setting bits"
|
|
group.long 0x104++0x07 "PSS Profile Register Group"
|
|
line.long 0x00 "SYSC_PSSCKSRER,PSS Clock Source Enable Register"
|
|
bitfld.long 0x00 4. " PLLEN ,PLL clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SCROSCEN ,Slow-CR clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CROSCEN ,Fast-CR clock oscillation enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SYSC_PSSCKSELR0,PSS Clock Selection Register 0"
|
|
bitfld.long 0x04 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "Fast-CR,Slow-CR,Main/Main /2,Fixed at L,PLL clock,Fixed at L,Fixed at L,Fixed at L"
|
|
group.long 0x110++0x0F
|
|
line.long 0x00 "SYSC_PSSCKER,PSS Clock Enable Register"
|
|
rbitfld.long 0x00 31. " ENCLKTRC ,TRC internal clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENCLKPERI7 ,PERI7 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ENCLKPERI6 ,PERI6 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENCLKPERI5 ,PERI5 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " ENCLKPERI4 ,PERI4 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENCLKPERI1 ,PERI1 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENCLKPERI0 ,PERI0 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENCLKSYSCPD1 ,SYSCPD1 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENCLKEXTBUS ,EXTBUS internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENCLKMEMC ,MEMC internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENCLKDMA ,DMA internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENCLKHPMPD2 ,HPMPD2 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENCLKATB ,ATB internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENCLKDBG ,DBG internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " ENCLKCPU1 ,CPU1 internal operation clock oscillation enable bit" "Disabled,"
|
|
rbitfld.long 0x00 0. " ENCLKCPU0 ,CPU0 internal operation clock oscillation enable bit" "Disabled,"
|
|
line.long 0x04 "SYSC_PSSCKDIVR0,PSS Clock Divider Register 0"
|
|
bitfld.long 0x04 28.--29. " HPMDIV ,HPM clock divider setting bits" "No division,/2,/4,/8"
|
|
bitfld.long 0x04 24.--25. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/4,/8"
|
|
rbitfld.long 0x04 20.--21. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8"
|
|
rbitfld.long 0x04 16.--17. " DBGDIV ,DBG clock divider setting bits" ",/2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,18,/19/,20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x08 "SYSC_PSSCKDIVR1,PSS Clock Divider Register 1"
|
|
bitfld.long 0x08 24.--27. " SYSCPD1DIV ,SYSC_PD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 12.--14. " EXTBUSDIV ,EXTBUS clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x0C "SYSC_PSSCKDIVR2,PSS Clock Divider Register 2"
|
|
bitfld.long 0x0C 20.--23. " PERI7DIV ,PERI7 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 16.--19. " PERI6DIV ,PERI6 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 12.--15. " PERI5DIV ,PERI5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 8.--11. " PERI4DIV ,PERI4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--7. " PERI1DIV ,PERI1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 0.--3. " PERI0DIV ,PERI0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SYSC_PSSPLLCNTR,PSS PLL Control Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " PLLDIVN ,PLL clock N-multiplier setting bits"
|
|
bitfld.long 0x00 8.--11. " PLLDIVM ,PLL clock M-divider setting bits" ",/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30"
|
|
bitfld.long 0x00 0.--1. " PLLDIVL ,PLL input clock divider setting bits" "No division,/2,/4,/6"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "SYSC_PSSLVDCFGR,PSS Low-voltage Detection Configuration Register"
|
|
rbitfld.long 0x00 17.--19. " SV12 ,1.2V reference voltage setting bits" ",,,,0.9V,?..."
|
|
rbitfld.long 0x00 16. " LVDE12 ,1.2V low-voltage detection operation enable bit" ",Enabled"
|
|
bitfld.long 0x00 6. " LVDS50 ,Low-voltage detection (5.0V) operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 1.--3. " SV50 ,5.0V reference voltage setting" ",,,,,3.9V,4.1V,4.3V"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LVDE50 ,5.0V low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "SYSC_PSSCSVCFGR,PSS Clock Supervisor Configuration Register"
|
|
bitfld.long 0x00 2. " PLLCSVE ,PLL clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "SYSC_PSSENR,PSS Profile Update Enable Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PSSEN1 ,PSS profile (sub status control 1) update enable setting bits"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSSEN0 ,PSS profile (main status control) update enable setting bits"
|
|
rgroup.long 0x184++0x07 "APPLIED Profile Register Group"
|
|
line.long 0x00 "SYSC_APPCKSRER,APPLIED Clock Source Enable Register"
|
|
bitfld.long 0x00 4. " PLLEN ,PLL clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SCROSCEN ,Slow-CR clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CROSCEN ,Fast-CR clock oscillation enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SYSC_APPCKSELR0,APPLIED Clock Selection Register 0"
|
|
bitfld.long 0x04 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "Fast-CR,Slow-CR,Main/Main /2,Fixed at L,PLL clock,Fixed at L,Fixed at L,Fixed at L"
|
|
rgroup.long 0x190++0x0F
|
|
line.long 0x00 "SYSC_APPCKER,APPLIED Clock Enable Register"
|
|
bitfld.long 0x00 31. " ENCLKTRC ,TRC internal clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENCLKPERI7 ,PERI7 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ENCLKPERI6 ,PERI6 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENCLKPERI5 ,PERI5 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " ENCLKPERI4 ,PERI4 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENCLKPERI1 ,PERI1 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENCLKPERI0 ,PERI0 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENCLKSYSCPD1 ,SYSCPD1 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENCLKEXTBUS ,EXTBUS internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENCLKMEMC ,MEMC internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENCLKDMA ,DMA internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENCLKHPMPD2 ,HPMPD2 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENCLKATB ,ATB internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENCLKDBG ,DBG internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENCLKCPU1 ,CPU1 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCLKCPU0 ,CPU0 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SYSC_APPCKDIVR0,APPLIED Clock Divider Register 0"
|
|
bitfld.long 0x04 28.--29. " HPMDIV ,HPM clock divider setting bits" "No division,/2,/4,/8"
|
|
bitfld.long 0x04 24.--25. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/4,/8"
|
|
bitfld.long 0x04 20.--21. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8"
|
|
bitfld.long 0x04 16.--17. " DBGDIV ,DBG clock divider setting bits" ",/2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,18,/19/,20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x08 "SYSC_APPCKDIVR1,APPLIED Clock Divider Register 1"
|
|
bitfld.long 0x08 24.--27. " SYSCPD1DIV ,SYSC_PD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 12.--14. " EXTBUSDIV ,EXTBUS clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x0C "SYSC_APPCKDIVR2,APPLIED Clock Divider Register 2"
|
|
bitfld.long 0x0C 20.--23. " PERI7DIV ,PERI7 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 16.--19. " PERI6DIV ,PERI6 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 12.--15. " PERI5DIV ,PERI5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 8.--11. " PERI4DIV ,PERI4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--7. " PERI1DIV ,PERI1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 0.--3. " PERI0DIV ,PERI0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "SYSC_APPPLLCNTR,APPLIED PLL Control Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " PLLDIVN ,PLL clock N-multiplier setting bits"
|
|
bitfld.long 0x00 8.--11. " PLLDIVM ,PLL clock M-divider setting bits" ",/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30"
|
|
bitfld.long 0x00 0.--1. " PLLDIVL ,PLL input clock divider setting bits" "No division,/2,/4,/6"
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "SYSC_APPLVDCFGR,APPLIED Low-voltage Detection Configuration Register"
|
|
bitfld.long 0x00 17.--19. " SV12 ,1.2V reference voltage setting bits" ",,,,0.9V,?..."
|
|
bitfld.long 0x00 16. " LVDE12 ,1.2V low-voltage detection operation enable bit" ",Enabled"
|
|
bitfld.long 0x00 6. " LVDS50 ,Low-voltage detection (5.0V) operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 1.--3. " SV50 ,5.0V reference voltage setting" ",,,,,3.9V,4.1V,4.3V"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LVDE50 ,5.0V low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "SYSC_APPCSVCFGR,APPLIED Clock Supervisor Configuration Register"
|
|
bitfld.long 0x00 2. " PLLCSVE ,PLL clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x204++0x07 "Status Profile Register Group"
|
|
line.long 0x00 "SYSC_STSCKSRER,Status Clock Source Enable Register"
|
|
bitfld.long 0x00 20. " PLLRDY ,PLL clock oscillation stabilization bit" "Wait state,RDY state"
|
|
bitfld.long 0x00 18. " MOSCRDY ,Main clock oscillation stabilization bit" "Wait state,RDY state"
|
|
bitfld.long 0x00 17. " SCROSCRDY ,Slow-CR clock oscillation stabilization bit" "Wait state,RDY state"
|
|
bitfld.long 0x00 16. " CROSCRDY ,Fast-CR clock oscillation stabilization bit" "Wait state,RDY state"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PLLEN ,PLL clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SCROSCEN ,Slow-CR clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CROSCEN ,Fast-CR clock oscillation enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SYSC_STSCKSELR0,Status Clock Selection Register 0"
|
|
bitfld.long 0x04 4.--6. " CD0CM ,Clock domain 0 clock selection monitoring bits" "Fast-CR,Slow-CR,Main,Fixed at L,PLL clock,Fixed at L,Fixed at L,Fixed at L"
|
|
bitfld.long 0x04 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "Fast-CR,Slow-CR,Main,Fixed at L,PLL clock,Fixed at L,Fixed at L,Fixed at L"
|
|
rgroup.long 0x210++0x0F
|
|
line.long 0x00 "SYSC_STSCKER,Status Clock Enable Register"
|
|
bitfld.long 0x00 31. " ENCLKTRC ,TRC internal clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENCLKPERI7 ,PERI7 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ENCLKPERI6 ,PERI6 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENCLKPERI5 ,PERI5 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " ENCLKPERI4 ,PERI4 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENCLKPERI1 ,PERI1 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENCLKPERI0 ,PERI0 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENCLKSYSCPD1 ,SYSCPD1 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENCLKEXTBUS ,EXTBUS internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENCLKMEMC ,MEMC internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENCLKDMA ,DMA internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENCLKHPMPD2 ,HPMPD2 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENCLKATB ,ATB internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENCLKDBG ,DBG internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENCLKCPU1 ,CPU1 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCLKCPU0 ,CPU0 internal operation clock oscillation enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SYSC_STSCKDIVR0,Status Clock Divider Register 0"
|
|
bitfld.long 0x04 28.--29. " HPMDIV ,HPM clock divider setting bits" "No division,/2,/4,/8"
|
|
bitfld.long 0x04 24.--25. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/4,/8"
|
|
bitfld.long 0x04 20.--21. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8"
|
|
bitfld.long 0x04 16.--17. " DBGDIV ,DBG clock divider setting bits" ",/2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,18,/19/,20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x08 "SYSC_STSCKDIVR1,Status Clock Divider Register 1"
|
|
bitfld.long 0x08 24.--27. " SYSCPD1DIV ,SYSC_PD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 12.--14. " EXTBUSDIV ,EXTBUS clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x0C "SYSC_STSCKDIVR2,Status Clock Divider Register 2"
|
|
bitfld.long 0x0C 20.--23. " PERI7DIV ,PERI7 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 16.--19. " PERI6DIV ,PERI6 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 12.--15. " PERI5DIV ,PERI5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 8.--11. " PERI4DIV ,PERI4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--7. " PERI1DIV ,PERI1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 0.--3. " PERI0DIV ,PERI0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
rgroup.long 0x228++0x03
|
|
line.long 0x00 "SYSC_STSPLLCNTR,Status PLL Control Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " PLLDIVN ,PLL clock N-multiplier setting bits"
|
|
bitfld.long 0x00 8.--11. " PLLDIVM ,PLL clock M-divider setting bits" "?,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30"
|
|
bitfld.long 0x00 0.--1. " PLLDIVL ,PLL input clock divider setting bits" "No division,/2,/4,/6"
|
|
rgroup.long 0x234++0x03
|
|
line.long 0x00 "SYSC_STSLVDCFGR,Status Low-voltage Detection Configuration Register"
|
|
bitfld.long 0x00 23. " VDRDY12 ,1.2V low-voltage detection ready status bit" "Waiting,Monitoring"
|
|
bitfld.long 0x00 17.--19. " SV12 ,1.2V reference voltage setting bits" ",,,,0.9V,?..."
|
|
bitfld.long 0x00 16. " LVDE12 ,1.2V low-voltage detection operation enable bit" ",Enabled"
|
|
bitfld.long 0x00 7. " VDRDY50 ,Low-voltage detection (5.0V) ready status bit" "Waiting,Monitoring"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LVDS50 ,Low-voltage detection (5.0V) operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 1.--3. " SV50 ,5.0V reference voltage setting" ",,,,,3.9V,4.1V,4.3V"
|
|
bitfld.long 0x00 0. " LVDE50 ,5.0V low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x23C++0x03
|
|
line.long 0x00 "SYSC_STSCSVCFGR,Status Clock Supervisor Configuration Register"
|
|
bitfld.long 0x00 2. " PLLCSVE ,PLL clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x288++0x03 "System Register Group"
|
|
line.long 0x00 "SYSC_SYSSTSR,System Status Register"
|
|
bitfld.long 0x00 15. " PSSSTS1 ,PSS profile (sub status control 1) update status bit" "Completed/Not updated,Updated"
|
|
bitfld.long 0x00 14. " RUNSTS1 ,RUN profile (sub status control 1) update status bit" "Completed/Not updated,Updated"
|
|
bitfld.long 0x00 13. " PSSDF1 ,PSS profile (sub status control 1) update completion flag bit" "Updated/Not updated,Completed"
|
|
bitfld.long 0x00 9. " CPUSTS1 ,CPU1 device status bit" "Operation status,WFI status"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DVSTS1 ,Device status of sub status control 1 bit" "PSS,RUN"
|
|
bitfld.long 0x00 7. " PSSSTS0 ,PSS profile (main status control) update status bit" "Updated/Not updated,Completed"
|
|
bitfld.long 0x00 6. " RUNSTS0 ,RUN profile (main status control) update status bit" "Completed/Not updated,Updated"
|
|
bitfld.long 0x00 5. " PSSDF0 ,PSS profile (main status control) update completion flag bit" "Updated/Not updated,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RUNDF0 ,RUN profile (main status control) update completion flag bit" "Updated/Not updated,Completed"
|
|
bitfld.long 0x00 1. " CPUSTS0 ,CPU0 device status bit" "Operation status,WFI status"
|
|
bitfld.long 0x00 0. " DVSTS0 ,Device status of main status control bit" "PSS,RUN"
|
|
group.long 0x28C++0x07
|
|
line.long 0x00 "SYSC_SYSINTER,System Status Interrupt Enable Register"
|
|
bitfld.long 0x00 4. " RUNDIE0 ,RUN profile (main status control) update completion interrupt enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SYSC_SYSICLR,System Status Flag And Interrupt Clear Register"
|
|
bitfld.long 0x04 13. " PSSDFCLR1 ,PSS profile (sub status control 1) update completion flag clear bit" "No effect,Clear"
|
|
bitfld.long 0x04 5. " PSSDFCLR0 ,PSS profile (main status control) update completion flag clear bit" "No effect,Clear"
|
|
bitfld.long 0x04 4. " RUNDFCLR0 ,RUN profile (main status control) update completion flag clear bit" "No effect,Clear"
|
|
rgroup.long 0x294++0x07
|
|
line.long 0x00 "SYSC_SYSERRIR0,System Error Interrupt Factor Register 0"
|
|
bitfld.long 0x00 24. " LVD50IF ,5.0V low-voltage detection interrupt request bit" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " SSPMIF ,Sub-system PLL oscillation abnormal monitor detection error interrupt request bit" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " PMIF ,PLL oscillation abnormal monitor detection error interrupt request bit" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " MOMIF ,Main oscillation abnormality detection error interrupt request bit" "Not requested,Requested"
|
|
line.long 0x04 "SYSC_SYSERRIR1,System Error Interrupt Factor Register 1"
|
|
bitfld.long 0x04 11. " PSSENERRIF1 ,PSS profile update enable write error interrupt request bit" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " PSSTRGCIF1 ,PSS trigger cancel interrupt request bit" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " PSSERRIF0 ,PSS profile error interrupt request bit" "Not requested,Requested"
|
|
bitfld.long 0x04 5. " RUNWKERRIF0 ,RUN profile (PSS recovery time) error interrupt request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 4. " RUNERRIF0 ,RUN profile error interrupt request bit" "Not requested,Requested"
|
|
bitfld.long 0x04 3. " PSSENERRIF0 ,PSS profile update enable write error interrupt request bit" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " PSSTRGCIF0 ,PSS trigger (main status control) cancel interrupt request bit" "Not requested,Requested"
|
|
bitfld.long 0x04 1. " RUNTRGERRIF ,RUN profile update enable write error interrupt request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRGERRIF ,Trigger error interrupt request bit" "Not requested,Requested"
|
|
group.long 0x29C++0x07
|
|
line.long 0x00 "SYSC_SYSERRICLR0,System Error Interrupt Factor Clear Register 0"
|
|
bitfld.long 0x00 24. " LVD50ICLR ,Internal low-voltage detection interrupt request clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 4. " SSPMICLR ,Sub-system PLL oscillation abnormal monitor detection error interrupt request clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 2. " PMICLR ,PLL oscillation abnormal monitor detection error interrupt request clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MOMICLR ,Main oscillation abnormality detection error interrupt request clear bit" "No effect,Clear"
|
|
line.long 0x04 "SYSC_SYSERRICLR1,System Error Interrupt Factor Clear Register 1"
|
|
bitfld.long 0x04 11. " PSSENERRICLR1 ,PSS profile update write error interrupt request clear bit" "No effect,Clear"
|
|
bitfld.long 0x04 10. " PSSTRGCICLR1 ,PSS trigger (sub status control 1) cancel interrupt request clear bit" "No effect,Clear"
|
|
bitfld.long 0x04 6. " PSSERRICLR0 ,PSS profile error interrupt request clear bit" "No effect,Clear"
|
|
bitfld.long 0x04 5. " RUNWKERRICLR0 ,RUN profile error interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " RUNERRICLR0 ,RUN profile error interrupt request clear bit" "No effect,Clear"
|
|
bitfld.long 0x04 3. " PSSENERRICLR0 ,PSS profile update enable write error interrupt request clear bit" "No effect,Clear"
|
|
bitfld.long 0x04 2. " PSSTRGCICLR0 ,PSS trigger (main status control) cancel interrupt request clear bit" "No effect,Clear"
|
|
bitfld.long 0x04 1. " RUNTRGERRICLR ,RUN profile update enable write error interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRGERRICLR ,Trigger error interrupt request clear bit" "No effect,Clear"
|
|
rgroup.long 0x2A4++0x0B
|
|
line.long 0x00 "SYSC_SYSPROSTSR,Profile Status Register"
|
|
bitfld.long 0x00 2. " PSSPSTS ,PSS profile setting status bit" "No error,Error"
|
|
bitfld.long 0x00 1. " RUNWKPSTS ,RUN profile (in PSS recovery) setting status bit" "No error,Error"
|
|
bitfld.long 0x00 0. " RUNPSTS ,RUN profile setting status bit" "No error,Error"
|
|
line.long 0x04 "SYSC_SYSRUNPEFR,RUN Profile Error Flag Register"
|
|
bitfld.long 0x04 9. " PEF9 ,RUN profile error flag bit 9" "No error,Error"
|
|
bitfld.long 0x04 8. " PEF8 ,RUN profile error flag bit 8" "No error,Error"
|
|
bitfld.long 0x04 7. " PEF7 ,RUN profile error flag bit 7" "No error,Error"
|
|
bitfld.long 0x04 6. " PEF6 ,RUN profile error flag bit 6" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PEF5 ,RUN profile error flag bit 5" "No error,Error"
|
|
bitfld.long 0x04 3. " PEF3 ,RUN profile error flag bit 3" "No error,Error"
|
|
bitfld.long 0x04 2. " PEF2 ,RUN profile error flag bit 2" "No error,Error"
|
|
bitfld.long 0x04 1. " PEF1 ,RUN profile error flag bit 1" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PEF0 ,RUN profile error flag bit 0" "No error,Error"
|
|
line.long 0x08 "SYSC_SYSPSSPEFR,PSS Profile Error Flag Register"
|
|
bitfld.long 0x08 10. " PEF10 ,PSS profile error flag bit 10" "No error,Error"
|
|
bitfld.long 0x08 9. " PEF9 ,PSS profile error flag bit 9" "No error,Error"
|
|
bitfld.long 0x08 8. " PEF8 ,PSS profile error flag bit 8" "No error,Error"
|
|
bitfld.long 0x08 7. " PEF7 ,PSS profile error flag bit 7" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PEF6 ,PSS profile error flag bit 6" "No error,Error"
|
|
bitfld.long 0x08 5. " PEF5 ,PSS profile error flag bit 5" "No error,Error"
|
|
bitfld.long 0x08 4. " PEF4 ,PSS profile error flag bit 4" "No error,Error"
|
|
bitfld.long 0x08 3. " PEF3 ,PSS profile error flag bit 3" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PEF1 ,PSS profile error flag bit 1" "No error,Error"
|
|
bitfld.long 0x08 0. " PEF0 ,PSS profile error flag bit 0" "No error,Error"
|
|
group.long 0x680++0x07 "Special Setting Register Group"
|
|
line.long 0x00 "SYSC_SPECFGR,System Special Configuration Register"
|
|
bitfld.long 0x00 23. " PSSPADCTRL ,Perform high impedance control of IO in the PSS" "Not performed,Performed"
|
|
line.long 0x04 "SYSC_SPECPUCFGR,CPU Control Register"
|
|
bitfld.long 0x04 8.--10. " CPUMD ,CPU operation mode setting bits" "2CPU mode,,,,1CPU0 mode,1CPU1 mode,?..."
|
|
bitfld.long 0x04 1. " HEN1 ,CPU1HALT control bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HEN0 ,CPU0HALT control bit" "Disabled,Enabled"
|
|
rgroup.long 0x700++0x03 "Debug Register Group"
|
|
line.long 0x00 "SYSC_JTAGDETECT,JTAG Detection Register"
|
|
bitfld.long 0x00 0. " DBGCON ,Debugger connection status bit" "Not connected,Connected"
|
|
group.long 0x704++0x07
|
|
line.long 0x00 "SYSC_JTAGCNFG,JTAG Configuration Register"
|
|
bitfld.long 0x00 0. " DBGDONE ,Debugger status bit" "Connected,Not connected/completed"
|
|
line.long 0x04 "SYSC_JTAGWAKEUP,JTAG Wakeup Register"
|
|
bitfld.long 0x04 0. " DBGWKEN ,Debugger wakeup enable bit" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSV (Clock Supervisor)"
|
|
base ad:0xB0600300
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "SYSC_CSVMOCFGR00,Main Clock Supervisor Configuration Register 00"
|
|
hexmask.long.word 0x00 16.--25. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x00 0.--9. 1. " LOWTHR , Lower-limit threshold value bits"
|
|
line.long 0x04 "SYSC_CSVMOCFGR01,Main Clock Supervisor Configuration Register 01"
|
|
bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Reset,Interrupt"
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
line.long 0x08 "SYSC_CSVMOCFGR10,Main Clock Supervisor Configuration Register 10"
|
|
hexmask.long.word 0x08 16.--25. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x08 0.--9. 1. " LOWTHR , Lower-limit threshold value bits"
|
|
line.long 0x0C "SYSC_CSVMOCFGR11,Main Clock Supervisor Configuration Register 11"
|
|
bitfld.long 0x0C 24. " REFCLKSEL ,Reference clock selection bit" "Fast-CR,Slow-CR"
|
|
hexmask.long.word 0x0C 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "SYSC_CSVPLLCFGR0,PLL Clock Supervisor Configuration Register 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x00 0.--9. 1. " LOWTHR , Lower-limit threshold value bits"
|
|
line.long 0x04 "SYSC_CSVPLLCFGR1,PLL Clock Supervisor Configuration Register 1"
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "SYSC_CSVSSCFGR0,Sub-system PLL Clock Supervisor Configuration Register 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits"
|
|
line.long 0x04 "SYSC_CSVSSCFGR1,Sub-system PLL Clock Supervisor Configuration Register 1"
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SYSC_CSVOUTER,Clock Supervisor Output Enable Register"
|
|
bitfld.long 0x00 0. " OUTEN ,Clock supervisor output enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SYSC_CSVTESTR,Clock Supervisor Test Register"
|
|
bitfld.long 0x04 4. " SSCLKGATE ,Sub-system PLL clock supervisor test bit" "Normal operation,Input clock gating"
|
|
bitfld.long 0x04 2. " PLLCLKGATE ,PLL clock supervisor test bit" "Normal operation,Input clock gating"
|
|
bitfld.long 0x04 0. " MOCLKGATE ,Main clock supervisor test bit" "Normal operation,Input clock gating"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCT (Source Clock Timer)"
|
|
base ad:0xB0600400
|
|
width 17.
|
|
if (((per.l(ad:0xB0600400+0x0C))&0x04)==0x00)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "SYSC_FCRCTTRGR,Fast-CR Clock Timer Trigger Register"
|
|
bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change settings/start counting"
|
|
line.long 0x04 "SYSC_FCRCTCNTR,Fast-CR Clock Timer Control Register"
|
|
bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stop"
|
|
bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shot,Continuous"
|
|
line.long 0x08 "SYSC_FCRCTCPR,Fast-CR Clock Timer Compare Prescaler Register"
|
|
bitfld.long 0x08 16.--19. " PSCL ,Prescaler bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits"
|
|
else
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "SYSC_FCRCTTRGR,Fast-CR Clock Timer Trigger Register"
|
|
bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change settings/start counting"
|
|
line.long 0x04 "SYSC_FCRCTCNTR,Fast-CR Clock Timer Control Register"
|
|
bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stop"
|
|
bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shot,Continuous"
|
|
line.long 0x08 "SYSC_FCRCTCPR,Fast-CR Clock Timer Compare Prescaler Register"
|
|
bitfld.long 0x08 16.--19. " PSCL ,Prescaler bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits"
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SYSC_FCRCTSTR,Fast-CR Clock Timer Status Register"
|
|
bitfld.long 0x00 2. " BUSY ,Setting update status bit" "Completed,In progress"
|
|
bitfld.long 0x00 1. " TST ,Timer status bit" "Stopped,Operating"
|
|
bitfld.long 0x00 0. " INTF ,Interrupt flag bit" "No interrupt,Interrupt"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "SYSC_FCRCTINTER,Fast-CR Clock Timer Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SYSC_FCRCTICLR,Fast-CR Clock Timer Interrupt Clear Register"
|
|
bitfld.long 0x04 0. " INTC ,Interrupt clear bit" "No effect,Clear"
|
|
if (((per.l(ad:0xB0600400+0x8C))&0x04)==0x00)
|
|
group.long 0x80++0x0B
|
|
line.long 0x00 "SYSC_SCRCTTRGR,Slow-CR Clock Timer Trigger Register"
|
|
bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change settings/Start counting"
|
|
line.long 0x04 "SYSC_SCRCTCNTR,Slow-CR Clock Timer Control Register"
|
|
bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stop"
|
|
bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shot,Continuous"
|
|
line.long 0x08 "SYSC_SCRCTCPR,Slow-CR Clock Timer Compare Prescaler Register"
|
|
bitfld.long 0x08 16.--19. " PSCL ,Prescaler bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits"
|
|
else
|
|
rgroup.long 0x80++0x0B
|
|
line.long 0x00 "SYSC_SCRCTTRGR,Slow-CR Clock Timer Trigger Register"
|
|
bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change settings/Start counting"
|
|
line.long 0x04 "SYSC_SCRCTCNTR,Slow-CR Clock Timer Control Register"
|
|
bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stop"
|
|
bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shot,Continuous"
|
|
line.long 0x08 "SYSC_SCRCTCPR,Slow-CR Clock Timer Compare Prescaler Register"
|
|
bitfld.long 0x08 16.--19. " PSCL ,Prescaler bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits"
|
|
endif
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "SYSC_SCRCTSTR,Slow-CR Clock Timer Status Register"
|
|
bitfld.long 0x00 2. " BUSY ,Setting update status bit" "Completed,In progress"
|
|
bitfld.long 0x00 1. " TST ,Timer status bit" "Stopped,Operating"
|
|
bitfld.long 0x00 0. " INTF ,Interrupt flag bit" "No interrupt,Interrupt"
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "SYSC_SCRCTINTER,Slow-CR Clock Timer Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SYSC_SCRCTICLR,Slow-CR Clock Timer Interrupt Clear Register"
|
|
bitfld.long 0x04 0. " INTC ,Interrupt clear bit" "No effect,Clear"
|
|
if (((per.l(ad:0xB0600400+0x10C))&0x04)==0x00)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "SYSC_MOCTTRGR,Main Clock Timer Trigger Register"
|
|
bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change settings/Start counting"
|
|
line.long 0x04 "SYSC_MOCTCNTR,Main Clock Timer Control Register"
|
|
bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stop"
|
|
bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shot,Continuous"
|
|
line.long 0x08 "SYSC_MOCTCPR,Main Clock Timer Compare Prescaler Register"
|
|
bitfld.long 0x08 16.--19. " PSCL ,Prescaler bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits"
|
|
else
|
|
rgroup.long 0x100++0x0B
|
|
line.long 0x00 "SYSC_MOCTTRGR,Main Clock Timer Trigger Register"
|
|
bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change settings/Start counting"
|
|
line.long 0x04 "SYSC_MOCTCNTR,Main Clock Timer Control Register"
|
|
bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stop"
|
|
bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shot,Continuous"
|
|
line.long 0x08 "SYSC_MOCTCPR,Main Clock Timer Compare Prescaler Register"
|
|
bitfld.long 0x08 16.--19. " PSCL ,Prescaler bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits"
|
|
endif
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "SYSC_MOCTSTR,Main Clock Timer Status Register"
|
|
bitfld.long 0x00 2. " BUSY ,Setting update status bit" "Completed,In progress"
|
|
bitfld.long 0x00 1. " TST ,Timer status bit" "Stopped,Operating"
|
|
bitfld.long 0x00 0. " INTF ,Interrupt flag bit" "No interrupt,Interrupt"
|
|
group.long 0x110++0x07
|
|
line.long 0x00 "SYSC_MOCTINTER,Main Clock Timer Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SYSC_MOCTICLR,Main Clock Timer Interrupt Clear Register"
|
|
bitfld.long 0x04 0. " INTC ,Interrupt clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "IRC (Interrupt Controller)"
|
|
tree "Unit 0"
|
|
base ad:0xB0400000
|
|
width 18.
|
|
rgroup.long 0x00++0x0F
|
|
line.long 0x00 "NMIVAS,IRC NMI Vector Address Status Register"
|
|
line.long 0x04 "NMIST,IRC NMI Status Register"
|
|
bitfld.long 0x04 8.--11. " NMPIS ,NMI priority status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--5. " NMISN ,NMI channel number bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
line.long 0x08 "IRQVAS,IRC IRQ Vector Address Status Register"
|
|
line.long 0x0C "IRQST,IRC IRQ Status Register"
|
|
bitfld.long 0x0C 24. " NIRQ ,IRQ interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--20. " IRQPS ,IRQ priority status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x0C 0.--9. 1. " IRQSN ,IRQ channel number bits"
|
|
tree "NMI Vector Address Registers"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "NMIVA0,(Nmix Pin) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "NMIVA4,(Low-voltage Detection) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
line.long 0x04 "NMIVA5,(Clock Supervisor/Profile) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
line.long 0x08 "NMIVA6,(Hardware Watchdog) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
line.long 0x0C "NMIVA7,(Software Watchdog) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
line.long 0x10 "NMIVA8,(Interrupt Controller 2-bit ECC Error Detection) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
line.long 0x14 "NMIVA9,(CPU Livelock) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "NMIVA13,(Memory Protection (MPU) Protection Violation) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "NMIVA18,(Time Protection (TPU) Protection Violation) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??AE")
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "NMIVA24,(R/D Converter Channel 0 Abnormal) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
line.long 0x04 "NMIVA25,(R/D Converter Channel 1 Abnormal) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
endif
|
|
tree.end
|
|
tree "IRQ Vector Address Registers"
|
|
group.long 0x94++0x0B
|
|
line.long 0x00 "IRQVA1,(LPC RUN Profile Update Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA2,(HW-WDT Prior Warning Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA3,(SW-WDT Prior Warning Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "IRQVA8,(TCFLASH 1-bit Error Correction Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0xB8++0x07
|
|
line.long 0x00 "IRQVA10,(WorkFLASH Unit0 Hang Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA11,(WorkFLASH Unit1 Hang Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "IRQVA16,(Interrupt Controller Unit0/1 ECC 1-bit Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0xE0++0x07
|
|
line.long 0x00 "IRQVA20,(WorkFLASH Unit0 1-bit Error Correction Interrupt/Ready Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA21,(WorkFLASH Unit1 1-bit Error Correction Interrupt/Ready Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0xF0++0x1F
|
|
line.long 0x00 "IRQVA24,(External Interrupt Ch.0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA25,(External Interrupt Ch.1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA26,(External Interrupt Ch.2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA27,(External Interrupt Ch.3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA28,(External Interrupt Ch.4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA29,(External Interrupt Ch.5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA30,(External Interrupt Ch.6) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA31,(External Interrupt Ch.7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x170++0x0B
|
|
line.long 0x00 "IRQVA56,(CAN Ch.0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA57,(CAN Ch.1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA58,(CAN Ch.2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x190++0x0F
|
|
line.long 0x00 "IRQVA64,(Multi-function Serial Interface Ch.0 Reception Complete/Status) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA65,(Multi-function Serial Interface Ch.0 Transmission Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA66,(Multi-function Serial Interface Ch.1 Reception Complete/Status) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA67,(Multi-function Serial Interface Ch.1 Transmission Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
sif cpuis("MB9DF56?M*")
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "IRQVA68,(Multi-function Serial Interface Ch.2 Reception Complete/Status) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA69,(Multi-function Serial Interface Ch.2 Transmission Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA70,(Multi-function Serial Interface Ch.3 Reception Complete/Status) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA71,(Multi-function Serial Interface Ch.3 Transmission Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
endif
|
|
group.long 0x1B0++0x07
|
|
line.long 0x00 "IRQVA72,(Multi-function Serial Interface Ch.4 Reception Complete/Status) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA73,(Multi-function Serial Interface Ch.4 Transmission Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQVA96,(Inter-processor Communication (IPCU) Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "IRQVA110,(TCRAM Unit0/1 RAM Diagnosis Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "IRQVA117,(CR Calibration Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x290++0x2F
|
|
line.long 0x00 "IRQVA128,(Base Timer Ch.0 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA129,(Base Timer Ch.1 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA130,(Base Timer Ch.2 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA131,(Base Timer Ch.3 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA132,(Base Timer Ch.4 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA133,(Base Timer Ch.5 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA134,(Base Timer Ch.6 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA135,(Base Timer Ch.7 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA136,(Base Timer Ch.8 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x24 "IRQVA137,(Base Timer Ch.9 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x24 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x28 "IRQVA138,(Base Timer Ch.10 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x28 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x2C "IRQVA139,(Base Timer Ch.11 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x2C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x350++0x13
|
|
line.long 0x00 "IRQVA176,(32-bit Free-run Timer Ch.0 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA177,(32-bit Free-run Timer Ch.1 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA178,(32-bit Free-run Timer Ch.2 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA179,(32-bit Free-run Timer Ch.3 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA180,(32-bit Free-run Timer Ch.4 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x390++0x0B
|
|
line.long 0x00 "IRQVA192,(32-bit Input Capture Ch.0, Ch.1 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA193,(32-bit Input Capture Ch.2, Ch.3 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA194,(32-bit Input Capture Ch.4, Ch.5 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x4D0++0x23
|
|
line.long 0x00 "IRQVA272,(DMAC Transfer Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA273,(DMAC Ch.0, Ch.8 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA274,(DMAC Ch.1, Ch.9 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA275,(DMAC Ch.2, Ch.10 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA276,(DMAC Ch.3, Ch.11 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA277,(DMAC Ch.4, Ch.12 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA278,(DMAC Ch.5, Ch.13 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA279,(DMAC Ch.6, Ch.14 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA280,(DMAC Ch.7, Ch.15 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x560++0x0B
|
|
line.long 0x00 "IRQVA308,(Fast-CR Clock Timer Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA309,(Slow-CR Clock Timer Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA310,(Main Clock Timer Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "IRQVA312,(PMU Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
group.long 0x590++0x0F
|
|
line.long 0x00 "IRQVA320,(FlexRay0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA321,(FlexRay1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA322,(FlexRay Timer 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA323,(FlexRay Timer 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
endif
|
|
group.long 0x5A0++0x7B
|
|
line.long 0x00 "IRQVA324,(16-bit Free-run Timer Ch.0 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA325,(16-bit Free-run Timer Ch.1 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA326,(16-bit Free-run Timer Ch.2 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA327,(16-bit Free-run Timer Ch.3 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA328,(16-bit Free-run Timer Ch.4 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA329,(16-bit Free-run Timer Ch.5 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA330,(16-bit Free-run Timer Ch.6 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA331,(16-bit Free-run Timer Ch.7 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA332,(16-bit Free-run Timer Ch.8 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x24 "IRQVA333,(16-bit Free-run Timer Ch.9 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x24 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x28 "IRQVA334,(16-bit Free-run Timer Ch.10 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x28 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x2C "IRQVA335,(16-bit Free-run Timer Ch.11 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x2C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x30 "IRQVA336,(16-bit Free-run Timer Ch.12 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x30 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x34 "IRQVA337,(16-bit Free-run Timer Ch.13 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x34 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x38 "IRQVA338,(16-bit Free-run Timer Ch.14 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x38 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x3C "IRQVA339,(16-bit Free-run Timer Ch.15 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x3C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x40 "IRQVA340,(16-bit Free-run Timer Ch.16 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x40 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x44 "IRQVA341,(16-bit Free-run Timer Ch.17 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x44 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x48 "IRQVA342,(MVA0 Angular Calculation End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x48 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x4C "IRQVA343,(MVA0 Three-phase Current Normalization End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x4C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x50 "IRQVA344,(MVA0 Three-phase To Two-phase DC Conversion End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x50 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x54 "IRQVA345,(MVA0 PID Control End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x54 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x58 "IRQVA346,(MVA0 Current To Voltage Conversion End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x58 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x5C "IRQVA347,(MVA0 Two-phase To Three-phase AC Conversion End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x5C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x60 "IRQVA348,(MVA0 Overflow Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x60 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x64 "IRQVA349,(MVA0 Underflow Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x64 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x68 "IRQVA350,(MVA0 Floating-point Non-normalized Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x68 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x6C "IRQVA351,(MVA0 Failure Detection Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x6C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x70 "IRQVA352,(MVA0 Calculation Data Update Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x70 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x74 "IRQVA353,(MVA0 R/D Converter Diagnosis Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x74 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x78 "IRQVA354,(MVA0 Cumulative Three-phase Current Abnormality Detection Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x78 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x620++0x3B
|
|
line.long 0x00 "IRQVA356,(MVA0 Three-phase To Two-phase DC Value Abnormality Detection Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA357,(MVA0 Calculation Overtime Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA358,(MVA1 Angular Calculation End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA359,(MVA1 Three-phase Current Normalization End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA360,(MVA1 Three-phase To Two-phase DC Conversion End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA361,(MVA1 PID Control End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA362,(MVA1 Current To Voltage Conversion End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA363,(MVA1 Two-phase To Three-phase AC Conversion End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA364,(MVA1 Overflow Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x24 "IRQVA365,(MVA1 Underflow Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x24 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x28 "IRQVA366,(MVA1 Floating-point Non-normalized Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x28 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x2C "IRQVA367,(MVA1 Failure Detection Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x2C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x30 "IRQVA368,(MVA1 Calculation Data Update Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x30 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x34 "IRQVA369,(MVA1 R/D Converter Diagnosis Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x34 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x38 "IRQVA370,(MVA1 Cumulative Three-phase Current Abnormality Detection Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x38 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x660++0x97
|
|
line.long 0x00 "IRQVA372,(MVA1 Three-phase To Two-phase DC Value Abnormality Detection Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA373,(MVA1 Calculation Overtime Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA374,(MVA0 Free-run Timer 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA375,(MVA1 Free-run Timer 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA376,(Waveform Generator Dead Timer Underflow 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA377,(Waveform Generator Dead Timer Reload 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA378,(Waveform Generator Dead Timer Underflow 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA379,(Waveform Generator Dead Timer Reload 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA380,(Waveform Generator Dead Timer Underflow 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x24 "IRQVA381,(Waveform Generator Dead Timer Reload 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x24 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x28 "IRQVA382,(Waveform Generator DTTI0, 1, 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x28 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x2C "IRQVA383,(Waveform Generator Dead Timer Underflow 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x2C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x30 "IRQVA384,(Waveform Generator Dead Timer Reload 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x30 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x34 "IRQVA385,(Waveform Generator Dead Timer Underflow 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x34 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x38 "IRQVA386,(Waveform Generator Dead Timer Reload 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x38 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x3C "IRQVA387,(Waveform Generator Dead Timer Underflow 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x3C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x40 "IRQVA388,(Waveform Generator Dead Timer Reload 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x40 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x44 "IRQVA389,(Waveform Generator DTTI3, 4, 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x44 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x48 "IRQVA390,(Waveform Generator Dead Timer Underflow 6) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x48 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x4C "IRQVA391,(Waveform Generator Dead Timer Reload 6) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x4C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x50 "IRQVA392,(Waveform Generator Dead Timer Underflow 7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x50 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x54 "IRQVA393,(Waveform Generator Dead Timer Reload 7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x54 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x58 "IRQVA394,(Waveform Generator Dead Timer Underflow 8) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x58 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x5C "IRQVA395,(Waveform Generator Dead Timer Reload 8) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x5C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x60 "IRQVA396,(Waveform Generator DTTI6, 7, 8) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x60 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x64 "IRQVA397,(Waveform Generator Dead Timer Underflow 9) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x64 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x68 "IRQVA398,(Waveform Generator Dead Timer Reload 9) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x68 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x6C "IRQVA399,(Waveform Generator Dead Timer Underflow 10) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x6C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x70 "IRQVA400,(Waveform Generator Dead Timer Reload 10) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x70 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x74 "IRQVA401,(Waveform Generator Dead Timer Underflow 11) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x74 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x78 "IRQVA402,(Waveform Generator Dead Timer Reload 11) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x78 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x7C "IRQVA403,(Waveform Generator DTTI9, 10, 11) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x7C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x80 "IRQVA404,(16-bit Output Compare Ch.0, Ch.1 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x80 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x84 "IRQVA405,(16-bit Output Compare Ch.2, Ch.3 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x84 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x88 "IRQVA406,(16-bit Output Compare Ch.4, Ch.5 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x88 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x8C "IRQVA407,(16-bit Output Compare Ch.6, Ch.7 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x8C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x90 "IRQVA408,(16-bit Output Compare Ch.8, Ch.9 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x90 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x94 "IRQVA409,(16-bit Output Compare Ch.10, Ch.11 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x94 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
sif cpuis("MB9DF56?M*")
|
|
group.long 0x6F8++0x0B
|
|
line.long 0x00 "IRQVA410,(16-bit Output Compare Ch.12, Ch.13 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA411,(16-bit Output Compare Ch.14, Ch.15 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA412,(16-bit Output Compare Ch.16, Ch.17 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
endif
|
|
group.long 0x704++0x17F
|
|
line.long 0x00 "IRQVA413,(16-bit Output Compare Ch.18, Ch.19 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA414,(16-bit Output Compare Ch.20, Ch.21 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA415,(16-bit Output Compare Ch.22, Ch.23 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA416,(Up/down Counter Unit0 Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA417,(Up/down Counter Unit0 Comparison Result Match Detection 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA418,(Up/down Counter Unit0 Comparison Result Match Detection 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA419,(Up/down Counter Unit0 Comparison Result Match Detection 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA420,(Up/down Counter Unit0 Comparison Result Match Detection 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA421,(Up/down Counter Unit0 Comparison Result Match Detection 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x24 "IRQVA422,(Up/down Counter Unit0 Comparison Result Match Detection 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x24 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x28 "IRQVA423,(Up/down Counter Unit1 Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x28 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x2C "IRQVA424,(Up/down Counter Unit1 Comparison Result Match Detection 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x2C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x30 "IRQVA425,(Up/down Counter Unit1 Comparison Result Match Detection 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x30 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x34 "IRQVA426,(Up/down Counter Unit1 Comparison Result Match Detection 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x34 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x38 "IRQVA427,(Up/down Counter Unit1 Comparison Result Match Detection 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x38 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x3C "IRQVA428,(Up/down Counter Unit1 Comparison Result Match Detection 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x3C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x40 "IRQVA429,(Up/down Counter Unit1 Comparison Result Match Detection 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x40 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x44 "IRQVA430,(Up/down Counter Unit2 Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x44 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x48 "IRQVA431,(Up/down Counter Unit2 Comparison Result Match Detection 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x48 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x4C "IRQVA432,(Up/down Counter Unit2 Comparison Result Match Detection 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x4C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x50 "IRQVA433,(Up/down Counter Unit2 Comparison Result Match Detection 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x50 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x54 "IRQVA434,(Up/down Counter Unit2 Comparison Result Match Detection 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x54 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x58 "IRQVA435,(Up/down Counter Unit2 Comparison Result Match Detection 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x58 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x5C "IRQVA436,(Up/down Counter Unit2 Comparison Result Match Detection 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x5C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x60 "IRQVA437,(Up/down Counter Unit3 Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x60 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x64 "IRQVA438,(Up/down Counter Unit3 Comparison Result Match Detection 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x64 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x68 "IRQVA439,(Up/down Counter Unit3 Comparison Result Match Detection 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x68 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x6C "IRQVA440,(Up/down Counter Unit3 Comparison Result Match Detection 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x6C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x70 "IRQVA441,(Up/down Counter Unit3 Comparison Result Match Detection 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x70 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x74 "IRQVA442,(Up/down Counter Unit3 Comparison Result Match Detection 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x74 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x78 "IRQVA443,(Up/down Counter Unit3 Comparison Result Match Detection 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x78 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x7C "IRQVA444,(4ch A/D Converter Unit0 Conversion Complete 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x7C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x80 "IRQVA445,(4ch A/D Converter Unit0 Conversion Complete 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x80 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x84 "IRQVA446,(4ch A/D Converter Unit0 Conversion Complete 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x84 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x88 "IRQVA447,(4ch A/D Converter Unit0 Conversion Complete 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x88 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x8C "IRQVA448,(4ch A/D Converter Unit0 Conversion Complete 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x8C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x90 "IRQVA449,(4ch A/D Converter Unit0 Conversion Complete 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x90 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x94 "IRQVA450,(4ch A/D Converter Unit0 Conversion Complete 6) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x94 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x98 "IRQVA451,(4ch A/D Converter Unit0 Conversion Complete 7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x98 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x9C "IRQVA452,(4ch A/D Converter Unit0 Range Comparison 0/1/2/3/4/5/6/7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x9C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xA0 "IRQVA453,(4ch A/D Converter Unit1 Conversion Complete 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xA0 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xA4 "IRQVA454,(4ch A/D Converter Unit1 Conversion Complete 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xA4 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xA8 "IRQVA455,(4ch A/D Converter Unit1 Conversion Complete 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xA8 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xAC "IRQVA456,(4ch A/D Converter Unit1 Conversion Complete 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xAC 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xB0 "IRQVA457,(4ch A/D Converter Unit1 Conversion Complete 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xB0 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xB4 "IRQVA458,(4ch A/D Converter Unit1 Conversion Complete 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xB4 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xB8 "IRQVA459,(4ch A/D Converter Unit1 Conversion Complete 6) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xB8 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xBC "IRQVA460,(4ch A/D Converter Unit1 Conversion Complete 7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xBC 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xC0 "IRQVA461,(4ch A/D Converter Unit1 Range Comparison 0/1/2/3/4/5/6/7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xC0 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xC4 "IRQVA462,(16-bit Input Capture Ch.0, Ch.1 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xC4 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xC8 "IRQVA463,(16-bit Input Capture Ch.2, Ch.3 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xC8 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xCC "IRQVA464,(16-bit Input Capture Ch.4, Ch.5 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xCC 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xD0 "IRQVA465,(16-bit Input Capture Ch.6, Ch.7 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xD0 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xD4 "IRQVA466,(16-bit Input Capture Ch.8, Ch.9 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xD4 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xD8 "IRQVA467,(16-bit Input Capture Ch.10, Ch.11 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xD8 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
sif cpuis("MB9DF56?M*")
|
|
group.long 0x7E0++0x07
|
|
line.long 0x00 "IRQVA468,(16-bit Input Capture Ch.12, Ch.13 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA469,(16-bit Input Capture Ch.14 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
else
|
|
group.long 0x7E0++0x03
|
|
line.long 0x00 "IRQVA468,(16-bit Input Capture Ch.12 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
endif
|
|
group.long 0x7E8++0x9B
|
|
line.long 0x00 "IRQVA470,(12-bit ADC Conversion Complete 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA471,(12-bit ADC Conversion Complete 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA472,(12-bit ADC Conversion Complete 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA473,(12-bit ADC Conversion Complete 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA474,(12-bit ADC Conversion Complete 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA475,(12-bit ADC Conversion Complete 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA476,(12-bit ADC Conversion Complete 6) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA477,(12-bit ADC Conversion Complete 7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA478,(12-bit ADC Conversion Complete 8) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x24 "IRQVA479,(12-bit ADC Conversion Complete 9) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x24 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x28 "IRQVA480,(12-bit ADC Conversion Complete 10) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x28 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x2C "IRQVA481,(12-bit ADC Conversion Complete 11) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x2C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x30 "IRQVA482,(12-bit ADC Conversion Complete 12) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x30 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x34 "IRQVA483,(12-bit ADC Conversion Complete 13) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x34 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x38 "IRQVA484,(12-bit ADC Conversion Complete 14) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x38 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x3C "IRQVA485,(12-bit ADC Conversion Complete 15) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x3C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x40 "IRQVA486,(12-bit ADC Conversion Complete 16) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x40 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x44 "IRQVA487,(12-bit ADC Conversion Complete 17) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x44 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x48 "IRQVA488,(12-bit ADC Conversion Complete 18) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x48 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x4C "IRQVA489,(12-bit ADC Conversion Complete 19) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x4C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x50 "IRQVA490,(12-bit ADC Conversion Complete 20) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x50 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x54 "IRQVA491,(12-bit ADC Conversion Complete 21) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x54 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x58 "IRQVA492,(12-bit ADC Conversion Complete 22) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x58 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x5C "IRQVA493,(12-bit ADC Conversion Complete 23) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x5C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x60 "IRQVA494,(12-bit ADC Conversion Complete 24) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x60 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x64 "IRQVA495,(12-bit ADC Conversion Complete 25) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x64 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x68 "IRQVA496,(12-bit ADC Conversion Complete 26) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x68 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x6C "IRQVA497,(12-bit ADC Conversion Complete 27) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x6C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x70 "IRQVA498,(12-bit ADC Conversion Complete 28) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x70 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x74 "IRQVA499,(12-bit ADC Conversion Complete 29) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x74 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x78 "IRQVA500,(12-bit ADC Conversion Complete 30) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x78 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x7C "IRQVA501,(12-bit ADC Conversion Complete 31) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x7C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x80 "IRQVA502,(12-bit ADC Range Comparison 0/1/2/3/4/5/6/7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x80 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x84 "IRQVA503,(12-bit ADC Range Comparison 8/9/10/11/12/13/14/15) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x84 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x88 "IRQVA504,(12-bit ADC Range Comparison 16/17/18/19/20/21/22/23) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x88 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x8C "IRQVA505,(12-bit ADC Range Comparison 24/25/26/27/28/29/30/31) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x8C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x90 "IRQVA506,(12-bit ADC Scan Conversion Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x90 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x94 "IRQVA507,(PLL Gear For FlexRay) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x94 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x98 "IRQVA508,(PLL Alarm For FlexRay) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x98 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
tree.end
|
|
tree "NMI Priority Level Registers"
|
|
group.long 0x890++0x13
|
|
line.long 0x00 "NMIPL0,IRC NMI Priority Level Register"
|
|
rbitfld.long 0x00 0.--3. " NMIPL0 ,NMI0 (NMIX pin) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x04 "NMIPL1,IRC NMI Priority Level Register"
|
|
bitfld.long 0x04 24.--27. " NMIPL7 ,NMI7 (SW-WDT) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
bitfld.long 0x04 16.--19. " NMIPL6 ,NMI6 (HW-WDT) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
bitfld.long 0x04 8.--11. " NMIPL5 ,NMI5 (CSV/profile) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
bitfld.long 0x04 0.--3. " NMIPL4 ,NMI4 (LVD) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x08 "NMIPL2,IRC NMI Priority Level Register"
|
|
bitfld.long 0x08 8.--11. " NMIPL9 ,NMI9 (CPU livelock) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
bitfld.long 0x08 0.--3. " NMIPL8 ,NMI8 (IRC 2-bit ECC error detection) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x0C "NMIPL3,IRC NMI Priority Level Register"
|
|
bitfld.long 0x0C 8.--11. " NMIPL13 ,NMI13 (Memory protection (MPU) protection violation) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x10 "NMIPL4,IRC NMI Priority Level Register"
|
|
bitfld.long 0x10 16.--19. " NMIPL18 ,NMI18 (Time protection (TPU) protection violation) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??AE")
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "NMIPL6,IRC NMI Priority Level Register"
|
|
bitfld.long 0x00 8.--11. " NMIPL25 ,NMI25 (R/D converter ch.1) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
bitfld.long 0x00 0.--3. " NMIPL24 ,NMI24 (R/D converter ch.0) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
endif
|
|
tree.end
|
|
tree "IRQ Priority Level Registers"
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "IRQPL0,IRQ Priority Level Register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (SW-WDT prior warning interrupt request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (HW-WDT prior warning interrupt request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (LPC RUN profile update complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "IRQPL2,IRQ Priority Level Register"
|
|
bitfld.long 0x00 24.--28. " IRQPL11 ,IRQ11 (WorkFLASH unit1 hang interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL10 ,IRQ10 (WorkFLASH unit0 hang interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL8 ,IRQ8 (TCFLASH unit 0/1 1-bit error correction/ready/hang interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8C0++0x0F
|
|
line.long 0x00 "IRQPL4,IRQ Priority Level Register"
|
|
bitfld.long 0x00 0.--4. " IRQPL16 ,IRQ16 (Interrupt controller unit 0/1 ECC 1-bit error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "IRQPL5,IRQ Priority Level Register"
|
|
bitfld.long 0x04 8.--12. " IRQPL21 ,IRQ21 (WorkFLASH unit 1 1-bit error correction interrupt/ready interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " IRQPL20 ,IRQ20 (WorkFLASH unit 0 1-bit error correction interrupt/ready interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "IRQPL6,IRQ Priority Level Register"
|
|
bitfld.long 0x08 24.--28. " IRQPL27 ,IRQ27 (External interrupt ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " IRQPL26 ,IRQ26 (External interrupt ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 8.--12. " IRQPL25 ,IRQ25 (External interrupt ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--4. " IRQPL24 ,IRQ24 (External interrupt ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "IRQPL7,IRQ Priority Level Register"
|
|
bitfld.long 0x0C 24.--28. " IRQPL31 ,IRQ31 (External interrupt ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 16.--20. " IRQPL30 ,IRQ30 (External interrupt ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 8.--12. " IRQPL29 ,IRQ29 (External interrupt ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 0.--4. " IRQPL28 ,IRQ28 (External interrupt ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "IRQPL14,IRQ Priority Level Register"
|
|
bitfld.long 0x00 16.--20. " IRQPL58 ,IRQ58 (CAN ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL57 ,IRQ57 (CAN ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL56 ,IRQ56 (CAN ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "IRQPL16,IRQ Priority Level Register"
|
|
bitfld.long 0x00 24.--28. " IRQPL67 ,IRQ67 (Multi-function serial interface ch.1 transmission complete) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL66 ,IRQ66 (Multi-function serial interface ch.1 reception complete/status) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL65 ,IRQ65 (Multi-function serial interface ch.0 transmission complete) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL64 ,IRQ64 (Multi-function serial interface ch.0 reception complete/status) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("MB9DF56?M*")
|
|
group.long 0x8F4++0x03
|
|
line.long 0x00 "IRQPL17,IRQ Priority Level Register"
|
|
bitfld.long 0x00 24.--28. " IRQPL71 ,IRQ71 (Multi-function serial interface ch.3 transmission complete) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL70 ,IRQ70 (Multi-function serial interface ch.3 reception complete/status) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL69 ,IRQ69 (Multi-function serial interface ch.2 transmission complete) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL68 ,IRQ68 (Multi-function serial interface ch.2 reception complete/status) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "IRQPL18,IRQ Priority Level Register"
|
|
bitfld.long 0x00 8.--12. " IRQPL73 ,IRQ73 (Multi-function serial interface ch.4 transmission complete) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL72 ,IRQ72 (Multi-function serial interface ch.4 reception complete/status) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8910++0x03
|
|
line.long 0x00 "IRQPL24,IRQ Priority Level Register"
|
|
bitfld.long 0x00 0.--4. " IRQPL96 ,IRQ96 (Inter-processor communication (IPCU) interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x891C++0x03
|
|
line.long 0x00 "IRQPL27,IRQ Priority Level Register"
|
|
bitfld.long 0x00 16.--20. " IRQPL110 ,IRQ110 (TCRAM unit 0/1 RAM diagnosis interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8924++0x03
|
|
line.long 0x00 "IRQPL29,IRQ Priority Level Register"
|
|
bitfld.long 0x00 8.--12. " IRQPL117 ,IRQ117 (CR calibration interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8930++0x07
|
|
line.long 0x00 "IRQPL32,IRQ Priority Level Register"
|
|
bitfld.long 0x00 24.--28. " IRQPL131 ,IRQ131 (Base timer ch.3 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL130 ,IRQ130 (Base timer ch.2 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL129 ,IRQ129 (Base timer ch.1 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL128 ,IRQ128 (Base timer ch.0 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "IRQPL33,IRQ Priority Level Register"
|
|
bitfld.long 0x04 24.--28. " IRQPL135 ,IRQ135 (Base timer ch.7 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--20. " IRQPL134 ,IRQ134 (Base timer ch.6 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x04 8.--12. " IRQPL133 ,IRQ133 (Base timer ch.5 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " IRQPL132 ,IRQ132 (Base timer ch.4 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("MB9DF56?M*")
|
|
group.long 0x8938++0x03
|
|
line.long 0x00 "IRQPL34,IRQ Priority Level Register"
|
|
bitfld.long 0x00 24.--28. " IRQPL139 ,IRQ139 (Base timer ch.11 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL138 ,IRQ138 (Base timer ch.10 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL137 ,IRQ137 (Base timer ch.9 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL136 ,IRQ136 (Base timer ch.8 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0x8960++0x07
|
|
line.long 0x00 "IRQPL44,IRQ Priority Level Register"
|
|
bitfld.long 0x00 24.--28. " IRQPL179 ,IRQ179 (32-bit free-run timer ch.3 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " IRQPL178 ,IRQ178 (32-bit free-run timer ch.2 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL177 ,IRQ177 (32-bit free-run timer ch.1 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL176 ,IRQ176 (32-bit free-run timer ch.0 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x04 "IRQPL45,IRQ Priority Level Register"
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bitfld.long 0x04 0.--4. " IRQPL180 ,IRQ180 (32-bit free-run timer ch.4 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x8970++0x03
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line.long 0x00 "IRQPL48,IRQ Priority Level Register"
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bitfld.long 0x00 16.--20. " IRQPL194 ,IRQ194 (32-bit input capture ch.4, ch.5 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL193 ,IRQ193 (32-bit input capture ch.2, ch.3 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL192 ,IRQ192 (32-bit input capture ch.0, ch.1 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x89C0++0x0B
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line.long 0x00 "IRQPL68,IRQ Priority Level Register"
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bitfld.long 0x00 24.--28. " IRQPL275 ,IRQ275 (DMAC ch.2, ch.10 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " IRQPL274 ,IRQ274 (DMAC ch.1, ch.9 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL273 ,IRQ273 (DMAC ch.0, ch.8 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL272 ,IRQ272 (DMAC transfer error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x04 "IRQPL69,IRQ Priority Level Register"
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bitfld.long 0x04 24.--28. " IRQPL279 ,IRQ279 (DMAC ch.6, ch.14 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 16.--20. " IRQPL278 ,IRQ278 (DMAC ch.5, ch.13 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 8.--12. " IRQPL277 ,IRQ277 (DMAC ch.4, ch.12 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--4. " IRQPL276 ,IRQ276 (DMAC ch.3, ch.11 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x08 "IRQPL70,IRQ Priority Level Register"
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bitfld.long 0x08 0.--4. " IRQPL280 ,IRQ280 (DMAC ch.7, ch.15 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x89E4++0x07
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line.long 0x00 "IRQPL77,IRQ Priority Level Register"
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bitfld.long 0x00 16.--20. " IRQPL310 ,IRQ310 (Main clock timer interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL309 ,IRQ309 (Slow-CR clock timer interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL308 ,IRQ308 (Fast-CR clock timer interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x04 "IRQPL78,IRQ Priority Level Register"
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bitfld.long 0x04 0.--4. " IRQPL312 ,IRQ312 (PMU interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
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group.long 0x89F0++0x03
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line.long 0x00 "IRQPL80,IRQ Priority Level Register"
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bitfld.long 0x00 24.--28. " IRQPL323 ,IRQ323 (FlexRay timer 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " IRQPL222 ,IRQ322 (FlexRay timer 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL321 ,IRQ321 (FlexRay1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL320 ,IRQ320 (FlexRay0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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endif
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group.long 0x89F4++0xBB
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line.long 0x00 "IRQPL81,IRQ Priority Level Register"
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bitfld.long 0x00 24.--28. " IRQPL327 ,IRQ327 (16-bit free-run timer ch.3 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " IRQPL326 ,IRQ326 (16-bit free-run timer ch.2 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL325 ,IRQ325 (16-bit free-run timer ch.1 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL324 ,IRQ324 (16-bit free-run timer ch.0 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x04 "IRQPL82,IRQ Priority Level Register"
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bitfld.long 0x04 24.--28. " IRQPL331 ,IRQ331 (16-bit free-run timer ch.7 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 16.--20. " IRQPL330 ,IRQ330 (16-bit free-run timer ch.6 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 8.--12. " IRQPL329 ,IRQ329 (16-bit free-run timer ch.5 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--4. " IRQPL328 ,IRQ328 (16-bit free-run timer ch.4 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x08 "IRQPL83,IRQ Priority Level Register"
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bitfld.long 0x08 24.--28. " IRQPL335 ,IRQ335 (16-bit free-run timer ch.11 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 16.--20. " IRQPL334 ,IRQ334 (16-bit free-run timer ch.10 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--12. " IRQPL333 ,IRQ333 (16-bit free-run timer ch.9 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 0.--4. " IRQPL332 ,IRQ332 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x0C "IRQPL84,IRQ Priority Level Register"
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bitfld.long 0x0C 24.--28. " IRQPL339 ,IRQ339 (16-bit free-run timer ch.15 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 16.--20. " IRQPL338 ,IRQ338 (16-bit free-run timer ch.14 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 8.--12. " IRQPL337 ,IRQ337 (16-bit free-run timer ch.13 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0.--4. " IRQPL336 ,IRQ336 (16-bit free-run timer ch.12 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x10 "IRQPL85,IRQ Priority Level Register"
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bitfld.long 0x10 24.--28. " IRQPL343 ,IRQ343 (MVA0 three-phase current normalization end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16.--20. " IRQPL342 ,IRQ342 (MVA0 angular calculation end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 8.--12. " IRQPL341 ,IRQ341 (16-bit free-run timer ch.17 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 0.--4. " IRQPL340 ,IRQ340 (16-bit free-run timer ch.16 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x14 "IRQPL86,IRQ Priority Level Register"
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bitfld.long 0x14 24.--28. " IRQPL347 ,IRQ347 (MVA0 two-phase to three-phase AC conversion end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 16.--20. " IRQPL346 ,IRQ346 (MVA0 current to voltage conversion end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 8.--12. " IRQPL345 ,IRQ345 (MVA0 PID control end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 0.--4. " IRQPL344 ,IRQ344 (MVA0 three-phase to two-phase DC conversion interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x18 "IRQPL87,IRQ Priority Level Register"
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bitfld.long 0x18 24.--28. " IRQPL351 ,IRQ351 (MVA0 failure detection error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 16.--20. " IRQPL350 ,IRQ350 (MVA0 floating-point non-normalized error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 8.--12. " IRQPL349 ,IRQ349 (MVA0 underflow interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 0.--4. " IRQPL348 ,IRQ348 (MVA0 overflow interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x1C "IRQPL88,IRQ Priority Level Register"
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bitfld.long 0x1C 16.--20. " IRQPL354 ,IRQ354 (MVA0 cumulative three-phase current abnormality detection error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 8.--12. " IRQPL353 ,IRQ353 (MVA0 R/D converter diagnosis error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 0.--4. " IRQPL352 ,IRQ352 (MVA0 calculation data update error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x20 "IRQPL89,IRQ Priority Level Register"
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bitfld.long 0x20 24.--28. " IRQPL359 ,IRQ359 (MVA1 three-phase current normalization end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 16.--20. " IRQPL358 ,IRQ358 (MVA1 angular calculation end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 8.--12. " IRQPL357 ,IRQ357 (MVA0 calculation overtime error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 0.--4. " IRQPL356 ,IRQ356 (MVA0 three-phase to two-phase DC value abnormality detection error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x24 "IRQPL90,IRQ Priority Level Register"
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bitfld.long 0x24 24.--28. " IRQPL363 ,IRQ363 (MVA1 two-phase to three-phase AC conversion end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 16.--20. " IRQPL362 ,IRQ362 (MVA1 current to voltage conversion end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 8.--12. " IRQPL361 ,IRQ361 (MVA1 PID control end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 0.--4. " IRQPL360 ,IRQ360 (MVA1 three-phase to two-phase DC conversion end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x28 "IRQPL91,IRQ Priority Level Register"
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bitfld.long 0x28 24.--28. " IRQPL367 ,IRQ367 (MVA1 failure detection error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x28 16.--20. " IRQPL366 ,IRQ366 (MVA1 floating-point non-normalized error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x28 8.--12. " IRQPL365 ,IRQ365 (MVA1 underflow interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x28 0.--4. " IRQPL364 ,IRQ364 (MVA1 overflow interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x2C "IRQPL92,IRQ Priority Level Register"
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bitfld.long 0x2C 16.--20. " IRQPL370 ,IRQ370 (MVA1 cumulative three-phase current abnormality detection error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x2C 8.--12. " IRQPL369 ,IRQ369 (MVA1 R/D converter diagnosis error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x2C 0.--4. " IRQPL368 ,IRQ368 (MVA1 calculation data update error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x30 "IRQPL93,IRQ Priority Level Register"
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bitfld.long 0x30 24.--28. " IRQPL375 ,IRQ375 (MVA1 free-run timer 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 16.--20. " IRQPL374 ,IRQ374 (MVA0 free-run timer 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 8.--12. " IRQPL373 ,IRQ373 (MVA1 calculation overtime error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 0.--4. " IRQPL372 ,IRQ372 (MVA1 three-phase to two-phase DC value abnormality detection error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x34 "IRQPL94,IRQ Priority Level Register"
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bitfld.long 0x34 24.--28. " IRQPL379 ,IRQ379 (Waveform generator dead timer reload 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 16.--20. " IRQPL378 ,IRQ378 (Waveform generator dead timer underflow 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 8.--12. " IRQPL377 ,IRQ377 (Waveform generator dead timer reload 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 0.--4. " IRQPL376 ,IRQ376 (Waveform generator dead timer underflow 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x38 "IRQPL95,IRQ Priority Level Register"
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bitfld.long 0x38 24.--28. " IRQPL383 ,IRQ383 (Waveform generator dead timer underflow 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 16.--20. " IRQPL382 ,IRQ382 (Waveform generator DTTI0, 1, 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 8.--12. " IRQPL381 ,IRQ381 (Waveform generator dead timer reload 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 0.--4. " IRQPL380 ,IRQ380 (Waveform generator dead timer underflow 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x3C "IRQPL96,IRQ Priority Level Register"
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bitfld.long 0x3C 24.--28. " IRQPL387 ,IRQ387 (Waveform generator dead timer underflow 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x3C 16.--20. " IRQPL386 ,IRQ386 (Waveform generator dead timer reload 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x3C 8.--12. " IRQPL385 ,IRQ385 (Waveform generator dead timer underflow 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x3C 0.--4. " IRQPL384 ,IRQ384 (Waveform generator dead timer reload 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x40 "IRQPL97,IRQ Priority Level Register"
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bitfld.long 0x40 24.--28. " IRQPL391 ,IRQ391 (Waveform generator dead timer reload 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 16.--20. " IRQPL390 ,IRQ390 (Waveform generator dead timer underflow 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 8.--12. " IRQPL389 ,IRQ389 (Waveform generator DTTI3, 4, 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 0.--4. " IRQPL388 ,IRQ388 (Waveform generator dead timer reload 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x44 "IRQPL98,IRQ Priority Level Register"
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bitfld.long 0x44 24.--28. " IRQPL395 ,IRQ395 (Waveform generator dead timer reload 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x44 16.--20. " IRQPL394 ,IRQ394 (Waveform generator dead timer underflow 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x44 8.--12. " IRQPL393 ,IRQ393 (Waveform generator dead timer reload 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x44 0.--4. " IRQPL392 ,IRQ392 (Waveform generator dead timer underflow 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x48 "IRQPL99,IRQ Priority Level Register"
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bitfld.long 0x48 24.--28. " IRQPL399 ,IRQ399 (Waveform generator dead timer underflow 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 16.--20. " IRQPL398 ,IRQ398 (Waveform generator dead timer reload 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 8.--12. " IRQPL397 ,IRQ397 (Waveform generator dead timer underflow 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 0.--4. " IRQPL396 ,IRQ396 (Waveform generator DTTI6, 7, 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x4C "IRQPL100,IRQ Priority Level Register"
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bitfld.long 0x4C 24.--28. " IRQPL403 ,IRQ403 (Waveform generator DTTI9, 10, 11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4C 16.--20. " IRQPL402 ,IRQ402 (Waveform generator dead timer reload 11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4C 8.--12. " IRQPL401 ,IRQ401 (Waveform generator dead timer underflow 11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4C 0.--4. " IRQPL400 ,IRQ400 (Waveform generator dead timer reload 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x50 "IRQPL101,IRQ Priority Level Register"
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bitfld.long 0x50 24.--28. " IRQPL407 ,IRQ407 (16-bit output compare ch.6, ch.7 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 16.--20. " IRQPL406 ,IRQ406 (16-bit output compare ch.4, ch.5 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 8.--12. " IRQPL405 ,IRQ405 (16-bit output compare ch.2, ch.3 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 0.--4. " IRQPL404 ,IRQ404 (16-bit output compare ch.0, ch.1 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x54 "IRQPL102,IRQ Priority Level Register"
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sif cpuis("MB9DF56?M*")
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bitfld.long 0x54 24.--28. " IRQPL411 ,IRQ411 (16-bit output compare ch.14, ch.15 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 16.--20. " IRQPL410 ,IRQ410 (16-bit output compare ch.12, ch.13 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 8.--12. " IRQPL409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 0.--4. " IRQPL408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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else
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bitfld.long 0x54 8.--12. " IRQPL409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 0.--4. " IRQPL408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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endif
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line.long 0x58 "IRQPL103,IRQ Priority Level Register"
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bitfld.long 0x58 24.--28. " IRQPL415 ,IRQ415 (16-bit output compare ch.22, ch.23 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 16.--20. " IRQPL414 ,IRQ414 (16-bit output compare ch.20, ch.21 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 8.--12. " IRQPL413 ,IRQ413 (16-bit output compare ch.18, ch.19 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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sif cpuis("MB9DF56?M*")
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bitfld.long 0x58 0.--4. " IRQPL412 ,IRQ412 (16-bit output compare ch.16, ch.17 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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endif
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line.long 0x5C "IRQPL104,IRQ Priority Level Register"
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bitfld.long 0x5C 24.--28. " IRQPL419 ,IRQ419 (Up/down counter unit0 comparison result match detection 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x5C 16.--20. " IRQPL418 ,IRQ418 (Up/down counter unit0 comparison result match detection 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x5C 8.--12. " IRQPL417 ,IRQ417 (Up/down counter unit0 comparison result match detection 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x5C 0.--4. " IRQPL416 ,IRQ416 (Up/down counter unit0 interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x60 "IRQPL105,IRQ Priority Level Register"
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bitfld.long 0x60 24.--28. " IRQPL423 ,IRQ423 (Up/down counter unit1 interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x60 16.--20. " IRQPL422 ,IRQ422 (Up/down counter unit0 comparison result match detection 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x60 8.--12. " IRQPL421 ,IRQ421 (Up/down counter unit0 comparison result match detection 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x60 0.--4. " IRQPL420 ,IRQ420 (Up/down counter unit0 comparison result match detection 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x64 "IRQPL106,IRQ Priority Level Register"
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bitfld.long 0x64 24.--28. " IRQPL427 ,IRQ427 (Up/down counter unit1 comparison result match detection 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x64 16.--20. " IRQPL426 ,IRQ426 (Up/down counter unit1 comparison result match detection 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x64 8.--12. " IRQPL425 ,IRQ425 (Up/down counter unit1 comparison result match detection 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x64 0.--4. " IRQPL424 ,IRQ424 (Up/down counter unit1 comparison result match detection 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x68 "IRQPL107,IRQ Priority Level Register"
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bitfld.long 0x68 24.--28. " IRQPL431 ,IRQ431 (Up/down counter unit2 comparison result match detection 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x68 16.--20. " IRQPL430 ,IRQ430 (Up/down counter unit2 interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x68 8.--12. " IRQPL429 ,IRQ429 (Up/down counter unit1 comparison result match detection 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x68 0.--4. " IRQPL428 ,IRQ428 (Up/down counter unit1 comparison result match detection 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x6C "IRQPL108,IRQ Priority Level Register"
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bitfld.long 0x6C 24.--28. " IRQPL435 ,IRQ435 (Up/down counter unit2 comparison result match detection 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x6C 16.--20. " IRQPL434 ,IRQ434 (Up/down counter unit2 comparison result match detection 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x6C 8.--12. " IRQPL433 ,IRQ433 (Up/down counter unit2 comparison result match detection 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x6C 0.--4. " IRQPL432 ,IRQ432 (Up/down counter unit2 comparison result match detection 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x70 "IRQPL109,IRQ Priority Level Register"
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bitfld.long 0x70 24.--28. " IRQPL439 ,IRQ439 (Up/down counter unit3 comparison result match detection 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x70 16.--20. " IRQPL438 ,IRQ438 (Up/down counter unit3 comparison result match detection 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x70 8.--12. " IRQPL437 ,IRQ437 (Up/down counter unit3 interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x70 0.--4. " IRQPL436 ,IRQ436 (Up/down counter unit2 comparison result match detection 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x74 "IRQPL110,IRQ Priority Level Register"
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bitfld.long 0x74 24.--28. " IRQPL443 ,IRQ443 (Up/down counter unit3 comparison result match detection 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x74 16.--20. " IRQPL442 ,IRQ442 (Up/down counter unit3 comparison result match detection 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x74 8.--12. " IRQPL441 ,IRQ441 (Up/down counter unit3 comparison result match detection 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x74 0.--4. " IRQPL440 ,IRQ440 (Up/down counter unit3 comparison result match detection 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x78 "IRQPL111,IRQ Priority Level Register"
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bitfld.long 0x78 24.--28. " IRQPL447 ,IRQ447 (4ch A/D converter unit0 conversion complete 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x78 16.--20. " IRQPL446 ,IRQ446 (4ch A/D converter unit0 conversion complete 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x78 8.--12. " IRQPL445 ,IRQ445 (4ch A/D converter unit0 conversion complete 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x78 0.--4. " IRQPL444 ,IRQ444 (4ch A/D converter unit0 conversion complete 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x7C "IRQPL112,IRQ Priority Level Register"
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bitfld.long 0x7C 24.--28. " IRQPL451 ,IRQ451 (4ch A/D converter unit0 conversion complete 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x7C 16.--20. " IRQPL450 ,IRQ450 (4ch A/D converter unit0 conversion complete 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x7C 8.--12. " IRQPL449 ,IRQ449 (4ch A/D converter unit0 conversion complete 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x7C 0.--4. " IRQPL448 ,IRQ448 (4ch A/D converter unit0 conversion complete 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x80 "IRQPL113,IRQ Priority Level Register"
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bitfld.long 0x80 24.--28. " IRQPL455 ,IRQ455 (4ch A/D converter unit1 conversion complete 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x80 16.--20. " IRQPL454 ,IRQ454 (4ch A/D converter unit1 conversion complete 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x80 8.--12. " IRQPL453 ,IRQ453 (4ch A/D converter unit1 conversion complete 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x80 0.--4. " IRQPL452 ,IRQ452 (4ch A/D converter unit0 range comparison 0/1/2/3/4/5/6/7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x84 "IRQPL114,IRQ Priority Level Register"
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bitfld.long 0x84 24.--28. " IRQPL459 ,IRQ459 (4ch A/D converter unit1 conversion complete 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x84 16.--20. " IRQPL458 ,IRQ458 (4ch A/D converter unit1 conversion complete 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x84 8.--12. " IRQPL457 ,IRQ457 (4ch A/D converter unit1 conversion complete 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x84 0.--4. " IRQPL456 ,IRQ456 (4ch A/D converter unit1 conversion complete 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x88 "IRQPL115,IRQ Priority Level Register"
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bitfld.long 0x88 24.--28. " IRQPL463 ,IRQ463 (16-bit input capture ch.2, ch.3 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x88 16.--20. " IRQPL462 ,IRQ462 (16-bit input capture ch.0, ch.1 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x88 8.--12. " IRQPL461 ,IRQ461 (4ch A/D converter unit1 range comparison 0/1/2/3/4/5/6/7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x88 0.--4. " IRQPL460 ,IRQ460 (4ch A/D converter unit1 conversion complete 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x8C "IRQPL116,IRQ Priority Level Register"
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bitfld.long 0x8C 24.--28. " IRQPL467 ,IRQ467 (16-bit input capture ch.10, ch.11 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x8C 16.--20. " IRQPL466 ,IRQ466 (16-bit input capture ch.8, ch.9 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x8C 8.--12. " IRQPL465 ,IRQ465 (16-bit input capture ch.6, ch.7 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x8C 0.--4. " IRQPL464 ,IRQ464 (16-bit input capture ch.4, ch.5 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x90 "IRQPL117,IRQ Priority Level Register"
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bitfld.long 0x90 24.--28. " IRQPL471 ,IRQ471 (12-bit ADC conversion complete 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x90 16.--20. " IRQPL470 ,IRQ470 (12-bit ADC conversion complete 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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sif cpuis("MB9DF56?M*")
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bitfld.long 0x90 8.--12. " IRQPL469 ,IRQ469 (16-bit input capture ch.14 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x90 0.--4. " IRQPL468 ,IRQ468 (16-bit input capture ch.12, ch.13 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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else
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bitfld.long 0x90 0.--4. " IRQPL468 ,IRQ468 (16-bit input capture ch.12 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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endif
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line.long 0x94 "IRQPL118,IRQ Priority Level Register"
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bitfld.long 0x94 24.--28. " IRQPL475 ,IRQ475 (12-bit ADC conversion complete 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x94 16.--20. " IRQPL474 ,IRQ474 (12-bit ADC conversion complete 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x94 8.--12. " IRQPL473 ,IRQ473 (12-bit ADC conversion complete 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x94 0.--4. " IRQPL472 ,IRQ472 (12-bit ADC conversion complete 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x98 "IRQPL119,IRQ Priority Level Register"
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bitfld.long 0x98 24.--28. " IRQPL479 ,IRQ479 (12-bit ADC conversion complete 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x98 16.--20. " IRQPL478 ,IRQ478 (12-bit ADC conversion complete 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x98 8.--12. " IRQPL477 ,IRQ477 (12-bit ADC conversion complete 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x98 0.--4. " IRQPL476 ,IRQ476 (12-bit ADC conversion complete 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x9C "IRQPL120,IRQ Priority Level Register"
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bitfld.long 0x9C 24.--28. " IRQPL483 ,IRQ483 (12-bit ADC conversion complete 13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x9C 16.--20. " IRQPL482 ,IRQ482 (12-bit ADC conversion complete 12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x9C 8.--12. " IRQPL481 ,IRQ481 (12-bit ADC conversion complete 11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x9C 0.--4. " IRQPL480 ,IRQ480 (12-bit ADC conversion complete 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0xA0 "IRQPL121,IRQ Priority Level Register"
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bitfld.long 0xA0 24.--28. " IRQPL487 ,IRQ487 (12-bit ADC conversion complete 17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xA0 16.--20. " IRQPL486 ,IRQ486 (12-bit ADC conversion complete 16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xA0 8.--12. " IRQPL485 ,IRQ485 (12-bit ADC conversion complete 15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xA0 0.--4. " IRQPL484 ,IRQ484 (12-bit ADC conversion complete 14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0xA4 "IRQPL122,IRQ Priority Level Register"
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bitfld.long 0xA4 24.--28. " IRQPL491 ,IRQ491 (12-bit ADC conversion complete 21) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xA4 16.--20. " IRQPL490 ,IRQ490 (12-bit ADC conversion complete 20) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xA4 8.--12. " IRQPL489 ,IRQ489 (12-bit ADC conversion complete 19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xA4 0.--4. " IRQPL488 ,IRQ488 (12-bit ADC conversion complete 18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0xA8 "IRQPL123,IRQ Priority Level Register"
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bitfld.long 0xA8 24.--28. " IRQPL495 ,IRQ495 (12-bit ADC conversion complete 25) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xA8 16.--20. " IRQPL494 ,IRQ494 (12-bit ADC conversion complete 24) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xA8 8.--12. " IRQPL493 ,IRQ493 (12-bit ADC conversion complete 23) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xA8 0.--4. " IRQPL492 ,IRQ492 (12-bit ADC conversion complete 22) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0xAC "IRQPL124,IRQ Priority Level Register"
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bitfld.long 0xAC 24.--28. " IRQPL499 ,IRQ499 (12-bit ADC conversion complete 29) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xAC 16.--20. " IRQPL498 ,IRQ498 (12-bit ADC conversion complete 28) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xAC 8.--12. " IRQPL497 ,IRQ497 (12-bit ADC conversion complete 27) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xAC 0.--4. " IRQPL496 ,IRQ496 (12-bit ADC conversion complete 26) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0xB0 "IRQPL125,IRQ Priority Level Register"
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bitfld.long 0xB0 24.--28. " IRQPL503 ,IRQ503 (12-bit ADC range comparison 8/9/10/11/12/13/14/15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xB0 16.--20. " IRQPL502 ,IRQ502 (12-bit ADC range comparison 0/1/2/3/4/5/6/7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xB0 8.--12. " IRQPL501 ,IRQ501 (12-bit ADC conversion complete 31) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xB0 0.--4. " IRQPL500 ,IRQ500 (12-bit ADC conversion complete 30) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0xB4 "IRQPL126,IRQ Priority Level Register"
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bitfld.long 0xB4 24.--28. " IRQPL507 ,IRQ507 (Pll gear for flexray) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xB4 16.--20. " IRQPL506 ,IRQ506 (12-bit ADC scan conversion complete) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xB4 8.--12. " IRQPL505 ,IRQ505 (12-bit ADC range comparison 24/25/26/27/28/29/30/31) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xB4 0.--4. " IRQPL504 ,IRQ504 (12-bit ADC range comparison 16/17/18/19/20/21/22/23) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xB8 "IRQPL127,IRQ Priority Level Register"
|
|
bitfld.long 0xB8 0.--4. " IRQPL508 ,IRQ508 (Pll alarm for flexray) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "NMI Software Interrupt Status Register"
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "NMISIS_SET/CLR,IRC NMI Software Interrupt Set/Clear Register"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??AE")
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " NMISIS25 ,NMI25 (R/D converter ch.0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " NMISIS24 ,NMI24 (R/D converter ch.1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " NMISIS18 ,NMI18 (Time protection (TPU) protection violation) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NMISIS13 ,NMI13 (Memory protection (MPU) protection violation) software interrupt status bits" "No interrupt,Interrupt"
|
|
else
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " NMISIS18 ,NMI18 (Time protection (TPU) protection violation) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NMISIS13 ,NMI13 (Memory protection (MPU) protection violation) software interrupt status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " NMISIS9 ,NMI9 (CPU livelock) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NMISIS8 ,NMI8 (IRC 2-bit ECC error detection) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " NMISIS7 ,NMI7 (SW-WDT) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " NMISIS6 ,NMI6 (HW-WDT) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " NMISIS5 ,NMI5 (CSV/profile) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NMISIS4 ,NMI4 (LVD) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " NMISIS0 ,NMI0 (NMIX pin) software interrupt status bits" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "IRQ Software Interrupt Status Register"
|
|
group.long 0xB40++0x1B
|
|
line.long 0x00 "IRQSIS0_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS31 ,IRQ31 (External interrupt ch.7) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQSIS30 ,IRQ30 (External interrupt ch.6) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQSIS29 ,IRQ29 (External interrupt ch.5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQSIS28 ,IRQ28 (External interrupt ch.4) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS27 ,IRQ27 (External interrupt ch.3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS26 ,IRQ26 (External interrupt ch.2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS25 ,IRQ25 (External interrupt ch.1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS24 ,IRQ24 (External interrupt ch.0) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS21 ,IRQ21 (WorkFLASH unit1 1-bit error correction interrupt/ready interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS20 ,IRQ20 (WorkFLASH unit0 1-bit error correction interrupt/ready interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS16 ,IRQ16 (Interrupt controller unit0/1 ECC 1-bit error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS11 ,IRQ11 (WorkFLASH unit1 hang interrupt) IRQ11 software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS10 ,IRQ10 (WorkFLASH unit0 hang interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. -0x80 8. -0x40 8. " IRQSIS8 ,IRQ8 (TCFLASH unit 0/1 1-bit error correction interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. -0x80 3. -0x40 3. " IRQSIS3 ,IRQ3 (SW-WDT unit 0/1 prior warning interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. -0x80 2. -0x40 2. " IRQSIS2 ,IRQ2 (HW-WDT prior warning interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x80 1. -0x40 1. " IRQSIS1 ,IRQ1 (LPC RUN profile update complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQSIS1_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x04 26. -0x7C 26. -0x3C 26. " IRQSIS58 ,IRQ58 (CAN ch.2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 25. -0x7C 25. -0x3C 25. " IRQSIS57 ,IRQ57 (CAN ch.1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 24. -0x7C 24. -0x3C 24. " IRQSIS56 ,IRQ56 (CAN ch.0) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQSIS2_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x08 9. -0x78 9. -0x38 9. " IRQSIS73 ,IRQ73 (Multi-function serial interface ch.4 transmission complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 8. -0x78 8. -0x38 8. " IRQSIS72 ,IRQ72 (Multi-function serial interface ch.4 reception complete/status) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 7. -0x78 7. -0x38 7. " IRQSIS71 ,IRQ71 (Multi-function serial interface ch.3 transmission complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 6. -0x78 6. -0x38 6. " IRQSIS70 ,IRQ70 (Multi-function serial interface ch.3 reception complete/status) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 5. -0x78 5. -0x38 5. " IRQSIS69 ,IRQ69 (Multi-function serial interface ch.2 transmission complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 4. -0x78 4. -0x38 4. " IRQSIS68 ,IRQ68 (Multi-function serial interface ch.2 reception complete/status) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 3. -0x78 3. -0x38 3. " IRQSIS67 ,IRQ67 (Multi-function serial interface ch.1 transmission complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 2. -0x78 2. -0x38 2. " IRQSIS66 ,IRQ66 (Multi-function serial interface ch.1 reception complete/status) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 1. -0x78 1. -0x38 1. " IRQSIS65 ,IRQ65 (Multi-function serial interface ch.0 transmission complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 0. -0x78 0. -0x38 0. " IRQSIS64 ,IRQ64 (Multi-function serial interface ch.0 reception complete/status) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x0C "IRQSIS3_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x0C 21. -0x74 21. -0x34 21. " IRQSIS117 ,IRQ117 (CR calibration interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 14. -0x74 14. -0x34 14. " IRQSIS110 ,IRQ110 (TCRAM unit 0/1 RAM diagnosis interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 0. -0x74 0. -0x34 0. " IRQSIS96 ,IRQ96 (Inter-processor communication (IPCU) interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x10 "IRQSIS4_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x10 11. -0x70 11. -0x30 11. " IRQSIS139 ,IRQ139 (Base timer ch.11 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 10. -0x70 10. -0x30 10. " IRQSIS138 ,IRQ138 (Base timer ch.10 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 9. -0x70 9. -0x30 9. " IRQSIS137 ,IRQ137 (Base timer ch.9 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 8. -0x70 8. -0x30 8. " IRQSIS136 ,IRQ136 (Base timer ch.8 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x10 7. -0x70 7. -0x30 7. " IRQSIS135 ,IRQ135 (Base timer ch.7 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 6. -0x70 6. -0x30 6. " IRQSIS134 ,IRQ134 (Base timer ch.6 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x10 5. -0x70 5. -0x30 5. " IRQSIS133 ,IRQ133 (Base timer ch.5 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 4. -0x70 4. -0x30 4. " IRQSIS132 ,IRQ132 (Base timer ch.4 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x10 3. -0x70 3. -0x30 3. " IRQSIS131 ,IRQ131 (Base timer ch.3 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 2. -0x70 2. -0x30 2. " IRQSIS130 ,IRQ130 (Base timer ch.2 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 1. -0x70 1. -0x30 1. " IRQSIS129 ,IRQ129 (Base timer ch.1 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 0. -0x70 0. -0x30 0. " IRQSIS128 ,IRQ128 (Base timer ch.0 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x14 "IRQSIS5_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " IRQSIS180 ,IRQ180 (32-bit free-run timer ch.4 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " IRQSIS179 ,IRQ179 (32-bit free-run timer ch.3 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " IRQSIS178 ,IRQ178 (32-bit free-run timer ch.2 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 17. -0x6C 17. -0x2C 17. " IRQSIS177 ,IRQ177 (32-bit free-run timer ch.1 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " IRQSIS176 ,IRQ176 (32-bit free-run timer ch.0 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x18 "IRQSIS6_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x18 2. -0x68 2. -0x28 2. " IRQSIS194 ,IRQ194 (32-bit input capture ch.4, ch.5 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 1. -0x68 1. -0x28 1. " IRQSIS193 ,IRQ193 (32-bit input capture ch.2, ch.3 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 0. -0x68 0. -0x28 0. " IRQSIS192 ,IRQ192 (32-bit input capture ch.0, ch.1 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
group.long 0xB60++0x1F
|
|
line.long 0x00 "IRQSIS8_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS280 ,IRQ280 (DMAC ch.7, ch.15 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS279 ,IRQ279 (DMAC ch.6, ch.14 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS278 ,IRQ278 (DMAC ch.5, ch.13 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS277 ,IRQ277 (DMAC ch.4, ch.12 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS276 ,IRQ276 (DMAC ch.3, ch.11 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS275 ,IRQ275 (DMAC ch.2, ch.10 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS274 ,IRQ274 (DMAC ch.1, ch.9 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS273 ,IRQ273 (DMAC ch.0, ch.8 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS272 ,IRQ272 (DMAC transfer error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQSIS9_SET/CLR,IRC IRQ Software Interrupt Set/Clear Status Register"
|
|
setclrfld.long 0x04 24. -0x7C 24. -0x3C 24. " IRQSIS312 ,IRQ312 (PMU interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 22. -0x7C 22. -0x3C 22. " IRQSIS310 ,IRQ310 (Main clock timer interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 21. -0x7C 21. -0x3C 21. " IRQSIS309 ,IRQ309 (Slow-CR clock timer interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 20. -0x7C 20. -0x3C 20. " IRQSIS308 ,IRQ308 (Fast-CR clock timer interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQSIS10_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x08 31. -0x78 31. -0x38 31. " IRQSIS351 ,IRQ351 (MVA0 failure detection error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 30. -0x78 30. -0x38 30. " IRQSIS350 ,IRQ350 (MVA0 floating-point non-normalized error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 29. -0x78 29. -0x38 29. " IRQSIS349 ,IRQ349 (MVA0 underflow interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 28. -0x78 28. -0x38 28. " IRQSIS348 ,IRQ348 (MVA0 overflow interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 27. -0x78 27. -0x38 27. " IRQSIS347 ,IRQ347 (MVA0 two-phase to three-phase AC conversion end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 26. -0x78 26. -0x38 26. " IRQSIS346 ,IRQ346 (MVA0 current to voltage conversion end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 25. -0x78 25. -0x38 25. " IRQSIS345 ,IRQ345 (MVA0 PID control end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 24. -0x78 24. -0x38 24. " IRQSIS344 ,IRQ344 (MVA0 three-phase to two-phase DC conversion end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 23. -0x78 23. -0x38 23. " IRQSIS343 ,IRQ343 (MVA0 three-phase current normalization end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 22. -0x78 22. -0x38 22. " IRQSIS342 ,IRQ342 (MVA0 angular calculation end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 21. -0x78 21. -0x38 21. " IRQSIS341 ,IRQ341 (16-bit free-run timer ch.17 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 20. -0x78 20. -0x38 20. " IRQSIS340 ,IRQ340 (16-bit free-run timer ch.16 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 19. -0x78 19. -0x38 19. " IRQSIS339 ,IRQ339 (16-bit free-run timer ch.15 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 18. -0x78 18. -0x38 18. " IRQSIS338 ,IRQ338 (16-bit free-run timer ch.14 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 17. -0x78 17. -0x38 17. " IRQSIS337 ,IRQ337 (16-bit free-run timer ch.13 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 16. -0x78 16. -0x38 16. " IRQSIS336 ,IRQ336 (16-bit free-run timer ch.12 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 15. -0x78 15. -0x38 15. " IRQSIS335 ,IRQ335 (16-bit free-run timer ch.11 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 14. -0x78 14. -0x38 14. " IRQSIS334 ,IRQ334 (16-bit free-run timer ch.10 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 13. -0x78 13. -0x38 13. " IRQSIS333 ,IRQ333 (16-bit free-run timer ch.9 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 12. -0x78 12. -0x38 12. " IRQSIS332 ,IRQ332 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 11. -0x78 11. -0x38 11. " IRQSIS331 ,IRQ331 (16-bit free-run timer ch.7 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 10. -0x78 10. -0x38 10. " IRQSIS330 ,IRQ330 (16-bit free-run timer ch.6 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 9. -0x78 9. -0x38 9. " IRQSIS329 ,IRQ329 (16-bit free-run timer ch.5 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 8. -0x78 8. -0x38 8. " IRQSIS328 ,IRQ328 (16-bit free-run timer ch.4 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 7. -0x78 7. -0x38 7. " IRQSIS327 ,IRQ327 (16-bit free-run timer ch.3 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 6. -0x78 6. -0x38 6. " IRQSIS326 ,IRQ326 (16-bit free-run timer ch.2 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 5. -0x78 5. -0x38 5. " IRQSIS325 ,IRQ325 (16-bit free-run timer ch.1 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 4. -0x78 4. -0x38 4. " IRQSIS324 ,IRQ324 (16-bit free-run timer ch.0 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
textline " "
|
|
setclrfld.long 0x08 3. -0x78 3. -0x38 3. " IRQSIS323 ,IRQ323 (FlexRay timer 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 2. -0x78 2. -0x38 2. " IRQSIS322 ,IRQ322 (FlexRay timer 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 1. -0x78 1. -0x38 1. " IRQSIS321 ,IRQ321 (FlexRay1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 0. -0x78 0. -0x38 0. " IRQSIS320 ,IRQ320 (FlexRay0) software interrupt status bits" "No interrupt,Interrupt"
|
|
endif
|
|
line.long 0x0C "IRQSIS11_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x0C 31. -0x74 31. -0x34 31. " IRQSIS383 ,IRQ383 (waveform generator dead timer underflow 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 30. -0x74 30. -0x34 30. " IRQSIS382 ,IRQ382 (waveform generator DTTI 0, 1, 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 29. -0x74 29. -0x34 29. " IRQSIS381 ,IRQ381 (waveform generator dead timer reload 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 28. -0x74 28. -0x34 28. " IRQSIS380 ,IRQ380 (waveform generator dead timer underflow 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 27. -0x74 27. -0x34 27. " IRQSIS379 ,IRQ379 (waveform generator dead timer reload 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 26. -0x74 26. -0x34 26. " IRQSIS378 ,IRQ378 (waveform generator dead timer underflow 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 25. -0x74 25. -0x34 25. " IRQSIS377 ,IRQ377 (waveform generator dead timer reload 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 24. -0x74 24. -0x34 24. " IRQSIS376 ,IRQ376 (waveform generator dead timer underflow 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 23. -0x74 23. -0x34 23. " IRQSIS375 ,IRQ375 (MVA1 free-run timer 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 22. -0x74 22. -0x34 22. " IRQSIS374 ,IRQ374 (MVA0 free-run timer 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 21. -0x74 21. -0x34 21. " IRQSIS373 ,IRQ373 (MVA1 calculation overtime error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 20. -0x74 20. -0x34 20. " IRQSIS372 ,IRQ372 (MVA1 three-phase to two-phase DC value abnormality detection error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 18. -0x74 18. -0x34 18. " IRQSIS370 ,IRQ370 (MVA1 cumulative three-phase current abnormality detection error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 17. -0x74 17. -0x34 17. " IRQSIS369 ,IRQ369 (MVA1 R/D converter diagnosis error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 16. -0x74 16. -0x34 16. " IRQSIS368 ,IRQ368 (MVA1 calculation data update error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 15. -0x74 15. -0x34 15. " IRQSIS367 ,IRQ367 (MVA1 failure detection error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 14. -0x74 14. -0x34 14. " IRQSIS366 ,IRQ366 (MVA1 floating-point non-normalized error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 13. -0x74 13. -0x34 13. " IRQSIS365 ,IRQ365 (MVA1 underflow interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 12. -0x74 12. -0x34 12. " IRQSIS364 ,IRQ364 (MVA1 overflow interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 11. -0x74 11. -0x34 11. " IRQSIS363 ,IRQ363 (MVA1 two-phase to three-phase AC conversion end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 10. -0x74 10. -0x34 10. " IRQSIS362 ,IRQ362 (MVA1 current to voltage conversion end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 9. -0x74 9. -0x34 9. " IRQSIS361 ,IRQ361 (MVA1 PID control end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 8. -0x74 8. -0x34 8. " IRQSIS360 ,IRQ360 (MVA1 three-phase to two-phase DC conversion end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 7. -0x74 7. -0x34 7. " IRQSIS359 ,IRQ359 (MVA1 three-phase current normalization end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 6. -0x74 6. -0x34 6. " IRQSIS358 ,IRQ358 (MVA1 angular calculation end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 5. -0x74 5. -0x34 5. " IRQSIS357 ,IRQ357 (MVA0 calculation overtime error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 4. -0x74 4. -0x34 4. " IRQSIS356 ,IRQ356 (MVA0 three-phase to two-phase DC value abnormality detection error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 2. -0x74 2. -0x34 2. " IRQSIS354 ,IRQ354 (MVA0 cumulative three-phase current abnormality detection error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 1. -0x74 1. -0x34 1. " IRQSIS353 ,IRQ353 (MVA0 R/D converter diagnosis error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 0. -0x74 0. -0x34 0. " IRQSIS352 ,IRQ352 (MVA0 calculation data update error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x10 "IRQSIS12_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x10 31. -0x70 31. -0x30 31. " IRQSIS415 ,IRQ415 (16-bit output compare ch.22, ch.23 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 30. -0x70 30. -0x30 30. " IRQSIS414 ,IRQ414 (16-bit output compare ch.20, ch.21 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 29. -0x70 29. -0x30 29. " IRQSIS413 ,IRQ413 (16-bit output compare ch.18, ch.19 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x10 28. -0x70 28. -0x30 28. " IRQSIS412 ,IRQ412 (16-bit output compare ch.16, ch.17 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x10 27. -0x70 27. -0x30 27. " IRQSIS411 ,IRQ411 (16-bit output compare ch.14, ch.15 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 26. -0x70 26. -0x30 26. " IRQSIS410 ,IRQ410 (16-bit output compare ch.12, ch.13 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 25. -0x70 25. -0x30 25. " IRQSIS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 24. -0x70 24. -0x30 24. " IRQSIS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x10 25. -0x70 25. -0x30 25. " IRQSIS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 24. -0x70 24. -0x30 24. " IRQSIS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x10 23. -0x70 23. -0x30 23. " IRQSIS407 ,IRQ407 (16-bit output compare ch.6, ch.7 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 22. -0x70 22. -0x30 22. " IRQSIS406 ,IRQ406 (16-bit output compare ch.4, ch.5 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 21. -0x70 21. -0x30 21. " IRQSIS405 ,IRQ405 (16-bit output compare ch.2, ch.3 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 20. -0x70 20. -0x30 20. " IRQSIS404 ,IRQ404 (16-bit output compare ch.0, ch.1 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x10 19. -0x70 19. -0x30 19. " IRQSIS403 ,IRQ403 (waveform generator DTTI 9, 10, 11) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 18. -0x70 18. -0x30 18. " IRQSIS402 ,IRQ402 (waveform generator dead timer reload 11) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 17. -0x70 17. -0x30 17. " IRQSIS401 ,IRQ401 (waveform generator dead timer underflow 11) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 16. -0x70 16. -0x30 16. " IRQSIS400 ,IRQ400 (waveform generator dead timer reload 10) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x10 15. -0x70 15. -0x30 15. " IRQSIS399 ,IRQ399 (waveform generator dead timer underflow 10) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 14. -0x70 14. -0x30 14. " IRQSIS398 ,IRQ398 (waveform generator dead timer reload 9) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 13. -0x70 13. -0x30 13. " IRQSIS397 ,IRQ397 (waveform generator dead timer underflow 9) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 12. -0x70 12. -0x30 12. " IRQSIS396 ,IRQ396 (waveform generator DTTI 6, 7, 8) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x10 11. -0x70 11. -0x30 11. " IRQSIS395 ,IRQ395 (waveform generator dead timer reload 8) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 10. -0x70 10. -0x30 10. " IRQSIS394 ,IRQ394 (waveform generator dead timer underflow 8) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 9. -0x70 9. -0x30 9. " IRQSIS393 ,IRQ393 (waveform generator dead timer reload 7) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 8. -0x70 8. -0x30 8. " IRQSIS392 ,IRQ392 (waveform generator dead timer underflow 7) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x10 7. -0x70 7. -0x30 7. " IRQSIS391 ,IRQ391 (waveform generator dead timer reload 6) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 6. -0x70 6. -0x30 6. " IRQSIS390 ,IRQ390 (waveform generator dead timer underflow 6) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 5. -0x70 5. -0x30 5. " IRQSIS389 ,IRQ389 (waveform generator DTTI 3, 4, 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 4. -0x70 4. -0x30 4. " IRQSIS388 ,IRQ388 (waveform generator dead timer reload 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x10 3. -0x70 3. -0x30 3. " IRQSIS387 ,IRQ387 (waveform generator dead timer underflow 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 2. -0x70 2. -0x30 2. " IRQSIS386 ,IRQ386 (waveform generator dead timer reload 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 1. -0x70 1. -0x30 1. " IRQSIS385 ,IRQ385 (waveform generator dead timer underflow 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 0. -0x70 0. -0x30 0. " IRQSIS384 ,IRQ384 (waveform generator dead timer reload 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x14 "IRQSIS13_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x14 31. -0x6C 31. -0x2C 31. " IRQSIS447 ,IRQ447 (4ch A/D converter unit0 conversion complete 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 30. -0x6C 30. -0x2C 30. " IRQSIS446 ,IRQ446 (4ch A/D converter unit0 conversion complete 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 29. -0x6C 29. -0x2C 29. " IRQSIS445 ,IRQ445 (4ch A/D converter unit0 conversion complete 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 28. -0x6C 28. -0x2C 28. " IRQSIS444 ,IRQ444 (4ch A/D converter unit0 conversion complete 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 27. -0x6C 27. -0x2C 27. " IRQSIS443 ,IRQ443 (up/down counter unit3 comparison result match detection 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 26. -0x6C 26. -0x2C 26. " IRQSIS442 ,IRQ442 (up/down counter unit3 comparison result match detection 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 25. -0x6C 25. -0x2C 25. " IRQSIS441 ,IRQ441 (up/down counter unit3 comparison result match detection 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 24. -0x6C 24. -0x2C 24. " IRQSIS440 ,IRQ440 (up/down counter unit3 comparison result match detection 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 23. -0x6C 23. -0x2C 23. " IRQSIS439 ,IRQ439 (up/down counter unit3 comparison result match detection 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 22. -0x6C 22. -0x2C 22. " IRQSIS438 ,IRQ438 (up/down counter unit3 comparison result match detection 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 21. -0x6C 21. -0x2C 21. " IRQSIS437 ,IRQ437 (up/down counter unit3 interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " IRQSIS436 ,IRQ436 (up/down counter unit2 comparison result match detection 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " IRQSIS435 ,IRQ435 (up/down counter unit2 comparison result match detection 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " IRQSIS434 ,IRQ434 (up/down counter unit2 comparison result match detection 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 17. -0x6C 17. -0x2C 17. " IRQSIS433 ,IRQ433 (up/down counter unit2 comparison result match detection 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " IRQSIS432 ,IRQ432 (up/down counter unit2 comparison result match detection 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 15. -0x6C 15. -0x2C 15. " IRQSIS431 ,IRQ431 (up/down counter unit2 comparison result match detection 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 14. -0x6C 14. -0x2C 14. " IRQSIS430 ,IRQ430 (up/down counter unit2 interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 13. -0x6C 13. -0x2C 13. " IRQSIS429 ,IRQ429 (up/down counter unit1 comparison result match detection 5 software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 12. -0x6C 12. -0x2C 12. " IRQSIS428 ,IRQ428 (up/down counter unit1 comparison result match detection 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 11. -0x6C 11. -0x2C 11. " IRQSIS427 ,IRQ427 (up/down counter unit1 comparison result match detection 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 10. -0x6C 10. -0x2C 10. " IRQSIS426 ,IRQ426 (up/down counter unit1 comparison result match detection 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 9. -0x6C 9. -0x2C 9. " IRQSIS425 ,IRQ425 (up/down counter unit1 comparison result match detection 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 8. -0x6C 8. -0x2C 8. " IRQSIS424 ,IRQ424 (up/down counter unit1 comparison result match detection 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 7. -0x6C 7. -0x2C 7. " IRQSIS423 ,IRQ423 (up/down counter unit1 interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 6. -0x6C 6. -0x2C 6. " IRQSIS422 ,IRQ422 (up/down counter unit0 comparison result match detection 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 5. -0x6C 5. -0x2C 5. " IRQSIS421 ,IRQ421 (up/down counter unit0 comparison result match detection 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 4. -0x6C 4. -0x2C 4. " IRQSIS420 ,IRQ420 (up/down counter unit0 comparison result match detection 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 3. -0x6C 3. -0x2C 3. " IRQSIS419 ,IRQ419 (up/down counter unit0 comparison result match detection 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 2. -0x6C 2. -0x2C 2. " IRQSIS418 ,IRQ418 (up/down counter unit0 comparison result match detection 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 1. -0x6C 1. -0x2C 1. " IRQSIS417 ,IRQ417 (up/down counter unit0 comparison result match detection 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 0. -0x6C 0. -0x2C 0. " IRQSIS416 ,IRQ416 (up/down counter unit0 interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x18 "IRQSIS14_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x18 31. -0x68 31. -0x28 31. " IRQSIS479 ,IRQ479 (12-bit ADC conversion complete 9) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 30. -0x68 30. -0x28 30. " IRQSIS478 ,IRQ478 (12-bit ADC conversion complete 8) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 29. -0x68 29. -0x28 29. " IRQSIS477 ,IRQ477 (12-bit ADC conversion complete 7) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 28. -0x68 28. -0x28 28. " IRQSIS476 ,IRQ476 (12-bit ADC conversion complete 6) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x18 27. -0x68 27. -0x28 27. " IRQSIS475 ,IRQ475 (12-bit ADC conversion complete 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 26. -0x68 26. -0x28 26. " IRQSIS474 ,IRQ474 (12-bit ADC conversion complete 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 25. -0x68 25. -0x28 25. " IRQSIS473 ,IRQ473 (12-bit ADC conversion complete 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 24. -0x68 24. -0x28 24. " IRQSIS472 ,IRQ472 (12-bit ADC conversion complete 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x18 23. -0x68 23. -0x28 23. " IRQSIS471 ,IRQ471 (12-bit ADC conversion complete 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 22. -0x68 22. -0x28 22. " IRQSIS470 ,IRQ470 (12-bit ADC conversion complete 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x18 21. -0x68 21. -0x28 21. " IRQSIS469 ,IRQ469 (16-bit input capture ch.14 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 20. -0x68 20. -0x28 20. " IRQSIS468 ,IRQ468 (16-bit input capture ch.12, ch.13 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
else
|
|
setclrfld.long 0x18 20. -0x68 20. -0x28 20. " IRQSIS468 ,IRQ468 (16-bit input capture ch.12 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x18 19. -0x68 19. -0x28 19. " IRQSIS467 ,IRQ467 (16-bit input capture ch.10, ch.11 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 18. -0x68 18. -0x28 18. " IRQSIS466 ,IRQ466 (16-bit input capture ch.8, ch.9 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 17. -0x68 17. -0x28 17. " IRQSIS465 ,IRQ465 (16-bit input capture ch.6, ch.7 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 16. -0x68 16. -0x28 16. " IRQSIS464 ,IRQ464 (16-bit input capture ch.4, ch.5 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x18 15. -0x68 15. -0x28 15. " IRQSIS463 ,IRQ463 (16-bit input capture ch.2, ch.3 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 14. -0x68 14. -0x28 14. " IRQSIS462 ,IRQ462 (16-bit input capture ch.0, ch.1 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 13. -0x68 13. -0x28 13. " IRQSIS461 ,IRQ461 (4ch A/D converter unit1 range comparison 0/1/2/3/4/5/6/7) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 12. -0x68 12. -0x28 12. " IRQSIS460 ,IRQ460 (4ch A/D converter unit1 conversion complete 7) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x18 11. -0x68 11. -0x28 11. " IRQSIS459 ,IRQ459 (4ch A/D converter unit1 conversion complete 6) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 10. -0x68 10. -0x28 10. " IRQSIS458 ,IRQ458 (4ch A/D converter unit1 conversion complete 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 9. -0x68 9. -0x28 9. " IRQSIS457 ,IRQ457 (4ch A/D converter unit1 conversion complete 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 8. -0x68 8. -0x28 8. " IRQSIS456 ,IRQ456 (4ch A/D converter unit1 conversion complete 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x18 7. -0x68 7. -0x28 7. " IRQSIS455 ,IRQ455 (4ch A/D converter unit1 conversion complete 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 6. -0x68 6. -0x28 6. " IRQSIS454 ,IRQ454 (4ch A/D converter unit1 conversion complete 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 5. -0x68 5. -0x28 5. " IRQSIS453 ,IRQ453 (4ch A/D converter unit1 conversion complete 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 4. -0x68 4. -0x28 4. " IRQSIS452 ,IRQ452 (4ch A/D converter unit0 range comparison 0/1/2/3/4/5/6/7) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x18 3. -0x68 3. -0x28 3. " IRQSIS451 ,IRQ451 (4ch A/D converter unit0 conversion complete 7) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 2. -0x68 2. -0x28 2. " IRQSIS450 ,IRQ450 (4ch A/D converter unit0 conversion complete 6) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 1. -0x68 1. -0x28 1. " IRQSIS449 ,IRQ449 (4ch A/D converter unit0 conversion complete 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 0. -0x68 0. -0x28 0. " IRQSIS448 ,IRQ448 (4ch A/D converter unit0 conversion complete 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x1C "IRQSIS15_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x1C 28. -0x64 28. -0x24 28. " IRQSIS508 ,IRQ508 (PLL Alarm For FlexRay) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 27. -0x64 27. -0x24 27. " IRQSIS507 ,IRQ507 (PLL Gear For FlexRay) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 26. -0x64 26. -0x24 26. " IRQSIS506 ,IRQ506 (12-bit ADC scan conversion complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 25. -0x64 25. -0x24 25. " IRQSIS505 ,IRQ505 (12-bit ADC range comparison 24/25/26/27/28/29/30/31) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 24. -0x64 24. -0x24 24. " IRQSIS504 ,IRQ504 (12-bit ADC range comparison 16/17/18/19/20/21/22/23) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 23. -0x64 23. -0x24 23. " IRQSIS503 ,IRQ503 (12-bit ADC range comparison 8/9/10/11/12/13/14/15) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 22. -0x64 22. -0x24 22. " IRQSIS502 ,IRQ502 (12-bit ADC range comparison 0/1/2/3/4/5/6/7) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 21. -0x64 21. -0x24 21. " IRQSIS501 ,IRQ501 (12-bit ADC conversion complete 31) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 20. -0x64 20. -0x24 20. " IRQSIS500 ,IRQ500 (12-bit ADC conversion complete 30) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 19. -0x64 19. -0x24 19. " IRQSIS499 ,IRQ499 (12-bit ADC conversion complete 29) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 18. -0x64 18. -0x24 18. " IRQSIS498 ,IRQ498 (12-bit ADC conversion complete 28) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 17. -0x64 17. -0x24 17. " IRQSIS497 ,IRQ497 (12-bit ADC conversion complete 27) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 16. -0x64 16. -0x24 16. " IRQSIS496 ,IRQ496 (12-bit ADC conversion complete 26) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 15. -0x64 15. -0x24 15. " IRQSIS495 ,IRQ495 (12-bit ADC conversion complete 25) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 14. -0x64 14. -0x24 14. " IRQSIS494 ,IRQ494 (12-bit ADC conversion complete 24) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 13. -0x64 13. -0x24 13. " IRQSIS493 ,IRQ493 (12-bit ADC conversion complete 23) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 12. -0x64 12. -0x24 12. " IRQSIS492 ,IRQ492 (12-bit ADC conversion complete 22) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 11. -0x64 11. -0x24 11. " IRQSIS491 ,IRQ491 (12-bit ADC conversion complete 21) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 10. -0x64 10. -0x24 10. " IRQSIS490 ,IRQ490 (12-bit ADC conversion complete 20) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 9. -0x64 9. -0x24 9. " IRQSIS489 ,IRQ489 (12-bit ADC conversion complete 19) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 8. -0x64 8. -0x24 8. " IRQSIS488 ,IRQ488 (12-bit ADC conversion complete 18) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 7. -0x64 7. -0x24 7. " IRQSIS487 ,IRQ487 (12-bit ADC conversion complete 17) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 6. -0x64 6. -0x24 6. " IRQSIS486 ,IRQ486 (12-bit ADC conversion complete 16) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 5. -0x64 5. -0x24 5. " IRQSIS485 ,IRQ485 (12-bit ADC conversion complete 15) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 4. -0x64 4. -0x24 4. " IRQSIS484 ,IRQ484 (12-bit ADC conversion complete 14) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 3. -0x64 3. -0x24 3. " IRQSIS483 ,IRQ483 (12-bit ADC conversion complete 13) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 2. -0x64 2. -0x24 2. " IRQSIS482 ,IRQ482 (12-bit ADC conversion complete 12) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 1. -0x64 1. -0x24 1. " IRQSIS481 ,IRQ481 (12-bit ADC conversion complete 11) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 0. -0x64 0. -0x24 0. " IRQSIS480 ,IRQ480 (12-bit ADC conversion complete 10) software interrupt status bits" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "IRQ Channel Enable Setting Register"
|
|
group.long 0xC00++0x1B
|
|
line.long 0x00 "IRQCE0_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE31 ,IRQ31 (external interrupt ch.7) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQCE30 ,IRQ30 (external interrupt ch.6) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQCE29 ,IRQ29 (external interrupt ch.5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQCE28 ,IRQ28 (external interrupt ch.4) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE27 ,IRQ27 (external interrupt ch.3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE26 ,IRQ26 (external interrupt ch.2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE25 ,IRQ25 (external interrupt ch.1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE24 ,IRQ24 (external interrupt ch.0) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE21 ,IRQ21 (WorkFLASH unit 1 1-bit error correction interrupt/ready interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE20 ,IRQ20 (WorkFLASH unit 0 1-bit error correction interrupt/ready interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE16 ,IRQ16 (Interrupt controller unit 0/1 ECC 1-bit error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE11 ,IRQ11 (WorkFLASH unit1 hang interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE10 ,IRQ10 (WorkFLASH unit0 hang interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x80 8. -0x40 8. " IRQCE8 ,IRQ8 (TCFLASH unit 0/1 1-bit error correction interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x80 3. -0x40 3. " IRQCE3 ,IRQ3 (SW-WDT unit 0/1 prior warning interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x80 2. -0x40 2. " IRQCE2 ,IRQ2 (HW-WDT prior warning interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x80 1. -0x40 1. " IRQCE1 ,IRQ1 (LPC RUN profile update complete) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x04 "IRQCE1_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x04 26. -0x7C 26. -0x3C 26. " IRQCE58 ,IRQ58 (CAN ch.2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x04 25. -0x7C 25. -0x3C 25. " IRQCE57 ,IRQ57 (CAN ch.1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. -0x7C 24. -0x3C 24. " IRQCE56 ,IRQ56 (CAN ch.0) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x08 "IRQCE2_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x08 9. -0x78 9. -0x38 9. " IRQCE73 ,IRQ73 (multi-function serial interface ch.4 transmission complete) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. -0x78 8. -0x38 8. " IRQCE72 ,IRQ72 (multi-function serial interface ch.4 reception complete/status) channel enable setting bits" "Disabled,Enabled"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x08 7. -0x78 7. -0x38 7. " IRQCE71 ,IRQ71 (multi-function serial interface ch.3 transmission complete) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. -0x78 6. -0x38 6. " IRQCE70 ,IRQ70 (multi-function serial interface ch.3 reception complete/status) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. -0x78 5. -0x38 5. " IRQCE69 ,IRQ69 (multi-function serial interface ch.2 transmission complete) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. -0x78 4. -0x38 4. " IRQCE68 ,IRQ68 (multi-function serial interface ch.2 reception complete/status) channel enable setting bits" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x08 3. -0x78 3. -0x38 3. " IRQCE67 ,IRQ67 (multi-function serial interface ch.1 transmission complete) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. -0x78 2. -0x38 2. " IRQCE66 ,IRQ66 (multi-function serial interface ch.1 reception complete/status) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. -0x78 1. -0x38 1. " IRQCE65 ,IRQ65 (multi-function serial interface ch.0 transmission complete) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. -0x78 0. -0x38 0. " IRQCE64 ,IRQ64 (multi-function serial interface ch.0 reception complete/status) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x0C "IRQCE3_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x0C 21. -0x74 21. -0x34 21. " IRQCE117 ,IRQ117 (CR calibration interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 14. -0x74 14. -0x34 14. " IRQCE110 ,IRQ110 (TCRAM unit 0/1 RAM diagnosis interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 0. -0x74 0. -0x34 0. " IRQCE96 ,IRQ96 (inter-processor communication (IPCU) interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x10 "IRQCE4_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x10 11. -0x70 11. -0x30 11. " IRQCE139 ,IRQ139 (base timer ch.11 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. -0x70 10. -0x30 10. " IRQCE138 ,IRQ138 (base timer ch.10 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. -0x70 9. -0x30 9. " IRQCE137 ,IRQ137 (base timer ch.9 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. -0x70 8. -0x30 8. " IRQCE136 ,IRQ136 (base timer ch.8 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x10 7. -0x70 7. -0x30 7. " IRQCE135 ,IRQ135 (base timer ch.7 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. -0x70 6. -0x30 6. " IRQCE134 ,IRQ134 (base timer ch.6 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x10 5. -0x70 5. -0x30 5. " IRQCE133 ,IRQ133 (base timer ch.5 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. -0x70 4. -0x30 4. " IRQCE132 ,IRQ132 (base timer ch.4 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x10 3. -0x70 3. -0x30 3. " IRQCE131 ,IRQ131 (base timer ch.3 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. -0x70 2. -0x30 2. " IRQCE130 ,IRQ130 (base timer ch.2 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 1. -0x70 1. -0x30 1. " IRQCE129 ,IRQ129 (base timer ch.1 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. -0x70 0. -0x30 0. " IRQCE128 ,IRQ128 (base timer ch.0 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x14 "IRQCE5_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " IRQCE180 ,IRQ180 (32-bit free-run timer ch.4 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " IRQCE179 ,IRQ179 (32-bit free-run timer ch.3 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " IRQCE178 ,IRQ178 (32-bit free-run timer ch.2 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. -0x6C 17. -0x2C 17. " IRQCE177 ,IRQ177 (32-bit free-run timer ch.1 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " IRQCE176 ,IRQ176 (32-bit free-run timer ch.0 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x18 "IRQCE6_SET/CLR,IRC IRQ Channel Enable Setting Register"
|
|
setclrfld.long 0x18 2. -0x68 2. -0x28 2. " IRQCE194 ,IRQ194 (32-bit input capture ch.4, ch.5 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 1. -0x68 1. -0x28 1. " IRQCE193 ,IRQ193 (32-bit input capture ch.2, ch.3 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. -0x68 0. -0x28 0. " IRQCE192 ,IRQ192 (32-bit input capture ch.0, ch.1 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
group.long 0xC20++0x1F
|
|
line.long 0x00 "IRQCE8_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE280 ,IRQ280 (DMAC ch.7, ch.15 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE279 ,IRQ279 (DMAC ch.6, ch.14 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE278 ,IRQ278 (DMAC ch.5, ch.13 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE277 ,IRQ277 (DMAC ch.4, ch.12 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE276 ,IRQ276 (DMAC ch.3, ch.11 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE275 ,IRQ275 (DMAC ch.2, ch.10 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE274 ,IRQ274 (DMAC ch.1, ch.9 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE273 ,IRQ273 (DMAC ch.0, ch.8 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE272 ,IRQ272 (DMAC transfer error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x04 "IRQCE9_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x04 24. -0x7C 24. -0x3C 24. " IRQCE312 ,IRQ312 (PMU interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. -0x7C 22. -0x3C 22. " IRQCE310 ,IRQ310 (main clock timer interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. -0x7C 21. -0x3C 21. " IRQCE309 ,IRQ309 (Slow-CR clock timer interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. -0x7C 20. -0x3C 20. " IRQCE308 ,IRQ308 (Fast-CR clock timer interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x08 "IRQCE10_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x08 31. -0x78 31. -0x38 31. " IRQCE351 ,IRQ351 (MVA0 failure detection error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. -0x78 30. -0x38 30. " IRQCE350 ,IRQ350 (MVA0 floating-point non-normalized error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. -0x78 29. -0x38 29. " IRQCE349 ,IRQ349 (MVA0 underflow interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. -0x78 28. -0x38 28. " IRQCE348 ,IRQ348 (MVA0 overflow interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. -0x78 27. -0x38 27. " IRQCE347 ,IRQ347 (MVA0 two-phase to three-phase AC conversion end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. -0x78 26. -0x38 26. " IRQCE346 ,IRQ346 (MVA0 current to voltage conversion end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 25. -0x78 25. -0x38 25. " IRQCE345 ,IRQ345 (MVA0 PID control end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. -0x78 24. -0x38 24. " IRQCE344 ,IRQ344 (MVA0 three-phase to two-phase DC conversion end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. -0x78 23. -0x38 23. " IRQCE343 ,IRQ343 (MVA0 three-phase current normalization end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. -0x78 22. -0x38 22. " IRQCE342 ,IRQ342 (MVA0 angular calculation end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. -0x78 21. -0x38 21. " IRQCE341 ,IRQ341 (16-bit free-run timer ch.17 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
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setclrfld.long 0x08 20. -0x78 20. -0x38 20. " IRQCE340 ,IRQ340 (16-bit free-run timer ch.16 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x08 19. -0x78 19. -0x38 19. " IRQCE339 ,IRQ339 (16-bit free-run timer ch.15 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. -0x78 18. -0x38 18. " IRQCE338 ,IRQ338 (16-bit free-run timer ch.14 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. -0x78 17. -0x38 17. " IRQCE337 ,IRQ337 (16-bit free-run timer ch.13 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. -0x78 16. -0x38 16. " IRQCE336 ,IRQ336 (16-bit free-run timer ch.12 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 15. -0x78 15. -0x38 15. " IRQCE335 ,IRQ335 (16-bit free-run timer ch.11 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. -0x78 14. -0x38 14. " IRQCE334 ,IRQ334 (16-bit free-run timer ch.10 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 13. -0x78 13. -0x38 13. " IRQCE333 ,IRQ333 (16-bit free-run timer ch.9 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. -0x78 12. -0x38 12. " IRQCE332 ,IRQ332 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. -0x78 11. -0x38 11. " IRQCE331 ,IRQ331 (16-bit free-run timer ch.7 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. -0x78 10. -0x38 10. " IRQCE330 ,IRQ330 (16-bit free-run timer ch.6 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. -0x78 9. -0x38 9. " IRQCE329 ,IRQ329 (16-bit free-run timer ch.5 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. -0x78 8. -0x38 8. " IRQCE328 ,IRQ328 (16-bit free-run timer ch.4 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. -0x78 7. -0x38 7. " IRQCE327 ,IRQ327 (16-bit free-run timer ch.3 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. -0x78 6. -0x38 6. " IRQCE326 ,IRQ326 (16-bit free-run timer ch.2 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. -0x78 5. -0x38 5. " IRQCE325 ,IRQ325 (16-bit free-run timer ch.1 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. -0x78 4. -0x38 4. " IRQCE324 ,IRQ324 (16-bit free-run timer ch.0 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
textline " "
|
|
setclrfld.long 0x08 3. -0x78 3. -0x38 3. " IRQCE323 ,IRQ323 (FlexRay Timer 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. -0x78 2. -0x38 2. " IRQCE322 ,IRQ322 (FlexRay Timer 0) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 1. -0x78 1. -0x38 1. " IRQCE321 ,IRQ321 (FlexRay1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. -0x78 0. -0x38 0. " IRQCE320 ,IRQ320 (FlexRay0) channel enable setting bits" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x0C "IRQCE11_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x0C 31. -0x78 31. -0x34 31. " IRQCE383 ,IRQ383 (waveform generator dead timer underflow 3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 30. -0x78 30. -0x34 30. " IRQCE382 ,IRQ382 (waveform generator DTTI 0, 1, 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 29. -0x78 29. -0x34 29. " IRQCE381 ,IRQ381 (waveform generator dead timer reload 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 28. -0x78 28. -0x34 28. " IRQCE380 ,IRQ380 (waveform generator dead timer underflow 2) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x0C 27. -0x78 27. -0x34 27. " IRQCE379 ,IRQ379 (waveform generator dead timer reload 1) channel enable setting bits" "Disabled,Enabled"
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|
setclrfld.long 0x0C 26. -0x78 26. -0x34 26. " IRQCE378 ,IRQ378 (waveform generator dead timer underflow 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 25. -0x78 25. -0x34 25. " IRQCE377 ,IRQ377 (waveform generator dead timer reload 0) channel enable setting bits" "Disabled,Enabled"
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|
setclrfld.long 0x0C 24. -0x78 24. -0x34 24. " IRQCE376 ,IRQ376 (waveform generator dead timer underflow 0) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x0C 23. -0x78 23. -0x34 23. " IRQCE375 ,IRQ375 (MVA1 free-run timer 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 22. -0x78 22. -0x34 22. " IRQCE374 ,IRQ374 (MVA0 free-run timer 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 21. -0x78 21. -0x34 21. " IRQCE373 ,IRQ373 (MVA1 calculation overtime error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 20. -0x78 20. -0x34 20. " IRQCE372 ,IRQ372 (MVA1 three-phase to two-phase DC value abnormality detection error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x0C 18. -0x78 18. -0x34 18. " IRQCE370 ,IRQ370 (MVA1 cumulative three-phase current abnormality detection error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 17. -0x78 17. -0x34 17. " IRQCE369 ,IRQ369 (MVA1 R/D converter diagnosis error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 16. -0x78 16. -0x34 16. " IRQCE368 ,IRQ368 (MVA1 calculation data update error interrupt) channel enable setting bits" "Disabled,Enabled"
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setclrfld.long 0x0C 15. -0x78 15. -0x34 15. " IRQCE367 ,IRQ367 (MVA1 failure detection error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x0C 14. -0x78 14. -0x34 14. " IRQCE366 ,IRQ366 (MVA1 floating-point non-normalized error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 13. -0x78 13. -0x34 13. " IRQCE365 ,IRQ365 (MVA1 underflow interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 12. -0x78 12. -0x34 12. " IRQCE364 ,IRQ364 (MVA1 overflow interrupt) channel enable setting bits" "Disabled,Enabled"
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setclrfld.long 0x0C 11. -0x78 11. -0x34 11. " IRQCE363 ,IRQ363 (MVA1 two-phase to three-phase AC conversion end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x0C 10. -0x78 10. -0x34 10. " IRQCE362 ,IRQ362 (MVA1 current to voltage conversion end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 9. -0x78 9. -0x34 9. " IRQCE361 ,IRQ361 (MVA1 PID control end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 8. -0x78 8. -0x34 8. " IRQCE360 ,IRQ360 (MVA1 three-phase to two-phase DC conversion end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 7. -0x78 7. -0x34 7. " IRQCE359 ,IRQ359 (MVA1 three-phase current normalization end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0C 6. -0x78 6. -0x34 6. " IRQCE358 ,IRQ358 (MVA1 angular calculation end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 5. -0x78 5. -0x34 5. " IRQCE357 ,IRQ357 (MVA0 calculation overtime error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 4. -0x78 4. -0x34 4. " IRQCE356 ,IRQ356 (MVA0 three-phase to two-phase DC value abnormality detection error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 2. -0x78 2. -0x34 2. " IRQCE354 ,IRQ354 (MVA0 cumulative three-phase current abnormality detection error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x0C 1. -0x78 1. -0x34 1. " IRQCE353 ,IRQ353 (MVA0 R/D converter diagnosis error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 0. -0x78 0. -0x34 0. " IRQCE352 ,IRQ352 (MVA0 calculation data update error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x10 "IRQCE12_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x10 31. -0x70 31. -0x30 31. " IRQCE415 ,IRQ415 (16-bit output compare ch.22, ch.23 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. -0x70 30. -0x30 30. " IRQCE414 ,IRQ414 (16-bit output compare ch.20, ch.21 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. -0x70 29. -0x30 29. " IRQCE413 ,IRQ413 (16-bit output compare ch.18, ch.19 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x10 28. -0x70 28. -0x30 28. " IRQCE412 ,IRQ412 (16-bit output compare ch.16, ch.17 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 27. -0x70 27. -0x30 27. " IRQCE411 ,IRQ411 (16-bit output compare ch.14, ch.15 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. -0x70 26. -0x30 26. " IRQCE410 ,IRQ410 (16-bit output compare ch.12, ch.13 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 25. -0x70 25. -0x30 25. " IRQCE409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. -0x70 24. -0x30 24. " IRQCE408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x10 25. -0x70 25. -0x30 25. " IRQCE409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. -0x70 24. -0x30 24. " IRQCE408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x10 23. -0x70 23. -0x30 23. " IRQCE407 ,IRQ407 (16-bit output compare ch.6, ch.7 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. -0x70 22. -0x30 22. " IRQCE406 ,IRQ406 (16-bit output compare ch.4, ch.5 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. -0x70 21. -0x30 21. " IRQCE405 ,IRQ405 (16-bit output compare ch.2, ch.3 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. -0x70 20. -0x30 20. " IRQCE404 ,IRQ404 (16-bit output compare ch.0, ch.1 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. -0x70 19. -0x30 19. " IRQCE403 ,IRQ403 (waveform generator DTTI 9, 10, 11) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. -0x70 18. -0x30 18. " IRQCE402 ,IRQ402 (waveform generator dead timer reload 11) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. -0x70 17. -0x30 17. " IRQCE401 ,IRQ401 (waveform generator dead timer underflow 11) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. -0x70 16. -0x30 16. " IRQCE400 ,IRQ400 (waveform generator dead timer reload 10) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 15. -0x70 15. -0x30 15. " IRQCE399 ,IRQ399 (waveform generator dead timer underflow 10) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. -0x70 14. -0x30 14. " IRQCE398 ,IRQ398 (waveform generator dead timer reload 9) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 13. -0x70 13. -0x30 13. " IRQCE397 ,IRQ397 (waveform generator dead timer underflow 9) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. -0x70 12. -0x30 12. " IRQCE396 ,IRQ396 (waveform generator DTTI 6, 7, 8) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 11. -0x70 11. -0x30 11. " IRQCE395 ,IRQ395 (waveform generator dead timer reload 8) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. -0x70 10. -0x30 10. " IRQCE394 ,IRQ394 (waveform generator dead timer underflow 8) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. -0x70 9. -0x30 9. " IRQCE393 ,IRQ393 (waveform generator dead timer reload 7) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. -0x70 8. -0x30 8. " IRQCE392 ,IRQ392 (waveform generator dead timer underflow 7) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. -0x70 7. -0x30 7. " IRQCE391 ,IRQ391 (waveform generator dead timer reload 6) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. -0x70 6. -0x30 6. " IRQCE390 ,IRQ390 (waveform generator dead timer underflow 6) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. -0x70 5. -0x30 5. " IRQCE389 ,IRQ389 (waveform generator DTTI 3, 4, 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. -0x70 4. -0x30 4. " IRQCE388 ,IRQ388 (waveform generator dead timer reload 5) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 3. -0x70 3. -0x30 3. " IRQCE387 ,IRQ387 (waveform generator dead timer underflow 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. -0x70 2. -0x30 2. " IRQCE386 ,IRQ386 (waveform generator dead timer reload 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 1. -0x70 1. -0x30 1. " IRQCE385 ,IRQ385 (waveform generator dead timer udnerflow 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. -0x70 0. -0x30 0. " IRQCE384 ,IRQ384 (waveform generator dead timer reload 3) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x14 "IRQCE13_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x14 31. -0x6C 31. -0x2C 31. " IRQCE447 ,IRQ447 (4ch A/D converter unit 0 conversion complete 3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. -0x6C 30. -0x2C 30. " IRQCE446 ,IRQ446 (4ch A/D converter unit 0 conversion complete 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. -0x6C 29. -0x2C 29. " IRQCE445 ,IRQ445 (4ch A/D converter unit 0 conversion complete 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. -0x6C 28. -0x2C 28. " IRQCE444 ,IRQ444 (4ch A/D converter unit 0 conversion complete 0) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 27. -0x6C 27. -0x2C 27. " IRQCE443 ,IRQ443 (up/down counter unit 3 comparison result match detection 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. -0x6C 26. -0x2C 26. " IRQCE442 ,IRQ442 (up/down counter unit 3 comparison result match detection 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 25. -0x6C 25. -0x2C 25. " IRQCE441 ,IRQ441 (up/down counter unit 3 comparison result match detection 3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. -0x6C 24. -0x2C 24. " IRQCE440 ,IRQ440 (up/down counter unit 3 comparison result match detection 2) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 23. -0x6C 23. -0x2C 23. " IRQCE439 ,IRQ439 (up/down counter unit 3 comparison result match detection 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. -0x6C 22. -0x2C 22. " IRQCE438 ,IRQ438 (up/down counter unit 3 comparison result match detection 0) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. -0x6C 21. -0x2C 21. " IRQCE437 ,IRQ437 (up/down counter unit 3 interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " IRQCE436 ,IRQ436 (up/down counter unit 2 comparison result match detection 5) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " IRQCE435 ,IRQ435 (up/down counter unit 2 comparison result match detection 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " IRQCE434 ,IRQ434 (up/down counter unit 2 comparison result match detection 3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. -0x6C 17. -0x2C 17. " IRQCE433 ,IRQ433 (up/down counter unit 2 comparison result match detection 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " IRQCE432 ,IRQ432 (up/down counter unit 2 comparison result match detection 1) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 15. -0x6C 15. -0x2C 15. " IRQCE431 ,IRQ431 (up/down counter unit 2 comparison result match detection 0) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. -0x6C 14. -0x2C 14. " IRQCE430 ,IRQ430 (up/down counter unit 2 interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 13. -0x6C 13. -0x2C 13. " IRQCE429 ,IRQ429 (up/down counter unit 1 comparison result match detection 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. -0x6C 12. -0x2C 12. " IRQCE428 ,IRQ428 (up/down counter unit 1 comparison result match detection 4) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 11. -0x6C 11. -0x2C 11. " IRQCE427 ,IRQ427 (up/down counter unit 1 comparison result match detection 3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. -0x6C 10. -0x2C 10. " IRQCE426 ,IRQ426 (up/down counter unit 1 comparison result match detection 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. -0x6C 9. -0x2C 9. " IRQCE425 ,IRQ425 (up/down counter unit 1 comparison result match detection 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. -0x6C 8. -0x2C 8. " IRQCE424 ,IRQ424 (up/down counter unit 1 comparison result match detection 0) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. -0x6C 7. -0x2C 7. " IRQCE423 ,IRQ423 (up/down counter unit 1 interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. -0x6C 6. -0x2C 6. " IRQCE422 ,IRQ422 (up/down counter unit 0 comparison result match detection 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. -0x6C 5. -0x2C 5. " IRQCE421 ,IRQ421 (up/down counter unit 0 comparison result match detection 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. -0x6C 4. -0x2C 4. " IRQCE420 ,IRQ420 (up/down counter unit 0 comparison result match detection 3) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 3. -0x6C 3. -0x2C 3. " IRQCE419 ,IRQ419 (up/down counter unit 0 comparison result match detection 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. -0x6C 2. -0x2C 2. " IRQCE418 ,IRQ418 (up/down counter unit 0 comparison result match detection 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 1. -0x6C 1. -0x2C 1. " IRQCE417 ,IRQ417 (up/down counter unit 0 comparison result match detection 0) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. -0x6C 0. -0x2C 0. " IRQCE416 ,IRQ416 (up/down counter unit 0 interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x18 "IRQCE14_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x18 31. -0x68 31. -0x28 31. " IRQCE479 ,IRQ479 (12-bit ADC conversion complete 9) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. -0x68 30. -0x28 30. " IRQCE478 ,IRQ478 (12-bit ADC conversion complete 8) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. -0x68 29. -0x28 29. " IRQCE477 ,IRQ477 (12-bit ADC conversion complete 7) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. -0x68 28. -0x28 28. " IRQCE476 ,IRQ476 (12-bit ADC conversion complete 6) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 27. -0x68 27. -0x28 27. " IRQCE475 ,IRQ475 (12-bit ADC conversion complete 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. -0x68 26. -0x28 26. " IRQCE474 ,IRQ474 (12-bit ADC conversion complete 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 25. -0x68 25. -0x28 25. " IRQCE473 ,IRQ473 (12-bit ADC conversion complete 3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. -0x68 24. -0x28 24. " IRQCE472 ,IRQ472 (12-bit ADC conversion complete 2) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 23. -0x68 23. -0x28 23. " IRQCE471 ,IRQ471 (12-bit ADC conversion complete 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. -0x68 22. -0x28 22. " IRQCE470 ,IRQ470 (12-bit ADC conversion complete 0) channel enable setting bits" "Disabled,Enabled"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x18 21. -0x68 21. -0x28 21. " IRQCE469 ,IRQ469 (16-bit input capture ch.14 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. -0x68 20. -0x28 20. " IRQCE468 ,IRQ468 (16-bit input capture ch.12, ch.13 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x18 20. -0x68 20. -0x28 20. " IRQCE468 ,IRQ468 (16-bit input capture ch.12 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x18 19. -0x68 19. -0x28 19. " IRQCE467 ,IRQ467 (16-bit input capture ch.10, ch.11 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. -0x68 18. -0x28 18. " IRQCE466 ,IRQ466 (16-bit input capture ch.8, ch.9 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. -0x68 17. -0x28 17. " IRQCE465 ,IRQ465 (16-bit input capture ch.6, ch.7 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. -0x68 16. -0x28 16. " IRQCE464 ,IRQ464 (16-bit input capture ch.4, ch.5 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 15. -0x68 15. -0x28 15. " IRQCE463 ,IRQ463 (16-bit input capture ch.2, ch.3 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. -0x68 14. -0x28 14. " IRQCE462 ,IRQ462 (16-bit input capture ch.0, ch.1 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 13. -0x68 13. -0x28 13. " IRQCE461 ,IRQ461 (4ch A/D converter unit 1 range comparison 0/1/2/3/4/5/6/7) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. -0x68 12. -0x28 12. " IRQCE460 ,IRQ460 (4ch A/D converter unit 1 conversion complete 7) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 11. -0x68 11. -0x28 11. " IRQCE459 ,IRQ459 (4ch A/D converter unit 1 conversion complete 6) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. -0x68 10. -0x28 10. " IRQCE458 ,IRQ458 (4ch A/D converter unit 1 conversion complete 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. -0x68 9. -0x28 9. " IRQCE457 ,IRQ457 (4ch A/D converter unit 1 conversion complete 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. -0x68 8. -0x28 8. " IRQCE456 ,IRQ456 (4ch A/D converter unit 1 conversion complete 3) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. -0x68 7. -0x28 7. " IRQCE455 ,IRQ455 (4ch A/D converter unit 1 conversion complete 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. -0x68 6. -0x28 6. " IRQCE454 ,IRQ454 (4ch A/D converter unit 1 conversion complete 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. -0x68 5. -0x28 5. " IRQCE453 ,IRQ453 (4ch A/D converter unit 1 conversion complete 0) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. -0x68 4. -0x28 4. " IRQCE452 ,IRQ452 (4ch A/D converter unit 0 range comparison 0/1/2/3/4/5/6/7) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 3. -0x68 3. -0x28 3. " IRQCE451 ,IRQ451 (4ch A/D converter unit 0 conversion complete 7) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. -0x68 2. -0x28 2. " IRQCE450 ,IRQ450 (4ch A/D converter unit 0 conversion complete 6) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 1. -0x68 1. -0x28 1. " IRQCE449 ,IRQ449 (4ch A/D converter unit 0 conversion complete 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. -0x68 0. -0x28 0. " IRQCE448 ,IRQ448 (4ch A/D converter unit 0 conversion complete 4) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x1C "IRQCE15_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x1C 28. -0x64 28. -0x24 28. " IRQCE508 ,IRQ508 (PLL alarm for FlexRay) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 27. -0x64 27. -0x24 27. " IRQCE507 ,IRQ507 (PLL gear for FlexRay) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 26. -0x64 26. -0x24 26. " IRQCE506 ,IRQ506 (12-bit ADC scan conversion complete) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 25. -0x64 25. -0x24 25. " IRQCE505 ,IRQ505 (12-bit ADC range comparison 24/25/26/27/28/29/30/31) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 24. -0x64 24. -0x24 24. " IRQCE504 ,IRQ504 (12-bit ADC range comparison 16/17/18/19/20/21/22/23) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 23. -0x64 23. -0x24 23. " IRQCE503 ,IRQ503 (12-bit ADC range comparison 8/9/10/11/12/13/14/15) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 22. -0x64 22. -0x24 22. " IRQCE502 ,IRQ502 (12-bit ADC range comparison 0/1/2/3/4/5/6/7) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 21. -0x64 21. -0x24 21. " IRQCE501 ,IRQ501 (12-bit ADC conversion complete 31) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 20. -0x64 20. -0x24 20. " IRQCE500 ,IRQ500 (12-bit ADC conversion complete 30) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 19. -0x64 19. -0x24 19. " IRQCE499 ,IRQ499 (12-bit ADC conversion complete 29) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 18. -0x64 18. -0x24 18. " IRQCE498 ,IRQ498 (12-bit ADC conversion complete 28) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 17. -0x64 17. -0x24 17. " IRQCE497 ,IRQ497 (12-bit ADC conversion complete 27) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 16. -0x64 16. -0x24 16. " IRQCE496 ,IRQ496 (12-bit ADC conversion complete 26) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 15. -0x64 15. -0x24 15. " IRQCE495 ,IRQ495 (12-bit ADC conversion complete 25) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 14. -0x64 14. -0x24 14. " IRQCE494 ,IRQ494 (12-bit ADC conversion complete 24) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 13. -0x64 13. -0x24 13. " IRQCE493 ,IRQ493 (12-bit ADC conversion complete 23) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 12. -0x64 12. -0x24 12. " IRQCE492 ,IRQ492 (12-bit ADC conversion complete 22) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 11. -0x64 11. -0x24 11. " IRQCE491 ,IRQ491 (12-bit ADC conversion complete 21) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 10. -0x64 10. -0x24 10. " IRQCE490 ,IRQ490 (12-bit ADC conversion complete 20) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 9. -0x64 9. -0x24 9. " IRQCE489 ,IRQ489 (12-bit ADC conversion complete 19) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 8. -0x64 8. -0x24 8. " IRQCE488 ,IRQ488 (12-bit ADC conversion complete 18) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 7. -0x64 7. -0x24 7. " IRQCE487 ,IRQ487 (12-bit ADC conversion complete 17) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 6. -0x64 6. -0x24 6. " IRQCE486 ,IRQ486 (12-bit ADC conversion complete 16) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 5. -0x64 5. -0x24 5. " IRQCE485 ,IRQ485 (12-bit ADC conversion complete 15) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 4. -0x64 4. -0x24 4. " IRQCE484 ,IRQ484 (12-bit ADC conversion complete 14) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 3. -0x64 3. -0x24 3. " IRQCE483 ,IRQ483 (12-bit ADC conversion complete 13) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 2. -0x64 2. -0x24 2. " IRQCE482 ,IRQ482 (12-bit ADC conversion complete 12) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 1. -0x64 1. -0x24 1. " IRQCE481 ,IRQ481 (12-bit ADC conversion complete 11) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 0. -0x64 0. -0x24 0. " IRQCE480 ,IRQ480 (12-bit ADC conversion complete 10) channel enable setting bits" "Disabled,Enabled"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0xC40++0x03
|
|
line.long 0x00 "NMIHC,IRC NMI Hold Clear Register"
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.long 0x00 0.--4. " NMIHCN ,Hold clear NMI channel number bits" "0,,,,4,5,6,7,8,9,,,,13,,,,,18,,,,,,24,25,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " NMIHCN ,Hold clear NMI channel number bits" "0,,,,4,5,6,7,8,9,,,,13,,,,,18,?..."
|
|
endif
|
|
rgroup.long 0xC44++0x03
|
|
line.long 0x00 "NMIHS,IRC NMI Hold Status Register"
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.long 0x00 25. " NMIHS25 ,NMI25 (R/D converter ch.1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " NMIHS24 ,NMI24 (R/D converter ch.0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 18. " NMIHS18 ,NMI6 (Time protection (TPU) protection violation) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 13. " NMIHS13 ,NMI5 (Memory protection (MPU) protection violation) hold status bits" "Not applied,Applied"
|
|
else
|
|
bitfld.long 0x00 18. " NMIHS18 ,NMI6 (Time protection (TPU) protection violation) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 13. " NMIHS13 ,NMI5 (Memory protection (MPU) protection violation) hold status bits" "Not applied,Applied"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " NMIHS9 ,NMI5 (CPU livelock)hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 8. " NMIHS8 ,NMI4 (IRC 2-bit ECC error detection) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 7. " NMIHS7 ,NMI7 (SW-WDT) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 6. " NMIHS6 ,NMI6 (HW-WDT) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NMIHS5 ,NMI5 (CSV/profile) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " NMIHS4 ,NMI4 (LVD) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 0. " NMIHS0 ,NMI0 (NMIX pin) hold status bits" "Not applied,Applied"
|
|
wgroup.long 0xC48++0x03
|
|
line.long 0x00 "IRQHC,IRC IRQ Hold Clear Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " IRQHCN ,Bits for IRQ channel number for which hold is to be cleared"
|
|
tree "IRQ Hold Status Register"
|
|
rgroup.long 0xC50++0x1B
|
|
line.long 0x00 "IRQHS0,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x00 31. " IRQHS31 ,IRQ31 (external interrupt ch.7) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 30. " IRQHS30 ,IRQ30 (external interrupt ch.6) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 29. " IRQHS29 ,IRQ29 (external interrupt ch.5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 28. " IRQHS28 ,IRQ28 (external interrupt ch.4) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQHS27 ,IRQ27 (external interrupt ch.3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 26. " IRQHS26 ,IRQ26 (external interrupt ch.2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 25. " IRQHS25 ,IRQ25 (external interrupt ch.1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " IRQHS24 ,IRQ24 (external interrupt ch.0) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IRQHS21 ,IRQ21 (WorkFLASH unit 1 1-bit error correction interrupt/ready interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " IRQHS20 ,IRQ20 (WorkFLASH unit 0 1-bit error correction interrupt/ready interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 16. " IRQHS16 ,IRQ16 (interrupt controller unit 0/1 ECC 1-bit error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 11. " IRQHS11 ,IRQ11 (WorkFLASH unit 1 hang interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQHS10 ,IRQ10 (WorkFLASH unit 0 hang interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 8. " IRQHS8 ,IRQ8 (TCFLASH unit 0/1 1-bit error correction interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 3. " IRQHS3 ,IRQ3 (SW-WDT unit 0/1 prior warning interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " IRQHS2 ,IRQ2 (HW-WDT prior warning interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQHS1 ,IRQ1 (LPC RUN profile update complete) hold status bits" "Not applied,Applied"
|
|
line.long 0x04 "IRQHS1,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x04 26. " IRQHS58 ,IRQ58 (CAN ch.2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x04 25. " IRQHS57 ,IRQ57 (CAN ch.1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x04 24. " IRQHS56 ,IRQ56 (CAN ch.0) hold status bits" "Not applied,Applied"
|
|
line.long 0x08 "IRQHS2,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x08 9. " IRQHS73 ,IRQ73 (multi-function serial interface ch.4 transmission complete) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 8. " IRQHS72 ,IRQ72 (multi-function serial interface ch.4 reception complete/status) hold status bits" "Not applied,Applied"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x08 7. " IRQHS71 ,IRQ71 (multi-function serial interface ch.3 transmission complete) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 6. " IRQHS70 ,IRQ70 (multi-function serial interface ch.3 reception complete/status) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IRQHS69 ,IRQ69 (multi-function serial interface ch.2 transmission complete) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 4. " IRQHS68 ,IRQ68 (multi-function serial interface ch.2 reception complete/status) hold status bits" "Not applied,Applied"
|
|
endif
|
|
bitfld.long 0x08 3. " IRQHS67 ,IRQ67 (multi-function serial interface ch.1 transmission complete) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 2. " IRQHS66 ,IRQ66 (multi-function serial interface ch.1 reception complete/status) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IRQHS65 ,IRQ65 (multi-function serial interface ch.0 transmission complete) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 0. " IRQHS64 ,IRQ64 (multi-function serial interface ch.0 reception complete/status) hold status bits" "Not applied,Applied"
|
|
line.long 0x0C "IRQHS3,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x0C 21. " IRQHS117 ,IRQ117 (CR calibration interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 14. " IRQHS110 ,IRQ110 (TCRAM unit 0/1 RAM diagnosis interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 0. " IRQHS96 ,IRQ96 (inter-processor communication (IPCU) Interrupt) hold status bits" "Not applied,Applied"
|
|
line.long 0x10 "IRQHS4,IRC IRQ Hold Status Register"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 11. " IRQHS139 ,IRQ139 (base timer ch.11 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 10. " IRQHS138 ,IRQ138 (base timer ch.10 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 9. " IRQHS137 ,IRQ137 (base timer ch.9 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 8. " IRQHS136 ,IRQ136 (base timer ch.8 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 7. " IRQHS135 ,IRQ135 (base timer ch.7 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 6. " IRQHS134 ,IRQ134 (base timer ch.6 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 5. " IRQHS133 ,IRQ133 (base timer ch.5 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 4. " IRQHS132 ,IRQ132 (base timer ch.4 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 3. " IRQHS131 ,IRQ131 (base timer ch.3 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 2. " IRQHS130 ,IRQ130 (base timer ch.2 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 1. " IRQHS129 ,IRQ129 (base timer ch.1 iRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 0. " IRQHS128 ,IRQ128 (base timer ch.0 iRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
line.long 0x14 "IRQHS5,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x14 20. " IRQHS180 ,IRQ180 (32-bit free-run timer ch.4 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 19. " IRQHS179 ,IRQ179 (32-bit free-run timer ch.3 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 18. " IRQHS178 ,IRQ178 (32-bit free-run timer ch.2 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 17. " IRQHS177 ,IRQ177 (32-bit free-run timer ch.1 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 16. " IRQHS176 ,IRQ176 (32-bit free-run timer ch.0 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
line.long 0x18 "IRQHS6,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x18 2. " IRQHS194 ,IRQ194 (32-bit input capture ch.4, ch.5 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 1. " IRQHS193 ,IRQ193 (32-bit input capture ch.2, ch.3 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 0. " IRQHS192 ,IRQ192 (32-bit input capture ch.0, ch.1 fetching) hold status bits" "Not applied,Applied"
|
|
rgroup.long 0xC70++0x1F
|
|
line.long 0x00 "IRQHS8,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x00 24. " IRQHS280 ,IRQ280 (DMAC ch.7, ch.15 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 23. " IRQHS279 ,IRQ279 (DMAC ch.6, ch.14 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 22. " IRQHS278 ,IRQ278 (DMAC ch.5, ch.13 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 21. " IRQHS277 ,IRQ277 (DMAC ch.4, ch.12 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 20. " IRQHS276 ,IRQ276 (DMAC ch.3, ch.11 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 19. " IRQHS275 ,IRQ275 (DMAC ch.2, ch.10 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 18. " IRQHS274 ,IRQ274 (DMAC ch.1, ch.9 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 17. " IRQHS273 ,IRQ273 (DMAC ch.0, ch.8 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQHS272 ,IRQ272 (DMAC transfer error interrupt) hold status bits" "Not applied,Applied"
|
|
line.long 0x04 "IRQHS9,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x04 24. " IRQHS312 ,IRQ312 (PMU interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x04 22. " IRQHS310 ,IRQ310 (main clock timer interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x04 21. " IRQHS309 ,IRQ309 (Slow-CR clock timer interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x04 20. " IRQHS308 ,IRQ308 (Fast-CR clock timer interrupt) hold status bits" "Not applied,Applied"
|
|
line.long 0x08 "IRQHS10,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x08 31. " IRQHS351 ,IRQ351 (MVA0 failure detection error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 30. " IRQHS350 ,IRQ350 (MVA0 floating-point non-normalized error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 29. " IRQHS349 ,IRQ349 (MVA0 underflow interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 28. " IRQHS348 ,IRQ348 (MVA0 overflow interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 27. " IRQHS347 ,IRQ347 (MVA0 two-phase to three-phase AC conversion end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 26. " IRQHS346 ,IRQ346 (MVA0 current to voltage conversion end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 25. " IRQHS345 ,IRQ345 (MVA0 PID control end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 24. " IRQHS344 ,IRQ344 (MVA0 three-phase to two-phase DC conversion end interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 23. " IRQHS343 ,IRQ343 (MVA0 three-phase current normalization end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 22. " IRQHS342 ,IRQ342 (MVA0 angular calculation end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 21. " IRQHS341 ,IRQ341 (16-bit free-run timer ch.17 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 20. " IRQHS340 ,IRQ340 (16-bit free-run timer ch.16 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IRQHS339 ,IRQ339 (16-bit free-run timer ch.15 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 18. " IRQHS338 ,IRQ338 (16-bit free-run timer ch.14 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 17. " IRQHS337 ,IRQ337 (16-bit free-run timer ch.13 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 16. " IRQHS336 ,IRQ336 (16-bit free-run timer ch.12 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 15. " IRQHS335 ,IRQ335 (16-bit free-run timer ch.11 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 14. " IRQHS334 ,IRQ334 (16-bit free-run timer ch.10 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 13. " IRQHS333 ,IRQ333 (16-bit free-run timer ch.9 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 12. " IRQHS332 ,IRQ332 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 11. " IRQHS331 ,IRQ331 (16-bit free-run timer ch.7 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 10. " IRQHS330 ,IRQ330 (16-bit free-run timer ch.6 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 9. " IRQHS329 ,IRQ329 (16-bit free-run timer ch.5 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 8. " IRQHS328 ,IRQ328 (16-bit free-run timer ch.4 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IRQHS327 ,IRQ327 (16-bit Free-run timer ch.3 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 6. " IRQHS326 ,IRQ326 (16-bit free-run timer ch.2 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 5. " IRQHS5325 ,IRQ325 (16-bit free-run timer ch.1 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 4. " IRQHS324 ,IRQ324 (16-bit free-run timer ch.0 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
textline " "
|
|
bitfld.long 0x08 3. " IRQHS323 ,IRQ323 (FlexRay Timer 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 2. " IRQHS222 ,IRQ322 (FlexRay Timer 0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 1. " IRQHS321 ,IRQ321 (FlexRay1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 0. " IRQHS320 ,IRQ320 (FlexRay0) hold status bits" "Not applied,Applied"
|
|
endif
|
|
line.long 0x0C "IRQHS11,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x0C 31. " IRQHS383 ,IRQ383 (waveform generator dead timer underflow 3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 30. " IRQHS382 ,IRQ382 (waveform generator DTTI 0, 1, 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 29. " IRQHS381 ,IRQ381 (waveform generator dead timer reload 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 28. " IRQHS380 ,IRQ380 (waveform generator dead timer underflow 2) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " IRQHS379 ,IRQ379 (waveform generator dead timer reload 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 26. " IRQHS378 ,IRQ378 (waveform generator dead timer underflow 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 25. " IRQHS377 ,IRQ377 (waveform generator dead timer reload 0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 24. " IRQHS376 ,IRQ376 (waveform generator dead timer underflow 0) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " IRQHS375 ,IRQ375 (MVA1 free-run timer 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 22. " IRQHS374 ,IRQ374 (MVA0 free-run timer 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 21. " IRQHS373 ,IRQ373 (MVA1 calculation overtime error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 20. " IRQHS372 ,IRQ372 (MVA1 three-phase to two-phase DC value abnormality detection error interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " IRQHS370 ,IRQ370 (MVA1 cumulative three-phase current abnormality detection error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 17. " IRQHS369 ,IRQ369 (MVA1 R/D converter diagnosis error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 16. " IRQHS368 ,IRQ368 (MVA1 calculation data update error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 15. " IRQHS367 ,IRQ367 (MVA1 failure detection error interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " IRQHS366 ,IRQ366 (MVA1 floating-point non-normalized error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 13. " IRQHS365 ,IRQ365 (MVA1 underflow interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 12. " IRQHS364 ,IRQ364 (MVA1 overflow interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 11. " IRQHS363 ,IRQ363 (MVA1 two-phase to three-phase AC conversion end interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " IRQHS362 ,IRQ362 (MVA1 current to voltage conversion end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 9. " IRQHS361 ,IRQ361 (MVA1 PID control end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 8. " IRQHS360 ,IRQ360 (MVA1 three-phase to two-phase DC conversion end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 7. " IRQHS359 ,IRQ359 (MVA1 three-phase current normalization end interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " IRQHS358 ,IRQ358 (MVA1 angular calculation end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 5. " IRQHS357 ,IRQ357 (MVA0 calculation overtime error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 4. " IRQHS356 ,IRQ356 (MVA0 three-phase to two-phase DC value abnormality detection error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 2. " IRQHS354 ,IRQ354 (MVA0 cumulative three-phase current abnormality detection error interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " IRQHS353 ,IRQ353 (MVA0 R/D converter diagnosis error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 0. " IRQHS352 ,IRQ352 (MVA0 calculation data update error interrupt) hold status bits" "Not applied,Applied"
|
|
line.long 0x10 "IRQHS12,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x10 31. " IRQHS415 ,IRQ415 (16-bit output compare ch.22, ch.23 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 30. " IRQHS414 ,IRQ414 (16-bit output compare ch.20, ch.21 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 29. " IRQHS413 ,IRQ413 (16-bit output compare ch.18, ch.19 compare match) hold status bits" "Not applied,Applied"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 28. " IRQHS412 ,IRQ412 (16-bit output compare ch.16, ch.17 compare match) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x10 27. " IRQHS411 ,IRQ411 (16-bit output compare ch.14, ch.15 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 26. " IRQHS410 ,IRQ410 (16-bit output compare ch.12, ch.13 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 25. " IRQHS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 24. " IRQHS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) hold status bits" "Not applied,Applied"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x10 25. " IRQHS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 24. " IRQHS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) hold status bits" "Not applied,Applied"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 23. " IRQHS407 ,IRQ407 (16-bit output compare ch.6, ch.7 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 22. " IRQHS406 ,IRQ406 (16-bit output compare ch.4, ch.5 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 21. " IRQHS405 ,IRQ405 (16-bit output compare ch.2, ch.3 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 20. " IRQHS404 ,IRQ404 (16-bit output compare ch.0, ch.1 compare match) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x10 19. " IRQHS403 ,IRQ403 (waveform generator DTTI 9, 10, 11) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 18. " IRQHS402 ,IRQ402 (waveform generator dead timer reload 11) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 17. " IRQHS401 ,IRQ401 (waveform generator dead timer underflow 11) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 16. " IRQHS400 ,IRQ400 (waveform generator dead timer reload 10) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x10 15. " IRQHS399 ,IRQ399 (waveform generator dead timer underflow 10) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 14. " IRQHS398 ,IRQ398 (waveform generator dead timer reload 9) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 13. " IRQHS397 ,IRQ397 (waveform generator dead timer underflow 9) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 12. " IRQHS396 ,IRQ396 (waveform generator DTTI 6, 7, 8) hold status bits" "not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x10 11. " IRQHS395 ,IRQ395 (waveform generator dead timer reload 8) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 10. " IRQHS394 ,IRQ394 (waveform generator dead timer underflow 8) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 9. " IRQHS393 ,IRQ393 (waveform generator dead timer reload 7) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 8. " IRQHS392 ,IRQ392 (waveform generator dead timer underflow 7) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x10 7. " IRQHS391 ,IRQ391 (waveform generator dead timer reload 6) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 6. " IRQHS390 ,IRQ390 (waveform generator dead timer underflow 6) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 5. " IRQHS389 ,IRQ389 (waveform generator DTTI 3, 4, 5) hold status bits" "not applied,Applied"
|
|
bitfld.long 0x10 4. " IRQHS388 ,IRQ388 (waveform generator dead timer reload 5) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x10 3. " IRQHS387 ,IRQ387 (waveform generator dead timer underflow 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 2. " IRQHS386 ,IRQ386 (waveform generator dead timer reload 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 1. " IRQHS385 ,IRQ385 (waveform generator dead timer underflow 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 0. " IRQHS384 ,IRQ384 (waveform generator dead timer reload 3) hold status bits" "Not applied,Applied"
|
|
line.long 0x14 "IRQHS13,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x14 31. " IRQHS447 ,IRQ447 (4ch A/D converter unit 0 conversion complete 3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 30. " IRQHS446 ,IRQ446 (4ch A/D converter unit 0 conversion complete 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 29. " IRQHS445 ,IRQ445 (4ch A/D converter unit 0 conversion complete 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 28. " IRQHS444 ,IRQ444 (4ch A/D converter unit 0 conversion complete 0) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 27. " IRQHS443 ,IRQ443 (up/down counter unit 3 comparison result match detection 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 26. " IRQHS442 ,IRQ442 (up/down counter unit 3 comparison result match detection 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 25. " IRQHS441 ,IRQ441 (up/down counter unit 3 comparison result match detection 3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 24. " IRQHS440 ,IRQ440 (up/down counter unit 3 comparison result match detection 2) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 23. " IRQHS439 ,IRQ439 (up/down counter unit 3 comparison result match detection 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 22. " IRQHS438 ,IRQ438 (up/down counter unit 3 comparison result match detection 0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 21. " IRQHS437 ,IRQ437 (up/down counter unit 3 interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 20. " IRQHS436 ,IRQ436 (up/down counter unit 2 comparison result match detection 5) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 19. " IRQHS435 ,IRQ435 (up/down counter unit 2 comparison result match detection 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 18. " IRQHS434 ,IRQ434 (up/down counter unit 2 comparison result match detection 3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 17. " IRQHS433 ,IRQ433 (up/down counter unit 2 comparison result match detection 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 16. " IRQHS432 ,IRQ432 (up/down counter unit 2 comparison result match detection 1) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 15. " IRQHS431 ,IRQ331 (up/down counter unit 2 comparison result match detection 0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 14. " IRQHS430 ,IRQ430 (up/down counter unit 2 interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 13. " IRQHS429 ,IRQ429 (up/down counter unit 1 comparison result match detection 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 12. " IRQHS428 ,IRQ428 (up/down counter unit 1 comparison result match detection 4) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 11. " IRQHS427 ,IRQ427 (up/down counter unit 1 comparison result match detection 3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 10. " IRQHS426 ,IRQ426 (up/down counter unit 1 comparison result match detection 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 9. " IRQHS425 ,IRQ425 (up/down counter unit 1 comparison result match detection 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 8. " IRQHS424 ,IRQ424 (up/down counter unit 1 comparison result match detection 0) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 7. " IRQHS423 ,IRQ423 (up/down counter unit 1 interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 6. " IRQHS422 ,IRQ422 (up/down counter unit 0 comparison result match detection 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 5. " IRQHS421 ,IRQ421 (up/down counter unit 0 comparison result match detection 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 4. " IRQHS420 ,IRQ420 (up/down counter unit 0 comparison result match detection 3) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 3. " IRQHS419 ,IRQ419 (up/down counter unit 0 comparison result match detection 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 2. " IRQHS418 ,IRQ418 (up/down counter unit 0 comparison result match detection 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 1. " IRQHS417 ,IRQ417 (up/down counter unit 0 comparison result match detection 0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 0. " IRQHS416 ,IRQ416 (up/down counter unit 0 interrupt) hold status bits" "Not applied,Applied"
|
|
line.long 0x18 "IRQHS14,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x18 31. " IRQHS479 ,IRQ479 (12-bit ADC conversion complete 9) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 30. " IRQHS478 ,IRQ478 (12-bit ADC conversion complete 8) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 29. " IRQHS477 ,IRQ477 (12-bit ADC conversion complete 7) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 28. " IRQHS476 ,IRQ476 (12-bit ADC conversion complete 6) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x18 27. " IRQHS475 ,IRQ475 (12-bit ADC conversion complete 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 26. " IRQHS474 ,IRQ474 (12-bit ADC conversion complete 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 25. " IRQHS473 ,IRQ473 (12-bit ADC conversion complete 3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 24. " IRQHS472 ,IRQ472 (12-bit ADC conversion complete 2) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x18 23. " IRQHS471 ,IRQ471 (12-bit ADC conversion complete 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 22. " IRQHS470 ,IRQ470 (12-bit ADC conversion complete 0) hold status bits" "Not applied,Applied"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x18 21. " IRQHS469 ,IRQ469 (16-bit input capture ch.14 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 20. " IRQHS468 ,IRQ468 (16-bit input capture ch.12, ch.13 fetching) hold status bits" "Not applied,Applied"
|
|
else
|
|
bitfld.long 0x18 20. " IRQHS468 ,IRQ468 (16-bit input capture ch.12 fetching) hold status bits" "Not applied,Applied"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 19. " IRQHS467 ,IRQ467 (16-bit input capture ch.10, ch.11 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 18. " IRQHS466 ,IRQ466 (16-bit input capture ch.8, ch.9 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 17. " IRQHS465 ,IRQ465 (16-bit input capture ch.6, ch.7 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 16. " IRQHS464 ,IRQ464 (16-bit input capture ch.4, ch.5 fetching) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x18 15. " IRQHS463 ,IRQ463 (16-bit input capture ch.2, ch.3 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 14. " IRQHS462 ,IRQ462 (16-bit input capture ch.0, ch.1 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 13. " IRQHS461 ,IRQ461 (4ch A/D converter unit 1 range comparison 0/1/2/3/4/5/6/7) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 12. " IRQHS460 ,IRQ460 (4ch A/D converter unit 1 conversion complete 7) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x18 11. " IRQHS459 ,IRQ459 (4ch A/D converter unit 1 conversion complete 6) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 10. " IRQHS458 ,IRQ458 (4ch A/D converter unit 1 conversion complete 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 9. " IRQHS457 ,IRQ457 (4ch A/D converter unit 1 conversion complete 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 8. " IRQHS456 ,IRQ456 (4ch A/D converter unit 1 conversion complete 3) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x18 7. " IRQHS455 ,IRQ455 (4ch A/D converter unit 1 conversion complete 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 6. " IRQHS454 ,IRQ454 (4ch A/D converter unit 1 conversion complete 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 5. " IRQHS453 ,IRQ453 (4ch A/D converter unit 1 conversion complete 0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 4. " IRQHS452 ,IRQ452 (4ch A/D converter unit 0 range comparison 0/1/2/3/4/5/6/7) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x18 3. " IRQHS451 ,IRQ451 (4ch A/D converter unit 0 conversion complete 7) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 2. " IRQHS450 ,IRQ450 (4ch A/D converter unit 0 conversion complete 6) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 1. " IRQHS449 ,IRQ449 (4ch A/D converter unit 0 conversion complete 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 0. " IRQHS448 ,IRQ448 (4ch A/D converter unit 0 conversion complete 4) hold status bits" "Not applied,Applied"
|
|
line.long 0x1C "IRQHS15,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x1C 28. " IRQHS508 ,IRQ508 (PLL alarm for FlexRay) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 27. " IRQHS507 ,IRQ507 (PLL gear for FlexRay) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 26. " IRQHS506 ,IRQ506 (12-bit ADC scan conversion complete) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 25. " IRQHS505 ,IRQ505 (12-bit ADC range comparison 24/25/26/27/28/29/30/31) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " IRQHS504 ,IRQ504 (12-bit ADC range comparison 16/17/18/19/20/21/22/23) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 23. " IRQHS503 ,IRQ503 (12-bit ADC range comparison 8/9/10/11/12/13/14/15) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 22. " IRQHS502 ,IRQ502 (12-bit ADC range comparison 0/1/2/3/4/5/6/7) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 21. " IRQHS501 ,IRQ501 (12-bit ADC conversion complete 31) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " IRQHS500 ,IRQ500 (12-bit ADC conversion complete 30) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 19. " IRQHS499 ,IRQ499 (12-bit ADC conversion complete 29) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 18. " IRQHS498 ,IRQ498 (12-bit ADC conversion complete 28) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 17. " IRQHS497 ,IRQ497 (12-bit ADC conversion complete 27) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 16. " IRQHS496 ,IRQ496 (12-bit ADC conversion complete 26) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 15. " IRQHS495 ,IRQ495 (12-bit ADC conversion complete 25) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 14. " IRQHS494 ,IRQ494 (12-bit ADC conversion complete 24) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 13. " IRQHS493 ,IRQ493 (12-bit ADC conversion complete 23) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " IRQHS492 ,IRQ492 (12-bit ADC conversion complete 22) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 11. " IRQHS491 ,IRQ491 (12-bit ADC conversion complete 21) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 10. " IRQHS490 ,IRQ490 (12-bit ADC conversion complete 20) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 9. " IRQHS489 ,IRQ489 (12-bit ADC conversion complete 19) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " IRQHS488 ,IRQ488 (12-bit ADC conversion complete 18) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 7. " IRQHS487 ,IRQ487 (12-bit ADC conversion complete 17) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 6. " IRQHS486 ,IRQ486 (12-bit ADC conversion complete 16) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 5. " IRQHS485 ,IRQ485 (12-bit ADC conversion complete 15) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " IRQHS484 ,IRQ484 (12-bit ADC conversion complete 14) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 3. " IRQHS483 ,IRQ483 (12-bit ADC conversion complete 13) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 2. " IRQHS482 ,IRQ482 (12-bit ADC conversion complete 12) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 1. " IRQHS481 ,IRQ481 (12-bit ADC conversion complete 11) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " IRQHS480 ,IRQ480 (12-bit ADC conversion complete 10) hold status bits" "Not applied,Applied"
|
|
tree.end
|
|
textline " "
|
|
group.long 0xC90++0x03
|
|
line.long 0x00 "IRQPLM,IRC IRQ Priority Level Mask Register"
|
|
bitfld.long 0x00 0.--5. " IRQPLM ,IRQ priority level mask bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xC98++0x03
|
|
line.long 0x00 "CSR,IRC Control/Status Register"
|
|
rbitfld.long 0x00 16. " LST ,Interrupt controller lock status" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " IRQEN ,IRQ processing block enable/disable setting bit" "Disabled,Enabled"
|
|
rgroup.long 0xCA8++0x03
|
|
line.long 0x00 "NMIRS,IRC NMI RAW Status Register"
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.long 0x00 25. " NMIRS25 ,RAW status bits for NMI25 (R/D converter ch.1)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " NMIRS24 ,RAW status bits for NMI24 (R/D converter ch.0)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " NMIRS18 ,RAW status bits for NMI6 (Time protection (TPU) protection violation)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " NMIRS13 ,RAW status bits for NMI5 (Memory protection (MPU) protection violation)" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 18. " NMIRS18 ,RAW status bits for NMI6 (Time protection (TPU) protection violation)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " NMIRS13 ,RAW status bits for NMI5 (Memory protection (MPU) protection violation)" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " NMIRS9 ,RAW status bits for NMI5 (CPU livelock)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " NMIRS8 ,RAW status bits for NMI4 (IRC 2-bit ECC error detection)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " NMIRS7 ,RAW status bits for NMI7 (SW-WDT)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " NMIRS6 ,RAW status bits for NMI6 (HW-WDT)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NMIRS5 ,RAW status bits for NMI5 (CSV/profile)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " NMIRS4 ,RAW status bits for NMI4 (LVD)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " NMIRS0 ,RAW status bits for NMI0 (NMIX pin)" "No interrupt,Interrupt"
|
|
rgroup.long 0xCAC++0x03
|
|
line.long 0x00 "NMIPS,IRC NMI Preprocessed Status Register"
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.long 0x00 25. " NMIPS25 ,Preprocessed status bits for NMI25 (R/D converter ch.1)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " NMIPS24 ,Preprocessed status bits for NMI24 (R/D converter ch.0)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " NMIPS18 ,Preprocessed status bits for NMI6 (Time protection (TPU) protection violation)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " NMIPS13 ,Preprocessed status bits for NMI5 (Memory protection (MPU) protection violation)" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 18. " NMIPS18 ,Preprocessed status bits for NMI6 (Time protection (TPU) protection violation)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " NMIPS13 ,Preprocessed status bits for NMI5 (Memory protection (MPU) protection violation)" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " NMIPS9 ,Preprocessed status bits for NMI5 (CPU livelock)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " NMIPS8 ,Preprocessed status bits for NMI4 (IRC 2-bit ECC error detection)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " NMIPS7 ,Preprocessed status bits for NMI7 (SW-WDT)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " NMIPS6 ,Preprocessed status bits for NMI6 (HW-WDT)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NMIPS5 ,Preprocessed status bits for NMI5 (CSV/profile)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " NMIPS4 ,Preprocessed status bits for NMI4 (LVD)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " NMIPS0 ,Preprocessed status bits for NMI0 (NMIX pin)" "No interrupt,Interrupt"
|
|
tree "IRC IRQ RAW Status Register"
|
|
rgroup.long 0xCB0++0x1B
|
|
line.long 0x00 "IRQRS0,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x00 31. " IRQRS31 ,IRQ31 (external interrupt ch.7) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQRS30 ,IRQ30 (external interrupt ch.6) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQRS29 ,IRQ29 (external interrupt ch.5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQRS28 ,IRQ28 (external interrupt ch.4) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQRS27 ,IRQ27 (external interrupt ch.3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQRS26 ,IRQ26 (external interrupt ch.2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQRS25 ,IRQ25 (external interrupt ch.1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQRS24 ,IRQ24 (external interrupt ch.0) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IRQRS21 ,IRQ21 (WorkFLASH unit 1 1-bit error correction interrupt/ready interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQRS20 ,IRQ20 (WorkFLASH unit 0 1-bit error correction interrupt/ready interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQRS16 ,IRQ16 (interrupt controller unit 0/1 ECC 1-bit error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " IRQRS11 ,IRQ11 (WorkFLASH unit 1 hang interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQRS10 ,IRQ10 (WorkFLASH unit 0 hang interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQRS8 ,IRQ8 (TCFLASH unit 0/1 1-bit error correction interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " IRQRS3 ,IRQ3 (SW-WDT unit 0/1 prior warning interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQRS2 ,IRQ2 (HW-WDT prior warning interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQRS1 ,IRQ1 (LPC RUN profile update complete) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQRS1,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x04 26. " IRQRS58 ,IRQ58 (CAN ch.2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " IRQRS57 ,IRQ57 (CAN ch.1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " IRQRS56 ,IRQ56 (CAN ch.0) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQRS2,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x08 9. " IRQRS73 ,IRQ73 (multi-function serial interface ch.4 transmission complete) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " IRQRS72 ,IRQ72 (multi-function serial interface ch.4 reception complete/status) RAW status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x08 7. " IRQRS71 ,IRQ71 (multi-function serial interface ch.3 transmission complete) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " IRQRS70 ,IRQ70 (multi-function serial interface ch.3 reception complete/status) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IRQRS69 ,IRQ69 (multi-function serial interface ch.2 transmission complete) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " IRQRS68 ,IRQ68 (multi-function serial interface ch.2 reception complete/status) RAW status bits" "No interrupt,Interrupt"
|
|
endif
|
|
bitfld.long 0x08 3. " IRQRS67 ,IRQ67 (multi-function serial interface ch.1 transmission complete) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " IRQRS66 ,IRQ66 (multi-function serial interface ch.1 reception complete/status) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IRQRS65 ,IRQ65 (multi-function serial interface ch.0 transmission complete) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " IRQRS64 ,IRQ64 (multi-function serial interface ch.0 reception complete/status) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x0C "IRQRS3,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x0C 21. " IRQRS117 ,IRQ117 (CR calibration interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 14. " IRQRS110 ,IRQ110 (TCRAM unit 0/1 RAM diagnosis interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " IRQRS96 ,IRQ96 (inter-processor Communication (IPCU) Interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x10 "IRQRS4,IRC IRQ RAW Status Register"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 11. " IRQRS139 ,IRQ139 (base timer ch.11 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 10. " IRQRS138 ,IRQ138 (base timer ch.10 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 9. " IRQRS137 ,IRQ137 (base timer ch.9 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 8. " IRQRS136 ,IRQ136 (base timer ch.8 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 7. " IRQRS135 ,IRQ135 (base timer ch.7 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 6. " IRQRS134 ,IRQ134 (base timer ch.6 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 5. " IRQRS133 ,IRQ133 (base timer ch.5 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " IRQRS132 ,IRQ132 (base timer ch.4 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 3. " IRQRS131 ,IRQ131 (base timer ch.3 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " IRQRS130 ,IRQ130 (base timer ch.2 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 1. " IRQRS129 ,IRQ129 (base timer ch.1 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " IRQRS128 ,IRQ128 (base timer ch.0 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x14 "IRQRS5,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x14 20. " IRQRS180 ,IRQ180 (32-bit free-run timer ch.4 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 19. " IRQRS179 ,IRQ179 (32-bit free-run timer ch.3 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 18. " IRQRS178 ,IRQ178 (32-bit free-run timer ch.2 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 17. " IRQRS177 ,IRQ177 (32-bit free-run timer ch.1 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 16. " IRQRS176 ,IRQ176 (32-bit free-run timer ch.0 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x18 "IRQRS6,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x18 2. " IRQRS194 ,IRQ194 (32-bit input capture ch.4, ch.5 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 1. " IRQRS193 ,IRQ193 (32-bit input capture ch.2, ch.3 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 0. " IRQRS192 ,IRQ192 (32-bit input capture ch.0, ch.1 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
rgroup.long 0xCD0++0x1F
|
|
line.long 0x00 "IRQRS8,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x00 24. " IRQRS280 ,IRQ280 (DMAC ch.7, ch.15 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " IRQRS279 ,IRQ279 (DMAC ch.6, ch.14 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQRS278 ,IRQ278 (DMAC ch.5, ch.13 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQRS277 ,IRQ277 (DMAC ch.4, ch.12 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " IRQRS276 ,IRQ276 (DMAC ch.3, ch.11 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " IRQRS275 ,IRQ275 (DMAC ch.2, ch.10 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQRS274 ,IRQ274 (DMAC ch.1, ch.9 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQRS273 ,IRQ273 (DMAC ch.0, ch.8 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQRS272 ,IRQ272 (DMAC transfer error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQRS9,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x04 24. " IRQRS312 ,IRQ312 (PMU interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " IRQRS310 ,IRQ310 (main clock timer interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " IRQRS309 ,IRQ309 (Slow-CR clock timer interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " IRQRS308 ,IRQ308 (Fast-CR clock timer interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQRS10,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x08 31. " IRQRS351 ,IRQ351 (MVA0 failure detection error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 30. " IRQRS350 ,IRQ350 (MVA0 floating-point non-normalized error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 29. " IRQRS349 ,IRQ349 (MVA0 underflow interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 28. " IRQRS348 ,IRQ348 (MVA0 overflow interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 27. " IRQRS347 ,IRQ347 (MVA0 two-phase to three-phase AC conversion end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 26. " IRQRS346 ,IRQ346 (MVA0 current to voltage conversion end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 25. " IRQRS345 ,IRQ345 (MVA0 PID control end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 24. " IRQRS344 ,IRQ344 (MVA0 three-phase to two-phase DC conversion end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 23. " IRQRS343 ,IRQ343 (MVA0 three-phase current normalization end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 22. " IRQRS342 ,IRQ342 (MVA0 angular calculation end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 21. " IRQRS341 ,IRQ341 (16-bit free-run timer ch.17 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 20. " IRQRS340 ,IRQ340 (16-bit free-run timer ch.16 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IRQRS339 ,IRQ339 (16-bit free-run timer ch.15 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 18. " IRQRS338 ,IRQ338 (16-bit free-run timer ch.14 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 17. " IRQRS337 ,IRQ337 (16-bit free-run timer ch.13 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16. " IRQRS336 ,IRQ336 (16-bit free-run timer ch.12 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 15. " IRQRS335 ,IRQ335 (16-bit free-run timer ch.11 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 14. " IRQRS334 ,IRQ334 (16-bit free-run timer ch.10 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 13. " IRQRS333 ,IRQ333 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 12. " IRQRS332 ,IRQ332 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 11. " IRQRS331 ,IRQ331 (16-bit free-run timer ch.7 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 10. " IRQRS330 ,IRQ330 (16-bit free-run timer ch.6 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 9. " IRQRS329 ,IRQ329 (16-bit free-run timer ch.5 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " IRQRS328 ,IRQ328 (16-bit free-run timer ch.4 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IRQRS327 ,IRQ327 (16-bit free-run timer ch.3 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " IRQRS326 ,IRQ326 (16-bit free-run timer ch.2 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 5. " IRQRS325 ,IRQ325 (16-bit free-run timer ch.1 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " IRQRS324 ,IRQ324 (16-bit free-run timer ch.0 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
textline " "
|
|
bitfld.long 0x08 3. " IRQRS323 ,IRQ323 (FlexRay timer 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " IRQRS222 ,IRQ322 (FlexRay timer 0) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 1. " IRQRS321 ,IRQ321 (FlexRay1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " IRQRS320 ,IRQ320 (FlexRay0) RAW status bits" "No interrupt,Interrupt"
|
|
endif
|
|
line.long 0x0C "IRQRS11,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x0C 31. " IRQRS383 ,IRQ383 (waveform generator dead timer underflow 3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 30. " IRQRS382 ,IRQ382 (waveform generator DTTI 0, 1, 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 29. " IRQRS381 ,IRQ381 (waveform generator dead timer reload 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 28. " IRQRS380 ,IRQ380 (waveform generator dead timer underflow 2) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " IRQRS379 ,IRQ379 (waveform generator dead timer reload 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 26. " IRQRS378 ,IRQ378 (waveform generator dead timer underflow 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 25. " IRQRS377 ,IRQ377 (waveform generator dead timer reload 0) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 24. " IRQRS376 ,IRQ376 (waveform generator dead timer underflow 0) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " IRQRS375 ,IRQ375 (MVA1 free-run timer 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 22. " IRQRS374 ,IRQ374 (MVA0 free-run timer 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 21. " IRQRS373 ,IRQ373 (MVA1 calculation overtime error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 20. " IRQRS372 ,IRQ372 (MVA1 three-phase to two-phase DC value abnormality detection error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " IRQRS370 ,IRQ370 (MVA1 cumulative three-phase current abnormality detection error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 17. " IRQRS369 ,IRQ369 (MVA1 R/D converter diagnosis error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16. " IRQRS368 ,IRQ368 (MVA1 calculation data update error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 15. " IRQRS367 ,IRQ367 (MVA1 failure detection error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " IRQRS366 ,IRQ366 (MVA1 floating-point non-normalized error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 13. " IRQRS365 ,IRQ365 (MVA1 underflow interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 12. " IRQRS364 ,IRQ364 (MVA1 overflow interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 11. " IRQRS363 ,IRQ363 (MVA1 two-phase to three-phase AC conversion end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " IRQRS362 ,IRQ362 (MVA1 current to voltage conversion end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 9. " IRQRS361 ,IRQ361 (MVA1 PID control end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 8. " IRQRS360 ,IRQ360 (MVA1 three-phase to two-phase DC conversion end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 7. " IRQRS359 ,IRQ359 (MVA1 three-phase current normalization end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " IRQRS358 ,IRQ358 (MVA1 angular calculation end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 5. " IRQRS357 ,IRQ357 (MVA0 calculation overtime error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " IRQRS356 ,IRQ356 (MVA0 three-phase to two-phase DC value abnormality detection error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " IRQRS354 ,IRQ354 (MVA0 cumulative three-phase current abnormality detection error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " IRQRS353 ,IRQ353 (MVA0 R/D converter diagnosis error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " IRQRS352 ,IRQ352 (MVA0 calculation data update error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x10 "IRQRS12,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x10 31. " IRQRS415 ,IRQ415 (16-bit output compare ch.22, ch.23 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 30. " IRQRS414 ,IRQ414 (16-bit output compare ch.20, ch.21 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 29. " IRQRS413 ,IRQ413 (16-bit output compare ch.18, ch.19 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 28. " IRQRS412 ,IRQ412 (16-bit output compare ch.16, ch.17 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 27. " IRQRS411 ,IRQ411 (16-bit output compare ch.14, ch.15 compare Match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 26. " IRQRS410 ,IRQ410 (16-bit output compare ch.12, ch.13 compare Match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 25. " IRQRS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 24. " IRQRS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x10 25. " IRQRS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 24. " IRQRS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 23. " IRQRS407 ,IRQ407 (16-bit output compare ch.6, ch.7 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 22. " IRQRS406 ,IRQ406 (16-bit output compare ch.4, ch.5 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 21. " IRQRS405 ,IRQ405 (16-bit output compare ch.2, ch.3 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 20. " IRQRS404 ,IRQ404 (16-bit output compare ch.0, ch.1 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 19. " IRQRS403 ,IRQ403 (waveform generator DTTI 9, 10, 11) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 18. " IRQRS402 ,IRQ402 (waveform generator dead timer reload 11) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 17. " IRQRS401 ,IRQ401 (waveform generator dead timer underflow 11) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16. " IRQRS400 ,IRQ400 (waveform generator dead timer reload 10) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 15. " IRQRS399 ,IRQ399 (waveform generator dead timer underflow 10) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 14. " IRQRS398 ,IRQ398 (waveform generator dead timer reload 9) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 13. " IRQRS397 ,IRQ397 (waveform generator dead timer underflow 9) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 12. " IRQRS396 ,IRQ396 (waveform generator DTTI 6, 7, 8) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 11. " IRQRS395 ,IRQ395 (waveform generator dead timer reload 8) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 10. " IRQRS394 ,IRQ394 (waveform generator dead timer underflow 8) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 9. " IRQRS393 ,IRQ393 (waveform generator dead timer reload 7) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 8. " IRQRS392 ,IRQ392 (waveform generator dead timer underflow 7) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 7. " IRQRS391 ,IRQ391 (waveform generator dead timer reload 6) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 6. " IRQRS390 ,IRQ390 (waveform generator dead timer underflow 6) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 5. " IRQRS389 ,IRQ389 (waveform generator DTTI 3, 4, 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " IRQRS388 ,IRQ388 (waveform generator dead timer reload 5) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 3. " IRQRS387 ,IRQ387 (waveform generator dead timer underflow 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " IRQRS386 ,IRQ386 (waveform generator dead timer reload 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 1. " IRQRS385 ,IRQ385 (waveform generator dead timer underflow 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " IRQRS384 ,IRQ384 (waveform generator dead timer reload 3) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x14 "IRQRS13,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x14 31. " IRQRS447 ,IRQ447 (4ch A/D converter unit 0 conversion complete 3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 30. " IRQRS446 ,IRQ446 (4ch A/D converter unit 0 conversion complete 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 29. " IRQRS445 ,IRQ445 (4ch A/D converter unit 0 conversion complete 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 28. " IRQRS444 ,IRQ444 (4ch A/D converter unit 0 conversion complete 0) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 27. " IRQRS443 ,IRQ443 (up/down counter unit 3 comparison result match detection 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 26. " IRQRS442 ,IRQ442 (up/down counter unit 3 comparison result match detection 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 25. " IRQRS441 ,IRQ441 (up/down counter unit 3 comparison result match detection 3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 24. " IRQRS440 ,IRQ440 (up/down counter unit 3 comparison result match detection 2) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 23. " IRQRS439 ,IRQ439 (up/down counter unit 3 comparison result match detection 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 22. " IRQRS438 ,IRQ438 (up/down counter unit 3 comparison result match detection 0) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 21. " IRQRS437 ,IRQ437 (up/down counter unit 3 interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 20. " IRQRS436 ,IRQ436 (up/down counter unit 2 comparison result match detection 5) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 19. " IRQRS435 ,IRQ435 (up/down counter unit 2 comparison result match detection 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 18. " IRQRS434 ,IRQ434 (up/down counter unit 2 comparison result match detection 3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 17. " IRQRS433 ,IRQ433 (up/down counter unit 2 comparison result match detection 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16. " IRQRS432 ,IRQ432 (up/down counter unit 2 comparison result match detection 1) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 15. " IRQRS431 ,IRQ431 (up/down counter unit 2 comparison result match detection 0) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 14. " IRQRS430 ,IRQ430 (up/down counter unit 2 interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 13. " IRQRS429 ,IRQ429 (up/down counter unit 1 comparison result match detection 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 12. " IRQRS428 ,IRQ428 (up/down counter unit 1 comparison result match detection 4) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 11. " IRQRS427 ,IRQ427 (up/down counter unit 1 comparison result match detection 3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 10. " IRQRS426 ,IRQ426 (up/down counter unit 1 comparison result match detection 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 9. " IRQRS425 ,IRQ425 (up/down counter unit 1 comparison result match detection 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 8. " IRQRS424 ,IRQ424 (up/down counter unit 1 comparison result match detection 0) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 7. " IRQRS423 ,IRQ423 (up/down counter unit 1 interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 6. " IRQRS422 ,IRQ422 (up/down counter unit 0 comparison result match detection 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 5. " IRQRS421 ,IRQ421 (up/down counter unit 0 comparison result match detection 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 4. " IRQRS420 ,IRQ420 (up/down counter unit 0 comparison result match detection 3) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 3. " IRQRS419 ,IRQ419 (up/down counter unit 0 comparison result match detection 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 2. " IRQRS418 ,IRQ418 (up/down counter unit 0 comparison result match detection 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 1. " IRQRS417 ,IRQ417 (up/down counter unit 0 comparison result match detection 0) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 0. " IRQRS416 ,IRQ416 (up/down counter unit 0 interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x18 "IRQRS14,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x18 31. " IRQRS479 ,IRQ479 (12-bit ADC conversion complete 9) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 30. " IRQRS478 ,IRQ478 (12-bit ADC conversion complete 8) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 29. " IRQRS477 ,IRQ477 (12-bit ADC conversion complete 7) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 28. " IRQRS476 ,IRQ476 (12-bit ADC conversion complete 6) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 27. " IRQRS475 ,IRQ475 (12-bit ADC conversion complete 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 26. " IRQRS474 ,IRQ474 (12-bit ADC conversion complete 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 25. " IRQRS473 ,IRQ473 (12-bit ADC conversion complete 3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 24. " IRQRS472 ,IRQ472 (12-bit ADC conversion complete 2) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 23. " IRQRS471 ,IRQ471 (12-bit ADC conversion complete 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 22. " IRQRS470 ,IRQ470 (12-bit ADC conversion complete 0) RAW status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x18 21. " IRQRS469 ,IRQ469 (16-bit input capture ch.14 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 20. " IRQRS468 ,IRQ468 (16-bit input capture ch.12, ch.13 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x18 20. " IRQRS468 ,IRQ468 (16-bit input capture ch.12 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 19. " IRQRS467 ,IRQ467 (16-bit input capture ch.10, ch.11 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 18. " IRQRS466 ,IRQ466 (16-bit input capture ch.8, ch.9 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 17. " IRQRS465 ,IRQ465 (16-bit input capture ch.6, ch.7 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16. " IRQRS464 ,IRQ464 (16-bit input capture ch.4, ch.5 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 15. " IRQRS463 ,IRQ463 (16-bit input capture ch.2, ch.3 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 14. " IRQRS462 ,IRQ462 (16-bit input capture ch.0, ch.1 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 13. " IRQRS461 ,IRQ461 (4ch A/D converter unit 1 range comparison 0/1/2/3/4/5/6/7) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 12. " IRQRS460 ,IRQ460 (4ch A/D converter unit 1 conversion complete 7) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 11. " IRQRS459 ,IRQ459 (4ch A/D converter unit 1 conversion complete 6) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 10. " IRQRS458 ,IRQ458 (4ch A/D converter unit 1 conversion complete 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 9. " IRQRS457 ,IRQ457 (4ch A/D converter unit 1 conversion complete 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 8. " IRQRS456 ,IRQ456 (4ch A/D converter unit 1 conversion complete 3) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 7. " IRQRS455 ,IRQ455 (4ch A/D converter unit 1 conversion complete 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 6. " IRQRS454 ,IRQ454 (4ch A/D converter unit 1 conversion complete 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 5. " IRQRS453 ,IRQ453 (4ch A/D converter unit 1 conversion complete 0) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 4. " IRQRS452 ,IRQ452 (4ch A/D converter unit 0 range comparison 0/1/2/3/4/5/6/7) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 3. " IRQRS451 ,IRQ451 (4ch A/D converter unit 0 conversion complete 7) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 2. " IRQRS450 ,IRQ450 (4ch A/D converter unit 0 conversion complete 6) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 1. " IRQRS449 ,IRQ449 (4ch A/D converter unit 0 conversion complete 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 0. " IRQRS448 ,IRQ448 (4ch A/D converter unit 0 conversion complete 4) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x1C "IRQRS15,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x1C 28. " IRQRS508 ,IRQ508 (PLL alarm for FlexRay) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 27. " IRQRS507 ,IRQ507 (PLL gear for FlexRay) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 26. " IRQRS506 ,IRQ506 (12-bit ADC scan conversion complete) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 25. " IRQRS505 ,IRQ505 (12-bit ADC range comparison 24/25/26/27/28/29/30/31) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " IRQRS504 ,IRQ504 (12-bit ADC range comparison 16/17/18/19/20/21/22/23) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 23. " IRQRS503 ,IRQ503 (12-bit ADC range comparison 8/9/10/11/12/13/14/15) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 22. " IRQRS502 ,IRQ502 (12-bit ADC range comparison 0/1/2/3/4/5/6/7) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 21. " IRQRS501 ,IRQ501 (12-bit ADC conversion complete 31) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " IRQRS500 ,IRQ500 (12-bit ADC conversion complete 30) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 19. " IRQRS499 ,IRQ499 (12-bit ADC conversion complete 29) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 18. " IRQRS498 ,IRQ498 (12-bit ADC conversion complete 28) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 17. " IRQRS497 ,IRQ497 (12-bit ADC conversion complete 27) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 16. " IRQRS496 ,IRQ496 (12-bit ADC conversion complete 26) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 15. " IRQRS495 ,IRQ495 (12-bit ADC conversion complete 25) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 14. " IRQRS494 ,IRQ494 (12-bit ADC conversion complete 24) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 13. " IRQRS493 ,IRQ493 (12-bit ADC conversion complete 23) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " IRQRS492 ,IRQ492 (12-bit ADC conversion complete 22) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 11. " IRQRS491 ,IRQ491 (12-bit ADC conversion complete 21) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 10. " IRQRS490 ,IRQ490 (12-bit ADC conversion complete 20) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 9. " IRQRS489 ,IRQ489 (12-bit ADC conversion complete 19) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " IRQRS488 ,IRQ488 (12-bit ADC conversion complete 18) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 7. " IRQRS487 ,IRQ487 (12-bit ADC conversion complete 17) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 6. " IRQRS486 ,IRQ486 (12-bit ADC conversion complete 16) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 5. " IRQRS485 ,IRQ485 (12-bit ADC conversion complete 15) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " IRQRS484 ,IRQ484 (12-bit ADC conversion complete 14) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 3. " IRQRS483 ,IRQ483 (12-bit ADC conversion complete 13) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 2. " IRQRS482 ,IRQ482 (12-bit ADC conversion complete 12) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 1. " IRQRS481 ,IRQ481 (12-bit ADC conversion complete 11) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " IRQRS480 ,IRQ480 (12-bit ADC conversion complete 10) RAW status bits" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "IRC IRQ Preprocessed Status Register"
|
|
rgroup.long 0xCF0++0x1B
|
|
line.long 0x00 "IRQPS0,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x00 31. " IRQPS31 ,IRQ31 (external interrupt ch.7) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQPS30 ,IRQ30 (external interrupt ch.6) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQPS29 ,IRQ29 (external interrupt ch.5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQPS28 ,IRQ28 (external interrupt ch.4) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQPS27 ,IRQ27 (external interrupt ch.3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQPS26 ,IRQ26 (external interrupt ch.2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQPS25 ,IRQ25 (external interrupt ch.1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQPS24 ,IRQ24 (external interrupt ch.0) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IRQPS21 ,IRQ21 (WorkFLASH unit 1 1-bit error correction interrupt/ready interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQPS20 ,IRQ20 (WorkFLASH unit 0 1-bit error correction interrupt/ready interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQPS16 ,IRQ16 (interrupt controller unit 0/1 ECC 1-bit error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " IRQPS11 ,IRQ11 (WorkFLASH unit 1 hang interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQPS10 ,IRQ10 (WorkFLASH unit 0 hang interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQPS8 ,IRQ8 (TCFLASH uniy 0/1 1-bit error correction interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " IRQPS3 ,IRQ3 (SW-WDT unit 0/1 prior warning interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQPS2 ,IRQ2 (HW-WDT prior warning interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQPS1 ,IRQ1 (LPC RUN profile update complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQPS1,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x04 26. " IRQPS58 ,IRQ58 (CAN ch.2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " IRQPS57 ,IRQ57 (CAN ch.1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " IRQPS56 ,IRQ56 (CAN ch.0) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQPS2,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x08 9. " IRQPS73 ,IRQ73 (multi-function serial interface ch.4 transmission complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " IRQPS72 ,IRQ72 (multi-function serial interface ch.4 reception complete/status) preprocessed status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x08 7. " IRQPS71 ,IRQ71 (multi-function serial interface ch.3 transmission complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " IRQPS70 ,IRQ70 (multi-function serial interface ch.3 reception complete/status) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IRQPS69 ,IRQ69 (multi-function serial interface ch.2 transmission complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " IRQPS68 ,IRQ68 (multi-function serial interface ch.2 reception complete/status) preprocessed status bits" "No interrupt,Interrupt"
|
|
endif
|
|
bitfld.long 0x08 3. " IRQPS67 ,IRQ67 (multi-function serial interface ch.1 transmission complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " IRQPS66 ,IRQ66 (multi-function serial interface ch.1 reception complete/status) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IRQPS65 ,IRQ65 (multi-function serial interface ch.0 transmission complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " IRQPS64 ,IRQ64 (multi-function serial interface ch.0 reception complete/status) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x0C "IRQPS3,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x0C 21. " IRQPS117 ,IRQ117 (CR calibration interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 14. " IRQPS110 ,IRQ110 (TCRAM unit 0/1 RAM diagnosis interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " IRQPS96 ,IRQ96 (inter-processor communication (IPCU) interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x10 "IRQPS4,IRC IRQ Preprocessed Status Register"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 11. " IRQPS139 ,IRQ139 (base timer ch.11 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 10. " IRQPS138 ,IRQ138 (base timer ch.10 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 9. " IRQPS137 ,IRQ137 (base timer ch.9 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 8. " IRQPS136 ,IRQ136 (base timer ch.8 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 7. " IRQPS135 ,IRQ135 (base timer ch.7 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 6. " IRQPS134 ,IRQ134 (base timer ch.6 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 5. " IRQPS133 ,IRQ133 (base timer ch.5 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " IRQPS132 ,IRQ132 (base timer ch.4 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 3. " IRQPS131 ,IRQ131 (base timer ch.3 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " IRQPS130 ,IRQ130 (base timer ch.2 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 1. " IRQPS129 ,IRQ129 (base timer ch.1 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " IRQPS128 ,IRQ128 (base timer ch.0 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x14 "IRQPS5,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x14 20. " IRQPS2180 ,IRQ180 (32-bit free-run timer ch.4 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 19. " IRQPS179 ,IRQ179 (32-bit free-run timer ch.3 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 18. " IRQPS178 ,IRQ178 (32-bit free-run timer ch.2 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 17. " IRQPS117 ,IRQ177 (32-bit free-run timer ch.1 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 16. " IRQPS176 ,IRQ176 (32-bit free-run timer ch.0 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x18 "IRQPS6,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x18 2. " IRQPS194 ,IRQ194 (32-bit input capture ch.4, ch.5 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 1. " IRQPS193 ,IRQ193 (32-bit input capture ch.2, ch.3 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 0. " IRQPS192 ,IRQ192 (32-bit input capture ch.0, ch.1 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
rgroup.long 0xD10++0x1F
|
|
line.long 0x00 "IRQPS8,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x00 24. " IRQPS280 ,IRQ280 (DMAC ch.7, ch.15 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " IRQPS279 ,IRQ279 (DMAC ch.6, ch.14 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQPS278 ,IRQ278 (DMAC ch.5, ch.13 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQPS277 ,IRQ277 (DMAC ch.4, ch.12 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " IRQPS276 ,IRQ276 (DMAC ch.3, ch.11 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " IRQPS275 ,IRQ275 (DMAC ch.2, ch.10 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQPS274 ,IRQ274 (DMAC ch.1, ch.9 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQPS273 ,IRQ273 (DMAC ch.0, ch.8 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQPS272 ,IRQ272 (DMAC transfer error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQPS9,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x04 24. " IRQPS312 ,IRQ312 (PMU interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " IRQPS310 ,IRQ310 (main clock timer interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " IRQPS309 ,IRQ309 (Slow-CR clock timer interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " IRQPS308 ,IRQ308 (Fast-CR clock timer interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQPS10,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x08 31. " IRQPS351 ,IRQ351 (MVA0 failure detection error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 30. " IRQPS350 ,IRQ350 (MVA0 floating-point non-normalized error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 29. " IRQPS349 ,IRQ349 (MVA0 underflow interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 28. " IRQPS348 ,IRQ348 (MVA0 overflow interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 27. " IRQPS347 ,IRQ347 (MVA0 two-phase to three-phase AC conversion end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 26. " IRQPS346 ,IRQ346 (MVA0 current to voltage conversion end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 25. " IRQPS345 ,IRQ345 (MVA0 PID control end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 24. " IRQPS344 ,IRQ344 (MVA0 three-phase to two-phase DC conversion end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 23. " IRQPS343 ,IRQ343 (MVA0 three-phase current normalization end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 22. " IRQPS342 ,IRQ342 (MVA0 angular calculation end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 21. " IRQPS341 ,IRQ341 (16-bit free-run timer ch.17 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 20. " IRQPS340 ,IRQ340 (16-bit free-run timer ch.16 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IRQPS339 ,IRQ339 (16-bit free-run timer ch.15 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 18. " IRQPS338 ,IRQ338 (16-bit free-run timer ch.14 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 17. " IRQPS337 ,IRQ337 (16-bit free-run timer ch.13 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16. " IRQPS336 ,IRQ336 (16-bit free-run timer ch.12 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 15. " IRQPS335 ,IRQ335 (16-bit free-run timer ch.11 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 14. " IRQPS334 ,IRQ334 (16-bit free-run timer ch.10 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 13. " IRQPS333 ,IRQ333 (16-bit free-run timer ch.9 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 12. " IRQPS332 ,IRQ332 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 11. " IRQPS331 ,IRQ331 (16-bit free-run timer ch.7 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 10. " IRQPS330 ,IRQ330 (16-bit free-run timer ch.6 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 9. " IRQPS329 ,IRQ329 (16-bit free-run timer ch.5 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " IRQPS328 ,IRQ328 (16-bit free-run timer ch.4 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IRQPS327 ,IRQ327 (16-bit free-run timer ch.3 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " IRQPS326 ,IRQ326 (16-bit free-run timer ch.2 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 5. " IRQPS325 ,IRQ325 (16-bit free-run timer ch.1 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " IRQPS324 ,IRQ324 (16-bit free-run timer ch.0 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
textline " "
|
|
bitfld.long 0x08 3. " IRQPS323 ,IRQ323 (FlexRay Timer 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " IRQPS322 ,IRQ322 (FlexRay Timer 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 1. " IRQPS321 ,IRQ321 (FlexRay1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " IRQPS320 ,IRQ320 (FlexRay0) preprocessed status bits" "No interrupt,Interrupt"
|
|
endif
|
|
line.long 0x0C "IRQPS11,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x0C 31. " IRQPS383 ,IRQ383 (waveform generator dead timer underflow 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 30. " IRQPS382 ,IRQ382 (waveform generator DTTI 0, 1, 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 29. " IRQPS381 ,IRQ381 (waveform generator dead timer reload 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 28. " IRQPS380 ,IRQ380 (waveform generator dead timer underflow 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " IRQPS379 ,IRQ379 (waveform generator dead timer reload 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 26. " IRQPS378 ,IRQ378 (waveform generator dead timer underflow 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 25. " IRQPS377 ,IRQ377 (waveform generator dead timer reload 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 24. " IRQPS376 ,IRQ376 (waveform generator dead timer underflow 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " IRQPS375 ,IRQ375 (MVA1 free-run timer 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 22. " IRQPS374 ,IRQ374 (MVA0 free-run timer 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 21. " IRQPS373 ,IRQ373 (MVA1 calculation overtime error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 20. " IRQPS372 ,IRQ372 (MVA1 three-phase to two-phase DC value abnormality detection error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " IRQPS370 ,IRQ370 (MVA1 cumulative three-phase current abnormality detection error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 17. " IRQPS369 ,IRQ369 (MVA1 R/D converter diagnosis error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16. " IRQPS368 ,IRQ368 (MVA1 calculation data update error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 15. " IRQPS367 ,IRQ367 (MVA1 failure detection error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " IRQPS366 ,IRQ366 (MVA1 floating-point non-normalized error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 13. " IRQPS365 ,IRQ365 (MVA1 underflow interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 12. " IRQPS364 ,IRQ364 (MVA1 overflow interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " IRQPS363 ,IRQ363 (MVA1 two-phase to three-phase AC conversion end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 10. " IRQPS362 ,IRQ362 (MVA1 current to voltage conversion end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 9. " IRQPS361 ,IRQ361 (MVA1 PID control end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 8. " IRQPS360 ,IRQ360 (MVA1 three-phase to two-phase DC conversion end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " IRQPS359 ,IRQ359 (MVA1 three-phase current normalization end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 6. " IRQPS358 ,IRQ358 (MVA1 angular calculation end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 5. " IRQPS357 ,IRQ357 (MVA0 calculation overtime error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " IRQPS356 ,IRQ356 (MVA0 three-phase to two-phase DC value abnormality detection error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " IRQPS354 ,IRQ354 (MVA0 cumulative three-phase current abnormality detection error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 1. " IRQPS353 ,IRQ353 (MVA0 R/D converter diagnosis error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " IRQPS352 ,IRQ352 (MVA0 calculation data update error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x10 "IRQPS12,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x10 31. " IRQPS415 ,IRQ415 (16-bit output compare ch.22, ch.23 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 30. " IRQPS414 ,IRQ414 (16-bit output compare ch.20, ch.21 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 29. " IRQPS413 ,IRQ413 (16-bit output compare ch.18, ch.19 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 28. " IRQPS412 ,IRQ412 (16-bit output compare ch.16, ch.17 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 27. " IRQPS411 ,IRQ411 (16-bit output compare ch.14, ch.15 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 26. " IRQPS410 ,IRQ410 (16-bit output compare ch.12, ch.13 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 25. " IRQPS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 24. " IRQPS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x10 25. " IRQPS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 24. " IRQPS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 23. " IRQPS407 ,IRQ407 (16-bit output compare ch.6, ch.7 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 22. " IRQPS406 ,IRQ406 (16-bit output compare ch.4, ch.5 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 21. " IRQPS405 ,IRQ405 (16-bit output compare ch.2, ch.3 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 20. " IRQPS404 ,IRQ404 (16-bit output compare ch.0, ch.1 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 19. " IRQPS403 ,IRQ403 (waveform generator DTTI 9, 10, 11) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 18. " IRQPS402 ,IRQ402 (waveform generator dead timer reload 11) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 17. " IRQPS401 ,IRQ401 (waveform generator dead timer underflow 11) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16. " IRQPS400 ,IRQ400 (waveform generator dead timer reload 10) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 15. " IRQPS399 ,IRQ399 (waveform generator dead timer underflow 10) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 14. " IRQPS398 ,IRQ398 (waveform generator dead timer reload 9) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 13. " IRQPS397 ,IRQ397 (waveform generator dead timer underflow 9) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 12. " IRQPS396 ,IRQ396 (waveform generator DTTI 6, 7, 8) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 11. " IRQPS395 ,IRQ395 (waveform generator dead timer reload 8) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 10. " IRQPS394 ,IRQ394 (waveform generator dead timer underflow 8) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 9. " IRQPS393 ,IRQ393 (waveform generator dead timer reload 7) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 8. " IRQPS392 ,IRQ392 (waveform generator dead timer underflow 7) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 7. " IRQPS391 ,IRQ391 (waveform generator dead timer reload 6) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 6. " IRQPS390 ,IRQ390 (waveform generator dead timer underflow 6) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 5. " IRQPS389 ,IRQ389 (waveform generator DTTI 3, 4, 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " IRQPS388 ,IRQ388 (waveform generator dead timer reload 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 3. " IRQPS387 ,IRQ387 (waveform generator dead timer underflow 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " IRQPS386 ,IRQ386 (waveform generator dead timer reload 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 1. " IRQPS385 ,IRQ385 (waveform generator dead timer underflow 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " IRQPS384 ,IRQ384 (waveform generator dead timer reload 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x14 "IRQPS13,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x14 31. " IRQPS447 ,IRQ447 (4ch A/D converter unit 0 conversion complete 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 30. " IRQPS446 ,IRQ446 (4ch A/D converter unit 0 conversion complete 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 29. " IRQPS445 ,IRQ445 (4ch A/D converter unit 0 conversion complete 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 28. " IRQPS444 ,IRQ444 (4ch A/D converter unit 0 conversion complete 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 27. " IRQPS443 ,IRQ443 (up/down counter unit 3 comparison result match detection 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 26. " IRQPS442 ,IRQ442 (up/down counter unit 3 comparison result match detection 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 25. " IRQPS441 ,IRQ441 (up/down counter unit 3 comparison result match detection 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 24. " IRQPS440 ,IRQ440 (up/down counter unit 3 comparison result match detection 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 23. " IRQPS439 ,IRQ439 (up/down counter unit 3 comparison result match detection 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 22. " IRQPS438 ,IRQ438 (up/down counter unit 3 comparison result match detection 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 21. " IRQPS437 ,IRQ437 (up/down counter unit 3 interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 20. " IRQPS436 ,IRQ436 (up/down counter unit 2 comparison result match detection 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 19. " IRQPS435 ,IRQ435 (up/down counter unit 2 comparison result match detection 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 18. " IRQPS434 ,IRQ434 (up/down counter unit 2 comparison result match detection 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 17. " IRQPS433 ,IRQ433 (up/down counter unit 2 comparison result match detection 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16. " IRQPS432 ,IRQ432 (up/down counter unit 2 comparison result match detection 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 15. " IRQPS431 ,IRQ431 (up/down counter unit 2 comparison result match detection 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 14. " IRQPS430 ,IRQ430 (up/down counter unit 2 interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 13. " IRQPS429 ,IRQ429 (up/down counter unit 1 comparison result match detection 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 12. " IRQPS428 ,IRQ428 (up/down counter unit 1 comparison result match detection 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 11. " IRQPS427 ,IRQ427 (up/down counter unit 1 comparison result match detection 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 10. " IRQPS426 ,IRQ426 (up/down counter unit 1 comparison result match detection 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 9. " IRQPS425 ,IRQ425 (up/down counter unit 1 comparison result match detection 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 8. " IRQPS424 ,IRQ424 (up/down counter unit 1 comparison result match detection 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 7. " IRQPS423 ,IRQ423 (up/down counter unit 1 interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 6. " IRQPS422 ,IRQ422 (up/down counter unit 0 comparison result match detection 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 5. " IRQPS421 ,IRQ421 (up/down counter unit 0 comparison result match detection 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 4. " IRQPS420 ,IRQ420 (up/down counter unit 0 comparison result match detection 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 3. " IRQPS419 ,IRQ419 (up/down counter unit 0 comparison result match detection 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 2. " IRQPS418 ,IRQ418 (up/down counter unit 0 comparison result match detection 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 1. " IRQPS417 ,IRQ417 (up/down counter unit 0 comparison result match detection 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 0. " IRQPS416 ,IRQ416 (up/down counter unit 0 interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x18 "IRQPS14,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x18 31. " IRQPS479 ,IRQ479 (12-bit ADC conversion complete 9) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 30. " IRQPS478 ,IRQ478 (12-bit ADC conversion complete 8) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 29. " IRQPS477 ,IRQ477 (12-bit ADC conversion complete 7) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 28. " IRQPS476 ,IRQ476 (12-bit ADC conversion complete 6) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 27. " IRQPS475 ,IRQ475 (12-bit ADC conversion complete 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 26. " IRQPS474 ,IRQ474 (12-bit ADC conversion complete 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 25. " IRQPS473 ,IRQ473 (12-bit ADC conversion complete 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 24. " IRQPS472 ,IRQ472 (12-bit ADC conversion complete 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 23. " IRQPS471 ,IRQ471 (12-bit ADC conversion complete 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 22. " IRQPS470 ,IRQ470 (12-bit ADC conversion complete 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x18 21. " IRQPS469 ,IRQ469 (16-bit input capture ch.14 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 20. " IRQPS468 ,IRQ468 (16-bit input capture ch.12, ch.13 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x18 20. " IRQPS468 ,IRQ468 (16-bit input capture ch.12 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 19. " IRQPS467 ,IRQ467 (16-bit input capture ch.10, ch.11 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 18. " IRQPS466 ,IRQ466 (16-bit input capture ch.8, ch.9 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 17. " IRQPS465 ,IRQ465 (16-bit input capture ch.6, ch.7 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16. " IRQPS464 ,IRQ464 (16-bit input capture ch.4, ch.5 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 15. " IRQPS463 ,IRQ463 (16-bit input capture ch.2, ch.3 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 14. " IRQPS462 ,IRQ462 (16-bit input capture ch.0, ch.1 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 13. " IRQPS461 ,IRQ461 (4ch A/D converter unit 1 range comparison 0/1/2/3/4/5/6/7) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 12. " IRQPS460 ,IRQ460 (4ch A/D converter unit 1 conversion complete 7) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 11. " IRQPS459 ,IRQ459 (4ch A/D converter unit 1 conversion complete 6) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 10. " IRQPS458 ,IRQ458 (4ch A/D converter unit 1 conversion complete 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 9. " IRQPS457 ,IRQ457 (4ch A/D converter unit 1 conversion complete 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 8. " IRQPS456 ,IRQ456 (4ch A/D converter unit 1 conversion complete 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 7. " IRQPS455 ,IRQ455 (4ch A/D converter unit 1 conversion complete 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 6. " IRQPS454 ,IRQ454 (4ch A/D converter unit 1 conversion complete 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 5. " IRQPS453 ,IRQ453 (4ch A/D converter unit 1 conversion complete 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 4. " IRQPS452 ,IRQ452 (4ch A/D converter unit 0 range comparison 0/1/2/3/4/5/6/7) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 3. " IRQPS451 ,IRQ451 (4ch A/D converter unit 0 conversion complete 7) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 2. " IRQPS450 ,IRQ450 (4ch A/D converter unit 0 conversion complete 6) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 1. " IRQPS449 ,IRQ449 (4ch A/D converter unit 0 conversion complete 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 0. " IRQPS448 ,IRQ448 (4ch A/D converter unit 0 conversion complete 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x1C "IRQPS15,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x1C 28. " IRQPS508 ,IRQ508 (PLL alarm for FlexRay) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 27. " IRQPS507 ,IRQ507 (PLL gear for FlexRay) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 26. " IRQPS506 ,IRQ506 (12-bit ADC scan conversion complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 25. " IRQPS505 ,IRQ505 (12-bit ADC range comparison 24/25/26/27/28/29/30/31) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " IRQPS504 ,IRQ504 (12-bit ADC range comparison 16/17/18/19/20/21/22/23) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 23. " IRQPS503 ,IRQ503 (12-bit ADC range comparison 8/9/10/11/12/13/14/15) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 22. " IRQPS502 ,IRQ502 (12-bit ADC range comparison 0/1/2/3/4/5/6/7) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 21. " IRQPS501 ,IRQ501 (12-bit ADC conversion complete 31) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " IRQPS500 ,IRQ500 (12-bit ADC conversion complete 30) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 19. " IRQPS499 ,IRQ499 (12-bit ADC conversion complete 29) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 18. " IRQPS498 ,IRQ498 (12-bit ADC conversion complete 28) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 17. " IRQPS497 ,IRQ497 (12-bit ADC conversion complete 27) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 16. " IRQPS496 ,IRQ496 (12-bit ADC conversion complete 26) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 15. " IRQPS495 ,IRQ495 (12-bit ADC conversion complete 25) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 14. " IRQPS494 ,IRQ494 (12-bit ADC conversion complete 24) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 13. " IRQPS493 ,IRQ493 (12-bit ADC conversion complete 23) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " IRQPS492 ,IRQ492 (12-bit ADC conversion complete 22) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 11. " IRQPS491 ,IRQ491 (12-bit ADC conversion complete 21) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 10. " IRQPS490 ,IRQ490 (12-bit ADC conversion complete 20) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 9. " IRQPS489 ,IRQ489 (12-bit ADC conversion complete 19) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " IRQPS488 ,IRQ488 (12-bit ADC conversion complete 18) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 7. " IRQPS487 ,IRQ487 (12-bit ADC conversion complete 17) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 6. " IRQPS486 ,IRQ486 (12-bit ADC conversion complete 16) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 5. " IRQPS485 ,IRQ485 (12-bit ADC conversion complete 15) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " IRQPS484 ,IRQ484 (12-bit ADC conversion complete 14) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 3. " IRQPS483 ,IRQ483 (12-bit ADC conversion complete 13) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 2. " IRQPS482 ,IRQ482 (12-bit ADC conversion complete 12) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 1. " IRQPS481 ,IRQ481 (12-bit ADC conversion complete 11) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " IRQPS480 ,IRQ480 (12-bit ADC conversion complete 10) preprocessed status bits" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0xD30++0x03
|
|
line.long 0x00 "UNLOCK,IRC Unlock Register"
|
|
group.long 0xD40++0x03
|
|
line.long 0x00 "EEI,IRC ECC Error Interrupt Register"
|
|
rbitfld.long 0x00 24. " EEIS ,ECC error IRQ status bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " EEIC ,ECC error IRQ clear bit" "No effect,Clear"
|
|
rbitfld.long 0x00 8. " EENS ,ECC error NMI status bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " EENC ,ECC error NMI clear bit" "No effect,Clear"
|
|
rgroup.long 0xD44++0x3
|
|
line.long 0x00 "EAN,IRC ECC Address Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " EAN ,ECC error occurrence address bits"
|
|
group.long 0xD48++0x0F
|
|
line.long 0x00 "ET,IRC ECC Test Register"
|
|
bitfld.long 0x00 0. " ET ,ECC test enable/disable setting bit" "Disabled,Enabled"
|
|
line.long 0x04 "EEB0,IRC ECC Error Bit Register"
|
|
hexmask.long 0x04 2.--31. 1. " EEB ,ECC error occurrence bits"
|
|
line.long 0x08 "EEB1,IRC ECC Error Bit Register"
|
|
hexmask.long 0x08 2.--31. 1. " EEB ,ECC error occurrence bits"
|
|
line.long 0x0C "EEB2,IRC ECC Error Bit Register"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " EEBO ,ECC error occurrence bits"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " EEBE ,ECC error occurrence bits"
|
|
group.long 0xD3C++0x3
|
|
line.long 0x00 "IRQEEVA,IRC ECC Error Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
width 0x0B
|
|
tree "Error Config Area"
|
|
base ad:0xFFFEE000
|
|
width 10.
|
|
hgroup.long 0x3FC++0x03
|
|
hide.long 0x00 "NMIVASBR,IRC NMI Vector Address Status Register"
|
|
in
|
|
tree.end
|
|
tree.end
|
|
tree "Unit 1"
|
|
base ad:0xB0401000
|
|
width 18.
|
|
rgroup.long 0x00++0x0F
|
|
line.long 0x00 "NMIVAS,IRC NMI Vector Address Status Register"
|
|
line.long 0x04 "NMIST,IRC NMI Status Register"
|
|
bitfld.long 0x04 8.--11. " NMPIS ,NMI priority status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--5. " NMISN ,NMI channel number bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
line.long 0x08 "IRQVAS,IRC IRQ Vector Address Status Register"
|
|
line.long 0x0C "IRQST,IRC IRQ Status Register"
|
|
bitfld.long 0x0C 24. " NIRQ ,IRQ interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--20. " IRQPS ,IRQ priority status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x0C 0.--9. 1. " IRQSN ,IRQ channel number bits"
|
|
tree "NMI Vector Address Registers"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "NMIVA0,(Nmix Pin) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "NMIVA4,(Low-voltage Detection) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
line.long 0x04 "NMIVA5,(Clock Supervisor/Profile) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
line.long 0x08 "NMIVA6,(Hardware Watchdog) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
line.long 0x0C "NMIVA7,(Software Watchdog) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
line.long 0x10 "NMIVA8,(Interrupt Controller 2-bit ECC Error Detection) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
line.long 0x14 "NMIVA9,(CPU Livelock) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "NMIVA13,(Memory Protection (MPU) Protection Violation) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "NMIVA18,(Time Protection (TPU) Protection Violation) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??AE")
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "NMIVA24,(R/D Converter Channel 0 Abnormal) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
line.long 0x04 "NMIVA25,(R/D Converter Channel 1 Abnormal) IRQ NMI Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " NMIVA[31:2] ,NMI vector address bits"
|
|
endif
|
|
tree.end
|
|
tree "IRQ Vector Address Registers"
|
|
group.long 0x94++0x0B
|
|
line.long 0x00 "IRQVA1,(LPC RUN Profile Update Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA2,(HW-WDT Prior Warning Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA3,(SW-WDT Prior Warning Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "IRQVA8,(TCFLASH 1-bit Error Correction Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0xB8++0x07
|
|
line.long 0x00 "IRQVA10,(WorkFLASH Unit0 Hang Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA11,(WorkFLASH Unit1 Hang Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "IRQVA16,(Interrupt Controller Unit0/1 ECC 1-bit Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0xE0++0x07
|
|
line.long 0x00 "IRQVA20,(WorkFLASH Unit0 1-bit Error Correction Interrupt/Ready Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA21,(WorkFLASH Unit1 1-bit Error Correction Interrupt/Ready Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0xF0++0x1F
|
|
line.long 0x00 "IRQVA24,(External Interrupt Ch.0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA25,(External Interrupt Ch.1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA26,(External Interrupt Ch.2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA27,(External Interrupt Ch.3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA28,(External Interrupt Ch.4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA29,(External Interrupt Ch.5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA30,(External Interrupt Ch.6) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA31,(External Interrupt Ch.7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x170++0x0B
|
|
line.long 0x00 "IRQVA56,(CAN Ch.0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA57,(CAN Ch.1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA58,(CAN Ch.2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x190++0x0F
|
|
line.long 0x00 "IRQVA64,(Multi-function Serial Interface Ch.0 Reception Complete/Status) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA65,(Multi-function Serial Interface Ch.0 Transmission Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA66,(Multi-function Serial Interface Ch.1 Reception Complete/Status) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA67,(Multi-function Serial Interface Ch.1 Transmission Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
sif cpuis("MB9DF56?M*")
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "IRQVA68,(Multi-function Serial Interface Ch.2 Reception Complete/Status) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA69,(Multi-function Serial Interface Ch.2 Transmission Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA70,(Multi-function Serial Interface Ch.3 Reception Complete/Status) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA71,(Multi-function Serial Interface Ch.3 Transmission Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
endif
|
|
group.long 0x1B0++0x07
|
|
line.long 0x00 "IRQVA72,(Multi-function Serial Interface Ch.4 Reception Complete/Status) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA73,(Multi-function Serial Interface Ch.4 Transmission Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQVA96,(Inter-processor Communication (IPCU) Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "IRQVA110,(TCRAM Unit0/1 RAM Diagnosis Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "IRQVA117,(CR Calibration Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x290++0x2F
|
|
line.long 0x00 "IRQVA128,(Base Timer Ch.0 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA129,(Base Timer Ch.1 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA130,(Base Timer Ch.2 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA131,(Base Timer Ch.3 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA132,(Base Timer Ch.4 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA133,(Base Timer Ch.5 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA134,(Base Timer Ch.6 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA135,(Base Timer Ch.7 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA136,(Base Timer Ch.8 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x24 "IRQVA137,(Base Timer Ch.9 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x24 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x28 "IRQVA138,(Base Timer Ch.10 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x28 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x2C "IRQVA139,(Base Timer Ch.11 IRQ0/IRQ1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x2C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x350++0x13
|
|
line.long 0x00 "IRQVA176,(32-bit Free-run Timer Ch.0 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA177,(32-bit Free-run Timer Ch.1 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA178,(32-bit Free-run Timer Ch.2 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA179,(32-bit Free-run Timer Ch.3 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA180,(32-bit Free-run Timer Ch.4 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x390++0x0B
|
|
line.long 0x00 "IRQVA192,(32-bit Input Capture Ch.0, Ch.1 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA193,(32-bit Input Capture Ch.2, Ch.3 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA194,(32-bit Input Capture Ch.4, Ch.5 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x4D0++0x23
|
|
line.long 0x00 "IRQVA272,(DMAC Transfer Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA273,(DMAC Ch.0, Ch.8 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA274,(DMAC Ch.1, Ch.9 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA275,(DMAC Ch.2, Ch.10 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA276,(DMAC Ch.3, Ch.11 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA277,(DMAC Ch.4, Ch.12 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA278,(DMAC Ch.5, Ch.13 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA279,(DMAC Ch.6, Ch.14 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA280,(DMAC Ch.7, Ch.15 Transfer Complete Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x560++0x0B
|
|
line.long 0x00 "IRQVA308,(Fast-CR Clock Timer Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA309,(Slow-CR Clock Timer Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA310,(Main Clock Timer Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "IRQVA312,(PMU Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
group.long 0x590++0x0F
|
|
line.long 0x00 "IRQVA320,(FlexRay0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA321,(FlexRay1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA322,(FlexRay Timer 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA323,(FlexRay Timer 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
endif
|
|
group.long 0x5A0++0x7B
|
|
line.long 0x00 "IRQVA324,(16-bit Free-run Timer Ch.0 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA325,(16-bit Free-run Timer Ch.1 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA326,(16-bit Free-run Timer Ch.2 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA327,(16-bit Free-run Timer Ch.3 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA328,(16-bit Free-run Timer Ch.4 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA329,(16-bit Free-run Timer Ch.5 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA330,(16-bit Free-run Timer Ch.6 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA331,(16-bit Free-run Timer Ch.7 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA332,(16-bit Free-run Timer Ch.8 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x24 "IRQVA333,(16-bit Free-run Timer Ch.9 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x24 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x28 "IRQVA334,(16-bit Free-run Timer Ch.10 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x28 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x2C "IRQVA335,(16-bit Free-run Timer Ch.11 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x2C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x30 "IRQVA336,(16-bit Free-run Timer Ch.12 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x30 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x34 "IRQVA337,(16-bit Free-run Timer Ch.13 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x34 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x38 "IRQVA338,(16-bit Free-run Timer Ch.14 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x38 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x3C "IRQVA339,(16-bit Free-run Timer Ch.15 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x3C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x40 "IRQVA340,(16-bit Free-run Timer Ch.16 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x40 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x44 "IRQVA341,(16-bit Free-run Timer Ch.17 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x44 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x48 "IRQVA342,(MVA0 Angular Calculation End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x48 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x4C "IRQVA343,(MVA0 Three-phase Current Normalization End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x4C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x50 "IRQVA344,(MVA0 Three-phase To Two-phase DC Conversion End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x50 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x54 "IRQVA345,(MVA0 PID Control End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x54 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x58 "IRQVA346,(MVA0 Current To Voltage Conversion End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x58 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x5C "IRQVA347,(MVA0 Two-phase To Three-phase AC Conversion End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x5C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x60 "IRQVA348,(MVA0 Overflow Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x60 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x64 "IRQVA349,(MVA0 Underflow Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x64 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x68 "IRQVA350,(MVA0 Floating-point Non-normalized Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x68 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x6C "IRQVA351,(MVA0 Failure Detection Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x6C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x70 "IRQVA352,(MVA0 Calculation Data Update Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x70 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x74 "IRQVA353,(MVA0 R/D Converter Diagnosis Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x74 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x78 "IRQVA354,(MVA0 Cumulative Three-phase Current Abnormality Detection Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x78 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x620++0x3B
|
|
line.long 0x00 "IRQVA356,(MVA0 Three-phase To Two-phase DC Value Abnormality Detection Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA357,(MVA0 Calculation Overtime Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA358,(MVA1 Angular Calculation End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA359,(MVA1 Three-phase Current Normalization End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA360,(MVA1 Three-phase To Two-phase DC Conversion End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA361,(MVA1 PID Control End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA362,(MVA1 Current To Voltage Conversion End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA363,(MVA1 Two-phase To Three-phase AC Conversion End Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA364,(MVA1 Overflow Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x24 "IRQVA365,(MVA1 Underflow Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x24 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x28 "IRQVA366,(MVA1 Floating-point Non-normalized Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x28 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x2C "IRQVA367,(MVA1 Failure Detection Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x2C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x30 "IRQVA368,(MVA1 Calculation Data Update Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x30 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x34 "IRQVA369,(MVA1 R/D Converter Diagnosis Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x34 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x38 "IRQVA370,(MVA1 Cumulative Three-phase Current Abnormality Detection Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x38 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
group.long 0x660++0x97
|
|
line.long 0x00 "IRQVA372,(MVA1 Three-phase To Two-phase DC Value Abnormality Detection Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA373,(MVA1 Calculation Overtime Error Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA374,(MVA0 Free-run Timer 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA375,(MVA1 Free-run Timer 0 Detection/Compare Clear Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA376,(Waveform Generator Dead Timer Underflow 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA377,(Waveform Generator Dead Timer Reload 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA378,(Waveform Generator Dead Timer Underflow 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA379,(Waveform Generator Dead Timer Reload 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA380,(Waveform Generator Dead Timer Underflow 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x24 "IRQVA381,(Waveform Generator Dead Timer Reload 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x24 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x28 "IRQVA382,(Waveform Generator DTTI0, 1, 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x28 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x2C "IRQVA383,(Waveform Generator Dead Timer Underflow 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x2C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x30 "IRQVA384,(Waveform Generator Dead Timer Reload 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x30 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x34 "IRQVA385,(Waveform Generator Dead Timer Underflow 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x34 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x38 "IRQVA386,(Waveform Generator Dead Timer Reload 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x38 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x3C "IRQVA387,(Waveform Generator Dead Timer Underflow 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x3C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x40 "IRQVA388,(Waveform Generator Dead Timer Reload 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x40 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x44 "IRQVA389,(Waveform Generator DTTI3, 4, 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x44 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x48 "IRQVA390,(Waveform Generator Dead Timer Underflow 6) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x48 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x4C "IRQVA391,(Waveform Generator Dead Timer Reload 6) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x4C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x50 "IRQVA392,(Waveform Generator Dead Timer Underflow 7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x50 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x54 "IRQVA393,(Waveform Generator Dead Timer Reload 7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x54 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x58 "IRQVA394,(Waveform Generator Dead Timer Underflow 8) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x58 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x5C "IRQVA395,(Waveform Generator Dead Timer Reload 8) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x5C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x60 "IRQVA396,(Waveform Generator DTTI6, 7, 8) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x60 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x64 "IRQVA397,(Waveform Generator Dead Timer Underflow 9) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x64 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x68 "IRQVA398,(Waveform Generator Dead Timer Reload 9) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x68 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x6C "IRQVA399,(Waveform Generator Dead Timer Underflow 10) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x6C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x70 "IRQVA400,(Waveform Generator Dead Timer Reload 10) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x70 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x74 "IRQVA401,(Waveform Generator Dead Timer Underflow 11) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x74 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x78 "IRQVA402,(Waveform Generator Dead Timer Reload 11) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x78 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x7C "IRQVA403,(Waveform Generator DTTI9, 10, 11) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x7C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x80 "IRQVA404,(16-bit Output Compare Ch.0, Ch.1 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x80 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x84 "IRQVA405,(16-bit Output Compare Ch.2, Ch.3 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x84 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x88 "IRQVA406,(16-bit Output Compare Ch.4, Ch.5 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x88 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x8C "IRQVA407,(16-bit Output Compare Ch.6, Ch.7 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x8C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x90 "IRQVA408,(16-bit Output Compare Ch.8, Ch.9 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x90 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x94 "IRQVA409,(16-bit Output Compare Ch.10, Ch.11 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x94 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
sif cpuis("MB9DF56?M*")
|
|
group.long 0x6F8++0x0B
|
|
line.long 0x00 "IRQVA410,(16-bit Output Compare Ch.12, Ch.13 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA411,(16-bit Output Compare Ch.14, Ch.15 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA412,(16-bit Output Compare Ch.16, Ch.17 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
endif
|
|
group.long 0x704++0x17F
|
|
line.long 0x00 "IRQVA413,(16-bit Output Compare Ch.18, Ch.19 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA414,(16-bit Output Compare Ch.20, Ch.21 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA415,(16-bit Output Compare Ch.22, Ch.23 Compare Match) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA416,(Up/down Counter Unit0 Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA417,(Up/down Counter Unit0 Comparison Result Match Detection 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA418,(Up/down Counter Unit0 Comparison Result Match Detection 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA419,(Up/down Counter Unit0 Comparison Result Match Detection 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA420,(Up/down Counter Unit0 Comparison Result Match Detection 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA421,(Up/down Counter Unit0 Comparison Result Match Detection 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x24 "IRQVA422,(Up/down Counter Unit0 Comparison Result Match Detection 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x24 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x28 "IRQVA423,(Up/down Counter Unit1 Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x28 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x2C "IRQVA424,(Up/down Counter Unit1 Comparison Result Match Detection 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x2C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x30 "IRQVA425,(Up/down Counter Unit1 Comparison Result Match Detection 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x30 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x34 "IRQVA426,(Up/down Counter Unit1 Comparison Result Match Detection 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x34 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x38 "IRQVA427,(Up/down Counter Unit1 Comparison Result Match Detection 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x38 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x3C "IRQVA428,(Up/down Counter Unit1 Comparison Result Match Detection 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x3C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x40 "IRQVA429,(Up/down Counter Unit1 Comparison Result Match Detection 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x40 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x44 "IRQVA430,(Up/down Counter Unit2 Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x44 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x48 "IRQVA431,(Up/down Counter Unit2 Comparison Result Match Detection 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x48 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x4C "IRQVA432,(Up/down Counter Unit2 Comparison Result Match Detection 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x4C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x50 "IRQVA433,(Up/down Counter Unit2 Comparison Result Match Detection 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x50 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x54 "IRQVA434,(Up/down Counter Unit2 Comparison Result Match Detection 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x54 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x58 "IRQVA435,(Up/down Counter Unit2 Comparison Result Match Detection 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x58 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x5C "IRQVA436,(Up/down Counter Unit2 Comparison Result Match Detection 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x5C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x60 "IRQVA437,(Up/down Counter Unit3 Interrupt) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x60 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x64 "IRQVA438,(Up/down Counter Unit3 Comparison Result Match Detection 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x64 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x68 "IRQVA439,(Up/down Counter Unit3 Comparison Result Match Detection 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x68 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x6C "IRQVA440,(Up/down Counter Unit3 Comparison Result Match Detection 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x6C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x70 "IRQVA441,(Up/down Counter Unit3 Comparison Result Match Detection 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x70 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x74 "IRQVA442,(Up/down Counter Unit3 Comparison Result Match Detection 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x74 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x78 "IRQVA443,(Up/down Counter Unit3 Comparison Result Match Detection 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x78 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x7C "IRQVA444,(4ch A/D Converter Unit0 Conversion Complete 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x7C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x80 "IRQVA445,(4ch A/D Converter Unit0 Conversion Complete 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x80 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x84 "IRQVA446,(4ch A/D Converter Unit0 Conversion Complete 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x84 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x88 "IRQVA447,(4ch A/D Converter Unit0 Conversion Complete 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x88 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x8C "IRQVA448,(4ch A/D Converter Unit0 Conversion Complete 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x8C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x90 "IRQVA449,(4ch A/D Converter Unit0 Conversion Complete 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x90 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x94 "IRQVA450,(4ch A/D Converter Unit0 Conversion Complete 6) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x94 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x98 "IRQVA451,(4ch A/D Converter Unit0 Conversion Complete 7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x98 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x9C "IRQVA452,(4ch A/D Converter Unit0 Range Comparison 0/1/2/3/4/5/6/7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x9C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xA0 "IRQVA453,(4ch A/D Converter Unit1 Conversion Complete 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xA0 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xA4 "IRQVA454,(4ch A/D Converter Unit1 Conversion Complete 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xA4 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xA8 "IRQVA455,(4ch A/D Converter Unit1 Conversion Complete 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xA8 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xAC "IRQVA456,(4ch A/D Converter Unit1 Conversion Complete 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xAC 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xB0 "IRQVA457,(4ch A/D Converter Unit1 Conversion Complete 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xB0 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xB4 "IRQVA458,(4ch A/D Converter Unit1 Conversion Complete 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xB4 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xB8 "IRQVA459,(4ch A/D Converter Unit1 Conversion Complete 6) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xB8 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xBC "IRQVA460,(4ch A/D Converter Unit1 Conversion Complete 7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xBC 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xC0 "IRQVA461,(4ch A/D Converter Unit1 Range Comparison 0/1/2/3/4/5/6/7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xC0 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xC4 "IRQVA462,(16-bit Input Capture Ch.0, Ch.1 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xC4 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xC8 "IRQVA463,(16-bit Input Capture Ch.2, Ch.3 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xC8 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xCC "IRQVA464,(16-bit Input Capture Ch.4, Ch.5 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xCC 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xD0 "IRQVA465,(16-bit Input Capture Ch.6, Ch.7 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xD0 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xD4 "IRQVA466,(16-bit Input Capture Ch.8, Ch.9 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xD4 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0xD8 "IRQVA467,(16-bit Input Capture Ch.10, Ch.11 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0xD8 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
sif cpuis("MB9DF56?M*")
|
|
group.long 0x7E0++0x07
|
|
line.long 0x00 "IRQVA468,(16-bit Input Capture Ch.12, Ch.13 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA469,(16-bit Input Capture Ch.14 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
else
|
|
group.long 0x7E0++0x03
|
|
line.long 0x00 "IRQVA468,(16-bit Input Capture Ch.12 Fetching) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
endif
|
|
group.long 0x7E8++0x9B
|
|
line.long 0x00 "IRQVA470,(12-bit ADC Conversion Complete 0) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x04 "IRQVA471,(12-bit ADC Conversion Complete 1) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x08 "IRQVA472,(12-bit ADC Conversion Complete 2) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x0C "IRQVA473,(12-bit ADC Conversion Complete 3) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x10 "IRQVA474,(12-bit ADC Conversion Complete 4) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x14 "IRQVA475,(12-bit ADC Conversion Complete 5) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x14 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x18 "IRQVA476,(12-bit ADC Conversion Complete 6) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x1C "IRQVA477,(12-bit ADC Conversion Complete 7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x1C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x20 "IRQVA478,(12-bit ADC Conversion Complete 8) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x20 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x24 "IRQVA479,(12-bit ADC Conversion Complete 9) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x24 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x28 "IRQVA480,(12-bit ADC Conversion Complete 10) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x28 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x2C "IRQVA481,(12-bit ADC Conversion Complete 11) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x2C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x30 "IRQVA482,(12-bit ADC Conversion Complete 12) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x30 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x34 "IRQVA483,(12-bit ADC Conversion Complete 13) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x34 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x38 "IRQVA484,(12-bit ADC Conversion Complete 14) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x38 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x3C "IRQVA485,(12-bit ADC Conversion Complete 15) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x3C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x40 "IRQVA486,(12-bit ADC Conversion Complete 16) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x40 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x44 "IRQVA487,(12-bit ADC Conversion Complete 17) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x44 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x48 "IRQVA488,(12-bit ADC Conversion Complete 18) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x48 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x4C "IRQVA489,(12-bit ADC Conversion Complete 19) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x4C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x50 "IRQVA490,(12-bit ADC Conversion Complete 20) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x50 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x54 "IRQVA491,(12-bit ADC Conversion Complete 21) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x54 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x58 "IRQVA492,(12-bit ADC Conversion Complete 22) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x58 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x5C "IRQVA493,(12-bit ADC Conversion Complete 23) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x5C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x60 "IRQVA494,(12-bit ADC Conversion Complete 24) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x60 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x64 "IRQVA495,(12-bit ADC Conversion Complete 25) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x64 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x68 "IRQVA496,(12-bit ADC Conversion Complete 26) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x68 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x6C "IRQVA497,(12-bit ADC Conversion Complete 27) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x6C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x70 "IRQVA498,(12-bit ADC Conversion Complete 28) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x70 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x74 "IRQVA499,(12-bit ADC Conversion Complete 29) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x74 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x78 "IRQVA500,(12-bit ADC Conversion Complete 30) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x78 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x7C "IRQVA501,(12-bit ADC Conversion Complete 31) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x7C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x80 "IRQVA502,(12-bit ADC Range Comparison 0/1/2/3/4/5/6/7) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x80 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x84 "IRQVA503,(12-bit ADC Range Comparison 8/9/10/11/12/13/14/15) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x84 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x88 "IRQVA504,(12-bit ADC Range Comparison 16/17/18/19/20/21/22/23) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x88 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x8C "IRQVA505,(12-bit ADC Range Comparison 24/25/26/27/28/29/30/31) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x8C 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x90 "IRQVA506,(12-bit ADC Scan Conversion Complete) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x90 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x94 "IRQVA507,(PLL Gear For FlexRay) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x94 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
line.long 0x98 "IRQVA508,(PLL Alarm For FlexRay) IRC IRQ Vector Address Register"
|
|
hexmask.long 0x98 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
tree.end
|
|
tree "NMI Priority Level Registers"
|
|
group.long 0x890++0x13
|
|
line.long 0x00 "NMIPL0,IRC NMI Priority Level Register"
|
|
rbitfld.long 0x00 0.--3. " NMIPL0 ,NMI0 (NMIX pin) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x04 "NMIPL1,IRC NMI Priority Level Register"
|
|
bitfld.long 0x04 24.--27. " NMIPL7 ,NMI7 (SW-WDT) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
bitfld.long 0x04 16.--19. " NMIPL6 ,NMI6 (HW-WDT) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
bitfld.long 0x04 8.--11. " NMIPL5 ,NMI5 (CSV/profile) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
bitfld.long 0x04 0.--3. " NMIPL4 ,NMI4 (LVD) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x08 "NMIPL2,IRC NMI Priority Level Register"
|
|
bitfld.long 0x08 8.--11. " NMIPL9 ,NMI9 (CPU livelock) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
bitfld.long 0x08 0.--3. " NMIPL8 ,NMI8 (IRC 2-bit ECC error detection) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x0C "NMIPL3,IRC NMI Priority Level Register"
|
|
bitfld.long 0x0C 8.--11. " NMIPL13 ,NMI13 (Memory protection (MPU) protection violation) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x10 "NMIPL4,IRC NMI Priority Level Register"
|
|
bitfld.long 0x10 16.--19. " NMIPL18 ,NMI18 (Time protection (TPU) protection violation) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??AE")
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "NMIPL6,IRC NMI Priority Level Register"
|
|
bitfld.long 0x00 8.--11. " NMIPL25 ,NMI25 (R/D converter ch.1) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
bitfld.long 0x00 0.--3. " NMIPL24 ,NMI24 (R/D converter ch.0) priority level bits" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
endif
|
|
tree.end
|
|
tree "IRQ Priority Level Registers"
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "IRQPL0,IRQ Priority Level Register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (SW-WDT prior warning interrupt request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (HW-WDT prior warning interrupt request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (LPC RUN profile update complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "IRQPL2,IRQ Priority Level Register"
|
|
bitfld.long 0x00 24.--28. " IRQPL11 ,IRQ11 (WorkFLASH unit1 hang interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL10 ,IRQ10 (WorkFLASH unit0 hang interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL8 ,IRQ8 (TCFLASH unit 0/1 1-bit error correction/ready/hang interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8C0++0x0F
|
|
line.long 0x00 "IRQPL4,IRQ Priority Level Register"
|
|
bitfld.long 0x00 0.--4. " IRQPL16 ,IRQ16 (Interrupt controller unit 0/1 ECC 1-bit error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "IRQPL5,IRQ Priority Level Register"
|
|
bitfld.long 0x04 8.--12. " IRQPL21 ,IRQ21 (WorkFLASH unit 1 1-bit error correction interrupt/ready interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " IRQPL20 ,IRQ20 (WorkFLASH unit 0 1-bit error correction interrupt/ready interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "IRQPL6,IRQ Priority Level Register"
|
|
bitfld.long 0x08 24.--28. " IRQPL27 ,IRQ27 (External interrupt ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " IRQPL26 ,IRQ26 (External interrupt ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 8.--12. " IRQPL25 ,IRQ25 (External interrupt ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 0.--4. " IRQPL24 ,IRQ24 (External interrupt ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x0C "IRQPL7,IRQ Priority Level Register"
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bitfld.long 0x0C 24.--28. " IRQPL31 ,IRQ31 (External interrupt ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 16.--20. " IRQPL30 ,IRQ30 (External interrupt ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 8.--12. " IRQPL29 ,IRQ29 (External interrupt ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0.--4. " IRQPL28 ,IRQ28 (External interrupt ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x8E8++0x03
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line.long 0x00 "IRQPL14,IRQ Priority Level Register"
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bitfld.long 0x00 16.--20. " IRQPL58 ,IRQ58 (CAN ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL57 ,IRQ57 (CAN ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL56 ,IRQ56 (CAN ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x8F0++0x03
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line.long 0x00 "IRQPL16,IRQ Priority Level Register"
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bitfld.long 0x00 24.--28. " IRQPL67 ,IRQ67 (Multi-function serial interface ch.1 transmission complete) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " IRQPL66 ,IRQ66 (Multi-function serial interface ch.1 reception complete/status) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL65 ,IRQ65 (Multi-function serial interface ch.0 transmission complete) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL64 ,IRQ64 (Multi-function serial interface ch.0 reception complete/status) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
sif cpuis("MB9DF56?M*")
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group.long 0x8F4++0x03
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line.long 0x00 "IRQPL17,IRQ Priority Level Register"
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bitfld.long 0x00 24.--28. " IRQPL71 ,IRQ71 (Multi-function serial interface ch.3 transmission complete) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " IRQPL70 ,IRQ70 (Multi-function serial interface ch.3 reception complete/status) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL69 ,IRQ69 (Multi-function serial interface ch.2 transmission complete) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL68 ,IRQ68 (Multi-function serial interface ch.2 reception complete/status) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
endif
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group.long 0x8F8++0x03
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line.long 0x00 "IRQPL18,IRQ Priority Level Register"
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|
bitfld.long 0x00 8.--12. " IRQPL73 ,IRQ73 (Multi-function serial interface ch.4 transmission complete) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL72 ,IRQ72 (Multi-function serial interface ch.4 reception complete/status) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x8910++0x03
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line.long 0x00 "IRQPL24,IRQ Priority Level Register"
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|
bitfld.long 0x00 0.--4. " IRQPL96 ,IRQ96 (Inter-processor communication (IPCU) interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x891C++0x03
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line.long 0x00 "IRQPL27,IRQ Priority Level Register"
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|
bitfld.long 0x00 16.--20. " IRQPL110 ,IRQ110 (TCRAM unit 0/1 RAM diagnosis interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x8924++0x03
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line.long 0x00 "IRQPL29,IRQ Priority Level Register"
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|
bitfld.long 0x00 8.--12. " IRQPL117 ,IRQ117 (CR calibration interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x8930++0x07
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line.long 0x00 "IRQPL32,IRQ Priority Level Register"
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|
bitfld.long 0x00 24.--28. " IRQPL131 ,IRQ131 (Base timer ch.3 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " IRQPL130 ,IRQ130 (Base timer ch.2 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL129 ,IRQ129 (Base timer ch.1 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL128 ,IRQ128 (Base timer ch.0 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x04 "IRQPL33,IRQ Priority Level Register"
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|
bitfld.long 0x04 24.--28. " IRQPL135 ,IRQ135 (Base timer ch.7 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x04 16.--20. " IRQPL134 ,IRQ134 (Base timer ch.6 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x04 8.--12. " IRQPL133 ,IRQ133 (Base timer ch.5 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x04 0.--4. " IRQPL132 ,IRQ132 (Base timer ch.4 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("MB9DF56?M*")
|
|
group.long 0x8938++0x03
|
|
line.long 0x00 "IRQPL34,IRQ Priority Level Register"
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|
bitfld.long 0x00 24.--28. " IRQPL139 ,IRQ139 (Base timer ch.11 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " IRQPL138 ,IRQ138 (Base timer ch.10 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL137 ,IRQ137 (Base timer ch.9 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL136 ,IRQ136 (Base timer ch.8 IRQ0/IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
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group.long 0x8960++0x07
|
|
line.long 0x00 "IRQPL44,IRQ Priority Level Register"
|
|
bitfld.long 0x00 24.--28. " IRQPL179 ,IRQ179 (32-bit free-run timer ch.3 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " IRQPL178 ,IRQ178 (32-bit free-run timer ch.2 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL177 ,IRQ177 (32-bit free-run timer ch.1 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL176 ,IRQ176 (32-bit free-run timer ch.0 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x04 "IRQPL45,IRQ Priority Level Register"
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bitfld.long 0x04 0.--4. " IRQPL180 ,IRQ180 (32-bit free-run timer ch.4 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x8970++0x03
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line.long 0x00 "IRQPL48,IRQ Priority Level Register"
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|
bitfld.long 0x00 16.--20. " IRQPL194 ,IRQ194 (32-bit input capture ch.4, ch.5 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL193 ,IRQ193 (32-bit input capture ch.2, ch.3 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL192 ,IRQ192 (32-bit input capture ch.0, ch.1 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x89C0++0x0B
|
|
line.long 0x00 "IRQPL68,IRQ Priority Level Register"
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|
bitfld.long 0x00 24.--28. " IRQPL275 ,IRQ275 (DMAC ch.2, ch.10 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " IRQPL274 ,IRQ274 (DMAC ch.1, ch.9 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " IRQPL273 ,IRQ273 (DMAC ch.0, ch.8 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL272 ,IRQ272 (DMAC transfer error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x04 "IRQPL69,IRQ Priority Level Register"
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bitfld.long 0x04 24.--28. " IRQPL279 ,IRQ279 (DMAC ch.6, ch.14 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 16.--20. " IRQPL278 ,IRQ278 (DMAC ch.5, ch.13 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 8.--12. " IRQPL277 ,IRQ277 (DMAC ch.4, ch.12 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--4. " IRQPL276 ,IRQ276 (DMAC ch.3, ch.11 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x08 "IRQPL70,IRQ Priority Level Register"
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|
bitfld.long 0x08 0.--4. " IRQPL280 ,IRQ280 (DMAC ch.7, ch.15 transfer complete interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0x89E4++0x07
|
|
line.long 0x00 "IRQPL77,IRQ Priority Level Register"
|
|
bitfld.long 0x00 16.--20. " IRQPL310 ,IRQ310 (Main clock timer interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 8.--12. " IRQPL309 ,IRQ309 (Slow-CR clock timer interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--4. " IRQPL308 ,IRQ308 (Fast-CR clock timer interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "IRQPL78,IRQ Priority Level Register"
|
|
bitfld.long 0x04 0.--4. " IRQPL312 ,IRQ312 (PMU interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
group.long 0x89F0++0x03
|
|
line.long 0x00 "IRQPL80,IRQ Priority Level Register"
|
|
bitfld.long 0x00 24.--28. " IRQPL323 ,IRQ323 (FlexRay timer 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL222 ,IRQ322 (FlexRay timer 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 8.--12. " IRQPL321 ,IRQ321 (FlexRay1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--4. " IRQPL320 ,IRQ320 (FlexRay0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0x89F4++0xBB
|
|
line.long 0x00 "IRQPL81,IRQ Priority Level Register"
|
|
bitfld.long 0x00 24.--28. " IRQPL327 ,IRQ327 (16-bit free-run timer ch.3 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL326 ,IRQ326 (16-bit free-run timer ch.2 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL325 ,IRQ325 (16-bit free-run timer ch.1 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IRQPL324 ,IRQ324 (16-bit free-run timer ch.0 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x04 "IRQPL82,IRQ Priority Level Register"
|
|
bitfld.long 0x04 24.--28. " IRQPL331 ,IRQ331 (16-bit free-run timer ch.7 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 16.--20. " IRQPL330 ,IRQ330 (16-bit free-run timer ch.6 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x04 8.--12. " IRQPL329 ,IRQ329 (16-bit free-run timer ch.5 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--4. " IRQPL328 ,IRQ328 (16-bit free-run timer ch.4 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x08 "IRQPL83,IRQ Priority Level Register"
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bitfld.long 0x08 24.--28. " IRQPL335 ,IRQ335 (16-bit free-run timer ch.11 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 16.--20. " IRQPL334 ,IRQ334 (16-bit free-run timer ch.10 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--12. " IRQPL333 ,IRQ333 (16-bit free-run timer ch.9 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 0.--4. " IRQPL332 ,IRQ332 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x0C "IRQPL84,IRQ Priority Level Register"
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bitfld.long 0x0C 24.--28. " IRQPL339 ,IRQ339 (16-bit free-run timer ch.15 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 16.--20. " IRQPL338 ,IRQ338 (16-bit free-run timer ch.14 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 8.--12. " IRQPL337 ,IRQ337 (16-bit free-run timer ch.13 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0.--4. " IRQPL336 ,IRQ336 (16-bit free-run timer ch.12 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x10 "IRQPL85,IRQ Priority Level Register"
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bitfld.long 0x10 24.--28. " IRQPL343 ,IRQ343 (MVA0 three-phase current normalization end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16.--20. " IRQPL342 ,IRQ342 (MVA0 angular calculation end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 8.--12. " IRQPL341 ,IRQ341 (16-bit free-run timer ch.17 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 0.--4. " IRQPL340 ,IRQ340 (16-bit free-run timer ch.16 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x14 "IRQPL86,IRQ Priority Level Register"
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bitfld.long 0x14 24.--28. " IRQPL347 ,IRQ347 (MVA0 two-phase to three-phase AC conversion end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 16.--20. " IRQPL346 ,IRQ346 (MVA0 current to voltage conversion end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 8.--12. " IRQPL345 ,IRQ345 (MVA0 PID control end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 0.--4. " IRQPL344 ,IRQ344 (MVA0 three-phase to two-phase DC conversion interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x18 "IRQPL87,IRQ Priority Level Register"
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bitfld.long 0x18 24.--28. " IRQPL351 ,IRQ351 (MVA0 failure detection error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 16.--20. " IRQPL350 ,IRQ350 (MVA0 floating-point non-normalized error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 8.--12. " IRQPL349 ,IRQ349 (MVA0 underflow interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 0.--4. " IRQPL348 ,IRQ348 (MVA0 overflow interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x1C "IRQPL88,IRQ Priority Level Register"
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bitfld.long 0x1C 16.--20. " IRQPL354 ,IRQ354 (MVA0 cumulative three-phase current abnormality detection error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 8.--12. " IRQPL353 ,IRQ353 (MVA0 R/D converter diagnosis error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 0.--4. " IRQPL352 ,IRQ352 (MVA0 calculation data update error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x20 "IRQPL89,IRQ Priority Level Register"
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bitfld.long 0x20 24.--28. " IRQPL359 ,IRQ359 (MVA1 three-phase current normalization end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 16.--20. " IRQPL358 ,IRQ358 (MVA1 angular calculation end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 8.--12. " IRQPL357 ,IRQ357 (MVA0 calculation overtime error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 0.--4. " IRQPL356 ,IRQ356 (MVA0 three-phase to two-phase DC value abnormality detection error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x24 "IRQPL90,IRQ Priority Level Register"
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bitfld.long 0x24 24.--28. " IRQPL363 ,IRQ363 (MVA1 two-phase to three-phase AC conversion end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 16.--20. " IRQPL362 ,IRQ362 (MVA1 current to voltage conversion end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 8.--12. " IRQPL361 ,IRQ361 (MVA1 PID control end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 0.--4. " IRQPL360 ,IRQ360 (MVA1 three-phase to two-phase DC conversion end interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x28 "IRQPL91,IRQ Priority Level Register"
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bitfld.long 0x28 24.--28. " IRQPL367 ,IRQ367 (MVA1 failure detection error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x28 16.--20. " IRQPL366 ,IRQ366 (MVA1 floating-point non-normalized error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x28 8.--12. " IRQPL365 ,IRQ365 (MVA1 underflow interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x28 0.--4. " IRQPL364 ,IRQ364 (MVA1 overflow interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x2C "IRQPL92,IRQ Priority Level Register"
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bitfld.long 0x2C 16.--20. " IRQPL370 ,IRQ370 (MVA1 cumulative three-phase current abnormality detection error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x2C 8.--12. " IRQPL369 ,IRQ369 (MVA1 R/D converter diagnosis error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x2C 0.--4. " IRQPL368 ,IRQ368 (MVA1 calculation data update error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x30 "IRQPL93,IRQ Priority Level Register"
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bitfld.long 0x30 24.--28. " IRQPL375 ,IRQ375 (MVA1 free-run timer 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 16.--20. " IRQPL374 ,IRQ374 (MVA0 free-run timer 0 detection/compare clear interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 8.--12. " IRQPL373 ,IRQ373 (MVA1 calculation overtime error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 0.--4. " IRQPL372 ,IRQ372 (MVA1 three-phase to two-phase DC value abnormality detection error interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x34 "IRQPL94,IRQ Priority Level Register"
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bitfld.long 0x34 24.--28. " IRQPL379 ,IRQ379 (Waveform generator dead timer reload 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 16.--20. " IRQPL378 ,IRQ378 (Waveform generator dead timer underflow 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 8.--12. " IRQPL377 ,IRQ377 (Waveform generator dead timer reload 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 0.--4. " IRQPL376 ,IRQ376 (Waveform generator dead timer underflow 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x38 "IRQPL95,IRQ Priority Level Register"
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bitfld.long 0x38 24.--28. " IRQPL383 ,IRQ383 (Waveform generator dead timer underflow 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 16.--20. " IRQPL382 ,IRQ382 (Waveform generator DTTI0, 1, 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 8.--12. " IRQPL381 ,IRQ381 (Waveform generator dead timer reload 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 0.--4. " IRQPL380 ,IRQ380 (Waveform generator dead timer underflow 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x3C "IRQPL96,IRQ Priority Level Register"
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bitfld.long 0x3C 24.--28. " IRQPL387 ,IRQ387 (Waveform generator dead timer underflow 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x3C 16.--20. " IRQPL386 ,IRQ386 (Waveform generator dead timer reload 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x3C 8.--12. " IRQPL385 ,IRQ385 (Waveform generator dead timer underflow 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x3C 0.--4. " IRQPL384 ,IRQ384 (Waveform generator dead timer reload 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x40 "IRQPL97,IRQ Priority Level Register"
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bitfld.long 0x40 24.--28. " IRQPL391 ,IRQ391 (Waveform generator dead timer reload 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 16.--20. " IRQPL390 ,IRQ390 (Waveform generator dead timer underflow 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 8.--12. " IRQPL389 ,IRQ389 (Waveform generator DTTI3, 4, 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 0.--4. " IRQPL388 ,IRQ388 (Waveform generator dead timer reload 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x44 "IRQPL98,IRQ Priority Level Register"
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bitfld.long 0x44 24.--28. " IRQPL395 ,IRQ395 (Waveform generator dead timer reload 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x44 16.--20. " IRQPL394 ,IRQ394 (Waveform generator dead timer underflow 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x44 8.--12. " IRQPL393 ,IRQ393 (Waveform generator dead timer reload 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x44 0.--4. " IRQPL392 ,IRQ392 (Waveform generator dead timer underflow 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x48 "IRQPL99,IRQ Priority Level Register"
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bitfld.long 0x48 24.--28. " IRQPL399 ,IRQ399 (Waveform generator dead timer underflow 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 16.--20. " IRQPL398 ,IRQ398 (Waveform generator dead timer reload 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 8.--12. " IRQPL397 ,IRQ397 (Waveform generator dead timer underflow 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 0.--4. " IRQPL396 ,IRQ396 (Waveform generator DTTI6, 7, 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x4C "IRQPL100,IRQ Priority Level Register"
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bitfld.long 0x4C 24.--28. " IRQPL403 ,IRQ403 (Waveform generator DTTI9, 10, 11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4C 16.--20. " IRQPL402 ,IRQ402 (Waveform generator dead timer reload 11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4C 8.--12. " IRQPL401 ,IRQ401 (Waveform generator dead timer underflow 11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4C 0.--4. " IRQPL400 ,IRQ400 (Waveform generator dead timer reload 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x50 "IRQPL101,IRQ Priority Level Register"
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bitfld.long 0x50 24.--28. " IRQPL407 ,IRQ407 (16-bit output compare ch.6, ch.7 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 16.--20. " IRQPL406 ,IRQ406 (16-bit output compare ch.4, ch.5 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 8.--12. " IRQPL405 ,IRQ405 (16-bit output compare ch.2, ch.3 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 0.--4. " IRQPL404 ,IRQ404 (16-bit output compare ch.0, ch.1 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x54 "IRQPL102,IRQ Priority Level Register"
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sif cpuis("MB9DF56?M*")
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bitfld.long 0x54 24.--28. " IRQPL411 ,IRQ411 (16-bit output compare ch.14, ch.15 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 16.--20. " IRQPL410 ,IRQ410 (16-bit output compare ch.12, ch.13 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 8.--12. " IRQPL409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 0.--4. " IRQPL408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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else
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bitfld.long 0x54 8.--12. " IRQPL409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 0.--4. " IRQPL408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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endif
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line.long 0x58 "IRQPL103,IRQ Priority Level Register"
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bitfld.long 0x58 24.--28. " IRQPL415 ,IRQ415 (16-bit output compare ch.22, ch.23 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 16.--20. " IRQPL414 ,IRQ414 (16-bit output compare ch.20, ch.21 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 8.--12. " IRQPL413 ,IRQ413 (16-bit output compare ch.18, ch.19 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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sif cpuis("MB9DF56?M*")
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bitfld.long 0x58 0.--4. " IRQPL412 ,IRQ412 (16-bit output compare ch.16, ch.17 compare match) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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endif
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line.long 0x5C "IRQPL104,IRQ Priority Level Register"
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bitfld.long 0x5C 24.--28. " IRQPL419 ,IRQ419 (Up/down counter unit0 comparison result match detection 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x5C 16.--20. " IRQPL418 ,IRQ418 (Up/down counter unit0 comparison result match detection 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x5C 8.--12. " IRQPL417 ,IRQ417 (Up/down counter unit0 comparison result match detection 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x5C 0.--4. " IRQPL416 ,IRQ416 (Up/down counter unit0 interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x60 "IRQPL105,IRQ Priority Level Register"
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bitfld.long 0x60 24.--28. " IRQPL423 ,IRQ423 (Up/down counter unit1 interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x60 16.--20. " IRQPL422 ,IRQ422 (Up/down counter unit0 comparison result match detection 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x60 8.--12. " IRQPL421 ,IRQ421 (Up/down counter unit0 comparison result match detection 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x60 0.--4. " IRQPL420 ,IRQ420 (Up/down counter unit0 comparison result match detection 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x64 "IRQPL106,IRQ Priority Level Register"
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bitfld.long 0x64 24.--28. " IRQPL427 ,IRQ427 (Up/down counter unit1 comparison result match detection 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x64 16.--20. " IRQPL426 ,IRQ426 (Up/down counter unit1 comparison result match detection 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x64 8.--12. " IRQPL425 ,IRQ425 (Up/down counter unit1 comparison result match detection 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x64 0.--4. " IRQPL424 ,IRQ424 (Up/down counter unit1 comparison result match detection 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x68 "IRQPL107,IRQ Priority Level Register"
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bitfld.long 0x68 24.--28. " IRQPL431 ,IRQ431 (Up/down counter unit2 comparison result match detection 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x68 16.--20. " IRQPL430 ,IRQ430 (Up/down counter unit2 interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x68 8.--12. " IRQPL429 ,IRQ429 (Up/down counter unit1 comparison result match detection 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x68 0.--4. " IRQPL428 ,IRQ428 (Up/down counter unit1 comparison result match detection 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x6C "IRQPL108,IRQ Priority Level Register"
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bitfld.long 0x6C 24.--28. " IRQPL435 ,IRQ435 (Up/down counter unit2 comparison result match detection 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x6C 16.--20. " IRQPL434 ,IRQ434 (Up/down counter unit2 comparison result match detection 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x6C 8.--12. " IRQPL433 ,IRQ433 (Up/down counter unit2 comparison result match detection 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x6C 0.--4. " IRQPL432 ,IRQ432 (Up/down counter unit2 comparison result match detection 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x70 "IRQPL109,IRQ Priority Level Register"
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bitfld.long 0x70 24.--28. " IRQPL439 ,IRQ439 (Up/down counter unit3 comparison result match detection 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x70 16.--20. " IRQPL438 ,IRQ438 (Up/down counter unit3 comparison result match detection 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x70 8.--12. " IRQPL437 ,IRQ437 (Up/down counter unit3 interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x70 0.--4. " IRQPL436 ,IRQ436 (Up/down counter unit2 comparison result match detection 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x74 "IRQPL110,IRQ Priority Level Register"
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bitfld.long 0x74 24.--28. " IRQPL443 ,IRQ443 (Up/down counter unit3 comparison result match detection 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x74 16.--20. " IRQPL442 ,IRQ442 (Up/down counter unit3 comparison result match detection 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x74 8.--12. " IRQPL441 ,IRQ441 (Up/down counter unit3 comparison result match detection 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x74 0.--4. " IRQPL440 ,IRQ440 (Up/down counter unit3 comparison result match detection 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x78 "IRQPL111,IRQ Priority Level Register"
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bitfld.long 0x78 24.--28. " IRQPL447 ,IRQ447 (4ch A/D converter unit0 conversion complete 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x78 16.--20. " IRQPL446 ,IRQ446 (4ch A/D converter unit0 conversion complete 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x78 8.--12. " IRQPL445 ,IRQ445 (4ch A/D converter unit0 conversion complete 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x78 0.--4. " IRQPL444 ,IRQ444 (4ch A/D converter unit0 conversion complete 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x7C "IRQPL112,IRQ Priority Level Register"
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bitfld.long 0x7C 24.--28. " IRQPL451 ,IRQ451 (4ch A/D converter unit0 conversion complete 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x7C 16.--20. " IRQPL450 ,IRQ450 (4ch A/D converter unit0 conversion complete 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x7C 8.--12. " IRQPL449 ,IRQ449 (4ch A/D converter unit0 conversion complete 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x7C 0.--4. " IRQPL448 ,IRQ448 (4ch A/D converter unit0 conversion complete 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x80 "IRQPL113,IRQ Priority Level Register"
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bitfld.long 0x80 24.--28. " IRQPL455 ,IRQ455 (4ch A/D converter unit1 conversion complete 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x80 16.--20. " IRQPL454 ,IRQ454 (4ch A/D converter unit1 conversion complete 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x80 8.--12. " IRQPL453 ,IRQ453 (4ch A/D converter unit1 conversion complete 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x80 0.--4. " IRQPL452 ,IRQ452 (4ch A/D converter unit0 range comparison 0/1/2/3/4/5/6/7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x84 "IRQPL114,IRQ Priority Level Register"
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bitfld.long 0x84 24.--28. " IRQPL459 ,IRQ459 (4ch A/D converter unit1 conversion complete 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x84 16.--20. " IRQPL458 ,IRQ458 (4ch A/D converter unit1 conversion complete 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x84 8.--12. " IRQPL457 ,IRQ457 (4ch A/D converter unit1 conversion complete 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x84 0.--4. " IRQPL456 ,IRQ456 (4ch A/D converter unit1 conversion complete 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x88 "IRQPL115,IRQ Priority Level Register"
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bitfld.long 0x88 24.--28. " IRQPL463 ,IRQ463 (16-bit input capture ch.2, ch.3 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x88 16.--20. " IRQPL462 ,IRQ462 (16-bit input capture ch.0, ch.1 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x88 8.--12. " IRQPL461 ,IRQ461 (4ch A/D converter unit1 range comparison 0/1/2/3/4/5/6/7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x88 0.--4. " IRQPL460 ,IRQ460 (4ch A/D converter unit1 conversion complete 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x8C "IRQPL116,IRQ Priority Level Register"
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bitfld.long 0x8C 24.--28. " IRQPL467 ,IRQ467 (16-bit input capture ch.10, ch.11 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x8C 16.--20. " IRQPL466 ,IRQ466 (16-bit input capture ch.8, ch.9 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x8C 8.--12. " IRQPL465 ,IRQ465 (16-bit input capture ch.6, ch.7 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x8C 0.--4. " IRQPL464 ,IRQ464 (16-bit input capture ch.4, ch.5 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x90 "IRQPL117,IRQ Priority Level Register"
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bitfld.long 0x90 24.--28. " IRQPL471 ,IRQ471 (12-bit ADC conversion complete 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x90 16.--20. " IRQPL470 ,IRQ470 (12-bit ADC conversion complete 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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sif cpuis("MB9DF56?M*")
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bitfld.long 0x90 8.--12. " IRQPL469 ,IRQ469 (16-bit input capture ch.14 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x90 0.--4. " IRQPL468 ,IRQ468 (16-bit input capture ch.12, ch.13 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.long 0x90 0.--4. " IRQPL468 ,IRQ468 (16-bit input capture ch.12 fetching) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
line.long 0x94 "IRQPL118,IRQ Priority Level Register"
|
|
bitfld.long 0x94 24.--28. " IRQPL475 ,IRQ475 (12-bit ADC conversion complete 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x94 16.--20. " IRQPL474 ,IRQ474 (12-bit ADC conversion complete 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x94 8.--12. " IRQPL473 ,IRQ473 (12-bit ADC conversion complete 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x94 0.--4. " IRQPL472 ,IRQ472 (12-bit ADC conversion complete 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x98 "IRQPL119,IRQ Priority Level Register"
|
|
bitfld.long 0x98 24.--28. " IRQPL479 ,IRQ479 (12-bit ADC conversion complete 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x98 16.--20. " IRQPL478 ,IRQ478 (12-bit ADC conversion complete 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x98 8.--12. " IRQPL477 ,IRQ477 (12-bit ADC conversion complete 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x98 0.--4. " IRQPL476 ,IRQ476 (12-bit ADC conversion complete 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x9C "IRQPL120,IRQ Priority Level Register"
|
|
bitfld.long 0x9C 24.--28. " IRQPL483 ,IRQ483 (12-bit ADC conversion complete 13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x9C 16.--20. " IRQPL482 ,IRQ482 (12-bit ADC conversion complete 12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x9C 8.--12. " IRQPL481 ,IRQ481 (12-bit ADC conversion complete 11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x9C 0.--4. " IRQPL480 ,IRQ480 (12-bit ADC conversion complete 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xA0 "IRQPL121,IRQ Priority Level Register"
|
|
bitfld.long 0xA0 24.--28. " IRQPL487 ,IRQ487 (12-bit ADC conversion complete 17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xA0 16.--20. " IRQPL486 ,IRQ486 (12-bit ADC conversion complete 16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xA0 8.--12. " IRQPL485 ,IRQ485 (12-bit ADC conversion complete 15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xA0 0.--4. " IRQPL484 ,IRQ484 (12-bit ADC conversion complete 14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xA4 "IRQPL122,IRQ Priority Level Register"
|
|
bitfld.long 0xA4 24.--28. " IRQPL491 ,IRQ491 (12-bit ADC conversion complete 21) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xA4 16.--20. " IRQPL490 ,IRQ490 (12-bit ADC conversion complete 20) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xA4 8.--12. " IRQPL489 ,IRQ489 (12-bit ADC conversion complete 19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xA4 0.--4. " IRQPL488 ,IRQ488 (12-bit ADC conversion complete 18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xA8 "IRQPL123,IRQ Priority Level Register"
|
|
bitfld.long 0xA8 24.--28. " IRQPL495 ,IRQ495 (12-bit ADC conversion complete 25) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xA8 16.--20. " IRQPL494 ,IRQ494 (12-bit ADC conversion complete 24) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xA8 8.--12. " IRQPL493 ,IRQ493 (12-bit ADC conversion complete 23) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xA8 0.--4. " IRQPL492 ,IRQ492 (12-bit ADC conversion complete 22) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xAC "IRQPL124,IRQ Priority Level Register"
|
|
bitfld.long 0xAC 24.--28. " IRQPL499 ,IRQ499 (12-bit ADC conversion complete 29) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xAC 16.--20. " IRQPL498 ,IRQ498 (12-bit ADC conversion complete 28) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xAC 8.--12. " IRQPL497 ,IRQ497 (12-bit ADC conversion complete 27) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xAC 0.--4. " IRQPL496 ,IRQ496 (12-bit ADC conversion complete 26) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xB0 "IRQPL125,IRQ Priority Level Register"
|
|
bitfld.long 0xB0 24.--28. " IRQPL503 ,IRQ503 (12-bit ADC range comparison 8/9/10/11/12/13/14/15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xB0 16.--20. " IRQPL502 ,IRQ502 (12-bit ADC range comparison 0/1/2/3/4/5/6/7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xB0 8.--12. " IRQPL501 ,IRQ501 (12-bit ADC conversion complete 31) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0xB0 0.--4. " IRQPL500 ,IRQ500 (12-bit ADC conversion complete 30) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0xB4 "IRQPL126,IRQ Priority Level Register"
|
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bitfld.long 0xB4 24.--28. " IRQPL507 ,IRQ507 (Pll gear for flexray) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0xB4 16.--20. " IRQPL506 ,IRQ506 (12-bit ADC scan conversion complete) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xB4 8.--12. " IRQPL505 ,IRQ505 (12-bit ADC range comparison 24/25/26/27/28/29/30/31) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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bitfld.long 0xB4 0.--4. " IRQPL504 ,IRQ504 (12-bit ADC range comparison 16/17/18/19/20/21/22/23) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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line.long 0xB8 "IRQPL127,IRQ Priority Level Register"
|
|
bitfld.long 0xB8 0.--4. " IRQPL508 ,IRQ508 (Pll alarm for flexray) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "NMI Software Interrupt Status Register"
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "NMISIS_SET/CLR,IRC NMI Software Interrupt Set/Clear Register"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??AE")
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " NMISIS25 ,NMI25 (R/D converter ch.0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " NMISIS24 ,NMI24 (R/D converter ch.1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " NMISIS18 ,NMI18 (Time protection (TPU) protection violation) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NMISIS13 ,NMI13 (Memory protection (MPU) protection violation) software interrupt status bits" "No interrupt,Interrupt"
|
|
else
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " NMISIS18 ,NMI18 (Time protection (TPU) protection violation) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NMISIS13 ,NMI13 (Memory protection (MPU) protection violation) software interrupt status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " NMISIS9 ,NMI9 (CPU livelock) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NMISIS8 ,NMI8 (IRC 2-bit ECC error detection) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " NMISIS7 ,NMI7 (SW-WDT) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " NMISIS6 ,NMI6 (HW-WDT) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " NMISIS5 ,NMI5 (CSV/profile) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NMISIS4 ,NMI4 (LVD) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " NMISIS0 ,NMI0 (NMIX pin) software interrupt status bits" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "IRQ Software Interrupt Status Register"
|
|
group.long 0xB40++0x1B
|
|
line.long 0x00 "IRQSIS0_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS31 ,IRQ31 (External interrupt ch.7) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQSIS30 ,IRQ30 (External interrupt ch.6) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQSIS29 ,IRQ29 (External interrupt ch.5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQSIS28 ,IRQ28 (External interrupt ch.4) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
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setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS27 ,IRQ27 (External interrupt ch.3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS26 ,IRQ26 (External interrupt ch.2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS25 ,IRQ25 (External interrupt ch.1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS24 ,IRQ24 (External interrupt ch.0) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS21 ,IRQ21 (WorkFLASH unit1 1-bit error correction interrupt/ready interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS20 ,IRQ20 (WorkFLASH unit0 1-bit error correction interrupt/ready interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS16 ,IRQ16 (Interrupt controller unit0/1 ECC 1-bit error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS11 ,IRQ11 (WorkFLASH unit1 hang interrupt) IRQ11 software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS10 ,IRQ10 (WorkFLASH unit0 hang interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. -0x80 8. -0x40 8. " IRQSIS8 ,IRQ8 (TCFLASH unit 0/1 1-bit error correction interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. -0x80 3. -0x40 3. " IRQSIS3 ,IRQ3 (SW-WDT unit 0/1 prior warning interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. -0x80 2. -0x40 2. " IRQSIS2 ,IRQ2 (HW-WDT prior warning interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x80 1. -0x40 1. " IRQSIS1 ,IRQ1 (LPC RUN profile update complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQSIS1_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x04 26. -0x7C 26. -0x3C 26. " IRQSIS58 ,IRQ58 (CAN ch.2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 25. -0x7C 25. -0x3C 25. " IRQSIS57 ,IRQ57 (CAN ch.1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 24. -0x7C 24. -0x3C 24. " IRQSIS56 ,IRQ56 (CAN ch.0) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQSIS2_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x08 9. -0x78 9. -0x38 9. " IRQSIS73 ,IRQ73 (Multi-function serial interface ch.4 transmission complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 8. -0x78 8. -0x38 8. " IRQSIS72 ,IRQ72 (Multi-function serial interface ch.4 reception complete/status) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 7. -0x78 7. -0x38 7. " IRQSIS71 ,IRQ71 (Multi-function serial interface ch.3 transmission complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 6. -0x78 6. -0x38 6. " IRQSIS70 ,IRQ70 (Multi-function serial interface ch.3 reception complete/status) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 5. -0x78 5. -0x38 5. " IRQSIS69 ,IRQ69 (Multi-function serial interface ch.2 transmission complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 4. -0x78 4. -0x38 4. " IRQSIS68 ,IRQ68 (Multi-function serial interface ch.2 reception complete/status) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 3. -0x78 3. -0x38 3. " IRQSIS67 ,IRQ67 (Multi-function serial interface ch.1 transmission complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 2. -0x78 2. -0x38 2. " IRQSIS66 ,IRQ66 (Multi-function serial interface ch.1 reception complete/status) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 1. -0x78 1. -0x38 1. " IRQSIS65 ,IRQ65 (Multi-function serial interface ch.0 transmission complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 0. -0x78 0. -0x38 0. " IRQSIS64 ,IRQ64 (Multi-function serial interface ch.0 reception complete/status) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x0C "IRQSIS3_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x0C 21. -0x74 21. -0x34 21. " IRQSIS117 ,IRQ117 (CR calibration interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 14. -0x74 14. -0x34 14. " IRQSIS110 ,IRQ110 (TCRAM unit 0/1 RAM diagnosis interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 0. -0x74 0. -0x34 0. " IRQSIS96 ,IRQ96 (Inter-processor communication (IPCU) interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x10 "IRQSIS4_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x10 11. -0x70 11. -0x30 11. " IRQSIS139 ,IRQ139 (Base timer ch.11 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 10. -0x70 10. -0x30 10. " IRQSIS138 ,IRQ138 (Base timer ch.10 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 9. -0x70 9. -0x30 9. " IRQSIS137 ,IRQ137 (Base timer ch.9 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 8. -0x70 8. -0x30 8. " IRQSIS136 ,IRQ136 (Base timer ch.8 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x10 7. -0x70 7. -0x30 7. " IRQSIS135 ,IRQ135 (Base timer ch.7 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 6. -0x70 6. -0x30 6. " IRQSIS134 ,IRQ134 (Base timer ch.6 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x10 5. -0x70 5. -0x30 5. " IRQSIS133 ,IRQ133 (Base timer ch.5 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 4. -0x70 4. -0x30 4. " IRQSIS132 ,IRQ132 (Base timer ch.4 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x10 3. -0x70 3. -0x30 3. " IRQSIS131 ,IRQ131 (Base timer ch.3 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 2. -0x70 2. -0x30 2. " IRQSIS130 ,IRQ130 (Base timer ch.2 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 1. -0x70 1. -0x30 1. " IRQSIS129 ,IRQ129 (Base timer ch.1 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 0. -0x70 0. -0x30 0. " IRQSIS128 ,IRQ128 (Base timer ch.0 IRQ0/IRQ1) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x14 "IRQSIS5_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " IRQSIS180 ,IRQ180 (32-bit free-run timer ch.4 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " IRQSIS179 ,IRQ179 (32-bit free-run timer ch.3 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " IRQSIS178 ,IRQ178 (32-bit free-run timer ch.2 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 17. -0x6C 17. -0x2C 17. " IRQSIS177 ,IRQ177 (32-bit free-run timer ch.1 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " IRQSIS176 ,IRQ176 (32-bit free-run timer ch.0 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x18 "IRQSIS6_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x18 2. -0x68 2. -0x28 2. " IRQSIS194 ,IRQ194 (32-bit input capture ch.4, ch.5 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 1. -0x68 1. -0x28 1. " IRQSIS193 ,IRQ193 (32-bit input capture ch.2, ch.3 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 0. -0x68 0. -0x28 0. " IRQSIS192 ,IRQ192 (32-bit input capture ch.0, ch.1 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
group.long 0xB60++0x1F
|
|
line.long 0x00 "IRQSIS8_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS280 ,IRQ280 (DMAC ch.7, ch.15 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS279 ,IRQ279 (DMAC ch.6, ch.14 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS278 ,IRQ278 (DMAC ch.5, ch.13 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS277 ,IRQ277 (DMAC ch.4, ch.12 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS276 ,IRQ276 (DMAC ch.3, ch.11 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS275 ,IRQ275 (DMAC ch.2, ch.10 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS274 ,IRQ274 (DMAC ch.1, ch.9 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS273 ,IRQ273 (DMAC ch.0, ch.8 transfer complete interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS272 ,IRQ272 (DMAC transfer error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQSIS9_SET/CLR,IRC IRQ Software Interrupt Set/Clear Status Register"
|
|
setclrfld.long 0x04 24. -0x7C 24. -0x3C 24. " IRQSIS312 ,IRQ312 (PMU interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 22. -0x7C 22. -0x3C 22. " IRQSIS310 ,IRQ310 (Main clock timer interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 21. -0x7C 21. -0x3C 21. " IRQSIS309 ,IRQ309 (Slow-CR clock timer interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 20. -0x7C 20. -0x3C 20. " IRQSIS308 ,IRQ308 (Fast-CR clock timer interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQSIS10_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x08 31. -0x78 31. -0x38 31. " IRQSIS351 ,IRQ351 (MVA0 failure detection error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 30. -0x78 30. -0x38 30. " IRQSIS350 ,IRQ350 (MVA0 floating-point non-normalized error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 29. -0x78 29. -0x38 29. " IRQSIS349 ,IRQ349 (MVA0 underflow interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 28. -0x78 28. -0x38 28. " IRQSIS348 ,IRQ348 (MVA0 overflow interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 27. -0x78 27. -0x38 27. " IRQSIS347 ,IRQ347 (MVA0 two-phase to three-phase AC conversion end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 26. -0x78 26. -0x38 26. " IRQSIS346 ,IRQ346 (MVA0 current to voltage conversion end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 25. -0x78 25. -0x38 25. " IRQSIS345 ,IRQ345 (MVA0 PID control end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 24. -0x78 24. -0x38 24. " IRQSIS344 ,IRQ344 (MVA0 three-phase to two-phase DC conversion end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 23. -0x78 23. -0x38 23. " IRQSIS343 ,IRQ343 (MVA0 three-phase current normalization end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 22. -0x78 22. -0x38 22. " IRQSIS342 ,IRQ342 (MVA0 angular calculation end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 21. -0x78 21. -0x38 21. " IRQSIS341 ,IRQ341 (16-bit free-run timer ch.17 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 20. -0x78 20. -0x38 20. " IRQSIS340 ,IRQ340 (16-bit free-run timer ch.16 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 19. -0x78 19. -0x38 19. " IRQSIS339 ,IRQ339 (16-bit free-run timer ch.15 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 18. -0x78 18. -0x38 18. " IRQSIS338 ,IRQ338 (16-bit free-run timer ch.14 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 17. -0x78 17. -0x38 17. " IRQSIS337 ,IRQ337 (16-bit free-run timer ch.13 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 16. -0x78 16. -0x38 16. " IRQSIS336 ,IRQ336 (16-bit free-run timer ch.12 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 15. -0x78 15. -0x38 15. " IRQSIS335 ,IRQ335 (16-bit free-run timer ch.11 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 14. -0x78 14. -0x38 14. " IRQSIS334 ,IRQ334 (16-bit free-run timer ch.10 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 13. -0x78 13. -0x38 13. " IRQSIS333 ,IRQ333 (16-bit free-run timer ch.9 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 12. -0x78 12. -0x38 12. " IRQSIS332 ,IRQ332 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 11. -0x78 11. -0x38 11. " IRQSIS331 ,IRQ331 (16-bit free-run timer ch.7 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 10. -0x78 10. -0x38 10. " IRQSIS330 ,IRQ330 (16-bit free-run timer ch.6 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 9. -0x78 9. -0x38 9. " IRQSIS329 ,IRQ329 (16-bit free-run timer ch.5 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 8. -0x78 8. -0x38 8. " IRQSIS328 ,IRQ328 (16-bit free-run timer ch.4 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x08 7. -0x78 7. -0x38 7. " IRQSIS327 ,IRQ327 (16-bit free-run timer ch.3 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 6. -0x78 6. -0x38 6. " IRQSIS326 ,IRQ326 (16-bit free-run timer ch.2 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 5. -0x78 5. -0x38 5. " IRQSIS325 ,IRQ325 (16-bit free-run timer ch.1 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 4. -0x78 4. -0x38 4. " IRQSIS324 ,IRQ324 (16-bit free-run timer ch.0 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
textline " "
|
|
setclrfld.long 0x08 3. -0x78 3. -0x38 3. " IRQSIS323 ,IRQ323 (FlexRay timer 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 2. -0x78 2. -0x38 2. " IRQSIS322 ,IRQ322 (FlexRay timer 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 1. -0x78 1. -0x38 1. " IRQSIS321 ,IRQ321 (FlexRay1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x08 0. -0x78 0. -0x38 0. " IRQSIS320 ,IRQ320 (FlexRay0) software interrupt status bits" "No interrupt,Interrupt"
|
|
endif
|
|
line.long 0x0C "IRQSIS11_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x0C 31. -0x74 31. -0x34 31. " IRQSIS383 ,IRQ383 (waveform generator dead timer underflow 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 30. -0x74 30. -0x34 30. " IRQSIS382 ,IRQ382 (waveform generator DTTI 0, 1, 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 29. -0x74 29. -0x34 29. " IRQSIS381 ,IRQ381 (waveform generator dead timer reload 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 28. -0x74 28. -0x34 28. " IRQSIS380 ,IRQ380 (waveform generator dead timer underflow 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 27. -0x74 27. -0x34 27. " IRQSIS379 ,IRQ379 (waveform generator dead timer reload 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 26. -0x74 26. -0x34 26. " IRQSIS378 ,IRQ378 (waveform generator dead timer underflow 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 25. -0x74 25. -0x34 25. " IRQSIS377 ,IRQ377 (waveform generator dead timer reload 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 24. -0x74 24. -0x34 24. " IRQSIS376 ,IRQ376 (waveform generator dead timer underflow 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 23. -0x74 23. -0x34 23. " IRQSIS375 ,IRQ375 (MVA1 free-run timer 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 22. -0x74 22. -0x34 22. " IRQSIS374 ,IRQ374 (MVA0 free-run timer 0 detection/compare clear interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 21. -0x74 21. -0x34 21. " IRQSIS373 ,IRQ373 (MVA1 calculation overtime error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 20. -0x74 20. -0x34 20. " IRQSIS372 ,IRQ372 (MVA1 three-phase to two-phase DC value abnormality detection error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 18. -0x74 18. -0x34 18. " IRQSIS370 ,IRQ370 (MVA1 cumulative three-phase current abnormality detection error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 17. -0x74 17. -0x34 17. " IRQSIS369 ,IRQ369 (MVA1 R/D converter diagnosis error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 16. -0x74 16. -0x34 16. " IRQSIS368 ,IRQ368 (MVA1 calculation data update error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 15. -0x74 15. -0x34 15. " IRQSIS367 ,IRQ367 (MVA1 failure detection error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 14. -0x74 14. -0x34 14. " IRQSIS366 ,IRQ366 (MVA1 floating-point non-normalized error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 13. -0x74 13. -0x34 13. " IRQSIS365 ,IRQ365 (MVA1 underflow interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 12. -0x74 12. -0x34 12. " IRQSIS364 ,IRQ364 (MVA1 overflow interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 11. -0x74 11. -0x34 11. " IRQSIS363 ,IRQ363 (MVA1 two-phase to three-phase AC conversion end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 10. -0x74 10. -0x34 10. " IRQSIS362 ,IRQ362 (MVA1 current to voltage conversion end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 9. -0x74 9. -0x34 9. " IRQSIS361 ,IRQ361 (MVA1 PID control end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 8. -0x74 8. -0x34 8. " IRQSIS360 ,IRQ360 (MVA1 three-phase to two-phase DC conversion end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 7. -0x74 7. -0x34 7. " IRQSIS359 ,IRQ359 (MVA1 three-phase current normalization end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 6. -0x74 6. -0x34 6. " IRQSIS358 ,IRQ358 (MVA1 angular calculation end interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 5. -0x74 5. -0x34 5. " IRQSIS357 ,IRQ357 (MVA0 calculation overtime error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 4. -0x74 4. -0x34 4. " IRQSIS356 ,IRQ356 (MVA0 three-phase to two-phase DC value abnormality detection error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 2. -0x74 2. -0x34 2. " IRQSIS354 ,IRQ354 (MVA0 cumulative three-phase current abnormality detection error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0C 1. -0x74 1. -0x34 1. " IRQSIS353 ,IRQ353 (MVA0 R/D converter diagnosis error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0C 0. -0x74 0. -0x34 0. " IRQSIS352 ,IRQ352 (MVA0 calculation data update error interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x10 "IRQSIS12_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x10 31. -0x70 31. -0x30 31. " IRQSIS415 ,IRQ415 (16-bit output compare ch.22, ch.23 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 30. -0x70 30. -0x30 30. " IRQSIS414 ,IRQ414 (16-bit output compare ch.20, ch.21 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 29. -0x70 29. -0x30 29. " IRQSIS413 ,IRQ413 (16-bit output compare ch.18, ch.19 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x10 28. -0x70 28. -0x30 28. " IRQSIS412 ,IRQ412 (16-bit output compare ch.16, ch.17 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x10 27. -0x70 27. -0x30 27. " IRQSIS411 ,IRQ411 (16-bit output compare ch.14, ch.15 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 26. -0x70 26. -0x30 26. " IRQSIS410 ,IRQ410 (16-bit output compare ch.12, ch.13 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 25. -0x70 25. -0x30 25. " IRQSIS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 24. -0x70 24. -0x30 24. " IRQSIS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x10 25. -0x70 25. -0x30 25. " IRQSIS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 24. -0x70 24. -0x30 24. " IRQSIS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x10 23. -0x70 23. -0x30 23. " IRQSIS407 ,IRQ407 (16-bit output compare ch.6, ch.7 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 22. -0x70 22. -0x30 22. " IRQSIS406 ,IRQ406 (16-bit output compare ch.4, ch.5 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 21. -0x70 21. -0x30 21. " IRQSIS405 ,IRQ405 (16-bit output compare ch.2, ch.3 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 20. -0x70 20. -0x30 20. " IRQSIS404 ,IRQ404 (16-bit output compare ch.0, ch.1 compare match) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x10 19. -0x70 19. -0x30 19. " IRQSIS403 ,IRQ403 (waveform generator DTTI 9, 10, 11) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 18. -0x70 18. -0x30 18. " IRQSIS402 ,IRQ402 (waveform generator dead timer reload 11) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 17. -0x70 17. -0x30 17. " IRQSIS401 ,IRQ401 (waveform generator dead timer underflow 11) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 16. -0x70 16. -0x30 16. " IRQSIS400 ,IRQ400 (waveform generator dead timer reload 10) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x10 15. -0x70 15. -0x30 15. " IRQSIS399 ,IRQ399 (waveform generator dead timer underflow 10) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 14. -0x70 14. -0x30 14. " IRQSIS398 ,IRQ398 (waveform generator dead timer reload 9) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 13. -0x70 13. -0x30 13. " IRQSIS397 ,IRQ397 (waveform generator dead timer underflow 9) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 12. -0x70 12. -0x30 12. " IRQSIS396 ,IRQ396 (waveform generator DTTI 6, 7, 8) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x10 11. -0x70 11. -0x30 11. " IRQSIS395 ,IRQ395 (waveform generator dead timer reload 8) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 10. -0x70 10. -0x30 10. " IRQSIS394 ,IRQ394 (waveform generator dead timer underflow 8) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 9. -0x70 9. -0x30 9. " IRQSIS393 ,IRQ393 (waveform generator dead timer reload 7) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 8. -0x70 8. -0x30 8. " IRQSIS392 ,IRQ392 (waveform generator dead timer underflow 7) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x10 7. -0x70 7. -0x30 7. " IRQSIS391 ,IRQ391 (waveform generator dead timer reload 6) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 6. -0x70 6. -0x30 6. " IRQSIS390 ,IRQ390 (waveform generator dead timer underflow 6) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 5. -0x70 5. -0x30 5. " IRQSIS389 ,IRQ389 (waveform generator DTTI 3, 4, 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 4. -0x70 4. -0x30 4. " IRQSIS388 ,IRQ388 (waveform generator dead timer reload 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x10 3. -0x70 3. -0x30 3. " IRQSIS387 ,IRQ387 (waveform generator dead timer underflow 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 2. -0x70 2. -0x30 2. " IRQSIS386 ,IRQ386 (waveform generator dead timer reload 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 1. -0x70 1. -0x30 1. " IRQSIS385 ,IRQ385 (waveform generator dead timer underflow 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 0. -0x70 0. -0x30 0. " IRQSIS384 ,IRQ384 (waveform generator dead timer reload 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x14 "IRQSIS13_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x14 31. -0x6C 31. -0x2C 31. " IRQSIS447 ,IRQ447 (4ch A/D converter unit0 conversion complete 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 30. -0x6C 30. -0x2C 30. " IRQSIS446 ,IRQ446 (4ch A/D converter unit0 conversion complete 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 29. -0x6C 29. -0x2C 29. " IRQSIS445 ,IRQ445 (4ch A/D converter unit0 conversion complete 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 28. -0x6C 28. -0x2C 28. " IRQSIS444 ,IRQ444 (4ch A/D converter unit0 conversion complete 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 27. -0x6C 27. -0x2C 27. " IRQSIS443 ,IRQ443 (up/down counter unit3 comparison result match detection 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 26. -0x6C 26. -0x2C 26. " IRQSIS442 ,IRQ442 (up/down counter unit3 comparison result match detection 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 25. -0x6C 25. -0x2C 25. " IRQSIS441 ,IRQ441 (up/down counter unit3 comparison result match detection 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 24. -0x6C 24. -0x2C 24. " IRQSIS440 ,IRQ440 (up/down counter unit3 comparison result match detection 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 23. -0x6C 23. -0x2C 23. " IRQSIS439 ,IRQ439 (up/down counter unit3 comparison result match detection 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 22. -0x6C 22. -0x2C 22. " IRQSIS438 ,IRQ438 (up/down counter unit3 comparison result match detection 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 21. -0x6C 21. -0x2C 21. " IRQSIS437 ,IRQ437 (up/down counter unit3 interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " IRQSIS436 ,IRQ436 (up/down counter unit2 comparison result match detection 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " IRQSIS435 ,IRQ435 (up/down counter unit2 comparison result match detection 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " IRQSIS434 ,IRQ434 (up/down counter unit2 comparison result match detection 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 17. -0x6C 17. -0x2C 17. " IRQSIS433 ,IRQ433 (up/down counter unit2 comparison result match detection 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " IRQSIS432 ,IRQ432 (up/down counter unit2 comparison result match detection 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 15. -0x6C 15. -0x2C 15. " IRQSIS431 ,IRQ431 (up/down counter unit2 comparison result match detection 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 14. -0x6C 14. -0x2C 14. " IRQSIS430 ,IRQ430 (up/down counter unit2 interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 13. -0x6C 13. -0x2C 13. " IRQSIS429 ,IRQ429 (up/down counter unit1 comparison result match detection 5 software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 12. -0x6C 12. -0x2C 12. " IRQSIS428 ,IRQ428 (up/down counter unit1 comparison result match detection 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 11. -0x6C 11. -0x2C 11. " IRQSIS427 ,IRQ427 (up/down counter unit1 comparison result match detection 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 10. -0x6C 10. -0x2C 10. " IRQSIS426 ,IRQ426 (up/down counter unit1 comparison result match detection 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 9. -0x6C 9. -0x2C 9. " IRQSIS425 ,IRQ425 (up/down counter unit1 comparison result match detection 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 8. -0x6C 8. -0x2C 8. " IRQSIS424 ,IRQ424 (up/down counter unit1 comparison result match detection 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 7. -0x6C 7. -0x2C 7. " IRQSIS423 ,IRQ423 (up/down counter unit1 interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 6. -0x6C 6. -0x2C 6. " IRQSIS422 ,IRQ422 (up/down counter unit0 comparison result match detection 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 5. -0x6C 5. -0x2C 5. " IRQSIS421 ,IRQ421 (up/down counter unit0 comparison result match detection 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 4. -0x6C 4. -0x2C 4. " IRQSIS420 ,IRQ420 (up/down counter unit0 comparison result match detection 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x14 3. -0x6C 3. -0x2C 3. " IRQSIS419 ,IRQ419 (up/down counter unit0 comparison result match detection 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 2. -0x6C 2. -0x2C 2. " IRQSIS418 ,IRQ418 (up/down counter unit0 comparison result match detection 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 1. -0x6C 1. -0x2C 1. " IRQSIS417 ,IRQ417 (up/down counter unit0 comparison result match detection 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 0. -0x6C 0. -0x2C 0. " IRQSIS416 ,IRQ416 (up/down counter unit0 interrupt) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x18 "IRQSIS14_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x18 31. -0x68 31. -0x28 31. " IRQSIS479 ,IRQ479 (12-bit ADC conversion complete 9) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 30. -0x68 30. -0x28 30. " IRQSIS478 ,IRQ478 (12-bit ADC conversion complete 8) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 29. -0x68 29. -0x28 29. " IRQSIS477 ,IRQ477 (12-bit ADC conversion complete 7) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 28. -0x68 28. -0x28 28. " IRQSIS476 ,IRQ476 (12-bit ADC conversion complete 6) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x18 27. -0x68 27. -0x28 27. " IRQSIS475 ,IRQ475 (12-bit ADC conversion complete 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 26. -0x68 26. -0x28 26. " IRQSIS474 ,IRQ474 (12-bit ADC conversion complete 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 25. -0x68 25. -0x28 25. " IRQSIS473 ,IRQ473 (12-bit ADC conversion complete 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 24. -0x68 24. -0x28 24. " IRQSIS472 ,IRQ472 (12-bit ADC conversion complete 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x18 23. -0x68 23. -0x28 23. " IRQSIS471 ,IRQ471 (12-bit ADC conversion complete 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 22. -0x68 22. -0x28 22. " IRQSIS470 ,IRQ470 (12-bit ADC conversion complete 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x18 21. -0x68 21. -0x28 21. " IRQSIS469 ,IRQ469 (16-bit input capture ch.14 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 20. -0x68 20. -0x28 20. " IRQSIS468 ,IRQ468 (16-bit input capture ch.12, ch.13 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
else
|
|
setclrfld.long 0x18 20. -0x68 20. -0x28 20. " IRQSIS468 ,IRQ468 (16-bit input capture ch.12 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x18 19. -0x68 19. -0x28 19. " IRQSIS467 ,IRQ467 (16-bit input capture ch.10, ch.11 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 18. -0x68 18. -0x28 18. " IRQSIS466 ,IRQ466 (16-bit input capture ch.8, ch.9 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 17. -0x68 17. -0x28 17. " IRQSIS465 ,IRQ465 (16-bit input capture ch.6, ch.7 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 16. -0x68 16. -0x28 16. " IRQSIS464 ,IRQ464 (16-bit input capture ch.4, ch.5 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x18 15. -0x68 15. -0x28 15. " IRQSIS463 ,IRQ463 (16-bit input capture ch.2, ch.3 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 14. -0x68 14. -0x28 14. " IRQSIS462 ,IRQ462 (16-bit input capture ch.0, ch.1 fetching) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 13. -0x68 13. -0x28 13. " IRQSIS461 ,IRQ461 (4ch A/D converter unit1 range comparison 0/1/2/3/4/5/6/7) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 12. -0x68 12. -0x28 12. " IRQSIS460 ,IRQ460 (4ch A/D converter unit1 conversion complete 7) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x18 11. -0x68 11. -0x28 11. " IRQSIS459 ,IRQ459 (4ch A/D converter unit1 conversion complete 6) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 10. -0x68 10. -0x28 10. " IRQSIS458 ,IRQ458 (4ch A/D converter unit1 conversion complete 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 9. -0x68 9. -0x28 9. " IRQSIS457 ,IRQ457 (4ch A/D converter unit1 conversion complete 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 8. -0x68 8. -0x28 8. " IRQSIS456 ,IRQ456 (4ch A/D converter unit1 conversion complete 3) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x18 7. -0x68 7. -0x28 7. " IRQSIS455 ,IRQ455 (4ch A/D converter unit1 conversion complete 2) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 6. -0x68 6. -0x28 6. " IRQSIS454 ,IRQ454 (4ch A/D converter unit1 conversion complete 1) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 5. -0x68 5. -0x28 5. " IRQSIS453 ,IRQ453 (4ch A/D converter unit1 conversion complete 0) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 4. -0x68 4. -0x28 4. " IRQSIS452 ,IRQ452 (4ch A/D converter unit0 range comparison 0/1/2/3/4/5/6/7) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x18 3. -0x68 3. -0x28 3. " IRQSIS451 ,IRQ451 (4ch A/D converter unit0 conversion complete 7) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 2. -0x68 2. -0x28 2. " IRQSIS450 ,IRQ450 (4ch A/D converter unit0 conversion complete 6) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 1. -0x68 1. -0x28 1. " IRQSIS449 ,IRQ449 (4ch A/D converter unit0 conversion complete 5) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x18 0. -0x68 0. -0x28 0. " IRQSIS448 ,IRQ448 (4ch A/D converter unit0 conversion complete 4) software interrupt status bits" "No interrupt,Interrupt"
|
|
line.long 0x1C "IRQSIS15_SET/CLR,IRC IRQ Software Interrupt Set/Clear Register"
|
|
setclrfld.long 0x1C 28. -0x64 28. -0x24 28. " IRQSIS508 ,IRQ508 (PLL Alarm For FlexRay) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 27. -0x64 27. -0x24 27. " IRQSIS507 ,IRQ507 (PLL Gear For FlexRay) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 26. -0x64 26. -0x24 26. " IRQSIS506 ,IRQ506 (12-bit ADC scan conversion complete) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 25. -0x64 25. -0x24 25. " IRQSIS505 ,IRQ505 (12-bit ADC range comparison 24/25/26/27/28/29/30/31) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 24. -0x64 24. -0x24 24. " IRQSIS504 ,IRQ504 (12-bit ADC range comparison 16/17/18/19/20/21/22/23) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 23. -0x64 23. -0x24 23. " IRQSIS503 ,IRQ503 (12-bit ADC range comparison 8/9/10/11/12/13/14/15) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 22. -0x64 22. -0x24 22. " IRQSIS502 ,IRQ502 (12-bit ADC range comparison 0/1/2/3/4/5/6/7) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 21. -0x64 21. -0x24 21. " IRQSIS501 ,IRQ501 (12-bit ADC conversion complete 31) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 20. -0x64 20. -0x24 20. " IRQSIS500 ,IRQ500 (12-bit ADC conversion complete 30) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 19. -0x64 19. -0x24 19. " IRQSIS499 ,IRQ499 (12-bit ADC conversion complete 29) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 18. -0x64 18. -0x24 18. " IRQSIS498 ,IRQ498 (12-bit ADC conversion complete 28) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 17. -0x64 17. -0x24 17. " IRQSIS497 ,IRQ497 (12-bit ADC conversion complete 27) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 16. -0x64 16. -0x24 16. " IRQSIS496 ,IRQ496 (12-bit ADC conversion complete 26) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 15. -0x64 15. -0x24 15. " IRQSIS495 ,IRQ495 (12-bit ADC conversion complete 25) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 14. -0x64 14. -0x24 14. " IRQSIS494 ,IRQ494 (12-bit ADC conversion complete 24) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 13. -0x64 13. -0x24 13. " IRQSIS493 ,IRQ493 (12-bit ADC conversion complete 23) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 12. -0x64 12. -0x24 12. " IRQSIS492 ,IRQ492 (12-bit ADC conversion complete 22) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 11. -0x64 11. -0x24 11. " IRQSIS491 ,IRQ491 (12-bit ADC conversion complete 21) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 10. -0x64 10. -0x24 10. " IRQSIS490 ,IRQ490 (12-bit ADC conversion complete 20) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 9. -0x64 9. -0x24 9. " IRQSIS489 ,IRQ489 (12-bit ADC conversion complete 19) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 8. -0x64 8. -0x24 8. " IRQSIS488 ,IRQ488 (12-bit ADC conversion complete 18) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 7. -0x64 7. -0x24 7. " IRQSIS487 ,IRQ487 (12-bit ADC conversion complete 17) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 6. -0x64 6. -0x24 6. " IRQSIS486 ,IRQ486 (12-bit ADC conversion complete 16) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 5. -0x64 5. -0x24 5. " IRQSIS485 ,IRQ485 (12-bit ADC conversion complete 15) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 4. -0x64 4. -0x24 4. " IRQSIS484 ,IRQ484 (12-bit ADC conversion complete 14) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 3. -0x64 3. -0x24 3. " IRQSIS483 ,IRQ483 (12-bit ADC conversion complete 13) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 2. -0x64 2. -0x24 2. " IRQSIS482 ,IRQ482 (12-bit ADC conversion complete 12) software interrupt status bits" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 1. -0x64 1. -0x24 1. " IRQSIS481 ,IRQ481 (12-bit ADC conversion complete 11) software interrupt status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x1C 0. -0x64 0. -0x24 0. " IRQSIS480 ,IRQ480 (12-bit ADC conversion complete 10) software interrupt status bits" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "IRQ Channel Enable Setting Register"
|
|
group.long 0xC00++0x1B
|
|
line.long 0x00 "IRQCE0_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE31 ,IRQ31 (external interrupt ch.7) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQCE30 ,IRQ30 (external interrupt ch.6) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQCE29 ,IRQ29 (external interrupt ch.5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQCE28 ,IRQ28 (external interrupt ch.4) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE27 ,IRQ27 (external interrupt ch.3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE26 ,IRQ26 (external interrupt ch.2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE25 ,IRQ25 (external interrupt ch.1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE24 ,IRQ24 (external interrupt ch.0) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE21 ,IRQ21 (WorkFLASH unit 1 1-bit error correction interrupt/ready interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE20 ,IRQ20 (WorkFLASH unit 0 1-bit error correction interrupt/ready interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE16 ,IRQ16 (Interrupt controller unit 0/1 ECC 1-bit error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE11 ,IRQ11 (WorkFLASH unit1 hang interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE10 ,IRQ10 (WorkFLASH unit0 hang interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x80 8. -0x40 8. " IRQCE8 ,IRQ8 (TCFLASH unit 0/1 1-bit error correction interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x80 3. -0x40 3. " IRQCE3 ,IRQ3 (SW-WDT unit 0/1 prior warning interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x80 2. -0x40 2. " IRQCE2 ,IRQ2 (HW-WDT prior warning interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x80 1. -0x40 1. " IRQCE1 ,IRQ1 (LPC RUN profile update complete) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x04 "IRQCE1_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x04 26. -0x7C 26. -0x3C 26. " IRQCE58 ,IRQ58 (CAN ch.2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x04 25. -0x7C 25. -0x3C 25. " IRQCE57 ,IRQ57 (CAN ch.1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. -0x7C 24. -0x3C 24. " IRQCE56 ,IRQ56 (CAN ch.0) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x08 "IRQCE2_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x08 9. -0x78 9. -0x38 9. " IRQCE73 ,IRQ73 (multi-function serial interface ch.4 transmission complete) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. -0x78 8. -0x38 8. " IRQCE72 ,IRQ72 (multi-function serial interface ch.4 reception complete/status) channel enable setting bits" "Disabled,Enabled"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x08 7. -0x78 7. -0x38 7. " IRQCE71 ,IRQ71 (multi-function serial interface ch.3 transmission complete) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. -0x78 6. -0x38 6. " IRQCE70 ,IRQ70 (multi-function serial interface ch.3 reception complete/status) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. -0x78 5. -0x38 5. " IRQCE69 ,IRQ69 (multi-function serial interface ch.2 transmission complete) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. -0x78 4. -0x38 4. " IRQCE68 ,IRQ68 (multi-function serial interface ch.2 reception complete/status) channel enable setting bits" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x08 3. -0x78 3. -0x38 3. " IRQCE67 ,IRQ67 (multi-function serial interface ch.1 transmission complete) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. -0x78 2. -0x38 2. " IRQCE66 ,IRQ66 (multi-function serial interface ch.1 reception complete/status) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. -0x78 1. -0x38 1. " IRQCE65 ,IRQ65 (multi-function serial interface ch.0 transmission complete) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. -0x78 0. -0x38 0. " IRQCE64 ,IRQ64 (multi-function serial interface ch.0 reception complete/status) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x0C "IRQCE3_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x0C 21. -0x74 21. -0x34 21. " IRQCE117 ,IRQ117 (CR calibration interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 14. -0x74 14. -0x34 14. " IRQCE110 ,IRQ110 (TCRAM unit 0/1 RAM diagnosis interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 0. -0x74 0. -0x34 0. " IRQCE96 ,IRQ96 (inter-processor communication (IPCU) interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x10 "IRQCE4_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x10 11. -0x70 11. -0x30 11. " IRQCE139 ,IRQ139 (base timer ch.11 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. -0x70 10. -0x30 10. " IRQCE138 ,IRQ138 (base timer ch.10 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. -0x70 9. -0x30 9. " IRQCE137 ,IRQ137 (base timer ch.9 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. -0x70 8. -0x30 8. " IRQCE136 ,IRQ136 (base timer ch.8 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x10 7. -0x70 7. -0x30 7. " IRQCE135 ,IRQ135 (base timer ch.7 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. -0x70 6. -0x30 6. " IRQCE134 ,IRQ134 (base timer ch.6 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x10 5. -0x70 5. -0x30 5. " IRQCE133 ,IRQ133 (base timer ch.5 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. -0x70 4. -0x30 4. " IRQCE132 ,IRQ132 (base timer ch.4 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x10 3. -0x70 3. -0x30 3. " IRQCE131 ,IRQ131 (base timer ch.3 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. -0x70 2. -0x30 2. " IRQCE130 ,IRQ130 (base timer ch.2 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 1. -0x70 1. -0x30 1. " IRQCE129 ,IRQ129 (base timer ch.1 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. -0x70 0. -0x30 0. " IRQCE128 ,IRQ128 (base timer ch.0 IRQ0/IRQ1) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x14 "IRQCE5_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " IRQCE180 ,IRQ180 (32-bit free-run timer ch.4 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " IRQCE179 ,IRQ179 (32-bit free-run timer ch.3 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " IRQCE178 ,IRQ178 (32-bit free-run timer ch.2 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. -0x6C 17. -0x2C 17. " IRQCE177 ,IRQ177 (32-bit free-run timer ch.1 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " IRQCE176 ,IRQ176 (32-bit free-run timer ch.0 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x18 "IRQCE6_SET/CLR,IRC IRQ Channel Enable Setting Register"
|
|
setclrfld.long 0x18 2. -0x68 2. -0x28 2. " IRQCE194 ,IRQ194 (32-bit input capture ch.4, ch.5 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 1. -0x68 1. -0x28 1. " IRQCE193 ,IRQ193 (32-bit input capture ch.2, ch.3 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. -0x68 0. -0x28 0. " IRQCE192 ,IRQ192 (32-bit input capture ch.0, ch.1 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
group.long 0xC20++0x1F
|
|
line.long 0x00 "IRQCE8_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE280 ,IRQ280 (DMAC ch.7, ch.15 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE279 ,IRQ279 (DMAC ch.6, ch.14 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE278 ,IRQ278 (DMAC ch.5, ch.13 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE277 ,IRQ277 (DMAC ch.4, ch.12 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE276 ,IRQ276 (DMAC ch.3, ch.11 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE275 ,IRQ275 (DMAC ch.2, ch.10 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE274 ,IRQ274 (DMAC ch.1, ch.9 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE273 ,IRQ273 (DMAC ch.0, ch.8 transfer complete interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE272 ,IRQ272 (DMAC transfer error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x04 "IRQCE9_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x04 24. -0x7C 24. -0x3C 24. " IRQCE312 ,IRQ312 (PMU interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. -0x7C 22. -0x3C 22. " IRQCE310 ,IRQ310 (main clock timer interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. -0x7C 21. -0x3C 21. " IRQCE309 ,IRQ309 (Slow-CR clock timer interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. -0x7C 20. -0x3C 20. " IRQCE308 ,IRQ308 (Fast-CR clock timer interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x08 "IRQCE10_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x08 31. -0x78 31. -0x38 31. " IRQCE351 ,IRQ351 (MVA0 failure detection error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. -0x78 30. -0x38 30. " IRQCE350 ,IRQ350 (MVA0 floating-point non-normalized error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. -0x78 29. -0x38 29. " IRQCE349 ,IRQ349 (MVA0 underflow interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. -0x78 28. -0x38 28. " IRQCE348 ,IRQ348 (MVA0 overflow interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. -0x78 27. -0x38 27. " IRQCE347 ,IRQ347 (MVA0 two-phase to three-phase AC conversion end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. -0x78 26. -0x38 26. " IRQCE346 ,IRQ346 (MVA0 current to voltage conversion end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 25. -0x78 25. -0x38 25. " IRQCE345 ,IRQ345 (MVA0 PID control end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. -0x78 24. -0x38 24. " IRQCE344 ,IRQ344 (MVA0 three-phase to two-phase DC conversion end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. -0x78 23. -0x38 23. " IRQCE343 ,IRQ343 (MVA0 three-phase current normalization end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. -0x78 22. -0x38 22. " IRQCE342 ,IRQ342 (MVA0 angular calculation end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. -0x78 21. -0x38 21. " IRQCE341 ,IRQ341 (16-bit free-run timer ch.17 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. -0x78 20. -0x38 20. " IRQCE340 ,IRQ340 (16-bit free-run timer ch.16 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. -0x78 19. -0x38 19. " IRQCE339 ,IRQ339 (16-bit free-run timer ch.15 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. -0x78 18. -0x38 18. " IRQCE338 ,IRQ338 (16-bit free-run timer ch.14 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. -0x78 17. -0x38 17. " IRQCE337 ,IRQ337 (16-bit free-run timer ch.13 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. -0x78 16. -0x38 16. " IRQCE336 ,IRQ336 (16-bit free-run timer ch.12 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 15. -0x78 15. -0x38 15. " IRQCE335 ,IRQ335 (16-bit free-run timer ch.11 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. -0x78 14. -0x38 14. " IRQCE334 ,IRQ334 (16-bit free-run timer ch.10 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 13. -0x78 13. -0x38 13. " IRQCE333 ,IRQ333 (16-bit free-run timer ch.9 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. -0x78 12. -0x38 12. " IRQCE332 ,IRQ332 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. -0x78 11. -0x38 11. " IRQCE331 ,IRQ331 (16-bit free-run timer ch.7 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. -0x78 10. -0x38 10. " IRQCE330 ,IRQ330 (16-bit free-run timer ch.6 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. -0x78 9. -0x38 9. " IRQCE329 ,IRQ329 (16-bit free-run timer ch.5 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. -0x78 8. -0x38 8. " IRQCE328 ,IRQ328 (16-bit free-run timer ch.4 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. -0x78 7. -0x38 7. " IRQCE327 ,IRQ327 (16-bit free-run timer ch.3 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. -0x78 6. -0x38 6. " IRQCE326 ,IRQ326 (16-bit free-run timer ch.2 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. -0x78 5. -0x38 5. " IRQCE325 ,IRQ325 (16-bit free-run timer ch.1 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. -0x78 4. -0x38 4. " IRQCE324 ,IRQ324 (16-bit free-run timer ch.0 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
textline " "
|
|
setclrfld.long 0x08 3. -0x78 3. -0x38 3. " IRQCE323 ,IRQ323 (FlexRay Timer 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. -0x78 2. -0x38 2. " IRQCE322 ,IRQ322 (FlexRay Timer 0) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 1. -0x78 1. -0x38 1. " IRQCE321 ,IRQ321 (FlexRay1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. -0x78 0. -0x38 0. " IRQCE320 ,IRQ320 (FlexRay0) channel enable setting bits" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x0C "IRQCE11_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x0C 31. -0x78 31. -0x34 31. " IRQCE383 ,IRQ383 (waveform generator dead timer underflow 3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 30. -0x78 30. -0x34 30. " IRQCE382 ,IRQ382 (waveform generator DTTI 0, 1, 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 29. -0x78 29. -0x34 29. " IRQCE381 ,IRQ381 (waveform generator dead timer reload 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 28. -0x78 28. -0x34 28. " IRQCE380 ,IRQ380 (waveform generator dead timer underflow 2) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0C 27. -0x78 27. -0x34 27. " IRQCE379 ,IRQ379 (waveform generator dead timer reload 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 26. -0x78 26. -0x34 26. " IRQCE378 ,IRQ378 (waveform generator dead timer underflow 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 25. -0x78 25. -0x34 25. " IRQCE377 ,IRQ377 (waveform generator dead timer reload 0) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 24. -0x78 24. -0x34 24. " IRQCE376 ,IRQ376 (waveform generator dead timer underflow 0) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0C 23. -0x78 23. -0x34 23. " IRQCE375 ,IRQ375 (MVA1 free-run timer 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 22. -0x78 22. -0x34 22. " IRQCE374 ,IRQ374 (MVA0 free-run timer 0 detection/compare clear interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 21. -0x78 21. -0x34 21. " IRQCE373 ,IRQ373 (MVA1 calculation overtime error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 20. -0x78 20. -0x34 20. " IRQCE372 ,IRQ372 (MVA1 three-phase to two-phase DC value abnormality detection error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0C 18. -0x78 18. -0x34 18. " IRQCE370 ,IRQ370 (MVA1 cumulative three-phase current abnormality detection error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 17. -0x78 17. -0x34 17. " IRQCE369 ,IRQ369 (MVA1 R/D converter diagnosis error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 16. -0x78 16. -0x34 16. " IRQCE368 ,IRQ368 (MVA1 calculation data update error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 15. -0x78 15. -0x34 15. " IRQCE367 ,IRQ367 (MVA1 failure detection error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0C 14. -0x78 14. -0x34 14. " IRQCE366 ,IRQ366 (MVA1 floating-point non-normalized error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 13. -0x78 13. -0x34 13. " IRQCE365 ,IRQ365 (MVA1 underflow interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 12. -0x78 12. -0x34 12. " IRQCE364 ,IRQ364 (MVA1 overflow interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 11. -0x78 11. -0x34 11. " IRQCE363 ,IRQ363 (MVA1 two-phase to three-phase AC conversion end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0C 10. -0x78 10. -0x34 10. " IRQCE362 ,IRQ362 (MVA1 current to voltage conversion end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 9. -0x78 9. -0x34 9. " IRQCE361 ,IRQ361 (MVA1 PID control end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 8. -0x78 8. -0x34 8. " IRQCE360 ,IRQ360 (MVA1 three-phase to two-phase DC conversion end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 7. -0x78 7. -0x34 7. " IRQCE359 ,IRQ359 (MVA1 three-phase current normalization end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0C 6. -0x78 6. -0x34 6. " IRQCE358 ,IRQ358 (MVA1 angular calculation end interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 5. -0x78 5. -0x34 5. " IRQCE357 ,IRQ357 (MVA0 calculation overtime error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 4. -0x78 4. -0x34 4. " IRQCE356 ,IRQ356 (MVA0 three-phase to two-phase DC value abnormality detection error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 2. -0x78 2. -0x34 2. " IRQCE354 ,IRQ354 (MVA0 cumulative three-phase current abnormality detection error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0C 1. -0x78 1. -0x34 1. " IRQCE353 ,IRQ353 (MVA0 R/D converter diagnosis error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 0. -0x78 0. -0x34 0. " IRQCE352 ,IRQ352 (MVA0 calculation data update error interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x10 "IRQCE12_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x10 31. -0x70 31. -0x30 31. " IRQCE415 ,IRQ415 (16-bit output compare ch.22, ch.23 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. -0x70 30. -0x30 30. " IRQCE414 ,IRQ414 (16-bit output compare ch.20, ch.21 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. -0x70 29. -0x30 29. " IRQCE413 ,IRQ413 (16-bit output compare ch.18, ch.19 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x10 28. -0x70 28. -0x30 28. " IRQCE412 ,IRQ412 (16-bit output compare ch.16, ch.17 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 27. -0x70 27. -0x30 27. " IRQCE411 ,IRQ411 (16-bit output compare ch.14, ch.15 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. -0x70 26. -0x30 26. " IRQCE410 ,IRQ410 (16-bit output compare ch.12, ch.13 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 25. -0x70 25. -0x30 25. " IRQCE409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. -0x70 24. -0x30 24. " IRQCE408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x10 25. -0x70 25. -0x30 25. " IRQCE409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. -0x70 24. -0x30 24. " IRQCE408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x10 23. -0x70 23. -0x30 23. " IRQCE407 ,IRQ407 (16-bit output compare ch.6, ch.7 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. -0x70 22. -0x30 22. " IRQCE406 ,IRQ406 (16-bit output compare ch.4, ch.5 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. -0x70 21. -0x30 21. " IRQCE405 ,IRQ405 (16-bit output compare ch.2, ch.3 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. -0x70 20. -0x30 20. " IRQCE404 ,IRQ404 (16-bit output compare ch.0, ch.1 compare match) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. -0x70 19. -0x30 19. " IRQCE403 ,IRQ403 (waveform generator DTTI 9, 10, 11) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. -0x70 18. -0x30 18. " IRQCE402 ,IRQ402 (waveform generator dead timer reload 11) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. -0x70 17. -0x30 17. " IRQCE401 ,IRQ401 (waveform generator dead timer underflow 11) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. -0x70 16. -0x30 16. " IRQCE400 ,IRQ400 (waveform generator dead timer reload 10) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 15. -0x70 15. -0x30 15. " IRQCE399 ,IRQ399 (waveform generator dead timer underflow 10) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. -0x70 14. -0x30 14. " IRQCE398 ,IRQ398 (waveform generator dead timer reload 9) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 13. -0x70 13. -0x30 13. " IRQCE397 ,IRQ397 (waveform generator dead timer underflow 9) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. -0x70 12. -0x30 12. " IRQCE396 ,IRQ396 (waveform generator DTTI 6, 7, 8) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 11. -0x70 11. -0x30 11. " IRQCE395 ,IRQ395 (waveform generator dead timer reload 8) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. -0x70 10. -0x30 10. " IRQCE394 ,IRQ394 (waveform generator dead timer underflow 8) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. -0x70 9. -0x30 9. " IRQCE393 ,IRQ393 (waveform generator dead timer reload 7) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. -0x70 8. -0x30 8. " IRQCE392 ,IRQ392 (waveform generator dead timer underflow 7) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. -0x70 7. -0x30 7. " IRQCE391 ,IRQ391 (waveform generator dead timer reload 6) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. -0x70 6. -0x30 6. " IRQCE390 ,IRQ390 (waveform generator dead timer underflow 6) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. -0x70 5. -0x30 5. " IRQCE389 ,IRQ389 (waveform generator DTTI 3, 4, 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. -0x70 4. -0x30 4. " IRQCE388 ,IRQ388 (waveform generator dead timer reload 5) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 3. -0x70 3. -0x30 3. " IRQCE387 ,IRQ387 (waveform generator dead timer underflow 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. -0x70 2. -0x30 2. " IRQCE386 ,IRQ386 (waveform generator dead timer reload 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 1. -0x70 1. -0x30 1. " IRQCE385 ,IRQ385 (waveform generator dead timer udnerflow 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. -0x70 0. -0x30 0. " IRQCE384 ,IRQ384 (waveform generator dead timer reload 3) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x14 "IRQCE13_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x14 31. -0x6C 31. -0x2C 31. " IRQCE447 ,IRQ447 (4ch A/D converter unit 0 conversion complete 3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. -0x6C 30. -0x2C 30. " IRQCE446 ,IRQ446 (4ch A/D converter unit 0 conversion complete 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. -0x6C 29. -0x2C 29. " IRQCE445 ,IRQ445 (4ch A/D converter unit 0 conversion complete 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. -0x6C 28. -0x2C 28. " IRQCE444 ,IRQ444 (4ch A/D converter unit 0 conversion complete 0) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 27. -0x6C 27. -0x2C 27. " IRQCE443 ,IRQ443 (up/down counter unit 3 comparison result match detection 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. -0x6C 26. -0x2C 26. " IRQCE442 ,IRQ442 (up/down counter unit 3 comparison result match detection 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 25. -0x6C 25. -0x2C 25. " IRQCE441 ,IRQ441 (up/down counter unit 3 comparison result match detection 3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. -0x6C 24. -0x2C 24. " IRQCE440 ,IRQ440 (up/down counter unit 3 comparison result match detection 2) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 23. -0x6C 23. -0x2C 23. " IRQCE439 ,IRQ439 (up/down counter unit 3 comparison result match detection 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. -0x6C 22. -0x2C 22. " IRQCE438 ,IRQ438 (up/down counter unit 3 comparison result match detection 0) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. -0x6C 21. -0x2C 21. " IRQCE437 ,IRQ437 (up/down counter unit 3 interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " IRQCE436 ,IRQ436 (up/down counter unit 2 comparison result match detection 5) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " IRQCE435 ,IRQ435 (up/down counter unit 2 comparison result match detection 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " IRQCE434 ,IRQ434 (up/down counter unit 2 comparison result match detection 3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. -0x6C 17. -0x2C 17. " IRQCE433 ,IRQ433 (up/down counter unit 2 comparison result match detection 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " IRQCE432 ,IRQ432 (up/down counter unit 2 comparison result match detection 1) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 15. -0x6C 15. -0x2C 15. " IRQCE431 ,IRQ431 (up/down counter unit 2 comparison result match detection 0) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. -0x6C 14. -0x2C 14. " IRQCE430 ,IRQ430 (up/down counter unit 2 interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 13. -0x6C 13. -0x2C 13. " IRQCE429 ,IRQ429 (up/down counter unit 1 comparison result match detection 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. -0x6C 12. -0x2C 12. " IRQCE428 ,IRQ428 (up/down counter unit 1 comparison result match detection 4) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 11. -0x6C 11. -0x2C 11. " IRQCE427 ,IRQ427 (up/down counter unit 1 comparison result match detection 3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. -0x6C 10. -0x2C 10. " IRQCE426 ,IRQ426 (up/down counter unit 1 comparison result match detection 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. -0x6C 9. -0x2C 9. " IRQCE425 ,IRQ425 (up/down counter unit 1 comparison result match detection 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. -0x6C 8. -0x2C 8. " IRQCE424 ,IRQ424 (up/down counter unit 1 comparison result match detection 0) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. -0x6C 7. -0x2C 7. " IRQCE423 ,IRQ423 (up/down counter unit 1 interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. -0x6C 6. -0x2C 6. " IRQCE422 ,IRQ422 (up/down counter unit 0 comparison result match detection 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. -0x6C 5. -0x2C 5. " IRQCE421 ,IRQ421 (up/down counter unit 0 comparison result match detection 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. -0x6C 4. -0x2C 4. " IRQCE420 ,IRQ420 (up/down counter unit 0 comparison result match detection 3) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 3. -0x6C 3. -0x2C 3. " IRQCE419 ,IRQ419 (up/down counter unit 0 comparison result match detection 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. -0x6C 2. -0x2C 2. " IRQCE418 ,IRQ418 (up/down counter unit 0 comparison result match detection 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 1. -0x6C 1. -0x2C 1. " IRQCE417 ,IRQ417 (up/down counter unit 0 comparison result match detection 0) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. -0x6C 0. -0x2C 0. " IRQCE416 ,IRQ416 (up/down counter unit 0 interrupt) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x18 "IRQCE14_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x18 31. -0x68 31. -0x28 31. " IRQCE479 ,IRQ479 (12-bit ADC conversion complete 9) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. -0x68 30. -0x28 30. " IRQCE478 ,IRQ478 (12-bit ADC conversion complete 8) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. -0x68 29. -0x28 29. " IRQCE477 ,IRQ477 (12-bit ADC conversion complete 7) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. -0x68 28. -0x28 28. " IRQCE476 ,IRQ476 (12-bit ADC conversion complete 6) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 27. -0x68 27. -0x28 27. " IRQCE475 ,IRQ475 (12-bit ADC conversion complete 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. -0x68 26. -0x28 26. " IRQCE474 ,IRQ474 (12-bit ADC conversion complete 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 25. -0x68 25. -0x28 25. " IRQCE473 ,IRQ473 (12-bit ADC conversion complete 3) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. -0x68 24. -0x28 24. " IRQCE472 ,IRQ472 (12-bit ADC conversion complete 2) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 23. -0x68 23. -0x28 23. " IRQCE471 ,IRQ471 (12-bit ADC conversion complete 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. -0x68 22. -0x28 22. " IRQCE470 ,IRQ470 (12-bit ADC conversion complete 0) channel enable setting bits" "Disabled,Enabled"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x18 21. -0x68 21. -0x28 21. " IRQCE469 ,IRQ469 (16-bit input capture ch.14 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. -0x68 20. -0x28 20. " IRQCE468 ,IRQ468 (16-bit input capture ch.12, ch.13 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x18 20. -0x68 20. -0x28 20. " IRQCE468 ,IRQ468 (16-bit input capture ch.12 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x18 19. -0x68 19. -0x28 19. " IRQCE467 ,IRQ467 (16-bit input capture ch.10, ch.11 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. -0x68 18. -0x28 18. " IRQCE466 ,IRQ466 (16-bit input capture ch.8, ch.9 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. -0x68 17. -0x28 17. " IRQCE465 ,IRQ465 (16-bit input capture ch.6, ch.7 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. -0x68 16. -0x28 16. " IRQCE464 ,IRQ464 (16-bit input capture ch.4, ch.5 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 15. -0x68 15. -0x28 15. " IRQCE463 ,IRQ463 (16-bit input capture ch.2, ch.3 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. -0x68 14. -0x28 14. " IRQCE462 ,IRQ462 (16-bit input capture ch.0, ch.1 fetching) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 13. -0x68 13. -0x28 13. " IRQCE461 ,IRQ461 (4ch A/D converter unit 1 range comparison 0/1/2/3/4/5/6/7) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. -0x68 12. -0x28 12. " IRQCE460 ,IRQ460 (4ch A/D converter unit 1 conversion complete 7) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 11. -0x68 11. -0x28 11. " IRQCE459 ,IRQ459 (4ch A/D converter unit 1 conversion complete 6) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. -0x68 10. -0x28 10. " IRQCE458 ,IRQ458 (4ch A/D converter unit 1 conversion complete 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. -0x68 9. -0x28 9. " IRQCE457 ,IRQ457 (4ch A/D converter unit 1 conversion complete 4) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. -0x68 8. -0x28 8. " IRQCE456 ,IRQ456 (4ch A/D converter unit 1 conversion complete 3) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. -0x68 7. -0x28 7. " IRQCE455 ,IRQ455 (4ch A/D converter unit 1 conversion complete 2) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. -0x68 6. -0x28 6. " IRQCE454 ,IRQ454 (4ch A/D converter unit 1 conversion complete 1) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. -0x68 5. -0x28 5. " IRQCE453 ,IRQ453 (4ch A/D converter unit 1 conversion complete 0) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. -0x68 4. -0x28 4. " IRQCE452 ,IRQ452 (4ch A/D converter unit 0 range comparison 0/1/2/3/4/5/6/7) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 3. -0x68 3. -0x28 3. " IRQCE451 ,IRQ451 (4ch A/D converter unit 0 conversion complete 7) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. -0x68 2. -0x28 2. " IRQCE450 ,IRQ450 (4ch A/D converter unit 0 conversion complete 6) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 1. -0x68 1. -0x28 1. " IRQCE449 ,IRQ449 (4ch A/D converter unit 0 conversion complete 5) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. -0x68 0. -0x28 0. " IRQCE448 ,IRQ448 (4ch A/D converter unit 0 conversion complete 4) channel enable setting bits" "Disabled,Enabled"
|
|
line.long 0x1C "IRQCE15_SET/CLR,IRC IRQ Channel Enable Setting Set/Clear Register"
|
|
setclrfld.long 0x1C 28. -0x64 28. -0x24 28. " IRQCE508 ,IRQ508 (PLL alarm for FlexRay) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 27. -0x64 27. -0x24 27. " IRQCE507 ,IRQ507 (PLL gear for FlexRay) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 26. -0x64 26. -0x24 26. " IRQCE506 ,IRQ506 (12-bit ADC scan conversion complete) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 25. -0x64 25. -0x24 25. " IRQCE505 ,IRQ505 (12-bit ADC range comparison 24/25/26/27/28/29/30/31) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 24. -0x64 24. -0x24 24. " IRQCE504 ,IRQ504 (12-bit ADC range comparison 16/17/18/19/20/21/22/23) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 23. -0x64 23. -0x24 23. " IRQCE503 ,IRQ503 (12-bit ADC range comparison 8/9/10/11/12/13/14/15) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 22. -0x64 22. -0x24 22. " IRQCE502 ,IRQ502 (12-bit ADC range comparison 0/1/2/3/4/5/6/7) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 21. -0x64 21. -0x24 21. " IRQCE501 ,IRQ501 (12-bit ADC conversion complete 31) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 20. -0x64 20. -0x24 20. " IRQCE500 ,IRQ500 (12-bit ADC conversion complete 30) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 19. -0x64 19. -0x24 19. " IRQCE499 ,IRQ499 (12-bit ADC conversion complete 29) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 18. -0x64 18. -0x24 18. " IRQCE498 ,IRQ498 (12-bit ADC conversion complete 28) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 17. -0x64 17. -0x24 17. " IRQCE497 ,IRQ497 (12-bit ADC conversion complete 27) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 16. -0x64 16. -0x24 16. " IRQCE496 ,IRQ496 (12-bit ADC conversion complete 26) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 15. -0x64 15. -0x24 15. " IRQCE495 ,IRQ495 (12-bit ADC conversion complete 25) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 14. -0x64 14. -0x24 14. " IRQCE494 ,IRQ494 (12-bit ADC conversion complete 24) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 13. -0x64 13. -0x24 13. " IRQCE493 ,IRQ493 (12-bit ADC conversion complete 23) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 12. -0x64 12. -0x24 12. " IRQCE492 ,IRQ492 (12-bit ADC conversion complete 22) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 11. -0x64 11. -0x24 11. " IRQCE491 ,IRQ491 (12-bit ADC conversion complete 21) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 10. -0x64 10. -0x24 10. " IRQCE490 ,IRQ490 (12-bit ADC conversion complete 20) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 9. -0x64 9. -0x24 9. " IRQCE489 ,IRQ489 (12-bit ADC conversion complete 19) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 8. -0x64 8. -0x24 8. " IRQCE488 ,IRQ488 (12-bit ADC conversion complete 18) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 7. -0x64 7. -0x24 7. " IRQCE487 ,IRQ487 (12-bit ADC conversion complete 17) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 6. -0x64 6. -0x24 6. " IRQCE486 ,IRQ486 (12-bit ADC conversion complete 16) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 5. -0x64 5. -0x24 5. " IRQCE485 ,IRQ485 (12-bit ADC conversion complete 15) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 4. -0x64 4. -0x24 4. " IRQCE484 ,IRQ484 (12-bit ADC conversion complete 14) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 3. -0x64 3. -0x24 3. " IRQCE483 ,IRQ483 (12-bit ADC conversion complete 13) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 2. -0x64 2. -0x24 2. " IRQCE482 ,IRQ482 (12-bit ADC conversion complete 12) channel enable setting bits" "Disabled,Enabled"
|
|
setclrfld.long 0x1C 1. -0x64 1. -0x24 1. " IRQCE481 ,IRQ481 (12-bit ADC conversion complete 11) channel enable setting bits" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1C 0. -0x64 0. -0x24 0. " IRQCE480 ,IRQ480 (12-bit ADC conversion complete 10) channel enable setting bits" "Disabled,Enabled"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0xC40++0x03
|
|
line.long 0x00 "NMIHC,IRC NMI Hold Clear Register"
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.long 0x00 0.--4. " NMIHCN ,Hold clear NMI channel number bits" "0,,,,4,5,6,7,8,9,,,,13,,,,,18,,,,,,24,25,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " NMIHCN ,Hold clear NMI channel number bits" "0,,,,4,5,6,7,8,9,,,,13,,,,,18,?..."
|
|
endif
|
|
rgroup.long 0xC44++0x03
|
|
line.long 0x00 "NMIHS,IRC NMI Hold Status Register"
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.long 0x00 25. " NMIHS25 ,NMI25 (R/D converter ch.1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " NMIHS24 ,NMI24 (R/D converter ch.0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 18. " NMIHS18 ,NMI6 (Time protection (TPU) protection violation) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 13. " NMIHS13 ,NMI5 (Memory protection (MPU) protection violation) hold status bits" "Not applied,Applied"
|
|
else
|
|
bitfld.long 0x00 18. " NMIHS18 ,NMI6 (Time protection (TPU) protection violation) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 13. " NMIHS13 ,NMI5 (Memory protection (MPU) protection violation) hold status bits" "Not applied,Applied"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " NMIHS9 ,NMI5 (CPU livelock)hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 8. " NMIHS8 ,NMI4 (IRC 2-bit ECC error detection) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 7. " NMIHS7 ,NMI7 (SW-WDT) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 6. " NMIHS6 ,NMI6 (HW-WDT) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NMIHS5 ,NMI5 (CSV/profile) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " NMIHS4 ,NMI4 (LVD) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 0. " NMIHS0 ,NMI0 (NMIX pin) hold status bits" "Not applied,Applied"
|
|
wgroup.long 0xC48++0x03
|
|
line.long 0x00 "IRQHC,IRC IRQ Hold Clear Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " IRQHCN ,Bits for IRQ channel number for which hold is to be cleared"
|
|
tree "IRQ Hold Status Register"
|
|
rgroup.long 0xC50++0x1B
|
|
line.long 0x00 "IRQHS0,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x00 31. " IRQHS31 ,IRQ31 (external interrupt ch.7) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 30. " IRQHS30 ,IRQ30 (external interrupt ch.6) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 29. " IRQHS29 ,IRQ29 (external interrupt ch.5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 28. " IRQHS28 ,IRQ28 (external interrupt ch.4) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQHS27 ,IRQ27 (external interrupt ch.3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 26. " IRQHS26 ,IRQ26 (external interrupt ch.2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 25. " IRQHS25 ,IRQ25 (external interrupt ch.1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " IRQHS24 ,IRQ24 (external interrupt ch.0) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IRQHS21 ,IRQ21 (WorkFLASH unit 1 1-bit error correction interrupt/ready interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " IRQHS20 ,IRQ20 (WorkFLASH unit 0 1-bit error correction interrupt/ready interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 16. " IRQHS16 ,IRQ16 (interrupt controller unit 0/1 ECC 1-bit error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 11. " IRQHS11 ,IRQ11 (WorkFLASH unit 1 hang interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQHS10 ,IRQ10 (WorkFLASH unit 0 hang interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 8. " IRQHS8 ,IRQ8 (TCFLASH unit 0/1 1-bit error correction interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 3. " IRQHS3 ,IRQ3 (SW-WDT unit 0/1 prior warning interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " IRQHS2 ,IRQ2 (HW-WDT prior warning interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQHS1 ,IRQ1 (LPC RUN profile update complete) hold status bits" "Not applied,Applied"
|
|
line.long 0x04 "IRQHS1,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x04 26. " IRQHS58 ,IRQ58 (CAN ch.2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x04 25. " IRQHS57 ,IRQ57 (CAN ch.1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x04 24. " IRQHS56 ,IRQ56 (CAN ch.0) hold status bits" "Not applied,Applied"
|
|
line.long 0x08 "IRQHS2,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x08 9. " IRQHS73 ,IRQ73 (multi-function serial interface ch.4 transmission complete) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 8. " IRQHS72 ,IRQ72 (multi-function serial interface ch.4 reception complete/status) hold status bits" "Not applied,Applied"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x08 7. " IRQHS71 ,IRQ71 (multi-function serial interface ch.3 transmission complete) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 6. " IRQHS70 ,IRQ70 (multi-function serial interface ch.3 reception complete/status) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IRQHS69 ,IRQ69 (multi-function serial interface ch.2 transmission complete) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 4. " IRQHS68 ,IRQ68 (multi-function serial interface ch.2 reception complete/status) hold status bits" "Not applied,Applied"
|
|
endif
|
|
bitfld.long 0x08 3. " IRQHS67 ,IRQ67 (multi-function serial interface ch.1 transmission complete) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 2. " IRQHS66 ,IRQ66 (multi-function serial interface ch.1 reception complete/status) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IRQHS65 ,IRQ65 (multi-function serial interface ch.0 transmission complete) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 0. " IRQHS64 ,IRQ64 (multi-function serial interface ch.0 reception complete/status) hold status bits" "Not applied,Applied"
|
|
line.long 0x0C "IRQHS3,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x0C 21. " IRQHS117 ,IRQ117 (CR calibration interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 14. " IRQHS110 ,IRQ110 (TCRAM unit 0/1 RAM diagnosis interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 0. " IRQHS96 ,IRQ96 (inter-processor communication (IPCU) Interrupt) hold status bits" "Not applied,Applied"
|
|
line.long 0x10 "IRQHS4,IRC IRQ Hold Status Register"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 11. " IRQHS139 ,IRQ139 (base timer ch.11 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 10. " IRQHS138 ,IRQ138 (base timer ch.10 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 9. " IRQHS137 ,IRQ137 (base timer ch.9 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 8. " IRQHS136 ,IRQ136 (base timer ch.8 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 7. " IRQHS135 ,IRQ135 (base timer ch.7 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 6. " IRQHS134 ,IRQ134 (base timer ch.6 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 5. " IRQHS133 ,IRQ133 (base timer ch.5 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 4. " IRQHS132 ,IRQ132 (base timer ch.4 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 3. " IRQHS131 ,IRQ131 (base timer ch.3 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 2. " IRQHS130 ,IRQ130 (base timer ch.2 IRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 1. " IRQHS129 ,IRQ129 (base timer ch.1 iRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 0. " IRQHS128 ,IRQ128 (base timer ch.0 iRQ0/IRQ1) hold status bits" "Not applied,Applied"
|
|
line.long 0x14 "IRQHS5,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x14 20. " IRQHS180 ,IRQ180 (32-bit free-run timer ch.4 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 19. " IRQHS179 ,IRQ179 (32-bit free-run timer ch.3 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 18. " IRQHS178 ,IRQ178 (32-bit free-run timer ch.2 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 17. " IRQHS177 ,IRQ177 (32-bit free-run timer ch.1 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 16. " IRQHS176 ,IRQ176 (32-bit free-run timer ch.0 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
line.long 0x18 "IRQHS6,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x18 2. " IRQHS194 ,IRQ194 (32-bit input capture ch.4, ch.5 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 1. " IRQHS193 ,IRQ193 (32-bit input capture ch.2, ch.3 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 0. " IRQHS192 ,IRQ192 (32-bit input capture ch.0, ch.1 fetching) hold status bits" "Not applied,Applied"
|
|
rgroup.long 0xC70++0x1F
|
|
line.long 0x00 "IRQHS8,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x00 24. " IRQHS280 ,IRQ280 (DMAC ch.7, ch.15 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 23. " IRQHS279 ,IRQ279 (DMAC ch.6, ch.14 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 22. " IRQHS278 ,IRQ278 (DMAC ch.5, ch.13 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 21. " IRQHS277 ,IRQ277 (DMAC ch.4, ch.12 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 20. " IRQHS276 ,IRQ276 (DMAC ch.3, ch.11 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 19. " IRQHS275 ,IRQ275 (DMAC ch.2, ch.10 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 18. " IRQHS274 ,IRQ274 (DMAC ch.1, ch.9 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x00 17. " IRQHS273 ,IRQ273 (DMAC ch.0, ch.8 transfer complete interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQHS272 ,IRQ272 (DMAC transfer error interrupt) hold status bits" "Not applied,Applied"
|
|
line.long 0x04 "IRQHS9,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x04 24. " IRQHS312 ,IRQ312 (PMU interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x04 22. " IRQHS310 ,IRQ310 (main clock timer interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x04 21. " IRQHS309 ,IRQ309 (Slow-CR clock timer interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x04 20. " IRQHS308 ,IRQ308 (Fast-CR clock timer interrupt) hold status bits" "Not applied,Applied"
|
|
line.long 0x08 "IRQHS10,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x08 31. " IRQHS351 ,IRQ351 (MVA0 failure detection error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 30. " IRQHS350 ,IRQ350 (MVA0 floating-point non-normalized error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 29. " IRQHS349 ,IRQ349 (MVA0 underflow interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 28. " IRQHS348 ,IRQ348 (MVA0 overflow interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 27. " IRQHS347 ,IRQ347 (MVA0 two-phase to three-phase AC conversion end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 26. " IRQHS346 ,IRQ346 (MVA0 current to voltage conversion end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 25. " IRQHS345 ,IRQ345 (MVA0 PID control end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 24. " IRQHS344 ,IRQ344 (MVA0 three-phase to two-phase DC conversion end interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 23. " IRQHS343 ,IRQ343 (MVA0 three-phase current normalization end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 22. " IRQHS342 ,IRQ342 (MVA0 angular calculation end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 21. " IRQHS341 ,IRQ341 (16-bit free-run timer ch.17 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 20. " IRQHS340 ,IRQ340 (16-bit free-run timer ch.16 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IRQHS339 ,IRQ339 (16-bit free-run timer ch.15 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 18. " IRQHS338 ,IRQ338 (16-bit free-run timer ch.14 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 17. " IRQHS337 ,IRQ337 (16-bit free-run timer ch.13 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 16. " IRQHS336 ,IRQ336 (16-bit free-run timer ch.12 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 15. " IRQHS335 ,IRQ335 (16-bit free-run timer ch.11 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 14. " IRQHS334 ,IRQ334 (16-bit free-run timer ch.10 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 13. " IRQHS333 ,IRQ333 (16-bit free-run timer ch.9 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 12. " IRQHS332 ,IRQ332 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 11. " IRQHS331 ,IRQ331 (16-bit free-run timer ch.7 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 10. " IRQHS330 ,IRQ330 (16-bit free-run timer ch.6 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 9. " IRQHS329 ,IRQ329 (16-bit free-run timer ch.5 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 8. " IRQHS328 ,IRQ328 (16-bit free-run timer ch.4 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IRQHS327 ,IRQ327 (16-bit Free-run timer ch.3 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 6. " IRQHS326 ,IRQ326 (16-bit free-run timer ch.2 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 5. " IRQHS5325 ,IRQ325 (16-bit free-run timer ch.1 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 4. " IRQHS324 ,IRQ324 (16-bit free-run timer ch.0 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
textline " "
|
|
bitfld.long 0x08 3. " IRQHS323 ,IRQ323 (FlexRay Timer 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 2. " IRQHS222 ,IRQ322 (FlexRay Timer 0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 1. " IRQHS321 ,IRQ321 (FlexRay1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x08 0. " IRQHS320 ,IRQ320 (FlexRay0) hold status bits" "Not applied,Applied"
|
|
endif
|
|
line.long 0x0C "IRQHS11,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x0C 31. " IRQHS383 ,IRQ383 (waveform generator dead timer underflow 3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 30. " IRQHS382 ,IRQ382 (waveform generator DTTI 0, 1, 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 29. " IRQHS381 ,IRQ381 (waveform generator dead timer reload 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 28. " IRQHS380 ,IRQ380 (waveform generator dead timer underflow 2) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " IRQHS379 ,IRQ379 (waveform generator dead timer reload 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 26. " IRQHS378 ,IRQ378 (waveform generator dead timer underflow 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 25. " IRQHS377 ,IRQ377 (waveform generator dead timer reload 0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 24. " IRQHS376 ,IRQ376 (waveform generator dead timer underflow 0) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " IRQHS375 ,IRQ375 (MVA1 free-run timer 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 22. " IRQHS374 ,IRQ374 (MVA0 free-run timer 0 detection/compare clear interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 21. " IRQHS373 ,IRQ373 (MVA1 calculation overtime error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 20. " IRQHS372 ,IRQ372 (MVA1 three-phase to two-phase DC value abnormality detection error interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " IRQHS370 ,IRQ370 (MVA1 cumulative three-phase current abnormality detection error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 17. " IRQHS369 ,IRQ369 (MVA1 R/D converter diagnosis error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 16. " IRQHS368 ,IRQ368 (MVA1 calculation data update error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 15. " IRQHS367 ,IRQ367 (MVA1 failure detection error interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " IRQHS366 ,IRQ366 (MVA1 floating-point non-normalized error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 13. " IRQHS365 ,IRQ365 (MVA1 underflow interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 12. " IRQHS364 ,IRQ364 (MVA1 overflow interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 11. " IRQHS363 ,IRQ363 (MVA1 two-phase to three-phase AC conversion end interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " IRQHS362 ,IRQ362 (MVA1 current to voltage conversion end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 9. " IRQHS361 ,IRQ361 (MVA1 PID control end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 8. " IRQHS360 ,IRQ360 (MVA1 three-phase to two-phase DC conversion end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 7. " IRQHS359 ,IRQ359 (MVA1 three-phase current normalization end interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " IRQHS358 ,IRQ358 (MVA1 angular calculation end interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 5. " IRQHS357 ,IRQ357 (MVA0 calculation overtime error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 4. " IRQHS356 ,IRQ356 (MVA0 three-phase to two-phase DC value abnormality detection error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 2. " IRQHS354 ,IRQ354 (MVA0 cumulative three-phase current abnormality detection error interrupt) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " IRQHS353 ,IRQ353 (MVA0 R/D converter diagnosis error interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x0C 0. " IRQHS352 ,IRQ352 (MVA0 calculation data update error interrupt) hold status bits" "Not applied,Applied"
|
|
line.long 0x10 "IRQHS12,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x10 31. " IRQHS415 ,IRQ415 (16-bit output compare ch.22, ch.23 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 30. " IRQHS414 ,IRQ414 (16-bit output compare ch.20, ch.21 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 29. " IRQHS413 ,IRQ413 (16-bit output compare ch.18, ch.19 compare match) hold status bits" "Not applied,Applied"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 28. " IRQHS412 ,IRQ412 (16-bit output compare ch.16, ch.17 compare match) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x10 27. " IRQHS411 ,IRQ411 (16-bit output compare ch.14, ch.15 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 26. " IRQHS410 ,IRQ410 (16-bit output compare ch.12, ch.13 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 25. " IRQHS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 24. " IRQHS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) hold status bits" "Not applied,Applied"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x10 25. " IRQHS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 24. " IRQHS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) hold status bits" "Not applied,Applied"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 23. " IRQHS407 ,IRQ407 (16-bit output compare ch.6, ch.7 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 22. " IRQHS406 ,IRQ406 (16-bit output compare ch.4, ch.5 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 21. " IRQHS405 ,IRQ405 (16-bit output compare ch.2, ch.3 compare match) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 20. " IRQHS404 ,IRQ404 (16-bit output compare ch.0, ch.1 compare match) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x10 19. " IRQHS403 ,IRQ403 (waveform generator DTTI 9, 10, 11) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 18. " IRQHS402 ,IRQ402 (waveform generator dead timer reload 11) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 17. " IRQHS401 ,IRQ401 (waveform generator dead timer underflow 11) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 16. " IRQHS400 ,IRQ400 (waveform generator dead timer reload 10) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x10 15. " IRQHS399 ,IRQ399 (waveform generator dead timer underflow 10) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 14. " IRQHS398 ,IRQ398 (waveform generator dead timer reload 9) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 13. " IRQHS397 ,IRQ397 (waveform generator dead timer underflow 9) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 12. " IRQHS396 ,IRQ396 (waveform generator DTTI 6, 7, 8) hold status bits" "not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x10 11. " IRQHS395 ,IRQ395 (waveform generator dead timer reload 8) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 10. " IRQHS394 ,IRQ394 (waveform generator dead timer underflow 8) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 9. " IRQHS393 ,IRQ393 (waveform generator dead timer reload 7) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 8. " IRQHS392 ,IRQ392 (waveform generator dead timer underflow 7) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x10 7. " IRQHS391 ,IRQ391 (waveform generator dead timer reload 6) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 6. " IRQHS390 ,IRQ390 (waveform generator dead timer underflow 6) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 5. " IRQHS389 ,IRQ389 (waveform generator DTTI 3, 4, 5) hold status bits" "not applied,Applied"
|
|
bitfld.long 0x10 4. " IRQHS388 ,IRQ388 (waveform generator dead timer reload 5) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x10 3. " IRQHS387 ,IRQ387 (waveform generator dead timer underflow 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 2. " IRQHS386 ,IRQ386 (waveform generator dead timer reload 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 1. " IRQHS385 ,IRQ385 (waveform generator dead timer underflow 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x10 0. " IRQHS384 ,IRQ384 (waveform generator dead timer reload 3) hold status bits" "Not applied,Applied"
|
|
line.long 0x14 "IRQHS13,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x14 31. " IRQHS447 ,IRQ447 (4ch A/D converter unit 0 conversion complete 3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 30. " IRQHS446 ,IRQ446 (4ch A/D converter unit 0 conversion complete 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 29. " IRQHS445 ,IRQ445 (4ch A/D converter unit 0 conversion complete 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 28. " IRQHS444 ,IRQ444 (4ch A/D converter unit 0 conversion complete 0) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 27. " IRQHS443 ,IRQ443 (up/down counter unit 3 comparison result match detection 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 26. " IRQHS442 ,IRQ442 (up/down counter unit 3 comparison result match detection 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 25. " IRQHS441 ,IRQ441 (up/down counter unit 3 comparison result match detection 3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 24. " IRQHS440 ,IRQ440 (up/down counter unit 3 comparison result match detection 2) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 23. " IRQHS439 ,IRQ439 (up/down counter unit 3 comparison result match detection 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 22. " IRQHS438 ,IRQ438 (up/down counter unit 3 comparison result match detection 0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 21. " IRQHS437 ,IRQ437 (up/down counter unit 3 interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 20. " IRQHS436 ,IRQ436 (up/down counter unit 2 comparison result match detection 5) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 19. " IRQHS435 ,IRQ435 (up/down counter unit 2 comparison result match detection 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 18. " IRQHS434 ,IRQ434 (up/down counter unit 2 comparison result match detection 3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 17. " IRQHS433 ,IRQ433 (up/down counter unit 2 comparison result match detection 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 16. " IRQHS432 ,IRQ432 (up/down counter unit 2 comparison result match detection 1) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 15. " IRQHS431 ,IRQ331 (up/down counter unit 2 comparison result match detection 0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 14. " IRQHS430 ,IRQ430 (up/down counter unit 2 interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 13. " IRQHS429 ,IRQ429 (up/down counter unit 1 comparison result match detection 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 12. " IRQHS428 ,IRQ428 (up/down counter unit 1 comparison result match detection 4) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 11. " IRQHS427 ,IRQ427 (up/down counter unit 1 comparison result match detection 3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 10. " IRQHS426 ,IRQ426 (up/down counter unit 1 comparison result match detection 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 9. " IRQHS425 ,IRQ425 (up/down counter unit 1 comparison result match detection 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 8. " IRQHS424 ,IRQ424 (up/down counter unit 1 comparison result match detection 0) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 7. " IRQHS423 ,IRQ423 (up/down counter unit 1 interrupt) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 6. " IRQHS422 ,IRQ422 (up/down counter unit 0 comparison result match detection 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 5. " IRQHS421 ,IRQ421 (up/down counter unit 0 comparison result match detection 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 4. " IRQHS420 ,IRQ420 (up/down counter unit 0 comparison result match detection 3) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x14 3. " IRQHS419 ,IRQ419 (up/down counter unit 0 comparison result match detection 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 2. " IRQHS418 ,IRQ418 (up/down counter unit 0 comparison result match detection 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 1. " IRQHS417 ,IRQ417 (up/down counter unit 0 comparison result match detection 0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x14 0. " IRQHS416 ,IRQ416 (up/down counter unit 0 interrupt) hold status bits" "Not applied,Applied"
|
|
line.long 0x18 "IRQHS14,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x18 31. " IRQHS479 ,IRQ479 (12-bit ADC conversion complete 9) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 30. " IRQHS478 ,IRQ478 (12-bit ADC conversion complete 8) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 29. " IRQHS477 ,IRQ477 (12-bit ADC conversion complete 7) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 28. " IRQHS476 ,IRQ476 (12-bit ADC conversion complete 6) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x18 27. " IRQHS475 ,IRQ475 (12-bit ADC conversion complete 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 26. " IRQHS474 ,IRQ474 (12-bit ADC conversion complete 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 25. " IRQHS473 ,IRQ473 (12-bit ADC conversion complete 3) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 24. " IRQHS472 ,IRQ472 (12-bit ADC conversion complete 2) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x18 23. " IRQHS471 ,IRQ471 (12-bit ADC conversion complete 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 22. " IRQHS470 ,IRQ470 (12-bit ADC conversion complete 0) hold status bits" "Not applied,Applied"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x18 21. " IRQHS469 ,IRQ469 (16-bit input capture ch.14 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 20. " IRQHS468 ,IRQ468 (16-bit input capture ch.12, ch.13 fetching) hold status bits" "Not applied,Applied"
|
|
else
|
|
bitfld.long 0x18 20. " IRQHS468 ,IRQ468 (16-bit input capture ch.12 fetching) hold status bits" "Not applied,Applied"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 19. " IRQHS467 ,IRQ467 (16-bit input capture ch.10, ch.11 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 18. " IRQHS466 ,IRQ466 (16-bit input capture ch.8, ch.9 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 17. " IRQHS465 ,IRQ465 (16-bit input capture ch.6, ch.7 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 16. " IRQHS464 ,IRQ464 (16-bit input capture ch.4, ch.5 fetching) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x18 15. " IRQHS463 ,IRQ463 (16-bit input capture ch.2, ch.3 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 14. " IRQHS462 ,IRQ462 (16-bit input capture ch.0, ch.1 fetching) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 13. " IRQHS461 ,IRQ461 (4ch A/D converter unit 1 range comparison 0/1/2/3/4/5/6/7) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 12. " IRQHS460 ,IRQ460 (4ch A/D converter unit 1 conversion complete 7) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x18 11. " IRQHS459 ,IRQ459 (4ch A/D converter unit 1 conversion complete 6) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 10. " IRQHS458 ,IRQ458 (4ch A/D converter unit 1 conversion complete 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 9. " IRQHS457 ,IRQ457 (4ch A/D converter unit 1 conversion complete 4) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 8. " IRQHS456 ,IRQ456 (4ch A/D converter unit 1 conversion complete 3) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x18 7. " IRQHS455 ,IRQ455 (4ch A/D converter unit 1 conversion complete 2) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 6. " IRQHS454 ,IRQ454 (4ch A/D converter unit 1 conversion complete 1) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 5. " IRQHS453 ,IRQ453 (4ch A/D converter unit 1 conversion complete 0) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 4. " IRQHS452 ,IRQ452 (4ch A/D converter unit 0 range comparison 0/1/2/3/4/5/6/7) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x18 3. " IRQHS451 ,IRQ451 (4ch A/D converter unit 0 conversion complete 7) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 2. " IRQHS450 ,IRQ450 (4ch A/D converter unit 0 conversion complete 6) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 1. " IRQHS449 ,IRQ449 (4ch A/D converter unit 0 conversion complete 5) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x18 0. " IRQHS448 ,IRQ448 (4ch A/D converter unit 0 conversion complete 4) hold status bits" "Not applied,Applied"
|
|
line.long 0x1C "IRQHS15,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x1C 28. " IRQHS508 ,IRQ508 (PLL alarm for FlexRay) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 27. " IRQHS507 ,IRQ507 (PLL gear for FlexRay) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 26. " IRQHS506 ,IRQ506 (12-bit ADC scan conversion complete) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 25. " IRQHS505 ,IRQ505 (12-bit ADC range comparison 24/25/26/27/28/29/30/31) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " IRQHS504 ,IRQ504 (12-bit ADC range comparison 16/17/18/19/20/21/22/23) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 23. " IRQHS503 ,IRQ503 (12-bit ADC range comparison 8/9/10/11/12/13/14/15) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 22. " IRQHS502 ,IRQ502 (12-bit ADC range comparison 0/1/2/3/4/5/6/7) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 21. " IRQHS501 ,IRQ501 (12-bit ADC conversion complete 31) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " IRQHS500 ,IRQ500 (12-bit ADC conversion complete 30) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 19. " IRQHS499 ,IRQ499 (12-bit ADC conversion complete 29) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 18. " IRQHS498 ,IRQ498 (12-bit ADC conversion complete 28) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 17. " IRQHS497 ,IRQ497 (12-bit ADC conversion complete 27) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 16. " IRQHS496 ,IRQ496 (12-bit ADC conversion complete 26) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 15. " IRQHS495 ,IRQ495 (12-bit ADC conversion complete 25) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 14. " IRQHS494 ,IRQ494 (12-bit ADC conversion complete 24) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 13. " IRQHS493 ,IRQ493 (12-bit ADC conversion complete 23) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " IRQHS492 ,IRQ492 (12-bit ADC conversion complete 22) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 11. " IRQHS491 ,IRQ491 (12-bit ADC conversion complete 21) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 10. " IRQHS490 ,IRQ490 (12-bit ADC conversion complete 20) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 9. " IRQHS489 ,IRQ489 (12-bit ADC conversion complete 19) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " IRQHS488 ,IRQ488 (12-bit ADC conversion complete 18) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 7. " IRQHS487 ,IRQ487 (12-bit ADC conversion complete 17) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 6. " IRQHS486 ,IRQ486 (12-bit ADC conversion complete 16) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 5. " IRQHS485 ,IRQ485 (12-bit ADC conversion complete 15) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " IRQHS484 ,IRQ484 (12-bit ADC conversion complete 14) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 3. " IRQHS483 ,IRQ483 (12-bit ADC conversion complete 13) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 2. " IRQHS482 ,IRQ482 (12-bit ADC conversion complete 12) hold status bits" "Not applied,Applied"
|
|
bitfld.long 0x1C 1. " IRQHS481 ,IRQ481 (12-bit ADC conversion complete 11) hold status bits" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " IRQHS480 ,IRQ480 (12-bit ADC conversion complete 10) hold status bits" "Not applied,Applied"
|
|
tree.end
|
|
textline " "
|
|
group.long 0xC90++0x03
|
|
line.long 0x00 "IRQPLM,IRC IRQ Priority Level Mask Register"
|
|
bitfld.long 0x00 0.--5. " IRQPLM ,IRQ priority level mask bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xC98++0x03
|
|
line.long 0x00 "CSR,IRC Control/Status Register"
|
|
rbitfld.long 0x00 16. " LST ,Interrupt controller lock status" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " IRQEN ,IRQ processing block enable/disable setting bit" "Disabled,Enabled"
|
|
rgroup.long 0xCA8++0x03
|
|
line.long 0x00 "NMIRS,IRC NMI RAW Status Register"
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.long 0x00 25. " NMIRS25 ,RAW status bits for NMI25 (R/D converter ch.1)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " NMIRS24 ,RAW status bits for NMI24 (R/D converter ch.0)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " NMIRS18 ,RAW status bits for NMI6 (Time protection (TPU) protection violation)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " NMIRS13 ,RAW status bits for NMI5 (Memory protection (MPU) protection violation)" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 18. " NMIRS18 ,RAW status bits for NMI6 (Time protection (TPU) protection violation)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " NMIRS13 ,RAW status bits for NMI5 (Memory protection (MPU) protection violation)" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " NMIRS9 ,RAW status bits for NMI5 (CPU livelock)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " NMIRS8 ,RAW status bits for NMI4 (IRC 2-bit ECC error detection)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " NMIRS7 ,RAW status bits for NMI7 (SW-WDT)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " NMIRS6 ,RAW status bits for NMI6 (HW-WDT)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NMIRS5 ,RAW status bits for NMI5 (CSV/profile)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " NMIRS4 ,RAW status bits for NMI4 (LVD)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " NMIRS0 ,RAW status bits for NMI0 (NMIX pin)" "No interrupt,Interrupt"
|
|
rgroup.long 0xCAC++0x03
|
|
line.long 0x00 "NMIPS,IRC NMI Preprocessed Status Register"
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.long 0x00 25. " NMIPS25 ,Preprocessed status bits for NMI25 (R/D converter ch.1)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " NMIPS24 ,Preprocessed status bits for NMI24 (R/D converter ch.0)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " NMIPS18 ,Preprocessed status bits for NMI6 (Time protection (TPU) protection violation)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " NMIPS13 ,Preprocessed status bits for NMI5 (Memory protection (MPU) protection violation)" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 18. " NMIPS18 ,Preprocessed status bits for NMI6 (Time protection (TPU) protection violation)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " NMIPS13 ,Preprocessed status bits for NMI5 (Memory protection (MPU) protection violation)" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " NMIPS9 ,Preprocessed status bits for NMI5 (CPU livelock)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " NMIPS8 ,Preprocessed status bits for NMI4 (IRC 2-bit ECC error detection)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " NMIPS7 ,Preprocessed status bits for NMI7 (SW-WDT)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " NMIPS6 ,Preprocessed status bits for NMI6 (HW-WDT)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NMIPS5 ,Preprocessed status bits for NMI5 (CSV/profile)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " NMIPS4 ,Preprocessed status bits for NMI4 (LVD)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " NMIPS0 ,Preprocessed status bits for NMI0 (NMIX pin)" "No interrupt,Interrupt"
|
|
tree "IRC IRQ RAW Status Register"
|
|
rgroup.long 0xCB0++0x1B
|
|
line.long 0x00 "IRQRS0,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x00 31. " IRQRS31 ,IRQ31 (external interrupt ch.7) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQRS30 ,IRQ30 (external interrupt ch.6) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQRS29 ,IRQ29 (external interrupt ch.5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQRS28 ,IRQ28 (external interrupt ch.4) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQRS27 ,IRQ27 (external interrupt ch.3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQRS26 ,IRQ26 (external interrupt ch.2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQRS25 ,IRQ25 (external interrupt ch.1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQRS24 ,IRQ24 (external interrupt ch.0) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IRQRS21 ,IRQ21 (WorkFLASH unit 1 1-bit error correction interrupt/ready interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQRS20 ,IRQ20 (WorkFLASH unit 0 1-bit error correction interrupt/ready interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQRS16 ,IRQ16 (interrupt controller unit 0/1 ECC 1-bit error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " IRQRS11 ,IRQ11 (WorkFLASH unit 1 hang interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQRS10 ,IRQ10 (WorkFLASH unit 0 hang interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQRS8 ,IRQ8 (TCFLASH unit 0/1 1-bit error correction interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " IRQRS3 ,IRQ3 (SW-WDT unit 0/1 prior warning interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQRS2 ,IRQ2 (HW-WDT prior warning interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQRS1 ,IRQ1 (LPC RUN profile update complete) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQRS1,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x04 26. " IRQRS58 ,IRQ58 (CAN ch.2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " IRQRS57 ,IRQ57 (CAN ch.1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " IRQRS56 ,IRQ56 (CAN ch.0) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQRS2,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x08 9. " IRQRS73 ,IRQ73 (multi-function serial interface ch.4 transmission complete) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " IRQRS72 ,IRQ72 (multi-function serial interface ch.4 reception complete/status) RAW status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x08 7. " IRQRS71 ,IRQ71 (multi-function serial interface ch.3 transmission complete) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " IRQRS70 ,IRQ70 (multi-function serial interface ch.3 reception complete/status) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IRQRS69 ,IRQ69 (multi-function serial interface ch.2 transmission complete) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " IRQRS68 ,IRQ68 (multi-function serial interface ch.2 reception complete/status) RAW status bits" "No interrupt,Interrupt"
|
|
endif
|
|
bitfld.long 0x08 3. " IRQRS67 ,IRQ67 (multi-function serial interface ch.1 transmission complete) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " IRQRS66 ,IRQ66 (multi-function serial interface ch.1 reception complete/status) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IRQRS65 ,IRQ65 (multi-function serial interface ch.0 transmission complete) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " IRQRS64 ,IRQ64 (multi-function serial interface ch.0 reception complete/status) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x0C "IRQRS3,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x0C 21. " IRQRS117 ,IRQ117 (CR calibration interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 14. " IRQRS110 ,IRQ110 (TCRAM unit 0/1 RAM diagnosis interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " IRQRS96 ,IRQ96 (inter-processor Communication (IPCU) Interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x10 "IRQRS4,IRC IRQ RAW Status Register"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 11. " IRQRS139 ,IRQ139 (base timer ch.11 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 10. " IRQRS138 ,IRQ138 (base timer ch.10 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 9. " IRQRS137 ,IRQ137 (base timer ch.9 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 8. " IRQRS136 ,IRQ136 (base timer ch.8 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 7. " IRQRS135 ,IRQ135 (base timer ch.7 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 6. " IRQRS134 ,IRQ134 (base timer ch.6 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 5. " IRQRS133 ,IRQ133 (base timer ch.5 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " IRQRS132 ,IRQ132 (base timer ch.4 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 3. " IRQRS131 ,IRQ131 (base timer ch.3 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " IRQRS130 ,IRQ130 (base timer ch.2 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 1. " IRQRS129 ,IRQ129 (base timer ch.1 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " IRQRS128 ,IRQ128 (base timer ch.0 IRQ0/IRQ1) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x14 "IRQRS5,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x14 20. " IRQRS180 ,IRQ180 (32-bit free-run timer ch.4 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 19. " IRQRS179 ,IRQ179 (32-bit free-run timer ch.3 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 18. " IRQRS178 ,IRQ178 (32-bit free-run timer ch.2 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 17. " IRQRS177 ,IRQ177 (32-bit free-run timer ch.1 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 16. " IRQRS176 ,IRQ176 (32-bit free-run timer ch.0 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x18 "IRQRS6,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x18 2. " IRQRS194 ,IRQ194 (32-bit input capture ch.4, ch.5 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 1. " IRQRS193 ,IRQ193 (32-bit input capture ch.2, ch.3 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 0. " IRQRS192 ,IRQ192 (32-bit input capture ch.0, ch.1 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
rgroup.long 0xCD0++0x1F
|
|
line.long 0x00 "IRQRS8,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x00 24. " IRQRS280 ,IRQ280 (DMAC ch.7, ch.15 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " IRQRS279 ,IRQ279 (DMAC ch.6, ch.14 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQRS278 ,IRQ278 (DMAC ch.5, ch.13 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQRS277 ,IRQ277 (DMAC ch.4, ch.12 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " IRQRS276 ,IRQ276 (DMAC ch.3, ch.11 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " IRQRS275 ,IRQ275 (DMAC ch.2, ch.10 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQRS274 ,IRQ274 (DMAC ch.1, ch.9 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQRS273 ,IRQ273 (DMAC ch.0, ch.8 transfer complete interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQRS272 ,IRQ272 (DMAC transfer error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQRS9,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x04 24. " IRQRS312 ,IRQ312 (PMU interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " IRQRS310 ,IRQ310 (main clock timer interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " IRQRS309 ,IRQ309 (Slow-CR clock timer interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " IRQRS308 ,IRQ308 (Fast-CR clock timer interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQRS10,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x08 31. " IRQRS351 ,IRQ351 (MVA0 failure detection error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 30. " IRQRS350 ,IRQ350 (MVA0 floating-point non-normalized error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 29. " IRQRS349 ,IRQ349 (MVA0 underflow interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 28. " IRQRS348 ,IRQ348 (MVA0 overflow interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 27. " IRQRS347 ,IRQ347 (MVA0 two-phase to three-phase AC conversion end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 26. " IRQRS346 ,IRQ346 (MVA0 current to voltage conversion end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 25. " IRQRS345 ,IRQ345 (MVA0 PID control end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 24. " IRQRS344 ,IRQ344 (MVA0 three-phase to two-phase DC conversion end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 23. " IRQRS343 ,IRQ343 (MVA0 three-phase current normalization end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 22. " IRQRS342 ,IRQ342 (MVA0 angular calculation end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 21. " IRQRS341 ,IRQ341 (16-bit free-run timer ch.17 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 20. " IRQRS340 ,IRQ340 (16-bit free-run timer ch.16 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IRQRS339 ,IRQ339 (16-bit free-run timer ch.15 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 18. " IRQRS338 ,IRQ338 (16-bit free-run timer ch.14 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 17. " IRQRS337 ,IRQ337 (16-bit free-run timer ch.13 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16. " IRQRS336 ,IRQ336 (16-bit free-run timer ch.12 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 15. " IRQRS335 ,IRQ335 (16-bit free-run timer ch.11 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 14. " IRQRS334 ,IRQ334 (16-bit free-run timer ch.10 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 13. " IRQRS333 ,IRQ333 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 12. " IRQRS332 ,IRQ332 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 11. " IRQRS331 ,IRQ331 (16-bit free-run timer ch.7 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 10. " IRQRS330 ,IRQ330 (16-bit free-run timer ch.6 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 9. " IRQRS329 ,IRQ329 (16-bit free-run timer ch.5 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " IRQRS328 ,IRQ328 (16-bit free-run timer ch.4 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IRQRS327 ,IRQ327 (16-bit free-run timer ch.3 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " IRQRS326 ,IRQ326 (16-bit free-run timer ch.2 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 5. " IRQRS325 ,IRQ325 (16-bit free-run timer ch.1 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " IRQRS324 ,IRQ324 (16-bit free-run timer ch.0 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
textline " "
|
|
bitfld.long 0x08 3. " IRQRS323 ,IRQ323 (FlexRay timer 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " IRQRS222 ,IRQ322 (FlexRay timer 0) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 1. " IRQRS321 ,IRQ321 (FlexRay1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " IRQRS320 ,IRQ320 (FlexRay0) RAW status bits" "No interrupt,Interrupt"
|
|
endif
|
|
line.long 0x0C "IRQRS11,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x0C 31. " IRQRS383 ,IRQ383 (waveform generator dead timer underflow 3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 30. " IRQRS382 ,IRQ382 (waveform generator DTTI 0, 1, 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 29. " IRQRS381 ,IRQ381 (waveform generator dead timer reload 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 28. " IRQRS380 ,IRQ380 (waveform generator dead timer underflow 2) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " IRQRS379 ,IRQ379 (waveform generator dead timer reload 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 26. " IRQRS378 ,IRQ378 (waveform generator dead timer underflow 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 25. " IRQRS377 ,IRQ377 (waveform generator dead timer reload 0) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 24. " IRQRS376 ,IRQ376 (waveform generator dead timer underflow 0) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " IRQRS375 ,IRQ375 (MVA1 free-run timer 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 22. " IRQRS374 ,IRQ374 (MVA0 free-run timer 0 detection/compare clear interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 21. " IRQRS373 ,IRQ373 (MVA1 calculation overtime error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 20. " IRQRS372 ,IRQ372 (MVA1 three-phase to two-phase DC value abnormality detection error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " IRQRS370 ,IRQ370 (MVA1 cumulative three-phase current abnormality detection error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 17. " IRQRS369 ,IRQ369 (MVA1 R/D converter diagnosis error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16. " IRQRS368 ,IRQ368 (MVA1 calculation data update error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 15. " IRQRS367 ,IRQ367 (MVA1 failure detection error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " IRQRS366 ,IRQ366 (MVA1 floating-point non-normalized error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 13. " IRQRS365 ,IRQ365 (MVA1 underflow interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 12. " IRQRS364 ,IRQ364 (MVA1 overflow interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 11. " IRQRS363 ,IRQ363 (MVA1 two-phase to three-phase AC conversion end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " IRQRS362 ,IRQ362 (MVA1 current to voltage conversion end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 9. " IRQRS361 ,IRQ361 (MVA1 PID control end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 8. " IRQRS360 ,IRQ360 (MVA1 three-phase to two-phase DC conversion end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 7. " IRQRS359 ,IRQ359 (MVA1 three-phase current normalization end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " IRQRS358 ,IRQ358 (MVA1 angular calculation end interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 5. " IRQRS357 ,IRQ357 (MVA0 calculation overtime error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " IRQRS356 ,IRQ356 (MVA0 three-phase to two-phase DC value abnormality detection error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " IRQRS354 ,IRQ354 (MVA0 cumulative three-phase current abnormality detection error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " IRQRS353 ,IRQ353 (MVA0 R/D converter diagnosis error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " IRQRS352 ,IRQ352 (MVA0 calculation data update error interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x10 "IRQRS12,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x10 31. " IRQRS415 ,IRQ415 (16-bit output compare ch.22, ch.23 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 30. " IRQRS414 ,IRQ414 (16-bit output compare ch.20, ch.21 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 29. " IRQRS413 ,IRQ413 (16-bit output compare ch.18, ch.19 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 28. " IRQRS412 ,IRQ412 (16-bit output compare ch.16, ch.17 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 27. " IRQRS411 ,IRQ411 (16-bit output compare ch.14, ch.15 compare Match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 26. " IRQRS410 ,IRQ410 (16-bit output compare ch.12, ch.13 compare Match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 25. " IRQRS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 24. " IRQRS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x10 25. " IRQRS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 24. " IRQRS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 23. " IRQRS407 ,IRQ407 (16-bit output compare ch.6, ch.7 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 22. " IRQRS406 ,IRQ406 (16-bit output compare ch.4, ch.5 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 21. " IRQRS405 ,IRQ405 (16-bit output compare ch.2, ch.3 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 20. " IRQRS404 ,IRQ404 (16-bit output compare ch.0, ch.1 compare match) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 19. " IRQRS403 ,IRQ403 (waveform generator DTTI 9, 10, 11) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 18. " IRQRS402 ,IRQ402 (waveform generator dead timer reload 11) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 17. " IRQRS401 ,IRQ401 (waveform generator dead timer underflow 11) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16. " IRQRS400 ,IRQ400 (waveform generator dead timer reload 10) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 15. " IRQRS399 ,IRQ399 (waveform generator dead timer underflow 10) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 14. " IRQRS398 ,IRQ398 (waveform generator dead timer reload 9) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 13. " IRQRS397 ,IRQ397 (waveform generator dead timer underflow 9) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 12. " IRQRS396 ,IRQ396 (waveform generator DTTI 6, 7, 8) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 11. " IRQRS395 ,IRQ395 (waveform generator dead timer reload 8) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 10. " IRQRS394 ,IRQ394 (waveform generator dead timer underflow 8) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 9. " IRQRS393 ,IRQ393 (waveform generator dead timer reload 7) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 8. " IRQRS392 ,IRQ392 (waveform generator dead timer underflow 7) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 7. " IRQRS391 ,IRQ391 (waveform generator dead timer reload 6) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 6. " IRQRS390 ,IRQ390 (waveform generator dead timer underflow 6) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 5. " IRQRS389 ,IRQ389 (waveform generator DTTI 3, 4, 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " IRQRS388 ,IRQ388 (waveform generator dead timer reload 5) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 3. " IRQRS387 ,IRQ387 (waveform generator dead timer underflow 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " IRQRS386 ,IRQ386 (waveform generator dead timer reload 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 1. " IRQRS385 ,IRQ385 (waveform generator dead timer underflow 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " IRQRS384 ,IRQ384 (waveform generator dead timer reload 3) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x14 "IRQRS13,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x14 31. " IRQRS447 ,IRQ447 (4ch A/D converter unit 0 conversion complete 3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 30. " IRQRS446 ,IRQ446 (4ch A/D converter unit 0 conversion complete 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 29. " IRQRS445 ,IRQ445 (4ch A/D converter unit 0 conversion complete 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 28. " IRQRS444 ,IRQ444 (4ch A/D converter unit 0 conversion complete 0) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 27. " IRQRS443 ,IRQ443 (up/down counter unit 3 comparison result match detection 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 26. " IRQRS442 ,IRQ442 (up/down counter unit 3 comparison result match detection 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 25. " IRQRS441 ,IRQ441 (up/down counter unit 3 comparison result match detection 3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 24. " IRQRS440 ,IRQ440 (up/down counter unit 3 comparison result match detection 2) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 23. " IRQRS439 ,IRQ439 (up/down counter unit 3 comparison result match detection 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 22. " IRQRS438 ,IRQ438 (up/down counter unit 3 comparison result match detection 0) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 21. " IRQRS437 ,IRQ437 (up/down counter unit 3 interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 20. " IRQRS436 ,IRQ436 (up/down counter unit 2 comparison result match detection 5) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 19. " IRQRS435 ,IRQ435 (up/down counter unit 2 comparison result match detection 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 18. " IRQRS434 ,IRQ434 (up/down counter unit 2 comparison result match detection 3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 17. " IRQRS433 ,IRQ433 (up/down counter unit 2 comparison result match detection 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16. " IRQRS432 ,IRQ432 (up/down counter unit 2 comparison result match detection 1) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 15. " IRQRS431 ,IRQ431 (up/down counter unit 2 comparison result match detection 0) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 14. " IRQRS430 ,IRQ430 (up/down counter unit 2 interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 13. " IRQRS429 ,IRQ429 (up/down counter unit 1 comparison result match detection 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 12. " IRQRS428 ,IRQ428 (up/down counter unit 1 comparison result match detection 4) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 11. " IRQRS427 ,IRQ427 (up/down counter unit 1 comparison result match detection 3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 10. " IRQRS426 ,IRQ426 (up/down counter unit 1 comparison result match detection 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 9. " IRQRS425 ,IRQ425 (up/down counter unit 1 comparison result match detection 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 8. " IRQRS424 ,IRQ424 (up/down counter unit 1 comparison result match detection 0) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 7. " IRQRS423 ,IRQ423 (up/down counter unit 1 interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 6. " IRQRS422 ,IRQ422 (up/down counter unit 0 comparison result match detection 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 5. " IRQRS421 ,IRQ421 (up/down counter unit 0 comparison result match detection 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 4. " IRQRS420 ,IRQ420 (up/down counter unit 0 comparison result match detection 3) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 3. " IRQRS419 ,IRQ419 (up/down counter unit 0 comparison result match detection 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 2. " IRQRS418 ,IRQ418 (up/down counter unit 0 comparison result match detection 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 1. " IRQRS417 ,IRQ417 (up/down counter unit 0 comparison result match detection 0) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 0. " IRQRS416 ,IRQ416 (up/down counter unit 0 interrupt) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x18 "IRQRS14,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x18 31. " IRQRS479 ,IRQ479 (12-bit ADC conversion complete 9) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 30. " IRQRS478 ,IRQ478 (12-bit ADC conversion complete 8) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 29. " IRQRS477 ,IRQ477 (12-bit ADC conversion complete 7) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 28. " IRQRS476 ,IRQ476 (12-bit ADC conversion complete 6) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 27. " IRQRS475 ,IRQ475 (12-bit ADC conversion complete 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 26. " IRQRS474 ,IRQ474 (12-bit ADC conversion complete 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 25. " IRQRS473 ,IRQ473 (12-bit ADC conversion complete 3) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 24. " IRQRS472 ,IRQ472 (12-bit ADC conversion complete 2) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 23. " IRQRS471 ,IRQ471 (12-bit ADC conversion complete 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 22. " IRQRS470 ,IRQ470 (12-bit ADC conversion complete 0) RAW status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x18 21. " IRQRS469 ,IRQ469 (16-bit input capture ch.14 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 20. " IRQRS468 ,IRQ468 (16-bit input capture ch.12, ch.13 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x18 20. " IRQRS468 ,IRQ468 (16-bit input capture ch.12 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 19. " IRQRS467 ,IRQ467 (16-bit input capture ch.10, ch.11 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 18. " IRQRS466 ,IRQ466 (16-bit input capture ch.8, ch.9 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 17. " IRQRS465 ,IRQ465 (16-bit input capture ch.6, ch.7 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16. " IRQRS464 ,IRQ464 (16-bit input capture ch.4, ch.5 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 15. " IRQRS463 ,IRQ463 (16-bit input capture ch.2, ch.3 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 14. " IRQRS462 ,IRQ462 (16-bit input capture ch.0, ch.1 fetching) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 13. " IRQRS461 ,IRQ461 (4ch A/D converter unit 1 range comparison 0/1/2/3/4/5/6/7) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 12. " IRQRS460 ,IRQ460 (4ch A/D converter unit 1 conversion complete 7) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 11. " IRQRS459 ,IRQ459 (4ch A/D converter unit 1 conversion complete 6) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 10. " IRQRS458 ,IRQ458 (4ch A/D converter unit 1 conversion complete 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 9. " IRQRS457 ,IRQ457 (4ch A/D converter unit 1 conversion complete 4) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 8. " IRQRS456 ,IRQ456 (4ch A/D converter unit 1 conversion complete 3) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 7. " IRQRS455 ,IRQ455 (4ch A/D converter unit 1 conversion complete 2) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 6. " IRQRS454 ,IRQ454 (4ch A/D converter unit 1 conversion complete 1) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 5. " IRQRS453 ,IRQ453 (4ch A/D converter unit 1 conversion complete 0) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 4. " IRQRS452 ,IRQ452 (4ch A/D converter unit 0 range comparison 0/1/2/3/4/5/6/7) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 3. " IRQRS451 ,IRQ451 (4ch A/D converter unit 0 conversion complete 7) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 2. " IRQRS450 ,IRQ450 (4ch A/D converter unit 0 conversion complete 6) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 1. " IRQRS449 ,IRQ449 (4ch A/D converter unit 0 conversion complete 5) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 0. " IRQRS448 ,IRQ448 (4ch A/D converter unit 0 conversion complete 4) RAW status bits" "No interrupt,Interrupt"
|
|
line.long 0x1C "IRQRS15,IRC IRQ RAW Status Register"
|
|
bitfld.long 0x1C 28. " IRQRS508 ,IRQ508 (PLL alarm for FlexRay) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 27. " IRQRS507 ,IRQ507 (PLL gear for FlexRay) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 26. " IRQRS506 ,IRQ506 (12-bit ADC scan conversion complete) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 25. " IRQRS505 ,IRQ505 (12-bit ADC range comparison 24/25/26/27/28/29/30/31) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " IRQRS504 ,IRQ504 (12-bit ADC range comparison 16/17/18/19/20/21/22/23) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 23. " IRQRS503 ,IRQ503 (12-bit ADC range comparison 8/9/10/11/12/13/14/15) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 22. " IRQRS502 ,IRQ502 (12-bit ADC range comparison 0/1/2/3/4/5/6/7) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 21. " IRQRS501 ,IRQ501 (12-bit ADC conversion complete 31) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " IRQRS500 ,IRQ500 (12-bit ADC conversion complete 30) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 19. " IRQRS499 ,IRQ499 (12-bit ADC conversion complete 29) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 18. " IRQRS498 ,IRQ498 (12-bit ADC conversion complete 28) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 17. " IRQRS497 ,IRQ497 (12-bit ADC conversion complete 27) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 16. " IRQRS496 ,IRQ496 (12-bit ADC conversion complete 26) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 15. " IRQRS495 ,IRQ495 (12-bit ADC conversion complete 25) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 14. " IRQRS494 ,IRQ494 (12-bit ADC conversion complete 24) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 13. " IRQRS493 ,IRQ493 (12-bit ADC conversion complete 23) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " IRQRS492 ,IRQ492 (12-bit ADC conversion complete 22) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 11. " IRQRS491 ,IRQ491 (12-bit ADC conversion complete 21) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 10. " IRQRS490 ,IRQ490 (12-bit ADC conversion complete 20) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 9. " IRQRS489 ,IRQ489 (12-bit ADC conversion complete 19) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " IRQRS488 ,IRQ488 (12-bit ADC conversion complete 18) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 7. " IRQRS487 ,IRQ487 (12-bit ADC conversion complete 17) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 6. " IRQRS486 ,IRQ486 (12-bit ADC conversion complete 16) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 5. " IRQRS485 ,IRQ485 (12-bit ADC conversion complete 15) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " IRQRS484 ,IRQ484 (12-bit ADC conversion complete 14) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 3. " IRQRS483 ,IRQ483 (12-bit ADC conversion complete 13) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 2. " IRQRS482 ,IRQ482 (12-bit ADC conversion complete 12) RAW status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 1. " IRQRS481 ,IRQ481 (12-bit ADC conversion complete 11) RAW status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " IRQRS480 ,IRQ480 (12-bit ADC conversion complete 10) RAW status bits" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "IRC IRQ Preprocessed Status Register"
|
|
rgroup.long 0xCF0++0x1B
|
|
line.long 0x00 "IRQPS0,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x00 31. " IRQPS31 ,IRQ31 (external interrupt ch.7) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQPS30 ,IRQ30 (external interrupt ch.6) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQPS29 ,IRQ29 (external interrupt ch.5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQPS28 ,IRQ28 (external interrupt ch.4) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQPS27 ,IRQ27 (external interrupt ch.3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQPS26 ,IRQ26 (external interrupt ch.2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQPS25 ,IRQ25 (external interrupt ch.1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQPS24 ,IRQ24 (external interrupt ch.0) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IRQPS21 ,IRQ21 (WorkFLASH unit 1 1-bit error correction interrupt/ready interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQPS20 ,IRQ20 (WorkFLASH unit 0 1-bit error correction interrupt/ready interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQPS16 ,IRQ16 (interrupt controller unit 0/1 ECC 1-bit error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " IRQPS11 ,IRQ11 (WorkFLASH unit 1 hang interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQPS10 ,IRQ10 (WorkFLASH unit 0 hang interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQPS8 ,IRQ8 (TCFLASH uniy 0/1 1-bit error correction interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " IRQPS3 ,IRQ3 (SW-WDT unit 0/1 prior warning interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQPS2 ,IRQ2 (HW-WDT prior warning interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQPS1 ,IRQ1 (LPC RUN profile update complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQPS1,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x04 26. " IRQPS58 ,IRQ58 (CAN ch.2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " IRQPS57 ,IRQ57 (CAN ch.1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " IRQPS56 ,IRQ56 (CAN ch.0) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQPS2,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x08 9. " IRQPS73 ,IRQ73 (multi-function serial interface ch.4 transmission complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " IRQPS72 ,IRQ72 (multi-function serial interface ch.4 reception complete/status) preprocessed status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x08 7. " IRQPS71 ,IRQ71 (multi-function serial interface ch.3 transmission complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " IRQPS70 ,IRQ70 (multi-function serial interface ch.3 reception complete/status) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IRQPS69 ,IRQ69 (multi-function serial interface ch.2 transmission complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " IRQPS68 ,IRQ68 (multi-function serial interface ch.2 reception complete/status) preprocessed status bits" "No interrupt,Interrupt"
|
|
endif
|
|
bitfld.long 0x08 3. " IRQPS67 ,IRQ67 (multi-function serial interface ch.1 transmission complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " IRQPS66 ,IRQ66 (multi-function serial interface ch.1 reception complete/status) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IRQPS65 ,IRQ65 (multi-function serial interface ch.0 transmission complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " IRQPS64 ,IRQ64 (multi-function serial interface ch.0 reception complete/status) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x0C "IRQPS3,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x0C 21. " IRQPS117 ,IRQ117 (CR calibration interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 14. " IRQPS110 ,IRQ110 (TCRAM unit 0/1 RAM diagnosis interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " IRQPS96 ,IRQ96 (inter-processor communication (IPCU) interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x10 "IRQPS4,IRC IRQ Preprocessed Status Register"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 11. " IRQPS139 ,IRQ139 (base timer ch.11 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 10. " IRQPS138 ,IRQ138 (base timer ch.10 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 9. " IRQPS137 ,IRQ137 (base timer ch.9 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 8. " IRQPS136 ,IRQ136 (base timer ch.8 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 7. " IRQPS135 ,IRQ135 (base timer ch.7 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 6. " IRQPS134 ,IRQ134 (base timer ch.6 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 5. " IRQPS133 ,IRQ133 (base timer ch.5 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " IRQPS132 ,IRQ132 (base timer ch.4 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 3. " IRQPS131 ,IRQ131 (base timer ch.3 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " IRQPS130 ,IRQ130 (base timer ch.2 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 1. " IRQPS129 ,IRQ129 (base timer ch.1 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " IRQPS128 ,IRQ128 (base timer ch.0 IRQ0/IRQ1) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x14 "IRQPS5,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x14 20. " IRQPS2180 ,IRQ180 (32-bit free-run timer ch.4 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 19. " IRQPS179 ,IRQ179 (32-bit free-run timer ch.3 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 18. " IRQPS178 ,IRQ178 (32-bit free-run timer ch.2 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 17. " IRQPS117 ,IRQ177 (32-bit free-run timer ch.1 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 16. " IRQPS176 ,IRQ176 (32-bit free-run timer ch.0 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x18 "IRQPS6,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x18 2. " IRQPS194 ,IRQ194 (32-bit input capture ch.4, ch.5 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 1. " IRQPS193 ,IRQ193 (32-bit input capture ch.2, ch.3 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 0. " IRQPS192 ,IRQ192 (32-bit input capture ch.0, ch.1 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
rgroup.long 0xD10++0x1F
|
|
line.long 0x00 "IRQPS8,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x00 24. " IRQPS280 ,IRQ280 (DMAC ch.7, ch.15 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " IRQPS279 ,IRQ279 (DMAC ch.6, ch.14 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQPS278 ,IRQ278 (DMAC ch.5, ch.13 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQPS277 ,IRQ277 (DMAC ch.4, ch.12 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " IRQPS276 ,IRQ276 (DMAC ch.3, ch.11 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " IRQPS275 ,IRQ275 (DMAC ch.2, ch.10 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQPS274 ,IRQ274 (DMAC ch.1, ch.9 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQPS273 ,IRQ273 (DMAC ch.0, ch.8 transfer complete interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQPS272 ,IRQ272 (DMAC transfer error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQPS9,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x04 24. " IRQPS312 ,IRQ312 (PMU interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " IRQPS310 ,IRQ310 (main clock timer interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " IRQPS309 ,IRQ309 (Slow-CR clock timer interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " IRQPS308 ,IRQ308 (Fast-CR clock timer interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQPS10,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x08 31. " IRQPS351 ,IRQ351 (MVA0 failure detection error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 30. " IRQPS350 ,IRQ350 (MVA0 floating-point non-normalized error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 29. " IRQPS349 ,IRQ349 (MVA0 underflow interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 28. " IRQPS348 ,IRQ348 (MVA0 overflow interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 27. " IRQPS347 ,IRQ347 (MVA0 two-phase to three-phase AC conversion end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 26. " IRQPS346 ,IRQ346 (MVA0 current to voltage conversion end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 25. " IRQPS345 ,IRQ345 (MVA0 PID control end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 24. " IRQPS344 ,IRQ344 (MVA0 three-phase to two-phase DC conversion end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 23. " IRQPS343 ,IRQ343 (MVA0 three-phase current normalization end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 22. " IRQPS342 ,IRQ342 (MVA0 angular calculation end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 21. " IRQPS341 ,IRQ341 (16-bit free-run timer ch.17 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 20. " IRQPS340 ,IRQ340 (16-bit free-run timer ch.16 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IRQPS339 ,IRQ339 (16-bit free-run timer ch.15 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 18. " IRQPS338 ,IRQ338 (16-bit free-run timer ch.14 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 17. " IRQPS337 ,IRQ337 (16-bit free-run timer ch.13 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16. " IRQPS336 ,IRQ336 (16-bit free-run timer ch.12 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 15. " IRQPS335 ,IRQ335 (16-bit free-run timer ch.11 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 14. " IRQPS334 ,IRQ334 (16-bit free-run timer ch.10 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 13. " IRQPS333 ,IRQ333 (16-bit free-run timer ch.9 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 12. " IRQPS332 ,IRQ332 (16-bit free-run timer ch.8 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 11. " IRQPS331 ,IRQ331 (16-bit free-run timer ch.7 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 10. " IRQPS330 ,IRQ330 (16-bit free-run timer ch.6 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 9. " IRQPS329 ,IRQ329 (16-bit free-run timer ch.5 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " IRQPS328 ,IRQ328 (16-bit free-run timer ch.4 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IRQPS327 ,IRQ327 (16-bit free-run timer ch.3 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " IRQPS326 ,IRQ326 (16-bit free-run timer ch.2 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 5. " IRQPS325 ,IRQ325 (16-bit free-run timer ch.1 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " IRQPS324 ,IRQ324 (16-bit free-run timer ch.0 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
textline " "
|
|
bitfld.long 0x08 3. " IRQPS323 ,IRQ323 (FlexRay Timer 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " IRQPS322 ,IRQ322 (FlexRay Timer 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 1. " IRQPS321 ,IRQ321 (FlexRay1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " IRQPS320 ,IRQ320 (FlexRay0) preprocessed status bits" "No interrupt,Interrupt"
|
|
endif
|
|
line.long 0x0C "IRQPS11,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x0C 31. " IRQPS383 ,IRQ383 (waveform generator dead timer underflow 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 30. " IRQPS382 ,IRQ382 (waveform generator DTTI 0, 1, 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 29. " IRQPS381 ,IRQ381 (waveform generator dead timer reload 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 28. " IRQPS380 ,IRQ380 (waveform generator dead timer underflow 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " IRQPS379 ,IRQ379 (waveform generator dead timer reload 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 26. " IRQPS378 ,IRQ378 (waveform generator dead timer underflow 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 25. " IRQPS377 ,IRQ377 (waveform generator dead timer reload 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 24. " IRQPS376 ,IRQ376 (waveform generator dead timer underflow 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " IRQPS375 ,IRQ375 (MVA1 free-run timer 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 22. " IRQPS374 ,IRQ374 (MVA0 free-run timer 0 detection/compare clear interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 21. " IRQPS373 ,IRQ373 (MVA1 calculation overtime error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 20. " IRQPS372 ,IRQ372 (MVA1 three-phase to two-phase DC value abnormality detection error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " IRQPS370 ,IRQ370 (MVA1 cumulative three-phase current abnormality detection error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 17. " IRQPS369 ,IRQ369 (MVA1 R/D converter diagnosis error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16. " IRQPS368 ,IRQ368 (MVA1 calculation data update error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 15. " IRQPS367 ,IRQ367 (MVA1 failure detection error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " IRQPS366 ,IRQ366 (MVA1 floating-point non-normalized error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 13. " IRQPS365 ,IRQ365 (MVA1 underflow interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 12. " IRQPS364 ,IRQ364 (MVA1 overflow interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " IRQPS363 ,IRQ363 (MVA1 two-phase to three-phase AC conversion end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 10. " IRQPS362 ,IRQ362 (MVA1 current to voltage conversion end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 9. " IRQPS361 ,IRQ361 (MVA1 PID control end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 8. " IRQPS360 ,IRQ360 (MVA1 three-phase to two-phase DC conversion end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " IRQPS359 ,IRQ359 (MVA1 three-phase current normalization end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 6. " IRQPS358 ,IRQ358 (MVA1 angular calculation end interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 5. " IRQPS357 ,IRQ357 (MVA0 calculation overtime error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " IRQPS356 ,IRQ356 (MVA0 three-phase to two-phase DC value abnormality detection error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " IRQPS354 ,IRQ354 (MVA0 cumulative three-phase current abnormality detection error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 1. " IRQPS353 ,IRQ353 (MVA0 R/D converter diagnosis error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " IRQPS352 ,IRQ352 (MVA0 calculation data update error interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x10 "IRQPS12,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x10 31. " IRQPS415 ,IRQ415 (16-bit output compare ch.22, ch.23 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 30. " IRQPS414 ,IRQ414 (16-bit output compare ch.20, ch.21 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 29. " IRQPS413 ,IRQ413 (16-bit output compare ch.18, ch.19 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 28. " IRQPS412 ,IRQ412 (16-bit output compare ch.16, ch.17 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 27. " IRQPS411 ,IRQ411 (16-bit output compare ch.14, ch.15 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 26. " IRQPS410 ,IRQ410 (16-bit output compare ch.12, ch.13 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 25. " IRQPS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 24. " IRQPS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x10 25. " IRQPS409 ,IRQ409 (16-bit output compare ch.10, ch.11 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 24. " IRQPS408 ,IRQ408 (16-bit output compare ch.8, ch.9 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 23. " IRQPS407 ,IRQ407 (16-bit output compare ch.6, ch.7 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 22. " IRQPS406 ,IRQ406 (16-bit output compare ch.4, ch.5 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 21. " IRQPS405 ,IRQ405 (16-bit output compare ch.2, ch.3 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 20. " IRQPS404 ,IRQ404 (16-bit output compare ch.0, ch.1 compare match) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 19. " IRQPS403 ,IRQ403 (waveform generator DTTI 9, 10, 11) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 18. " IRQPS402 ,IRQ402 (waveform generator dead timer reload 11) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 17. " IRQPS401 ,IRQ401 (waveform generator dead timer underflow 11) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16. " IRQPS400 ,IRQ400 (waveform generator dead timer reload 10) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 15. " IRQPS399 ,IRQ399 (waveform generator dead timer underflow 10) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 14. " IRQPS398 ,IRQ398 (waveform generator dead timer reload 9) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 13. " IRQPS397 ,IRQ397 (waveform generator dead timer underflow 9) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 12. " IRQPS396 ,IRQ396 (waveform generator DTTI 6, 7, 8) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 11. " IRQPS395 ,IRQ395 (waveform generator dead timer reload 8) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 10. " IRQPS394 ,IRQ394 (waveform generator dead timer underflow 8) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 9. " IRQPS393 ,IRQ393 (waveform generator dead timer reload 7) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 8. " IRQPS392 ,IRQ392 (waveform generator dead timer underflow 7) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 7. " IRQPS391 ,IRQ391 (waveform generator dead timer reload 6) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 6. " IRQPS390 ,IRQ390 (waveform generator dead timer underflow 6) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 5. " IRQPS389 ,IRQ389 (waveform generator DTTI 3, 4, 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " IRQPS388 ,IRQ388 (waveform generator dead timer reload 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 3. " IRQPS387 ,IRQ387 (waveform generator dead timer underflow 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " IRQPS386 ,IRQ386 (waveform generator dead timer reload 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 1. " IRQPS385 ,IRQ385 (waveform generator dead timer underflow 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " IRQPS384 ,IRQ384 (waveform generator dead timer reload 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x14 "IRQPS13,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x14 31. " IRQPS447 ,IRQ447 (4ch A/D converter unit 0 conversion complete 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 30. " IRQPS446 ,IRQ446 (4ch A/D converter unit 0 conversion complete 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 29. " IRQPS445 ,IRQ445 (4ch A/D converter unit 0 conversion complete 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 28. " IRQPS444 ,IRQ444 (4ch A/D converter unit 0 conversion complete 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 27. " IRQPS443 ,IRQ443 (up/down counter unit 3 comparison result match detection 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 26. " IRQPS442 ,IRQ442 (up/down counter unit 3 comparison result match detection 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 25. " IRQPS441 ,IRQ441 (up/down counter unit 3 comparison result match detection 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 24. " IRQPS440 ,IRQ440 (up/down counter unit 3 comparison result match detection 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 23. " IRQPS439 ,IRQ439 (up/down counter unit 3 comparison result match detection 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 22. " IRQPS438 ,IRQ438 (up/down counter unit 3 comparison result match detection 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 21. " IRQPS437 ,IRQ437 (up/down counter unit 3 interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 20. " IRQPS436 ,IRQ436 (up/down counter unit 2 comparison result match detection 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 19. " IRQPS435 ,IRQ435 (up/down counter unit 2 comparison result match detection 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 18. " IRQPS434 ,IRQ434 (up/down counter unit 2 comparison result match detection 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 17. " IRQPS433 ,IRQ433 (up/down counter unit 2 comparison result match detection 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16. " IRQPS432 ,IRQ432 (up/down counter unit 2 comparison result match detection 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 15. " IRQPS431 ,IRQ431 (up/down counter unit 2 comparison result match detection 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 14. " IRQPS430 ,IRQ430 (up/down counter unit 2 interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 13. " IRQPS429 ,IRQ429 (up/down counter unit 1 comparison result match detection 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 12. " IRQPS428 ,IRQ428 (up/down counter unit 1 comparison result match detection 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 11. " IRQPS427 ,IRQ427 (up/down counter unit 1 comparison result match detection 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 10. " IRQPS426 ,IRQ426 (up/down counter unit 1 comparison result match detection 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 9. " IRQPS425 ,IRQ425 (up/down counter unit 1 comparison result match detection 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 8. " IRQPS424 ,IRQ424 (up/down counter unit 1 comparison result match detection 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 7. " IRQPS423 ,IRQ423 (up/down counter unit 1 interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 6. " IRQPS422 ,IRQ422 (up/down counter unit 0 comparison result match detection 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 5. " IRQPS421 ,IRQ421 (up/down counter unit 0 comparison result match detection 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 4. " IRQPS420 ,IRQ420 (up/down counter unit 0 comparison result match detection 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 3. " IRQPS419 ,IRQ419 (up/down counter unit 0 comparison result match detection 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 2. " IRQPS418 ,IRQ418 (up/down counter unit 0 comparison result match detection 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 1. " IRQPS417 ,IRQ417 (up/down counter unit 0 comparison result match detection 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 0. " IRQPS416 ,IRQ416 (up/down counter unit 0 interrupt) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x18 "IRQPS14,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x18 31. " IRQPS479 ,IRQ479 (12-bit ADC conversion complete 9) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 30. " IRQPS478 ,IRQ478 (12-bit ADC conversion complete 8) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 29. " IRQPS477 ,IRQ477 (12-bit ADC conversion complete 7) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 28. " IRQPS476 ,IRQ476 (12-bit ADC conversion complete 6) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 27. " IRQPS475 ,IRQ475 (12-bit ADC conversion complete 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 26. " IRQPS474 ,IRQ474 (12-bit ADC conversion complete 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 25. " IRQPS473 ,IRQ473 (12-bit ADC conversion complete 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 24. " IRQPS472 ,IRQ472 (12-bit ADC conversion complete 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 23. " IRQPS471 ,IRQ471 (12-bit ADC conversion complete 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 22. " IRQPS470 ,IRQ470 (12-bit ADC conversion complete 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x18 21. " IRQPS469 ,IRQ469 (16-bit input capture ch.14 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 20. " IRQPS468 ,IRQ468 (16-bit input capture ch.12, ch.13 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x18 20. " IRQPS468 ,IRQ468 (16-bit input capture ch.12 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 19. " IRQPS467 ,IRQ467 (16-bit input capture ch.10, ch.11 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 18. " IRQPS466 ,IRQ466 (16-bit input capture ch.8, ch.9 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 17. " IRQPS465 ,IRQ465 (16-bit input capture ch.6, ch.7 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16. " IRQPS464 ,IRQ464 (16-bit input capture ch.4, ch.5 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 15. " IRQPS463 ,IRQ463 (16-bit input capture ch.2, ch.3 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 14. " IRQPS462 ,IRQ462 (16-bit input capture ch.0, ch.1 fetching) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 13. " IRQPS461 ,IRQ461 (4ch A/D converter unit 1 range comparison 0/1/2/3/4/5/6/7) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 12. " IRQPS460 ,IRQ460 (4ch A/D converter unit 1 conversion complete 7) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 11. " IRQPS459 ,IRQ459 (4ch A/D converter unit 1 conversion complete 6) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 10. " IRQPS458 ,IRQ458 (4ch A/D converter unit 1 conversion complete 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 9. " IRQPS457 ,IRQ457 (4ch A/D converter unit 1 conversion complete 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 8. " IRQPS456 ,IRQ456 (4ch A/D converter unit 1 conversion complete 3) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 7. " IRQPS455 ,IRQ455 (4ch A/D converter unit 1 conversion complete 2) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 6. " IRQPS454 ,IRQ454 (4ch A/D converter unit 1 conversion complete 1) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 5. " IRQPS453 ,IRQ453 (4ch A/D converter unit 1 conversion complete 0) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 4. " IRQPS452 ,IRQ452 (4ch A/D converter unit 0 range comparison 0/1/2/3/4/5/6/7) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 3. " IRQPS451 ,IRQ451 (4ch A/D converter unit 0 conversion complete 7) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 2. " IRQPS450 ,IRQ450 (4ch A/D converter unit 0 conversion complete 6) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 1. " IRQPS449 ,IRQ449 (4ch A/D converter unit 0 conversion complete 5) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 0. " IRQPS448 ,IRQ448 (4ch A/D converter unit 0 conversion complete 4) preprocessed status bits" "No interrupt,Interrupt"
|
|
line.long 0x1C "IRQPS15,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x1C 28. " IRQPS508 ,IRQ508 (PLL alarm for FlexRay) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 27. " IRQPS507 ,IRQ507 (PLL gear for FlexRay) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 26. " IRQPS506 ,IRQ506 (12-bit ADC scan conversion complete) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 25. " IRQPS505 ,IRQ505 (12-bit ADC range comparison 24/25/26/27/28/29/30/31) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " IRQPS504 ,IRQ504 (12-bit ADC range comparison 16/17/18/19/20/21/22/23) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 23. " IRQPS503 ,IRQ503 (12-bit ADC range comparison 8/9/10/11/12/13/14/15) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 22. " IRQPS502 ,IRQ502 (12-bit ADC range comparison 0/1/2/3/4/5/6/7) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 21. " IRQPS501 ,IRQ501 (12-bit ADC conversion complete 31) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " IRQPS500 ,IRQ500 (12-bit ADC conversion complete 30) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 19. " IRQPS499 ,IRQ499 (12-bit ADC conversion complete 29) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 18. " IRQPS498 ,IRQ498 (12-bit ADC conversion complete 28) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 17. " IRQPS497 ,IRQ497 (12-bit ADC conversion complete 27) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 16. " IRQPS496 ,IRQ496 (12-bit ADC conversion complete 26) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 15. " IRQPS495 ,IRQ495 (12-bit ADC conversion complete 25) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 14. " IRQPS494 ,IRQ494 (12-bit ADC conversion complete 24) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 13. " IRQPS493 ,IRQ493 (12-bit ADC conversion complete 23) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " IRQPS492 ,IRQ492 (12-bit ADC conversion complete 22) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 11. " IRQPS491 ,IRQ491 (12-bit ADC conversion complete 21) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 10. " IRQPS490 ,IRQ490 (12-bit ADC conversion complete 20) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 9. " IRQPS489 ,IRQ489 (12-bit ADC conversion complete 19) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " IRQPS488 ,IRQ488 (12-bit ADC conversion complete 18) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 7. " IRQPS487 ,IRQ487 (12-bit ADC conversion complete 17) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 6. " IRQPS486 ,IRQ486 (12-bit ADC conversion complete 16) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 5. " IRQPS485 ,IRQ485 (12-bit ADC conversion complete 15) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " IRQPS484 ,IRQ484 (12-bit ADC conversion complete 14) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 3. " IRQPS483 ,IRQ483 (12-bit ADC conversion complete 13) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 2. " IRQPS482 ,IRQ482 (12-bit ADC conversion complete 12) preprocessed status bits" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 1. " IRQPS481 ,IRQ481 (12-bit ADC conversion complete 11) preprocessed status bits" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " IRQPS480 ,IRQ480 (12-bit ADC conversion complete 10) preprocessed status bits" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0xD30++0x03
|
|
line.long 0x00 "UNLOCK,IRC Unlock Register"
|
|
group.long 0xD40++0x03
|
|
line.long 0x00 "EEI,IRC ECC Error Interrupt Register"
|
|
rbitfld.long 0x00 24. " EEIS ,ECC error IRQ status bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " EEIC ,ECC error IRQ clear bit" "No effect,Clear"
|
|
rbitfld.long 0x00 8. " EENS ,ECC error NMI status bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " EENC ,ECC error NMI clear bit" "No effect,Clear"
|
|
rgroup.long 0xD44++0x3
|
|
line.long 0x00 "EAN,IRC ECC Address Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " EAN ,ECC error occurrence address bits"
|
|
group.long 0xD48++0x0F
|
|
line.long 0x00 "ET,IRC ECC Test Register"
|
|
bitfld.long 0x00 0. " ET ,ECC test enable/disable setting bit" "Disabled,Enabled"
|
|
line.long 0x04 "EEB0,IRC ECC Error Bit Register"
|
|
hexmask.long 0x04 2.--31. 1. " EEB ,ECC error occurrence bits"
|
|
line.long 0x08 "EEB1,IRC ECC Error Bit Register"
|
|
hexmask.long 0x08 2.--31. 1. " EEB ,ECC error occurrence bits"
|
|
line.long 0x0C "EEB2,IRC ECC Error Bit Register"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " EEBO ,ECC error occurrence bits"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " EEBE ,ECC error occurrence bits"
|
|
group.long 0xD3C++0x3
|
|
line.long 0x00 "IRQEEVA,IRC ECC Error Vector Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " IRQVA[31:2] ,IRQ vector address bits"
|
|
width 0x0B
|
|
tree "Error Config Area"
|
|
base ad:0xFFFEE400
|
|
width 10.
|
|
hgroup.long 0x3FC++0x03
|
|
hide.long 0x00 "NMIVASBR,IRC NMI Vector Address Status Register"
|
|
in
|
|
tree.end
|
|
tree.end
|
|
tree "Mirror Error Config Area"
|
|
base ad:0xFFFEF800
|
|
width 10.
|
|
hgroup.long 0x3FC++0x03
|
|
hide.long 0x00 "NMIVASBR,IRC NMI Vector Address Status Register"
|
|
in
|
|
tree.end
|
|
tree.end
|
|
tree "BRIF (BootROM Hardware Interface)"
|
|
base ad:0xFFFEFC00
|
|
width 13.
|
|
wgroup.long 0x358++0x03
|
|
line.long 0x00 "UNLOCK,EXCFG Lock Release Register"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "CNFG,EXCFG Setting Register"
|
|
bitfld.long 0x00 8. " SWAP ,Exception vector register swap" "No effect,Swap"
|
|
rbitfld.long 0x00 0. " LST ,BootROM hardware interface lock status" "Unlocked,Locked"
|
|
group.long 0x384++0x0F
|
|
line.long 0x00 "UNDEFINACT,EXCFG Inactive Set - Undefined Instruction Vector Register"
|
|
line.long 0x04 "SVCINACT,EXCFG Inactive Set - Supervisor Call Vector Register"
|
|
line.long 0x08 "PABORTINACT,EXCFG Inactive Set - Prefetch Abort Vector Register"
|
|
line.long 0x0C "DABORTINACT,EXCFG Inactive Set - Data Abort Vector Register"
|
|
rgroup.long 0x3C4++0x0F
|
|
line.long 0x00 "UNDEFACT,EXCFG Active Set - Undefined Instruction Vector Register"
|
|
line.long 0x04 "SVCACT,EXCFG Active Set - Supervisor Call Vector Register"
|
|
line.long 0x08 "PABORTACT,EXCFG Active Set - Prefetch Abort Vector Register"
|
|
line.long 0x0C "DABORTACT,EXCFG Active Set - Data Abort Vector Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NMID (NMI Distribution)"
|
|
base ad:0xB0407000
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "UNLOCK,NMID Lock Release Register"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "LST,NMID Lock Status Register"
|
|
bitfld.long 0x00 0. " LST ,Lock status of the NMI distribution unit" "Not locked,Locked"
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "DIST0,NMID NMI0 Distribution Enable Register"
|
|
bitfld.byte 0x00 1. " EN1 ,NMI0 distribution enable for CPU1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EN0 ,NMI0 distribution enable for CPU0" "Disabled,Enabled"
|
|
group.byte 0x14++0x03
|
|
line.byte 0x00 "DIST4,NMID NMI4 Distribution Enable Register"
|
|
bitfld.byte 0x00 1. " EN1 ,NMI4 distribution enable for CPU1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EN0 ,NMI4 distribution enable for CPU0" "Disabled,Enabled"
|
|
group.byte 0x15++0x03
|
|
line.byte 0x00 "DIST5,NMID NMI5 Distribution Enable Register"
|
|
bitfld.byte 0x00 1. " EN1 ,NMI5 distribution enable for CPU1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EN0 ,NMI5 distribution enable for CPU0" "Disabled,Enabled"
|
|
group.byte 0x16++0x03
|
|
line.byte 0x00 "DIST6,NMID NMI6 Distribution Enable Register"
|
|
bitfld.byte 0x00 1. " EN1 ,NMI6 distribution enable for CPU1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EN0 ,NMI6 distribution enable for CPU0" "Disabled,Enabled"
|
|
group.byte 0x17++0x03
|
|
line.byte 0x00 "DIST7,NMID NMI7 Distribution Enable Register"
|
|
bitfld.byte 0x00 1. " EN1 ,NMI7 distribution enable for CPU1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EN0 ,NMI7 distribution enable for CPU0" "Disabled,Enabled"
|
|
group.byte 0x18++0x03
|
|
line.byte 0x00 "DIST8,NMID NMI8 Distribution Enable Register"
|
|
bitfld.byte 0x00 1. " EN1 ,NMI8 distribution enable for CPU1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EN0 ,NMI8 distribution enable for CPU0" "Disabled,Enabled"
|
|
group.byte 0x19++0x03
|
|
line.byte 0x00 "DIST9,NMID NMI9 Distribution Enable Register"
|
|
bitfld.byte 0x00 1. " EN1 ,NMI9 distribution enable for CPU1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EN0 ,NMI9 distribution enable for CPU0" "Disabled,Enabled"
|
|
group.byte 0x1D++0x03
|
|
line.byte 0x00 "DIST13,NMID NMI13 Distribution Enable Register"
|
|
bitfld.byte 0x00 1. " EN1 ,NMI13 distribution enable for CPU1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EN0 ,NMI13 distribution enable for CPU0" "Disabled,Enabled"
|
|
group.byte 0x22++0x03
|
|
line.byte 0x00 "DIST18,NMID NMI18 Distribution Enable Register"
|
|
bitfld.byte 0x00 1. " EN1 ,NMI18 distribution enable for CPU1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EN0 ,NMI18 distribution enable for CPU0" "Disabled,Enabled"
|
|
group.byte 0x28++0x03
|
|
line.byte 0x00 "DIST24,NMID NMI24 Distribution Enable Register"
|
|
bitfld.byte 0x00 1. " EN1 ,NMI24 distribution enable for CPU1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EN0 ,NMI24 distribution enable for CPU0" "Disabled,Enabled"
|
|
group.byte 0x29++0x03
|
|
line.byte 0x00 "DIST25,NMID NMI25 Distribution Enable Register"
|
|
bitfld.byte 0x00 1. " EN1 ,NMI25 distribution enable for CPU1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EN0 ,NMI25 distribution enable for CPU0" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EIC (External Interrupt)"
|
|
base ad:0xB0620000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ENIR_SET/CLR,External Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " EN7 ,External interrupt 7 enable" "Disabled,Enabled"
|
|
sif cpuis("MB9DF564MAE")||cpuis("MB9DF564MGE")||cpuis("MB9DF564MLE")||cpuis("MB9DF564MQE")||cpuis("MB9DF565MAE")||cpuis("MB9DF565MGE")||cpuis("MB9DF565MLE")||cpuis("MB9DF565MQE")||cpuis("MB9DF566MAE")||cpuis("MB9DF566MGE")||cpuis("MB9DF566MLE")||cpuis("MB9DF566MQE")
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " EN6 ,External interrupt 6 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " EN5 ,External interrupt 5 enable" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " EN4 ,External interrupt 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " EN3 ,External interrupt 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " EN2 ,External interrupt 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " EN1 ,External interrupt 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " EN0 ,External interrupt 0 enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "EIRR,External Interrupt Factor Register"
|
|
bitfld.long 0x00 7. " ER7 ,External interrupt factor 7 detection bits" "Not detected,Detected"
|
|
sif cpuis("MB9DF564MAE")||cpuis("MB9DF564MGE")||cpuis("MB9DF564MLE")||cpuis("MB9DF564MQE")||cpuis("MB9DF565MAE")||cpuis("MB9DF565MGE")||cpuis("MB9DF565MLE")||cpuis("MB9DF565MQE")||cpuis("MB9DF566MAE")||cpuis("MB9DF566MGE")||cpuis("MB9DF566MLE")||cpuis("MB9DF566MQE")
|
|
bitfld.long 0x00 6. " ER6 ,External interrupt factor 6 detection" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " ER5 ,External interrupt factor 5 detection" "Not detected,Detected"
|
|
endif
|
|
bitfld.long 0x00 4. " ER4 ,External interrupt factor 4 detection" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ER3 ,External interrupt factor 3 detection" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " ER2 ,External interrupt factor 2 detection" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " ER1 ,External interrupt factor 1 detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " ER0 ,External interrupt factor 0 detection" "Not detected,Detected"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "EIRCR,External Interrupt Factor Clear Register"
|
|
bitfld.long 0x00 7. " ERC7 ,External interrupt factor 7 clear" ",Clear"
|
|
sif cpuis("MB9DF564MAE")||cpuis("MB9DF564MGE")||cpuis("MB9DF564MLE")||cpuis("MB9DF564MQE")||cpuis("MB9DF565MAE")||cpuis("MB9DF565MGE")||cpuis("MB9DF565MLE")||cpuis("MB9DF565MQE")||cpuis("MB9DF566MAE")||cpuis("MB9DF566MGE")||cpuis("MB9DF566MLE")||cpuis("MB9DF566MQE")
|
|
bitfld.long 0x00 6. " ERC6 ,External interrupt factor 6 clear" ",Clear"
|
|
bitfld.long 0x00 5. " ERC5 ,External interrupt factor 5 clear" ",Clear"
|
|
endif
|
|
bitfld.long 0x00 4. " ERC4 ,External interrupt factor 4 clear" ",Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERC3 ,External interrupt factor 3 clear" ",Clear"
|
|
bitfld.long 0x00 2. " ERC2 ,External interrupt 2 factor clear" ",Clear"
|
|
bitfld.long 0x00 1. " ERC1 ,External interrupt 1 factor clear" ",Clear"
|
|
bitfld.long 0x00 0. " ERC0 ,External interrupt 0 factor clear" ",Clear"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "NFER_SET/CLR,Noise Filter Enable Set/Clear Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " NFE7 ,Noise filter 7 enable" "Disabled,Enabled"
|
|
sif cpuis("MB9DF564MAE")||cpuis("MB9DF564MGE")||cpuis("MB9DF564MLE")||cpuis("MB9DF564MQE")||cpuis("MB9DF565MAE")||cpuis("MB9DF565MGE")||cpuis("MB9DF565MLE")||cpuis("MB9DF565MQE")||cpuis("MB9DF566MAE")||cpuis("MB9DF566MGE")||cpuis("MB9DF566MLE")||cpuis("MB9DF566MQE")
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " NFE6 ,Noise filter 6 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " NFE5 ,Noise filter 5 enable" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " NFE4 ,Noise filter 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " NFE3 ,Noise filter 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " NFE2 ,Noise filter 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " NFE1 ,Noise filter 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " NFE0 ,Noise filter 0 enable" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ELVR0,External Interrupt Level Registers"
|
|
bitfld.long 0x00 28.--30. " LC/LB/LA7 ,INT7 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
sif cpuis("MB9DF564MAE")||cpuis("MB9DF564MGE")||cpuis("MB9DF564MLE")||cpuis("MB9DF564MQE")||cpuis("MB9DF565MAE")||cpuis("MB9DF565MGE")||cpuis("MB9DF565MLE")||cpuis("MB9DF565MQE")||cpuis("MB9DF566MAE")||cpuis("MB9DF566MGE")||cpuis("MB9DF566MLE")||cpuis("MB9DF566MQE")
|
|
bitfld.long 0x00 24.--26. " LC/LB/LA6 ,INT6 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 20.--22. " LC/LB/LA5 ,INT5 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
endif
|
|
bitfld.long 0x00 16.--18. " LC/LB/LA4 ,INT4 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " LC/LB/LA3 ,INT3 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 8.--10. " LC/LB/LA2 ,INT2 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 4.--6. " LC/LB/LA1 ,INT1 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 0.--2. " LC/LB/LA0 ,INT0 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "NMIR,Non-maskable Interrupt Register"
|
|
bitfld.long 0x00 8. " NMICLR ,Non-maskable interrupt clear" ",Clear"
|
|
rbitfld.long 0x00 0. " NMIINT ,Non-maskable interrupt request detection" "Not detected,Detected"
|
|
line.long 0x04 "DRER_SET/CLR,DMA Request Enable Set/Clear Register"
|
|
setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " DRE7 ,DMA request 7 enable" "Disabled,Enabled"
|
|
sif cpuis("MB9DF564MAE")||cpuis("MB9DF564MGE")||cpuis("MB9DF564MLE")||cpuis("MB9DF564MQE")||cpuis("MB9DF565MAE")||cpuis("MB9DF565MGE")||cpuis("MB9DF565MLE")||cpuis("MB9DF565MQE")||cpuis("MB9DF566MAE")||cpuis("MB9DF566MGE")||cpuis("MB9DF566MLE")||cpuis("MB9DF566MQE")
|
|
setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " DRE6 ,DMA request 6 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " DRE5 ,DMA request 5 enable" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " DRE4 ,DMA request 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " DRE3 ,DMA request 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " DRE2 ,DMA request 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " DRE1 ,DMA request 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " DRE0 ,DMA request 0 enable" "Disabled,Enabled"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "DRFR,DMA Request Flag Register"
|
|
bitfld.long 0x00 7. " DRF7 ,DMA request 7 detection" "Not detected,Detected"
|
|
sif cpuis("MB9DF564MAE")||cpuis("MB9DF564MGE")||cpuis("MB9DF564MLE")||cpuis("MB9DF564MQE")||cpuis("MB9DF565MAE")||cpuis("MB9DF565MGE")||cpuis("MB9DF565MLE")||cpuis("MB9DF565MQE")||cpuis("MB9DF566MAE")||cpuis("MB9DF566MGE")||cpuis("MB9DF566MLE")||cpuis("MB9DF566MQE")
|
|
bitfld.long 0x00 6. " DRF6 ,DMA request 6 detection" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " DRF5 ,DMA request 5 detection" "Not detected,Detected"
|
|
endif
|
|
bitfld.long 0x00 4. " DRF4 ,DMA request 4 detection" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRF3 ,DMA request 3 detection" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " DRF2 ,DMA request 2 detection" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " DRF1 ,DMA request 1 detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DRF0 ,DMA request 0 detection" "Not detected,Detected"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "TCFLASH"
|
|
tree "Unit 0"
|
|
base ad:0xB0411000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCPROTKEY,TCFLASH Configuration Protection Key Register"
|
|
if (((per.l(ad:0xB0411000))&0xFFFFFFFF)==0xFFFFFFFF)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FCFGR,TCFLASH Configuration Register"
|
|
bitfld.long 0x00 6. " SWFRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " TCMPR ,TCM priority enable" "AXI and TCM,TCM"
|
|
bitfld.long 0x00 4. " WE ,Program enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " FAWC ,Flash wait control" "No wait,1 cycle,2 cycles,3 cycles"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FECCCTRL,TCFLASH ECC Control Register"
|
|
bitfld.long 0x00 0. " ECCOFF ,Disable operation of ECC logic for AXI accessess" "No,Yes"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "FDATEIR,TCFLASH Data Bit Error Injection Register"
|
|
line.long 0x04 "FECCEIR,TCFLASH ECC Bit Error Injection Register"
|
|
bitfld.long 0x04 25. " LMASK1 ,Error injection lane 1 mask" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " LMASK0 ,Error injection lane 0 mask" "Not masked,Masked"
|
|
hexmask.long.byte 0x04 0.--6. 1. " FECCEIR ,ECC bit error injection point"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "FCFGR,TCFLASH Configuration Register"
|
|
bitfld.long 0x00 6. " SWFRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " TCMPR ,TCM priority enable" "AXI and TCM,TCM"
|
|
bitfld.long 0x00 4. " WE ,Program enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " FAWC ,Flash wait control" "No wait,1 cycle,2 cycles,3 cycles"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FECCCTRL,TCFLASH ECC Control Register"
|
|
bitfld.long 0x00 0. " ECCOFF ,Disable operation of ECC logic for AXI accessess" "No,Yes"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "FDATEIR,TCFLASH Data Bit Error Injection Register"
|
|
line.long 0x04 "FECCEIR,TCFLASH ECC Bit Error Injection Register"
|
|
bitfld.long 0x04 25. " LMASK1 ,Error injection lane 1 mask" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " LMASK0 ,Error injection lane 0 mask" "Not masked,Masked"
|
|
hexmask.long.byte 0x04 0.--6. 1. " FECCEIR ,ECC bit error injection point"
|
|
endif
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "FICTRL0,TCFLASH Interrupt Control Register 0"
|
|
bitfld.long 0x00 10. " WR32FC ,32-bit programming flag clear" ",Clear"
|
|
bitfld.long 0x00 9. " HANGIC ,Hang interrupt clear" ",Clear"
|
|
bitfld.long 0x00 8. " RDYIC ,Ready interrupt clear" ",Clear"
|
|
bitfld.long 0x00 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDYIE ,Programming/erasing ready interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "FICTRL1,TCFLASH Interrupt Control Register 1"
|
|
bitfld.long 0x04 10. " WR32FC ,32-bit programming flag clear" ",Clear"
|
|
bitfld.long 0x04 9. " HANGIC ,Hang interrupt clear" ",Clear"
|
|
bitfld.long 0x04 8. " RDYIC ,Ready interrupt clear" ",Clear"
|
|
bitfld.long 0x04 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " RDYIE ,Programming/erasing ready interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x38++0x07
|
|
line.long 0x00 "FSTAT0,TCFLASH Status Register 0"
|
|
bitfld.long 0x00 9. " HANGINT ,Hang-up interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RDYINT ,Programming/erasing ready interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " WR32F ,32-bit programming control flag" "Lower,Upper"
|
|
bitfld.long 0x00 1. " HANG ,Hang-up" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDY ,Programming/erasing ready" "Not ready,Ready"
|
|
line.long 0x04 "FSTAT1,TCFLASH Status Register 1"
|
|
bitfld.long 0x04 9. " HANGINT ,Hang-up interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RDYINT ,Programming/erasing ready interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " WR32F ,32-bit programming control flag" "Lower,Upper"
|
|
bitfld.long 0x04 1. " HANG ,Hang-up" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " RDY ,Programming/erasing ready" "Not ready,Ready"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FSECIR,TCFLASH SEC Interrupt Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " SYN ,Syndrome"
|
|
rbitfld.long 0x00 16. " SECINT ,1-bit error correction interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SECIC ,1-bit error correction interrupt clear" ",Clear"
|
|
bitfld.long 0x00 0. " SECIE ,1-bit error correction interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x54++0x07
|
|
line.long 0x00 "FECCEAR,TCFLASH ECC Error Address Register"
|
|
line.long 0x04 "FMIDR,TCFLASH Module Identification Register"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FUCEDIR,TCFLASH Uncorrectable Error Detection Interrupt Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " SYN ,Syndrome"
|
|
rbitfld.long 0x00 16. " UCEDINT ,Uncorrectable error detection interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " UCEDIC ,Uncorrectable error detection interrupt clear" ",Clear"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "FUCEAR,TCFLASH Uncorrectable Error Address Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 1"
|
|
base ad:0xB0411400
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCPROTKEY,TCFLASH Configuration Protection Key Register"
|
|
if (((per.l(ad:0xB0411400))&0xFFFFFFFF)==0xFFFFFFFF)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FCFGR,TCFLASH Configuration Register"
|
|
bitfld.long 0x00 6. " SWFRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " TCMPR ,TCM priority enable" "AXI and TCM,TCM"
|
|
bitfld.long 0x00 4. " WE ,Program enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " FAWC ,Flash wait control" "No wait,1 cycle,2 cycles,3 cycles"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FECCCTRL,TCFLASH ECC Control Register"
|
|
bitfld.long 0x00 0. " ECCOFF ,Disable operation of ECC logic for AXI accessess" "No,Yes"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "FDATEIR,TCFLASH Data Bit Error Injection Register"
|
|
line.long 0x04 "FECCEIR,TCFLASH ECC Bit Error Injection Register"
|
|
bitfld.long 0x04 25. " LMASK1 ,Error injection lane 1 mask" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " LMASK0 ,Error injection lane 0 mask" "Not masked,Masked"
|
|
hexmask.long.byte 0x04 0.--6. 1. " FECCEIR ,ECC bit error injection point"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "FCFGR,TCFLASH Configuration Register"
|
|
bitfld.long 0x00 6. " SWFRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " TCMPR ,TCM priority enable" "AXI and TCM,TCM"
|
|
bitfld.long 0x00 4. " WE ,Program enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " FAWC ,Flash wait control" "No wait,1 cycle,2 cycles,3 cycles"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FECCCTRL,TCFLASH ECC Control Register"
|
|
bitfld.long 0x00 0. " ECCOFF ,Disable operation of ECC logic for AXI accessess" "No,Yes"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "FDATEIR,TCFLASH Data Bit Error Injection Register"
|
|
line.long 0x04 "FECCEIR,TCFLASH ECC Bit Error Injection Register"
|
|
bitfld.long 0x04 25. " LMASK1 ,Error injection lane 1 mask" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " LMASK0 ,Error injection lane 0 mask" "Not masked,Masked"
|
|
hexmask.long.byte 0x04 0.--6. 1. " FECCEIR ,ECC bit error injection point"
|
|
endif
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "FICTRL0,TCFLASH Interrupt Control Register 0"
|
|
bitfld.long 0x00 10. " WR32FC ,32-bit programming flag clear" ",Clear"
|
|
bitfld.long 0x00 9. " HANGIC ,Hang interrupt clear" ",Clear"
|
|
bitfld.long 0x00 8. " RDYIC ,Ready interrupt clear" ",Clear"
|
|
bitfld.long 0x00 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDYIE ,Programming/erasing ready interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "FICTRL1,TCFLASH Interrupt Control Register 1"
|
|
bitfld.long 0x04 10. " WR32FC ,32-bit programming flag clear" ",Clear"
|
|
bitfld.long 0x04 9. " HANGIC ,Hang interrupt clear" ",Clear"
|
|
bitfld.long 0x04 8. " RDYIC ,Ready interrupt clear" ",Clear"
|
|
bitfld.long 0x04 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " RDYIE ,Programming/erasing ready interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x38++0x07
|
|
line.long 0x00 "FSTAT0,TCFLASH Status Register 0"
|
|
bitfld.long 0x00 9. " HANGINT ,Hang-up interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RDYINT ,Programming/erasing ready interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " WR32F ,32-bit programming control flag" "Lower,Upper"
|
|
bitfld.long 0x00 1. " HANG ,Hang-up" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDY ,Programming/erasing ready" "Not ready,Ready"
|
|
line.long 0x04 "FSTAT1,TCFLASH Status Register 1"
|
|
bitfld.long 0x04 9. " HANGINT ,Hang-up interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RDYINT ,Programming/erasing ready interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " WR32F ,32-bit programming control flag" "Lower,Upper"
|
|
bitfld.long 0x04 1. " HANG ,Hang-up" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " RDY ,Programming/erasing ready" "Not ready,Ready"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FSECIR,TCFLASH SEC Interrupt Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " SYN ,Syndrome"
|
|
rbitfld.long 0x00 16. " SECINT ,1-bit error correction interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SECIC ,1-bit error correction interrupt clear" ",Clear"
|
|
bitfld.long 0x00 0. " SECIE ,1-bit error correction interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x54++0x07
|
|
line.long 0x00 "FECCEAR,TCFLASH ECC Error Address Register"
|
|
line.long 0x04 "FMIDR,TCFLASH Module Identification Register"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FUCEDIR,TCFLASH Uncorrectable Error Detection Interrupt Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " SYN ,Syndrome"
|
|
rbitfld.long 0x00 16. " UCEDINT ,Uncorrectable error detection interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " UCEDIC ,Uncorrectable error detection interrupt clear" ",Clear"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "FUCEAR,TCFLASH Uncorrectable Error Address Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "TCRAM Interface"
|
|
tree "Unit 0"
|
|
base ad:0xB0410000
|
|
width 11.
|
|
if (((per.l(ad:0xB0410000))&0x100)==0x00)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TCMCFG0,TCRAM IF Configuration Register 0"
|
|
bitfld.long 0x00 24.--25. " DWAIT ,Number of data wait bits" "0,1,2,3"
|
|
rbitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERRECC ,ECC data error insertion bits"
|
|
line.long 0x04 "TCMCFG1,TCRAM IF Configuration Register 1"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "TCMCFG0,TCRAM IF Configuration Register 0"
|
|
bitfld.long 0x00 24.--25. " DWAIT ,Number of data wait bits" "0,1,2,3"
|
|
bitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERRECC ,ECC data error insertion bits"
|
|
line.long 0x04 "TCMCFG1,TCRAM IF Configuration Register 1"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "TCMUNLOCK,TCRAM IF Unlock Register"
|
|
if ((per.l(ad:0xB0410000+0x30)&0xE0000000)!=0x00)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TEAR0,TCRAM IF Test Error Address Register 0"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error source identification" "No error,March,Checker,,Unique,?..."
|
|
hexmask.long.word 0x00 0.--14. 0x01 " ERR_ADDR ,Error occurrence address"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TEAR0,TCRAM IF Test Error Address Register 0"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error source identification" "No error,March,Checker,,Unique,?..."
|
|
endif
|
|
if ((per.l(ad:0xB0410000+0x34)&0xE0000000)!=0x00)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TEAR1,TCRAM IF Test Error Address Register 1"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error source identification" "No error,March,Checker,,Unique,?..."
|
|
hexmask.long.word 0x00 0.--14. 0x01 " ERR_ADDR ,Error occurrence address"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TEAR1,TCRAM IF Test Error Address Register 1"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error source identification" "No error,March,Checker,,Unique,?..."
|
|
endif
|
|
if ((per.l(ad:0xB0410000+0x38)&0xE0000000)!=0x00)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TEAR2,TCRAM IF Test Error Address Register 2"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error source identification" "No error,March,Checker,,Unique,?..."
|
|
hexmask.long.word 0x00 0.--14. 0x01 " ERR_ADDR ,Error occurrence address"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TEAR2,TCRAM IF Test Error Address Register 2"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error source identification" "No error,March,Checker,,Unique,?..."
|
|
endif
|
|
if ((per.l(ad:0xB0410000)&0x100)==0x00)
|
|
group.word 0x3C++0x03
|
|
line.word 0x00 "TAEAR,TCRAM IF Test End Address Register"
|
|
hexmask.word 0x00 0.--14. 0x01 " EADDR ,RAM diagnosis end address"
|
|
line.word 0x02 "TASAR,TCRAM IF Test Start Address Register"
|
|
hexmask.word 0x02 0.--14. 0x01 " SADDR ,RAM diagnosis start address"
|
|
group.byte 0x40++0x01
|
|
line.byte 0x00 "TFECR,TCRAM IF Test Pseudo Error Generation Control Register"
|
|
bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo error generation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ETYP[2] ,Generate pseudo-errors during unique diagnosis" "Not generated,Generated"
|
|
bitfld.byte 0x00 1. " [1] ,Generate pseudo-errors during checker diagnosis" "Not generated,Generated"
|
|
bitfld.byte 0x00 0. " [0] ,Generate pseudo-errors during march diagnosis" "Not generated,Generated"
|
|
line.byte 0x01 "TICR,TCRAM IF Test Initialization Function Register"
|
|
bitfld.byte 0x01 3. " ICIE ,RAM initialization end source interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " ICI ,RAM initialization completion" "Not completed,Completed"
|
|
bitfld.byte 0x01 1. " ITYP ,RAM initialization contents specification" "0,1"
|
|
rbitfld.byte 0x01 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress"
|
|
group.word 0x42++0x01
|
|
line.word 0x00 "TTCR,TCRAM IF Test Diagnosis Function Register"
|
|
rbitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error"
|
|
rbitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or less,4 or more"
|
|
bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TEI ,Diagnosis-time error generation" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TCIE ,Diagnosis end source interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed"
|
|
bitfld.word 0x00 3. " TTYP[3] ,Perform unique diagnosis" "Not performed,Performed"
|
|
bitfld.word 0x00 2. " [2] ,Perform checker diagnosis" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " [1] ,Perform march diagnosis" "Not performed,Performed"
|
|
rbitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "TSRCR,TCRAM IF Test Soft Reset Generation Control Register"
|
|
bitfld.byte 0x00 7. " SRST ,Software reset" "No reset,Reset"
|
|
group.byte 0x47++0x00
|
|
line.byte 0x00 "TKCCR,TCRAM IF Test Key Code Control Register"
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11"
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forcibly terminate,Activate initialization,Activate diagnosis,?..."
|
|
else
|
|
rgroup.word 0x3C++0x03
|
|
line.word 0x00 "TAEAR,TCRAM IF Test End Address Register"
|
|
hexmask.word 0x00 0.--14. 0x01 " EADDR ,RAM diagnosis end address"
|
|
line.word 0x02 "TASAR,TCRAM IF Test Start Address Register"
|
|
hexmask.word 0x02 0.--14. 0x01 " SADDR ,RAM diagnosis start address"
|
|
rgroup.byte 0x40++0x01
|
|
line.byte 0x00 "TFECR,TCRAM IF Test Pseudo Error Generation Control Register"
|
|
bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo error generation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ETYP[2] ,Generate pseudo-errors during unique diagnosis" "Not generated,Generated"
|
|
bitfld.byte 0x00 1. " [1] ,Generate pseudo-errors during checker diagnosis" "Not generated,Generated"
|
|
bitfld.byte 0x00 0. " [0] ,Generate pseudo-errors during march diagnosis" "Not generated,Generated"
|
|
line.byte 0x01 "TICR,TCRAM IF Test Initialization Function Register"
|
|
bitfld.byte 0x01 3. " ICIE ,RAM initialization end source interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " ICI ,RAM initialization completion" "Not completed,Completed"
|
|
bitfld.byte 0x01 1. " ITYP ,RAM initialization contents specification" "0,1"
|
|
bitfld.byte 0x01 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "TTCR,TCRAM IF Test Diagnosis Function Register"
|
|
bitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error"
|
|
bitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or less,4 or more"
|
|
bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TEI ,Diagnosis-time error generation" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TCIE ,Diagnosis end source interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed"
|
|
bitfld.word 0x00 3. " TTYP[3] ,Perform unique diagnosis" "Not performed,Performed"
|
|
bitfld.word 0x00 2. " [2] ,Perform checker diagnosis" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " [1] ,Perform march diagnosis" "Not performed,Performed"
|
|
bitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress"
|
|
rgroup.byte 0x44++0x00
|
|
line.byte 0x00 "TSRCR,TCRAM IF Test Soft Reset Generation Control Register"
|
|
bitfld.byte 0x00 7. " SRST ,Software reset" "No reset,Reset"
|
|
rgroup.byte 0x47++0x00
|
|
line.byte 0x00 "TKCCR,TCRAM IF Test Key Code Control Register"
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11"
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forcibly terminate,Activate initialization,Activate diagnosis,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 1"
|
|
base ad:0xB0410400
|
|
width 11.
|
|
if (((per.l(ad:0xB0410400))&0x100)==0x00)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TCMCFG0,TCRAM IF Configuration Register 0"
|
|
bitfld.long 0x00 24.--25. " DWAIT ,Number of data wait bits" "0,1,2,3"
|
|
rbitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERRECC ,ECC data error insertion bits"
|
|
line.long 0x04 "TCMCFG1,TCRAM IF Configuration Register 1"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "TCMCFG0,TCRAM IF Configuration Register 0"
|
|
bitfld.long 0x00 24.--25. " DWAIT ,Number of data wait bits" "0,1,2,3"
|
|
bitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERRECC ,ECC data error insertion bits"
|
|
line.long 0x04 "TCMCFG1,TCRAM IF Configuration Register 1"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "TCMUNLOCK,TCRAM IF Unlock Register"
|
|
if ((per.l(ad:0xB0410400+0x30)&0xE0000000)!=0x00)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TEAR0,TCRAM IF Test Error Address Register 0"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error source identification" "No error,March,Checker,,Unique,?..."
|
|
hexmask.long.word 0x00 0.--14. 0x01 " ERR_ADDR ,Error occurrence address"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TEAR0,TCRAM IF Test Error Address Register 0"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error source identification" "No error,March,Checker,,Unique,?..."
|
|
endif
|
|
if ((per.l(ad:0xB0410400+0x34)&0xE0000000)!=0x00)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TEAR1,TCRAM IF Test Error Address Register 1"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error source identification" "No error,March,Checker,,Unique,?..."
|
|
hexmask.long.word 0x00 0.--14. 0x01 " ERR_ADDR ,Error occurrence address"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TEAR1,TCRAM IF Test Error Address Register 1"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error source identification" "No error,March,Checker,,Unique,?..."
|
|
endif
|
|
if ((per.l(ad:0xB0410400+0x38)&0xE0000000)!=0x00)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TEAR2,TCRAM IF Test Error Address Register 2"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error source identification" "No error,March,Checker,,Unique,?..."
|
|
hexmask.long.word 0x00 0.--14. 0x01 " ERR_ADDR ,Error occurrence address"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TEAR2,TCRAM IF Test Error Address Register 2"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error source identification" "No error,March,Checker,,Unique,?..."
|
|
endif
|
|
if ((per.l(ad:0xB0410400)&0x100)==0x00)
|
|
group.word 0x3C++0x03
|
|
line.word 0x00 "TAEAR,TCRAM IF Test End Address Register"
|
|
hexmask.word 0x00 0.--14. 0x01 " EADDR ,RAM diagnosis end address"
|
|
line.word 0x02 "TASAR,TCRAM IF Test Start Address Register"
|
|
hexmask.word 0x02 0.--14. 0x01 " SADDR ,RAM diagnosis start address"
|
|
group.byte 0x40++0x01
|
|
line.byte 0x00 "TFECR,TCRAM IF Test Pseudo Error Generation Control Register"
|
|
bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo error generation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ETYP[2] ,Generate pseudo-errors during unique diagnosis" "Not generated,Generated"
|
|
bitfld.byte 0x00 1. " [1] ,Generate pseudo-errors during checker diagnosis" "Not generated,Generated"
|
|
bitfld.byte 0x00 0. " [0] ,Generate pseudo-errors during march diagnosis" "Not generated,Generated"
|
|
line.byte 0x01 "TICR,TCRAM IF Test Initialization Function Register"
|
|
bitfld.byte 0x01 3. " ICIE ,RAM initialization end source interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " ICI ,RAM initialization completion" "Not completed,Completed"
|
|
bitfld.byte 0x01 1. " ITYP ,RAM initialization contents specification" "0,1"
|
|
rbitfld.byte 0x01 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress"
|
|
group.word 0x42++0x01
|
|
line.word 0x00 "TTCR,TCRAM IF Test Diagnosis Function Register"
|
|
rbitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error"
|
|
rbitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or less,4 or more"
|
|
bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TEI ,Diagnosis-time error generation" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TCIE ,Diagnosis end source interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed"
|
|
bitfld.word 0x00 3. " TTYP[3] ,Perform unique diagnosis" "Not performed,Performed"
|
|
bitfld.word 0x00 2. " [2] ,Perform checker diagnosis" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " [1] ,Perform march diagnosis" "Not performed,Performed"
|
|
rbitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "TSRCR,TCRAM IF Test Soft Reset Generation Control Register"
|
|
bitfld.byte 0x00 7. " SRST ,Software reset" "No reset,Reset"
|
|
group.byte 0x47++0x00
|
|
line.byte 0x00 "TKCCR,TCRAM IF Test Key Code Control Register"
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11"
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forcibly terminate,Activate initialization,Activate diagnosis,?..."
|
|
else
|
|
rgroup.word 0x3C++0x03
|
|
line.word 0x00 "TAEAR,TCRAM IF Test End Address Register"
|
|
hexmask.word 0x00 0.--14. 0x01 " EADDR ,RAM diagnosis end address"
|
|
line.word 0x02 "TASAR,TCRAM IF Test Start Address Register"
|
|
hexmask.word 0x02 0.--14. 0x01 " SADDR ,RAM diagnosis start address"
|
|
rgroup.byte 0x40++0x01
|
|
line.byte 0x00 "TFECR,TCRAM IF Test Pseudo Error Generation Control Register"
|
|
bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo error generation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ETYP[2] ,Generate pseudo-errors during unique diagnosis" "Not generated,Generated"
|
|
bitfld.byte 0x00 1. " [1] ,Generate pseudo-errors during checker diagnosis" "Not generated,Generated"
|
|
bitfld.byte 0x00 0. " [0] ,Generate pseudo-errors during march diagnosis" "Not generated,Generated"
|
|
line.byte 0x01 "TICR,TCRAM IF Test Initialization Function Register"
|
|
bitfld.byte 0x01 3. " ICIE ,RAM initialization end source interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " ICI ,RAM initialization completion" "Not completed,Completed"
|
|
bitfld.byte 0x01 1. " ITYP ,RAM initialization contents specification" "0,1"
|
|
bitfld.byte 0x01 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "TTCR,TCRAM IF Test Diagnosis Function Register"
|
|
bitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error"
|
|
bitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or less,4 or more"
|
|
bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TEI ,Diagnosis-time error generation" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TCIE ,Diagnosis end source interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed"
|
|
bitfld.word 0x00 3. " TTYP[3] ,Perform unique diagnosis" "Not performed,Performed"
|
|
bitfld.word 0x00 2. " [2] ,Perform checker diagnosis" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " [1] ,Perform march diagnosis" "Not performed,Performed"
|
|
bitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress"
|
|
rgroup.byte 0x44++0x00
|
|
line.byte 0x00 "TSRCR,TCRAM IF Test Soft Reset Generation Control Register"
|
|
bitfld.byte 0x00 7. " SRST ,Software reset" "No reset,Reset"
|
|
rgroup.byte 0x47++0x00
|
|
line.byte 0x00 "TKCCR,TCRAM IF Test Key Code Control Register"
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11"
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forcibly terminate,Activate initialization,Activate diagnosis,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "WorkFLASH"
|
|
tree "Unit 0"
|
|
base ad:0xB0412000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CPR,WorkFLASH Configuration Protection Key Register"
|
|
if (((per.l(ad:0xB0412000))&0xFFFFFFFF)==0x00)
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "CR,WorkFLASH Configuration Register"
|
|
bitfld.long 0x00 16. " SWFRST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " WE ,Program enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " FAWC ,Flash wait control" "No wait,1 cycle,2 cycles,3 cycles"
|
|
line.long 0x04 "ECR,WorkFLASH ECC Control Register"
|
|
bitfld.long 0x04 0. " ECCOFF ,Disable ECC generation and check by access via mirror area 1" "No,Yes"
|
|
else
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "CR,WorkFLASH Configuration Register"
|
|
bitfld.long 0x00 16. " SWFRST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " WE ,Program Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " FAWC ,Flash wait control" "No wait,1 cycle,2 cycles,3 cycles"
|
|
line.long 0x04 "ECR,WorkFLASH ECC Control Register"
|
|
bitfld.long 0x04 0. " ECCOFF ,Disable ECC generation and check by access via mirror area 1" "No,Yes"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "WCR,WorkFLASH Write Command Sequencer Configuration Register"
|
|
bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "WSR,WorkFLASH Write Command Sequencer Status Register"
|
|
bitfld.long 0x00 0.--1. " ST ,Write command sequencer status" "Idle state,Sending,Waiting,?..."
|
|
if (((per.l(ad:0xB0412000))&0xFFFFFFFF)==0x00)
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "DBEIR,WorkFLASH Data Bit Error Injection Register"
|
|
line.long 0x04 "EEIR,WorkFLASH ECC Bit Error Injection Register"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EEIR ,ECC bit error injection location"
|
|
else
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "DBEIR,WorkFLASH Data Bit Error Injection Register"
|
|
line.long 0x04 "EEIR,WorkFLASH ECC Bit Error Injection Register"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EEIR ,ECC bit error injection location"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ICR,WorkFLASH Interrupt Control Register"
|
|
bitfld.long 0x00 9. " HANGIC ,Hang interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RDYIC ,Ready interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RDYIE ,Programming/erasing ready interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SR,WorkFLASH Status Register"
|
|
bitfld.long 0x00 9. " HANGINT ,Hang-up interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RDYINT ,Programming/erasing ready interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RDY ,Programming/erasing ready" "Not ready,Ready"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SECIR,WorkFLASH SEC Interrupt Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " SYN ,Syndrome"
|
|
rbitfld.long 0x00 16. " SECINT ,1-bit error correction interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SECIC ,1-bit error correction interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " SECIE ,1-bit error correction interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "EEAR,WorkFLASH ECC Error Address Register"
|
|
line.long 0x04 "MIR,WorkFLASH Module Identification Register"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SEQCM,WorkFLASH Sequencer Command Register"
|
|
bitfld.long 0x00 23. " ERS7E ,Sector 7 erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ERS6E ,Sector 6 erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ERS5E ,Sector 5 erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ERS4E ,Sector 4 erase enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERS3E ,Sector 3 erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ERS2E ,Sector 2 erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ERS1E ,Sector 1 erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ERS0E ,Sector 0 erase enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " OPC ,Command" ",Read/reset,Erase/macro erase,?..."
|
|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "BERR,WorkFLASH Bus Error Response Factor Register"
|
|
bitfld.long 0x00 9. " WTTM ,Writing to the corresponding reserved area in mirror area 2" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ACCIGN ,Command overrun" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " ECRWL ,Protection sequence violation" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " UNACC ,Unprivileged writing" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RESA ,Reserved area access" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " SIZE ,Access size violation" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " CRWE ,Writing prohibition violation" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DED ,Uncorrectable error detection" "Not detected,Detected"
|
|
wgroup.long 0x64++0x07
|
|
line.long 0x00 "BERRCLR,WorkFLASH Bus Error Response Factor Clear Register"
|
|
bitfld.long 0x00 9. " WTTMCLR ,WTTM clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " ACCIGNCLR ,ACCIGN clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " ECRWLCLR ,ECRWL clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " UNACCLR ,UNACC clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RESACLR ,RESA clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " SIZECLR ,SIZE clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CRWECLR ,CRWE clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DEDCLR ,DED clear" "No effect,Clear"
|
|
rgroup.long 0x6C++0x07
|
|
line.long 0x00 "UCESR,WorkFLASH Uncorrectable Error Status Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " SYN ,Syndrome"
|
|
line.long 0x04 "UCEAR,WorkFLASH Uncorrectable Error Address Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 1"
|
|
base ad:0xB0412400
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CPR,WorkFLASH Configuration Protection Key Register"
|
|
if (((per.l(ad:0xB0412400))&0xFFFFFFFF)==0x00)
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "CR,WorkFLASH Configuration Register"
|
|
bitfld.long 0x00 16. " SWFRST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " WE ,Program enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " FAWC ,Flash wait control" "No wait,1 cycle,2 cycles,3 cycles"
|
|
line.long 0x04 "ECR,WorkFLASH ECC Control Register"
|
|
bitfld.long 0x04 0. " ECCOFF ,Disable ECC generation and check by access via mirror area 1" "No,Yes"
|
|
else
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "CR,WorkFLASH Configuration Register"
|
|
bitfld.long 0x00 16. " SWFRST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " WE ,Program Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " FAWC ,Flash wait control" "No wait,1 cycle,2 cycles,3 cycles"
|
|
line.long 0x04 "ECR,WorkFLASH ECC Control Register"
|
|
bitfld.long 0x04 0. " ECCOFF ,Disable ECC generation and check by access via mirror area 1" "No,Yes"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "WCR,WorkFLASH Write Command Sequencer Configuration Register"
|
|
bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "WSR,WorkFLASH Write Command Sequencer Status Register"
|
|
bitfld.long 0x00 0.--1. " ST ,Write command sequencer status" "Idle state,Sending,Waiting,?..."
|
|
if (((per.l(ad:0xB0412400))&0xFFFFFFFF)==0x00)
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "DBEIR,WorkFLASH Data Bit Error Injection Register"
|
|
line.long 0x04 "EEIR,WorkFLASH ECC Bit Error Injection Register"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EEIR ,ECC bit error injection location"
|
|
else
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "DBEIR,WorkFLASH Data Bit Error Injection Register"
|
|
line.long 0x04 "EEIR,WorkFLASH ECC Bit Error Injection Register"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EEIR ,ECC bit error injection location"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ICR,WorkFLASH Interrupt Control Register"
|
|
bitfld.long 0x00 9. " HANGIC ,Hang interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RDYIC ,Ready interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RDYIE ,Programming/erasing ready interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SR,WorkFLASH Status Register"
|
|
bitfld.long 0x00 9. " HANGINT ,Hang-up interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RDYINT ,Programming/erasing ready interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RDY ,Programming/erasing ready" "Not ready,Ready"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SECIR,WorkFLASH SEC Interrupt Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " SYN ,Syndrome"
|
|
rbitfld.long 0x00 16. " SECINT ,1-bit error correction interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SECIC ,1-bit error correction interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " SECIE ,1-bit error correction interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "EEAR,WorkFLASH ECC Error Address Register"
|
|
line.long 0x04 "MIR,WorkFLASH Module Identification Register"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SEQCM,WorkFLASH Sequencer Command Register"
|
|
bitfld.long 0x00 23. " ERS7E ,Sector 7 erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ERS6E ,Sector 6 erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ERS5E ,Sector 5 erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ERS4E ,Sector 4 erase enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERS3E ,Sector 3 erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ERS2E ,Sector 2 erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ERS1E ,Sector 1 erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ERS0E ,Sector 0 erase enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " OPC ,Command" ",Read/reset,Erase/macro erase,?..."
|
|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "BERR,WorkFLASH Bus Error Response Factor Register"
|
|
bitfld.long 0x00 9. " WTTM ,Writing to the corresponding reserved area in mirror area 2" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ACCIGN ,Command overrun" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " ECRWL ,Protection sequence violation" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " UNACC ,Unprivileged writing" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RESA ,Reserved area access" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " SIZE ,Access size violation" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " CRWE ,Writing prohibition violation" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DED ,Uncorrectable error detection" "Not detected,Detected"
|
|
wgroup.long 0x64++0x07
|
|
line.long 0x00 "BERRCLR,WorkFLASH Bus Error Response Factor Clear Register"
|
|
bitfld.long 0x00 9. " WTTMCLR ,WTTM clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " ACCIGNCLR ,ACCIGN clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " ECRWLCLR ,ECRWL clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " UNACCLR ,UNACC clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RESACLR ,RESA clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " SIZECLR ,SIZE clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CRWECLR ,CRWE clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DEDCLR ,DED clear" "No effect,Clear"
|
|
rgroup.long 0x6C++0x07
|
|
line.long 0x00 "UCESR,WorkFLASH Uncorrectable Error Status Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " SYN ,Syndrome"
|
|
line.long 0x04 "UCEAR,WorkFLASH Uncorrectable Error Address Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "HWDG (Hardware Watchdog Timer)"
|
|
base ad:0xB060C000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PROT,Hardware Watchdog Protection Register"
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "CNT,Hardware Watchdog Counter Register"
|
|
line.long 0x04 "RSTCAUSE,Hardware Watchdog Reset Factor Register (Read Only)"
|
|
bitfld.long 0x04 4. " RSTCAUSE4 ,Reset factor bit 4" "Not detected,Detected"
|
|
bitfld.long 0x04 3. " RSTCAUSE3 ,Reset factor bit 3" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " RSTCAUSE2 ,Reset factor bit 2" "Not detected,Detected"
|
|
bitfld.long 0x04 1. " RSTCAUSE1 ,Reset factor bit 1" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 0. " RSTCAUSE0 ,Reset factor bit 0" "Not detected,Detected"
|
|
if (((per.l(ad:0xB060C000))&0xFFFFFFFF)==0xFFFFFFFF)&&(((per.l(ad:0xB060C000+0x48))&0x1000000)==0x00)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "RSTCAUSE,Hardware Watchdog Reset Factor Register (Write Only)"
|
|
bitfld.long 0x00 4. " RSTCAUSE4 ,Reset factor bit 4" "Clear,?..."
|
|
bitfld.long 0x00 3. " RSTCAUSE3 ,Reset factor bit 3" "Clear,?..."
|
|
bitfld.long 0x00 2. " RSTCAUSE2 ,Reset factor bit 2" "Clear,?..."
|
|
bitfld.long 0x00 1. " RSTCAUSE1 ,Reset factor bit 1" "Clear,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " RSTCAUSE0 ,Reset factor bit 0" "Clear,?..."
|
|
endif
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "TRG0,Hardware Watchdog Trigger 0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0 ,Watchdog trigger 0"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "TRG1,Hardware Watchdog Trigger 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG1 ,Watchdog trigger 1"
|
|
if (((per.l(ad:0xB060C000))&0xFFFFFFFF)==0xFFFFFFFF)&&(((per.l(ad:0xB060C000+0x48))&0x1000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "INT,Hardware Watchdog Interrupt Configuration Register"
|
|
bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable" "NMI,Reset"
|
|
bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "INT,Hardware Watchdog Interrupt Configuration Register"
|
|
bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable" "NMI,Reset"
|
|
bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected"
|
|
endif
|
|
if (((per.l(ad:0xB060C000))&0xFFFFFFFF)==0xFFFFFFFF)
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "INTCLR,Hardware Watchdog Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " NMICLR ,NMI flag clear" ",Clear"
|
|
bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear" ",Clear"
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "INTCLR,Hardware Watchdog Interrupt Clear Register"
|
|
endif
|
|
if (((per.l(ad:0xB060C000))&0xFFFFFFFF)==0xFFFFFFFF)&&(((per.l(ad:0xB060C000+0x48))&0x1000000)==0x00)
|
|
group.long 0x2C++0x1F
|
|
line.long 0x00 "TRG0CFG,Hardware Watchdog Trigger 0 Configuration Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration"
|
|
line.long 0x04 "TRG1CFG,Hardware Watchdog Trigger 1 Configuration Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration"
|
|
line.long 0x08 "RUNLLS,Hardware Watchdog Lower Limit RUN Setting Register"
|
|
line.long 0x0C "RUNULS,Hardware Watchdog Upper Limit RUN Setting Register"
|
|
line.long 0x10 "PSSLLS,Hardware Watchdog Lower Limit PSS Setting Register"
|
|
line.long 0x14 "PSSULS,Hardware Watchdog Upper Limit PSS Setting Register"
|
|
line.long 0x18 "RSTDLY,Hardware Watchdog Reset Delay Counter Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter"
|
|
line.long 0x1C "CFG,Hardware Watchdog Configuration Register"
|
|
bitfld.long 0x1C 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x1C 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x1C 8.--9. " CLKSEL ,Clock selection" "Fast-CR,Slow-CR,Fast-CR,Slow-CR"
|
|
rbitfld.long 0x1C 2. " ALLOWSTOPCLK ,Clock stop for PSS enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x1C 1. " WDENPSS ,Watchdog counter for PSS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x1C 0. " WDENRUN ,Watchdog counter for RUN enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x2C++0x1F
|
|
line.long 0x00 "TRG0CFG,Hardware Watchdog Trigger 0 Configuration Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration"
|
|
line.long 0x04 "TRG1CFG,Hardware Watchdog Trigger 1 Configuration Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration"
|
|
line.long 0x08 "RUNLLS,Hardware Watchdog Lower Limit RUN Setting Register"
|
|
line.long 0x0C "RUNULS,Hardware Watchdog Upper Limit RUN Setting Register"
|
|
line.long 0x10 "PSSLLS,Hardware Watchdog Lower Limit PSS Setting Register"
|
|
line.long 0x14 "PSSULS,Hardware Watchdog Upper Limit PSS Setting Register"
|
|
line.long 0x18 "RSTDLY,Hardware Watchdog Reset Delay Counter Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter"
|
|
line.long 0x1C "CFG,Hardware Watchdog Configuration Register"
|
|
bitfld.long 0x1C 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x1C 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x1C 8.--9. " CLKSEL ,Clock selection" "Fast-CR,Slow-CR,Fast-CR,Slow-CR"
|
|
bitfld.long 0x1C 2. " ALLOWSTOPCLK ,Clock stop for PSS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " WDENPSS ,Watchdog counter for PSS enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " WDENRUN ,Watchdog counter for RUN enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x4C++0x0F
|
|
line.long 0x00 "RUNLLC,Hardware Watchdog Lower Limit RUN Current Register"
|
|
line.long 0x04 "RUNULC,Hardware Watchdog Upper Limit RUN Current Register"
|
|
line.long 0x08 "PSSLLC,Hardware Watchdog Lower Limit PSS Current Register"
|
|
line.long 0x0C "PSSULC,Hardware Watchdog Upper Limit PSS Current Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "SWDG (Software Watchdog Timer)"
|
|
tree "Unit 0"
|
|
base ad:0xB0608000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PROT,Software Watchdog Protection Register"
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "CNT,Software Watchdog Counter Register"
|
|
line.long 0x04 "RSTCAUSE,Software Watchdog Reset Factor Register (Read Only)"
|
|
bitfld.long 0x04 4. " RSTCAUSE4 ,Reset factor bit 4" "Not detected,Detected"
|
|
bitfld.long 0x04 3. " RSTCAUSE3 ,Reset factor bit 3" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " RSTCAUSE2 ,Reset factor bit 2" "Not detected,Detected"
|
|
bitfld.long 0x04 1. " RSTCAUSE1 ,Reset factor bit 1" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 0. " RSTCAUSE0 ,Reset factor bit 0" "Not detected,Detected"
|
|
if (((per.l(ad:0xB0608000))&0xFFFFFFFF)==0xFFFFFFFF)&&(((per.l(ad:0xB0608000+0x48))&0x1000000)==0x00)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "RSTCAUSE,Software Watchdog Reset Factor Register (Write Only)"
|
|
bitfld.long 0x00 4. " RSTCAUSE4 ,Reset factor bit 4" "Clear,?..."
|
|
bitfld.long 0x00 3. " RSTCAUSE3 ,Reset factor bit 3" "Clear,?..."
|
|
bitfld.long 0x00 2. " RSTCAUSE2 ,Reset factor bit 2" "Clear,?..."
|
|
bitfld.long 0x00 1. " RSTCAUSE1 ,Reset factor bit 1" "Clear,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " RSTCAUSE0 ,Reset factor bit 0" "Clear,?..."
|
|
endif
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "TRG0,Software Watchdog Trigger 0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0 ,Watchdog trigger 0"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "TRG1,Software Watchdog Trigger 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG1 ,Watchdog trigger 1"
|
|
if (((per.l(ad:0xB0608000))&0xFFFFFFFF)==0xFFFFFFFF)&&(((per.l(ad:0xB0608000+0x48))&0x1000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "INT,Software Watchdog Interrupt Configuration Register"
|
|
bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable" "NMI,Reset"
|
|
bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "INT,Software Watchdog Interrupt Configuration Register"
|
|
bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable bit" "NMI,Reset"
|
|
bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected"
|
|
endif
|
|
if (((per.l(ad:0xB0608000))&0xFFFFFFFF)==0xFFFFFFFF)
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " NMICLR ,NMIFLAG clear" ",Clear"
|
|
bitfld.long 0x00 0. " IRQCLR ,IRQFLAG clear" ",Clear"
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register"
|
|
endif
|
|
if (((per.l(ad:0xB0608000))&0xFFFFFFFF)==0xFFFFFFFF)&&(((per.l(ad:0xB0608000+0x48))&0x1000000)==0x00)
|
|
group.long 0x2C++0x07
|
|
line.long 0x00 "TRG0CFG,Software Watchdog Trigger 0 Configuration Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration"
|
|
line.long 0x04 "TRG1CFG,Software Watchdog Trigger 1 Configuration Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration"
|
|
else
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "TRG0CFG,Software Watchdog Trigger 0 Configuration Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration"
|
|
line.long 0x04 "TRG1CFG,Software Watchdog Trigger 1 Configuration Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration"
|
|
endif
|
|
if (((per.l(ad:0xB0608000))&0xFFFFFFFF)==0xFFFFFFFF)
|
|
group.long 0x34++0x0F
|
|
line.long 0x00 "RUNLLS,Software Watchdog Lower Limit RUN Setting Register"
|
|
line.long 0x04 "RUNULS,Software Watchdog Upper Limit RUN Setting Register"
|
|
line.long 0x08 "PSSLLS,Software Watchdog Lower Limit PSS Setting Register"
|
|
line.long 0x0C "PSSULS,Software Watchdog Upper Limit PSS Setting Register"
|
|
else
|
|
rgroup.long 0x34++0x0F
|
|
line.long 0x00 "RUNLLS,Software Watchdog Lower Limit RUN Setting Register"
|
|
line.long 0x04 "RUNULS,Software Watchdog Upper Limit RUN Setting Register"
|
|
line.long 0x08 "PSSLLS,Software Watchdog Lower Limit PSS Setting Register"
|
|
line.long 0x0C "PSSULS,Software Watchdog Upper Limit PSS Setting Register"
|
|
endif
|
|
if (((per.l(ad:0xB0608000))&0xFFFFFFFF)==0xFFFFFFFF)&&(((per.l(ad:0xB0608000+0x48))&0x1000000)==0x00)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "RSTDLY,Software Watchdog Reset Delay Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter"
|
|
line.long 0x04 "CFG,Software Watchdog Configuration Register"
|
|
bitfld.long 0x04 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x04 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--9. " CLKSEL ,Clock selection" "Fast-CR,Slow-CR,,Main clock"
|
|
bitfld.long 0x04 2. " ALLOWSTOPCLK ,Clock stop for PSS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WDENPSS ,Watchdog counter for PSS enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WDENRUN ,Watchdog counter for RUN enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x44++0x07
|
|
line.long 0x00 "RSTDLY,Software Watchdog Reset Delay Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter"
|
|
line.long 0x04 "CFG,Software Watchdog Configuration Register"
|
|
bitfld.long 0x04 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x04 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--9. " CLKSEL ,Clock selection" "Fast-CR,Slow-CR,,Main clock"
|
|
bitfld.long 0x04 2. " ALLOWSTOPCLK ,Clock stop for PSS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WDENPSS ,Watchdog counter for PSS enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WDENRUN ,Watchdog counter for RUN enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x4C++0x0F
|
|
line.long 0x00 "RUNLLC,Software Watchdog Lower Limit RUN Current Register"
|
|
line.long 0x04 "RUNULC,Software Watchdog Upper Limit RUN Current Register"
|
|
line.long 0x08 "PSSLLC,Software Watchdog Lower Limit PSS Current Register"
|
|
line.long 0x0C "PSSULC,Software Watchdog Upper Limit PSS Current Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 1"
|
|
base ad:0xB0609000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PROT,Software Watchdog Protection Register"
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "CNT,Software Watchdog Counter Register"
|
|
line.long 0x04 "RSTCAUSE,Software Watchdog Reset Factor Register (Read Only)"
|
|
bitfld.long 0x04 4. " RSTCAUSE4 ,Reset factor bit 4" "Not detected,Detected"
|
|
bitfld.long 0x04 3. " RSTCAUSE3 ,Reset factor bit 3" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " RSTCAUSE2 ,Reset factor bit 2" "Not detected,Detected"
|
|
bitfld.long 0x04 1. " RSTCAUSE1 ,Reset factor bit 1" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 0. " RSTCAUSE0 ,Reset factor bit 0" "Not detected,Detected"
|
|
if (((per.l(ad:0xB0608000))&0xFFFFFFFF)==0xFFFFFFFF)&&(((per.l(ad:0xB0608000+0x48))&0x1000000)==0x00)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "RSTCAUSE,Software Watchdog Reset Factor Register (Write Only)"
|
|
bitfld.long 0x00 4. " RSTCAUSE4 ,Reset factor bit 4" "Clear,?..."
|
|
bitfld.long 0x00 3. " RSTCAUSE3 ,Reset factor bit 3" "Clear,?..."
|
|
bitfld.long 0x00 2. " RSTCAUSE2 ,Reset factor bit 2" "Clear,?..."
|
|
bitfld.long 0x00 1. " RSTCAUSE1 ,Reset factor bit 1" "Clear,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " RSTCAUSE0 ,Reset factor bit 0" "Clear,?..."
|
|
endif
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "TRG0,Software Watchdog Trigger 0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0 ,Watchdog trigger 0"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "TRG1,Software Watchdog Trigger 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG1 ,Watchdog trigger 1"
|
|
if (((per.l(ad:0xB0608000))&0xFFFFFFFF)==0xFFFFFFFF)&&(((per.l(ad:0xB0608000+0x48))&0x1000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "INT,Software Watchdog Interrupt Configuration Register"
|
|
bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable" "NMI,Reset"
|
|
bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "INT,Software Watchdog Interrupt Configuration Register"
|
|
bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable bit" "NMI,Reset"
|
|
bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected"
|
|
endif
|
|
if (((per.l(ad:0xB0608000))&0xFFFFFFFF)==0xFFFFFFFF)
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " NMICLR ,NMIFLAG clear" ",Clear"
|
|
bitfld.long 0x00 0. " IRQCLR ,IRQFLAG clear" ",Clear"
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register"
|
|
endif
|
|
if (((per.l(ad:0xB0608000))&0xFFFFFFFF)==0xFFFFFFFF)&&(((per.l(ad:0xB0608000+0x48))&0x1000000)==0x00)
|
|
group.long 0x2C++0x07
|
|
line.long 0x00 "TRG0CFG,Software Watchdog Trigger 0 Configuration Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration"
|
|
line.long 0x04 "TRG1CFG,Software Watchdog Trigger 1 Configuration Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration"
|
|
else
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "TRG0CFG,Software Watchdog Trigger 0 Configuration Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration"
|
|
line.long 0x04 "TRG1CFG,Software Watchdog Trigger 1 Configuration Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration"
|
|
endif
|
|
if (((per.l(ad:0xB0608000))&0xFFFFFFFF)==0xFFFFFFFF)
|
|
group.long 0x34++0x0F
|
|
line.long 0x00 "RUNLLS,Software Watchdog Lower Limit RUN Setting Register"
|
|
line.long 0x04 "RUNULS,Software Watchdog Upper Limit RUN Setting Register"
|
|
line.long 0x08 "PSSLLS,Software Watchdog Lower Limit PSS Setting Register"
|
|
line.long 0x0C "PSSULS,Software Watchdog Upper Limit PSS Setting Register"
|
|
else
|
|
rgroup.long 0x34++0x0F
|
|
line.long 0x00 "RUNLLS,Software Watchdog Lower Limit RUN Setting Register"
|
|
line.long 0x04 "RUNULS,Software Watchdog Upper Limit RUN Setting Register"
|
|
line.long 0x08 "PSSLLS,Software Watchdog Lower Limit PSS Setting Register"
|
|
line.long 0x0C "PSSULS,Software Watchdog Upper Limit PSS Setting Register"
|
|
endif
|
|
if (((per.l(ad:0xB0608000))&0xFFFFFFFF)==0xFFFFFFFF)&&(((per.l(ad:0xB0608000+0x48))&0x1000000)==0x00)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "RSTDLY,Software Watchdog Reset Delay Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter"
|
|
line.long 0x04 "CFG,Software Watchdog Configuration Register"
|
|
bitfld.long 0x04 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x04 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--9. " CLKSEL ,Clock selection" "Fast-CR,Slow-CR,,Main clock"
|
|
bitfld.long 0x04 2. " ALLOWSTOPCLK ,Clock stop for PSS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WDENPSS ,Watchdog counter for PSS enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WDENRUN ,Watchdog counter for RUN enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x44++0x07
|
|
line.long 0x00 "RSTDLY,Software Watchdog Reset Delay Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter"
|
|
line.long 0x04 "CFG,Software Watchdog Configuration Register"
|
|
bitfld.long 0x04 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x04 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--9. " CLKSEL ,Clock selection" "Fast-CR,Slow-CR,,Main clock"
|
|
bitfld.long 0x04 2. " ALLOWSTOPCLK ,Clock stop for PSS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WDENPSS ,Watchdog counter for PSS enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WDENRUN ,Watchdog counter for RUN enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x4C++0x0F
|
|
line.long 0x00 "RUNLLC,Software Watchdog Lower Limit RUN Current Register"
|
|
line.long 0x04 "RUNULC,Software Watchdog Upper Limit RUN Current Register"
|
|
line.long 0x08 "PSSLLC,Software Watchdog Lower Limit PSS Current Register"
|
|
line.long 0x0C "PSSULC,Software Watchdog Upper Limit PSS Current Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "DMAC (DMA Controller)"
|
|
base ad:0xB0700000
|
|
width 16.
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "DMA0_R,DMA Controller Global Configuration Register"
|
|
bitfld.long 0x00 31. " DE ,DMA enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 30. " DSHR ,DMA stop/halt request flag" "Removed,Halted/Disabled"
|
|
bitfld.long 0x00 29. " DBE ,Debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " PR ,Priority type" "Fixed,Dynamic,Round robin,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " DH ,DMA halt" "Not halted,Halted"
|
|
bitfld.long 0x00 24.--25. " DB ,Debug behavior" "Continued,Halted,Stopped,?..."
|
|
rbitfld.long 0x00 0. " DSHS ,DMA stop/halt status flag" "Running,Halted/Disabled"
|
|
rgroup.long 0x1004++0x03
|
|
line.long 0x00 "DMA0_DIRQ1,DMA Controller Global Completion Interrupt 1 Register"
|
|
bitfld.long 0x00 15. " DIRQ[15] ,Channel 15 completion interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " DIRQ[14] ,Channel 14 completion interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " DIRQ[13] ,Channel 13 completion interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " DIRQ[12] ,Channel 12 completion interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DIRQ[11] ,Channel 11 completion interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " DIRQ[10] ,Channel 10completion interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " DIRQ[9] ,Channel 9 completion interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " DIRQ[8] ,Channel 8 completion interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIRQ[7] ,Channel 7 completion interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " DIRQ[6] ,Channel 6 completion interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " DIRQ[5] ,Channel 5 completion interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " DIRQ[4] ,Channel 4 completion interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIRQ[3] ,Channel 3 completion interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " DIRQ[2] ,Channel 2 completion interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " DIRQ[1] ,Channel 1 completion interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DIRQ[0] ,Channel 0 completion interrupt" "No interrupt,Interrupt"
|
|
rgroup.long 0x100C++0x03
|
|
line.long 0x00 "DMA0_EDIRQ1,DMA Controller Global Error Interrupt 1 Register"
|
|
bitfld.long 0x00 15. " EDIRQ[15] ,Channel 15 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " EDIRQ[14] ,Channel 14 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " EDIRQ[13] ,Channel 13 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " EDIRQ[12] ,Channel 12 error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDIRQ[11] ,Channel 11 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " EDIRQ[10] ,Channel 10 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " EDIRQ[9] ,Channel 9 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " EDIRQ[8] ,Channel 8 error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EDIRQ[7] ,Channel 7 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " EDIRQ[6] ,Channel 6 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " EDIRQ[5] ,Channel 5 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " EDIRQ[4] ,Channel 4 error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EDIRQ[3] ,Channel 3 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " EDIRQ[2] ,Channel 2 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " EDIRQ[1] ,Channel 1 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " EDIRQ[0] ,Channel 0 error interrupt" "No interrupt,Interrupt"
|
|
rgroup.long 0x1014++0x03
|
|
line.long 0x00 "DMA0_ID,DMA Controller ID Register"
|
|
tree "Channel Configuration A Registers"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "DMA0_A0,DMA Controller Channel Configuration A Register Channel 0"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA0_A1,DMA Controller Channel Configuration A Register Channel 1"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DMA0_A2,DMA Controller Channel Configuration A Register Channel 2"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DMA0_A3,DMA Controller Channel Configuration A Register Channel 3"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DMA0_A4,DMA Controller Channel Configuration A Register Channel 4"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DMA0_A5,DMA Controller Channel Configuration A Register Channel 5"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DMA0_A6,DMA Controller Channel Configuration A Register Channel 6"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "DMA0_A7,DMA Controller Channel Configuration A Register Channel 7"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DMA0_A8,DMA Controller Channel Configuration A Register Channel 8"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "DMA0_A9,DMA Controller Channel Configuration A Register Channel 9"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "DMA0_A10,DMA Controller Channel Configuration A Register Channel 10"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "DMA0_A11,DMA Controller Channel Configuration A Register Channel 11"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "DMA0_A12,DMA Controller Channel Configuration A Register Channel 12"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "DMA0_A13,DMA Controller Channel Configuration A Register Channel 13"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "DMA0_A14,DMA Controller Channel Configuration A Register Channel 14"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "DMA0_A15,DMA Controller Channel Configuration A Register Channel 15"
|
|
bitfld.long 0x00 31. " EB ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat limit" "SINGLE,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 20.--23. " BC ,Block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 16.--19. " TO ,Timeout" ",,,,,,,,,,,,,,,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
tree.end
|
|
tree "Channel Configuration B Registers"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "DMA0_B0,DMA Controller Channel Configuration B Register Channel 0"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DMA0_B1,DMA Controller Channel Configuration B Register Channel 1"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "DMA0_B2,DMA Controller Channel Configuration B Register Channel 2"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DMA0_B3,DMA Controller Channel Configuration B Register Channel 3"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DMA0_B4,DMA Controller Channel Configuration B Register Channel 4"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DMA0_B5,DMA Controller Channel Configuration B Register Channel 5"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "DMA0_B6,DMA Controller Channel Configuration B Register Channel 6"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "DMA0_B7,DMA Controller Channel Configuration B Register Channel 7"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "DMA0_B8,DMA Controller Channel Configuration B Register Channel 8"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "DMA0_B9,DMA Controller Channel Configuration B Register Channel 9"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "DMA0_B10,DMA Controller Channel Configuration B Register Channel 10"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "DMA0_B11,DMA Controller Channel Configuration B Register Channel 11"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DMA0_B12,DMA Controller Channel Configuration B Register Channel 12"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "DMA0_B13,DMA Controller Channel Configuration B Register Channel 13"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "DMA0_B14,DMA Controller Channel Configuration B Register Channel 14"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x3C4++0x03
|
|
line.long 0x00 "DMA0_B15,DMA Controller Channel Configuration B Register Channel 15"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer data width" "Byte,Half word,Word,Double word"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[3] ,Source access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 12. " SP[0] ,Source access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP[3] ,Destination access protection bit 3" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination access protection bit 2" "Not bufferable,Bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination access protection bit 1" "User access,Privileged access"
|
|
bitfld.long 0x00 8. " DP[0] ,Destination access protection bit 0" "Instruction access,Data access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
tree.end
|
|
tree "Channel Configuration Source Address Registers"
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x8-0x08))&0x80000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "DMA0_SA0,DMA Controller Channel Configuration Source Address Register Channel 0"
|
|
else
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "DMA0_SA0,DMA Controller Channel Configuration Source Address Register Channel 0"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x48-0x08))&0x80000000)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA0_SA1,DMA Controller Channel Configuration Source Address Register Channel 1"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "DMA0_SA1,DMA Controller Channel Configuration Source Address Register Channel 1"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x88-0x08))&0x80000000)==0x00)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "DMA0_SA2,DMA Controller Channel Configuration Source Address Register Channel 2"
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "DMA0_SA2,DMA Controller Channel Configuration Source Address Register Channel 2"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0xC8-0x08))&0x80000000)==0x00)
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DMA0_SA3,DMA Controller Channel Configuration Source Address Register Channel 3"
|
|
else
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "DMA0_SA3,DMA Controller Channel Configuration Source Address Register Channel 3"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x108-0x08))&0x80000000)==0x00)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DMA0_SA4,DMA Controller Channel Configuration Source Address Register Channel 4"
|
|
else
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "DMA0_SA4,DMA Controller Channel Configuration Source Address Register Channel 4"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x148-0x08))&0x80000000)==0x00)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DMA0_SA5,DMA Controller Channel Configuration Source Address Register Channel 5"
|
|
else
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "DMA0_SA5,DMA Controller Channel Configuration Source Address Register Channel 5"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x188-0x08))&0x80000000)==0x00)
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "DMA0_SA6,DMA Controller Channel Configuration Source Address Register Channel 6"
|
|
else
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "DMA0_SA6,DMA Controller Channel Configuration Source Address Register Channel 6"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x1C8-0x08))&0x80000000)==0x00)
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "DMA0_SA7,DMA Controller Channel Configuration Source Address Register Channel 7"
|
|
else
|
|
rgroup.long 0x1C8++0x03
|
|
line.long 0x00 "DMA0_SA7,DMA Controller Channel Configuration Source Address Register Channel 7"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x208-0x08))&0x80000000)==0x00)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "DMA0_SA8,DMA Controller Channel Configuration Source Address Register Channel 8"
|
|
else
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "DMA0_SA8,DMA Controller Channel Configuration Source Address Register Channel 8"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x248-0x08))&0x80000000)==0x00)
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "DMA0_SA9,DMA Controller Channel Configuration Source Address Register Channel 9"
|
|
else
|
|
rgroup.long 0x248++0x03
|
|
line.long 0x00 "DMA0_SA9,DMA Controller Channel Configuration Source Address Register Channel 9"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x288-0x08))&0x80000000)==0x00)
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "DMA0_SA10,DMA Controller Channel Configuration Source Address Register Channel 10"
|
|
else
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "DMA0_SA10,DMA Controller Channel Configuration Source Address Register Channel 10"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x2C8-0x08))&0x80000000)==0x00)
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "DMA0_SA11,DMA Controller Channel Configuration Source Address Register Channel 11"
|
|
else
|
|
rgroup.long 0x2C8++0x03
|
|
line.long 0x00 "DMA0_SA11,DMA Controller Channel Configuration Source Address Register Channel 11"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x308-0x08))&0x80000000)==0x00)
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "DMA0_SA12,DMA Controller Channel Configuration Source Address Register Channel 12"
|
|
else
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "DMA0_SA12,DMA Controller Channel Configuration Source Address Register Channel 12"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x348-0x08))&0x80000000)==0x00)
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "DMA0_SA13,DMA Controller Channel Configuration Source Address Register Channel 13"
|
|
else
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "DMA0_SA13,DMA Controller Channel Configuration Source Address Register Channel 13"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x388-0x08))&0x80000000)==0x00)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "DMA0_SA14,DMA Controller Channel Configuration Source Address Register Channel 14"
|
|
else
|
|
rgroup.long 0x388++0x03
|
|
line.long 0x00 "DMA0_SA14,DMA Controller Channel Configuration Source Address Register Channel 14"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x3C8-0x08))&0x80000000)==0x00)
|
|
group.long 0x3C8++0x03
|
|
line.long 0x00 "DMA0_SA15,DMA Controller Channel Configuration Source Address Register Channel 15"
|
|
else
|
|
rgroup.long 0x3C8++0x03
|
|
line.long 0x00 "DMA0_SA15,DMA Controller Channel Configuration Source Address Register Channel 15"
|
|
endif
|
|
tree.end
|
|
tree "Channel Configuration Destination Address Registers"
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0xC-0x0C))&0x80000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "DMA0_DA0,DMA Controller Channel Configuration Destination Address Register Channel 0"
|
|
else
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "DMA0_DA0,DMA Controller Channel Configuration Destination Address Register Channel 0"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x4C-0x0C))&0x80000000)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMA0_DA1,DMA Controller Channel Configuration Destination Address Register Channel 1"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA0_DA1,DMA Controller Channel Configuration Destination Address Register Channel 1"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x8C-0x0C))&0x80000000)==0x00)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "DMA0_DA2,DMA Controller Channel Configuration Destination Address Register Channel 2"
|
|
else
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "DMA0_DA2,DMA Controller Channel Configuration Destination Address Register Channel 2"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0xCC-0x0C))&0x80000000)==0x00)
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "DMA0_DA3,DMA Controller Channel Configuration Destination Address Register Channel 3"
|
|
else
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "DMA0_DA3,DMA Controller Channel Configuration Destination Address Register Channel 3"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x10C-0x0C))&0x80000000)==0x00)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DMA0_DA4,DMA Controller Channel Configuration Destination Address Register Channel 4"
|
|
else
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "DMA0_DA4,DMA Controller Channel Configuration Destination Address Register Channel 4"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x14C-0x0C))&0x80000000)==0x00)
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "DMA0_DA5,DMA Controller Channel Configuration Destination Address Register Channel 5"
|
|
else
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "DMA0_DA5,DMA Controller Channel Configuration Destination Address Register Channel 5"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x18C-0x0C))&0x80000000)==0x00)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "DMA0_DA6,DMA Controller Channel Configuration Destination Address Register Channel 6"
|
|
else
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "DMA0_DA6,DMA Controller Channel Configuration Destination Address Register Channel 6"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x1CC-0x0C))&0x80000000)==0x00)
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "DMA0_DA7,DMA Controller Channel Configuration Destination Address Register Channel 7"
|
|
else
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "DMA0_DA7,DMA Controller Channel Configuration Destination Address Register Channel 7"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x20C-0x0C))&0x80000000)==0x00)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "DMA0_DA8,DMA Controller Channel Configuration Destination Address Register Channel 8"
|
|
else
|
|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "DMA0_DA8,DMA Controller Channel Configuration Destination Address Register Channel 8"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x24C-0x0C))&0x80000000)==0x00)
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "DMA0_DA9,DMA Controller Channel Configuration Destination Address Register Channel 9"
|
|
else
|
|
rgroup.long 0x24C++0x03
|
|
line.long 0x00 "DMA0_DA9,DMA Controller Channel Configuration Destination Address Register Channel 9"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x28C-0x0C))&0x80000000)==0x00)
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "DMA0_DA10,DMA Controller Channel Configuration Destination Address Register Channel 10"
|
|
else
|
|
rgroup.long 0x28C++0x03
|
|
line.long 0x00 "DMA0_DA10,DMA Controller Channel Configuration Destination Address Register Channel 10"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x2CC-0x0C))&0x80000000)==0x00)
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "DMA0_DA11,DMA Controller Channel Configuration Destination Address Register Channel 11"
|
|
else
|
|
rgroup.long 0x2CC++0x03
|
|
line.long 0x00 "DMA0_DA11,DMA Controller Channel Configuration Destination Address Register Channel 11"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x30C-0x0C))&0x80000000)==0x00)
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "DMA0_DA12,DMA Controller Channel Configuration Destination Address Register Channel 12"
|
|
else
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "DMA0_DA12,DMA Controller Channel Configuration Destination Address Register Channel 12"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x34C-0x0C))&0x80000000)==0x00)
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "DMA0_DA13,DMA Controller Channel Configuration Destination Address Register Channel 13"
|
|
else
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "DMA0_DA13,DMA Controller Channel Configuration Destination Address Register Channel 13"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x38C-0x0C))&0x80000000)==0x00)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "DMA0_DA14,DMA Controller Channel Configuration Destination Address Register Channel 14"
|
|
else
|
|
rgroup.long 0x38C++0x03
|
|
line.long 0x00 "DMA0_DA14,DMA Controller Channel Configuration Destination Address Register Channel 14"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1000))&0x80000000)==0x00)||(((per.l(ad:0xB0700000+0x3CC-0x0C))&0x80000000)==0x00)
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "DMA0_DA15,DMA Controller Channel Configuration Destination Address Register Channel 15"
|
|
else
|
|
rgroup.long 0x3CC++0x03
|
|
line.long 0x00 "DMA0_DA15,DMA Controller Channel Configuration Destination Address Register Channel 15"
|
|
endif
|
|
tree.end
|
|
tree "Channel Configuration C Registers"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "DMA0_C0,DMA Controller Channel Configuration C Register Channel 0"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "DMA0_C1,DMA Controller Channel Configuration C Register Channel 1"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x90++0x03
|
|
line.long 0x00 "DMA0_C2,DMA Controller Channel Configuration C Register Channel 2"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0xD0++0x03
|
|
line.long 0x00 "DMA0_C3,DMA Controller Channel Configuration C Register Channel 3"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x110++0x03
|
|
line.long 0x00 "DMA0_C4,DMA Controller Channel Configuration C Register Channel 4"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x150++0x03
|
|
line.long 0x00 "DMA0_C5,DMA Controller Channel Configuration C Register Channel 5"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x190++0x03
|
|
line.long 0x00 "DMA0_C6,DMA Controller Channel Configuration C Register Channel 6"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x1D0++0x03
|
|
line.long 0x00 "DMA0_C7,DMA Controller Channel Configuration C Register Channel 7"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x210++0x03
|
|
line.long 0x00 "DMA0_C8,DMA Controller Channel Configuration C Register Channel 8"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x250++0x03
|
|
line.long 0x00 "DMA0_C9,DMA Controller Channel Configuration C Register Channel 9"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x290++0x03
|
|
line.long 0x00 "DMA0_C10,DMA Controller Channel Configuration C Register Channel 10"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x2D0++0x03
|
|
line.long 0x00 "DMA0_C11,DMA Controller Channel Configuration C Register Channel 11"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x310++0x03
|
|
line.long 0x00 "DMA0_C12,DMA Controller Channel Configuration C Register Channel 12"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x350++0x03
|
|
line.long 0x00 "DMA0_C13,DMA Controller Channel Configuration C Register Channel 13"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x390++0x03
|
|
line.long 0x00 "DMA0_C14,DMA Controller Channel Configuration C Register Channel 14"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
wgroup.long 0x3D0++0x03
|
|
line.long 0x00 "DMA0_C15,DMA Controller Channel Configuration C Register Channel 15"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
tree.end
|
|
tree "Channel Configuration D Registers"
|
|
if (((per.l(ad:0xB0700000+0x14-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x14))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x14))&0x10001000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DMA0_D0,DMA Controller Channel Configuration D Register Channel 0"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x14))&0x10001000)==0x1000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DMA0_D0,DMA Controller Channel Configuration D Register Channel 0"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x14))&0x10001000)==0x10000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DMA0_D0,DMA Controller Channel Configuration D Register Channel 0"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DMA0_D0,DMA Controller Channel Configuration D Register Channel 0"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x14))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x14))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DMA0_D0,DMA Controller Channel Configuration D Register Channel 0"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DMA0_D0,DMA Controller Channel Configuration D Register Channel 0"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x14))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x14))&0x00001000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DMA0_D0,DMA Controller Channel Configuration D Register Channel 0"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DMA0_D0,DMA Controller Channel Configuration D Register Channel 0"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DMA0_D0,DMA Controller Channel Configuration D Register Channel 0"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DMA0_D0,DMA Controller Channel Configuration D Register Channel 0"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x54-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x54))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x54))&0x10001000)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DMA0_D1,DMA Controller Channel Configuration D Register Channel 1"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x54))&0x10001000)==0x1000)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DMA0_D1,DMA Controller Channel Configuration D Register Channel 1"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x54))&0x10001000)==0x10000000)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DMA0_D1,DMA Controller Channel Configuration D Register Channel 1"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DMA0_D1,DMA Controller Channel Configuration D Register Channel 1"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x54))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x54))&0x10000000)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DMA0_D1,DMA Controller Channel Configuration D Register Channel 1"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DMA0_D1,DMA Controller Channel Configuration D Register Channel 1"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x54))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x54))&0x00001000)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DMA0_D1,DMA Controller Channel Configuration D Register Channel 1"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DMA0_D1,DMA Controller Channel Configuration D Register Channel 1"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DMA0_D1,DMA Controller Channel Configuration D Register Channel 1"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DMA0_D1,DMA Controller Channel Configuration D Register Channel 1"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x94-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x94))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x94))&0x10001000)==0x00)
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "DMA0_D2,DMA Controller Channel Configuration D Register Channel 2"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x94))&0x10001000)==0x1000)
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "DMA0_D2,DMA Controller Channel Configuration D Register Channel 2"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x94))&0x10001000)==0x10000000)
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "DMA0_D2,DMA Controller Channel Configuration D Register Channel 2"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "DMA0_D2,DMA Controller Channel Configuration D Register Channel 2"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x94))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x94))&0x10000000)==0x00)
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "DMA0_D2,DMA Controller Channel Configuration D Register Channel 2"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "DMA0_D2,DMA Controller Channel Configuration D Register Channel 2"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x94))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x94))&0x00001000)==0x00)
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "DMA0_D2,DMA Controller Channel Configuration D Register Channel 2"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "DMA0_D2,DMA Controller Channel Configuration D Register Channel 2"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "DMA0_D2,DMA Controller Channel Configuration D Register Channel 2"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "DMA0_D2,DMA Controller Channel Configuration D Register Channel 2"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0xD4-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0xD4))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0xD4))&0x10001000)==0x00)
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "DMA0_D3,DMA Controller Channel Configuration D Register Channel 3"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0xD4))&0x10001000)==0x1000)
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "DMA0_D3,DMA Controller Channel Configuration D Register Channel 3"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0xD4))&0x10001000)==0x10000000)
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "DMA0_D3,DMA Controller Channel Configuration D Register Channel 3"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "DMA0_D3,DMA Controller Channel Configuration D Register Channel 3"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0xD4))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0xD4))&0x10000000)==0x00)
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "DMA0_D3,DMA Controller Channel Configuration D Register Channel 3"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "DMA0_D3,DMA Controller Channel Configuration D Register Channel 3"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0xD4))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0xD4))&0x00001000)==0x00)
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "DMA0_D3,DMA Controller Channel Configuration D Register Channel 3"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "DMA0_D3,DMA Controller Channel Configuration D Register Channel 3"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "DMA0_D3,DMA Controller Channel Configuration D Register Channel 3"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "DMA0_D3,DMA Controller Channel Configuration D Register Channel 3"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x114-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x114))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x114))&0x10001000)==0x00)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DMA0_D4,DMA Controller Channel Configuration D Register Channel 4"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x114))&0x10001000)==0x1000)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DMA0_D4,DMA Controller Channel Configuration D Register Channel 4"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x114))&0x10001000)==0x10000000)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DMA0_D4,DMA Controller Channel Configuration D Register Channel 4"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DMA0_D4,DMA Controller Channel Configuration D Register Channel 4"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x114))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x114))&0x10000000)==0x00)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DMA0_D4,DMA Controller Channel Configuration D Register Channel 4"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DMA0_D4,DMA Controller Channel Configuration D Register Channel 4"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x114))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x114))&0x00001000)==0x00)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DMA0_D4,DMA Controller Channel Configuration D Register Channel 4"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DMA0_D4,DMA Controller Channel Configuration D Register Channel 4"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DMA0_D4,DMA Controller Channel Configuration D Register Channel 4"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DMA0_D4,DMA Controller Channel Configuration D Register Channel 4"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x154-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x154))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x154))&0x10001000)==0x00)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DMA0_D5,DMA Controller Channel Configuration D Register Channel 5"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x154))&0x10001000)==0x1000)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DMA0_D5,DMA Controller Channel Configuration D Register Channel 5"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x154))&0x10001000)==0x10000000)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DMA0_D5,DMA Controller Channel Configuration D Register Channel 5"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DMA0_D5,DMA Controller Channel Configuration D Register Channel 5"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x154))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x154))&0x10000000)==0x00)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DMA0_D5,DMA Controller Channel Configuration D Register Channel 5"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DMA0_D5,DMA Controller Channel Configuration D Register Channel 5"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x154))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x154))&0x00001000)==0x00)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DMA0_D5,DMA Controller Channel Configuration D Register Channel 5"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DMA0_D5,DMA Controller Channel Configuration D Register Channel 5"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DMA0_D5,DMA Controller Channel Configuration D Register Channel 5"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DMA0_D5,DMA Controller Channel Configuration D Register Channel 5"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x194-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x194))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x194))&0x10001000)==0x00)
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "DMA0_D6,DMA Controller Channel Configuration D Register Channel 6"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x194))&0x10001000)==0x1000)
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "DMA0_D6,DMA Controller Channel Configuration D Register Channel 6"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x194))&0x10001000)==0x10000000)
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "DMA0_D6,DMA Controller Channel Configuration D Register Channel 6"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "DMA0_D6,DMA Controller Channel Configuration D Register Channel 6"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x194))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x194))&0x10000000)==0x00)
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "DMA0_D6,DMA Controller Channel Configuration D Register Channel 6"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "DMA0_D6,DMA Controller Channel Configuration D Register Channel 6"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x194))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x194))&0x00001000)==0x00)
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "DMA0_D6,DMA Controller Channel Configuration D Register Channel 6"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "DMA0_D6,DMA Controller Channel Configuration D Register Channel 6"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "DMA0_D6,DMA Controller Channel Configuration D Register Channel 6"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "DMA0_D6,DMA Controller Channel Configuration D Register Channel 6"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x1D4-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x1D4))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x1D4))&0x10001000)==0x00)
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "DMA0_D7,DMA Controller Channel Configuration D Register Channel 7"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x1D4))&0x10001000)==0x1000)
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "DMA0_D7,DMA Controller Channel Configuration D Register Channel 7"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x1D4))&0x10001000)==0x10000000)
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "DMA0_D7,DMA Controller Channel Configuration D Register Channel 7"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "DMA0_D7,DMA Controller Channel Configuration D Register Channel 7"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x1D4))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x1D4))&0x10000000)==0x00)
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "DMA0_D7,DMA Controller Channel Configuration D Register Channel 7"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "DMA0_D7,DMA Controller Channel Configuration D Register Channel 7"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x1D4))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x1D4))&0x00001000)==0x00)
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "DMA0_D7,DMA Controller Channel Configuration D Register Channel 7"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "DMA0_D7,DMA Controller Channel Configuration D Register Channel 7"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "DMA0_D7,DMA Controller Channel Configuration D Register Channel 7"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "DMA0_D7,DMA Controller Channel Configuration D Register Channel 7"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x214-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x214))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x214))&0x10001000)==0x00)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DMA0_D8,DMA Controller Channel Configuration D Register Channel 8"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x214))&0x10001000)==0x1000)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DMA0_D8,DMA Controller Channel Configuration D Register Channel 8"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x214))&0x10001000)==0x10000000)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DMA0_D8,DMA Controller Channel Configuration D Register Channel 8"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DMA0_D8,DMA Controller Channel Configuration D Register Channel 8"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x214))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x214))&0x10000000)==0x00)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DMA0_D8,DMA Controller Channel Configuration D Register Channel 8"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DMA0_D8,DMA Controller Channel Configuration D Register Channel 8"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x214))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x214))&0x00001000)==0x00)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DMA0_D8,DMA Controller Channel Configuration D Register Channel 8"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DMA0_D8,DMA Controller Channel Configuration D Register Channel 8"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DMA0_D8,DMA Controller Channel Configuration D Register Channel 8"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DMA0_D8,DMA Controller Channel Configuration D Register Channel 8"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x254-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x254))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x254))&0x10001000)==0x00)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "DMA0_D9,DMA Controller Channel Configuration D Register Channel 9"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x254))&0x10001000)==0x1000)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "DMA0_D9,DMA Controller Channel Configuration D Register Channel 9"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x254))&0x10001000)==0x10000000)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "DMA0_D9,DMA Controller Channel Configuration D Register Channel 9"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "DMA0_D9,DMA Controller Channel Configuration D Register Channel 9"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x254))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x254))&0x10000000)==0x00)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "DMA0_D9,DMA Controller Channel Configuration D Register Channel 9"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "DMA0_D9,DMA Controller Channel Configuration D Register Channel 9"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x254))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x254))&0x00001000)==0x00)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "DMA0_D9,DMA Controller Channel Configuration D Register Channel 9"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "DMA0_D9,DMA Controller Channel Configuration D Register Channel 9"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "DMA0_D9,DMA Controller Channel Configuration D Register Channel 9"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "DMA0_D9,DMA Controller Channel Configuration D Register Channel 9"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x294-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x294))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x294))&0x10001000)==0x00)
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DMA0_D10,DMA Controller Channel Configuration D Register Channel 10"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x294))&0x10001000)==0x1000)
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DMA0_D10,DMA Controller Channel Configuration D Register Channel 10"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x294))&0x10001000)==0x10000000)
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DMA0_D10,DMA Controller Channel Configuration D Register Channel 10"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DMA0_D10,DMA Controller Channel Configuration D Register Channel 10"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x294))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x294))&0x10000000)==0x00)
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DMA0_D10,DMA Controller Channel Configuration D Register Channel 10"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DMA0_D10,DMA Controller Channel Configuration D Register Channel 10"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x294))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x294))&0x00001000)==0x00)
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DMA0_D10,DMA Controller Channel Configuration D Register Channel 10"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DMA0_D10,DMA Controller Channel Configuration D Register Channel 10"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DMA0_D10,DMA Controller Channel Configuration D Register Channel 10"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DMA0_D10,DMA Controller Channel Configuration D Register Channel 10"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x2D4-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x2D4))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x2D4))&0x10001000)==0x00)
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "DMA0_D11,DMA Controller Channel Configuration D Register Channel 11"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x2D4))&0x10001000)==0x1000)
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "DMA0_D11,DMA Controller Channel Configuration D Register Channel 11"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x2D4))&0x10001000)==0x10000000)
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "DMA0_D11,DMA Controller Channel Configuration D Register Channel 11"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "DMA0_D11,DMA Controller Channel Configuration D Register Channel 11"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x2D4))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x2D4))&0x10000000)==0x00)
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "DMA0_D11,DMA Controller Channel Configuration D Register Channel 11"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "DMA0_D11,DMA Controller Channel Configuration D Register Channel 11"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x2D4))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x2D4))&0x00001000)==0x00)
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "DMA0_D11,DMA Controller Channel Configuration D Register Channel 11"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "DMA0_D11,DMA Controller Channel Configuration D Register Channel 11"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "DMA0_D11,DMA Controller Channel Configuration D Register Channel 11"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "DMA0_D11,DMA Controller Channel Configuration D Register Channel 11"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x314-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x314))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x314))&0x10001000)==0x00)
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DMA0_D12,DMA Controller Channel Configuration D Register Channel 12"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x314))&0x10001000)==0x1000)
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DMA0_D12,DMA Controller Channel Configuration D Register Channel 12"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x314))&0x10001000)==0x10000000)
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DMA0_D12,DMA Controller Channel Configuration D Register Channel 12"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DMA0_D12,DMA Controller Channel Configuration D Register Channel 12"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x314))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x314))&0x10000000)==0x00)
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DMA0_D12,DMA Controller Channel Configuration D Register Channel 12"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DMA0_D12,DMA Controller Channel Configuration D Register Channel 12"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x314))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x314))&0x00001000)==0x00)
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DMA0_D12,DMA Controller Channel Configuration D Register Channel 12"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DMA0_D12,DMA Controller Channel Configuration D Register Channel 12"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DMA0_D12,DMA Controller Channel Configuration D Register Channel 12"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DMA0_D12,DMA Controller Channel Configuration D Register Channel 12"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x354-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x354))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x354))&0x10001000)==0x00)
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "DMA0_D13,DMA Controller Channel Configuration D Register Channel 13"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x354))&0x10001000)==0x1000)
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "DMA0_D13,DMA Controller Channel Configuration D Register Channel 13"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x354))&0x10001000)==0x10000000)
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "DMA0_D13,DMA Controller Channel Configuration D Register Channel 13"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "DMA0_D13,DMA Controller Channel Configuration D Register Channel 13"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x354))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x354))&0x10000000)==0x00)
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "DMA0_D13,DMA Controller Channel Configuration D Register Channel 13"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "DMA0_D13,DMA Controller Channel Configuration D Register Channel 13"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x354))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x354))&0x00001000)==0x00)
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "DMA0_D13,DMA Controller Channel Configuration D Register Channel 13"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "DMA0_D13,DMA Controller Channel Configuration D Register Channel 13"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "DMA0_D13,DMA Controller Channel Configuration D Register Channel 13"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "DMA0_D13,DMA Controller Channel Configuration D Register Channel 13"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x394-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x394))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x394))&0x10001000)==0x00)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "DMA0_D14,DMA Controller Channel Configuration D Register Channel 14"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x394))&0x10001000)==0x1000)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "DMA0_D14,DMA Controller Channel Configuration D Register Channel 14"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x394))&0x10001000)==0x10000000)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "DMA0_D14,DMA Controller Channel Configuration D Register Channel 14"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "DMA0_D14,DMA Controller Channel Configuration D Register Channel 14"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x394))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x394))&0x10000000)==0x00)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "DMA0_D14,DMA Controller Channel Configuration D Register Channel 14"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "DMA0_D14,DMA Controller Channel Configuration D Register Channel 14"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x394))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x394))&0x00001000)==0x00)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "DMA0_D14,DMA Controller Channel Configuration D Register Channel 14"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "DMA0_D14,DMA Controller Channel Configuration D Register Channel 14"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "DMA0_D14,DMA Controller Channel Configuration D Register Channel 14"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "DMA0_D14,DMA Controller Channel Configuration D Register Channel 14"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
if (((per.l(ad:0xB0700000+0x3D4-0x10))&0x30000000)==(0x10000000||0x00))
|
|
if (((per.l(ad:0xB0700000+0x3D4))&0x80008000)==0x00)
|
|
if (((per.l(ad:0xB0700000+0x3D4))&0x10001000)==0x00)
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "DMA0_D15,DMA Controller Channel Configuration D Register Channel 15"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x3D4))&0x10001000)==0x1000)
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "DMA0_D15,DMA Controller Channel Configuration D Register Channel 15"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
elif (((per.l(ad:0xB0700000+0x3D4))&0x10001000)==0x10000000)
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "DMA0_D15,DMA Controller Channel Configuration D Register Channel 15"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "DMA0_D15,DMA Controller Channel Configuration D Register Channel 15"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x3D4))&0x80008000)==0x8000)
|
|
if (((per.l(ad:0xB0700000+0x3D4))&0x10000000)==0x00)
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "DMA0_D15,DMA Controller Channel Configuration D Register Channel 15"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
else
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "DMA0_D15,DMA Controller Channel Configuration D Register Channel 15"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented"
|
|
bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
elif (((per.l(ad:0xB0700000+0x3D4))&0x80008000)==0x80000000)
|
|
if (((per.l(ad:0xB0700000+0x3D4))&0x00001000)==0x00)
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "DMA0_D15,DMA Controller Channel Configuration D Register Channel 15"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "DMA0_D15,DMA Controller Channel Configuration D Register Channel 15"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "DMA0_D15,DMA Controller Channel Configuration D Register Channel 15"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
else
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "DMA0_D15,DMA Controller Channel Configuration D Register Channel 15"
|
|
bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Fixed"
|
|
endif
|
|
tree.end
|
|
tree "Channel Configration Source Address Shadow Registers"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "DMA0_SASHDW0,DMA Controller Channel Configuration Source Address Shadow Register Channel 0"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "DMA0_SASHDW1,DMA Controller Channel Configuration Source Address Shadow Register Channel 1"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "DMA0_SASHDW2,DMA Controller Channel Configuration Source Address Shadow Register Channel 2"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "DMA0_SASHDW3,DMA Controller Channel Configuration Source Address Shadow Register Channel 3"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "DMA0_SASHDW4,DMA Controller Channel Configuration Source Address Shadow Register Channel 4"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "DMA0_SASHDW5,DMA Controller Channel Configuration Source Address Shadow Register Channel 5"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "DMA0_SASHDW6,DMA Controller Channel Configuration Source Address Shadow Register Channel 6"
|
|
rgroup.long 0x1D8++0x03
|
|
line.long 0x00 "DMA0_SASHDW7,DMA Controller Channel Configuration Source Address Shadow Register Channel 7"
|
|
rgroup.long 0x218++0x03
|
|
line.long 0x00 "DMA0_SASHDW8,DMA Controller Channel Configuration Source Address Shadow Register Channel 8"
|
|
rgroup.long 0x258++0x03
|
|
line.long 0x00 "DMA0_SASHDW9,DMA Controller Channel Configuration Source Address Shadow Register Channel 9"
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "DMA0_SASHDW10,DMA Controller Channel Configuration Source Address Shadow Register Channel 10"
|
|
rgroup.long 0x2D8++0x03
|
|
line.long 0x00 "DMA0_SASHDW11,DMA Controller Channel Configuration Source Address Shadow Register Channel 11"
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "DMA0_SASHDW12,DMA Controller Channel Configuration Source Address Shadow Register Channel 12"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "DMA0_SASHDW13,DMA Controller Channel Configuration Source Address Shadow Register Channel 13"
|
|
rgroup.long 0x398++0x03
|
|
line.long 0x00 "DMA0_SASHDW14,DMA Controller Channel Configuration Source Address Shadow Register Channel 14"
|
|
rgroup.long 0x3D8++0x03
|
|
line.long 0x00 "DMA0_SASHDW15,DMA Controller Channel Configuration Source Address Shadow Register Channel 15"
|
|
tree.end
|
|
tree "Channel Configuration Destination Address Shadow Registers"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DMA0_DASHDW0,DMA Controller Channel Configuration Destination Address Shadow Register Channel 0"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "DMA0_DASHDW1,DMA Controller Channel Configuration Destination Address Shadow Register Channel 1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "DMA0_DASHDW2,DMA Controller Channel Configuration Destination Address Shadow Register Channel 2"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "DMA0_DASHDW3,DMA Controller Channel Configuration Destination Address Shadow Register Channel 3"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "DMA0_DASHDW4,DMA Controller Channel Configuration Destination Address Shadow Register Channel 4"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "DMA0_DASHDW5,DMA Controller Channel Configuration Destination Address Shadow Register Channel 5"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "DMA0_DASHDW6,DMA Controller Channel Configuration Destination Address Shadow Register Channel 6"
|
|
rgroup.long 0x1DC++0x03
|
|
line.long 0x00 "DMA0_DASHDW7,DMA Controller Channel Configuration Destination Address Shadow Register Channel 7"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "DMA0_DASHDW8,DMA Controller Channel Configuration Destination Address Shadow Register Channel 8"
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "DMA0_DASHDW9,DMA Controller Channel Configuration Destination Address Shadow Register Channel 9"
|
|
rgroup.long 0x29C++0x03
|
|
line.long 0x00 "DMA0_DASHDW10,DMA Controller Channel Configuration Destination Address Shadow Register Channel 10"
|
|
rgroup.long 0x2DC++0x03
|
|
line.long 0x00 "DMA0_DASHDW11,DMA Controller Channel Configuration Destination Address Shadow Register Channel 11"
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "DMA0_DASHDW12,DMA Controller Channel Configuration Destination Address Shadow Register Channel 12"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "DMA0_DASHDW13,DMA Controller Channel Configuration Destination Address Shadow Register Channel 13"
|
|
rgroup.long 0x39C++0x03
|
|
line.long 0x00 "DMA0_DASHDW14,DMA Controller Channel Configuration Destination Address Shadow Register Channel 14"
|
|
rgroup.long 0x3DC++0x03
|
|
line.long 0x00 "DMA0_DASHDW15,DMA Controller Channel Configuration Destination Address Shadow Register Channel 15"
|
|
tree.end
|
|
tree "Client Matrix Internal Client Interface Configration Registers"
|
|
group.long 0x2020++0x3
|
|
line.long 0x00 "DMA0_CMICIC8,DMA Controller Client Matrix Internal Client Interface Configuration Register 8"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2024++0x3
|
|
line.long 0x00 "DMA0_CMICIC9,DMA Controller Client Matrix Internal Client Interface Configuration Register 9"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2028++0x3
|
|
line.long 0x00 "DMA0_CMICIC10,DMA Controller Client Matrix Internal Client Interface Configuration Register 10"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x202C++0x3
|
|
line.long 0x00 "DMA0_CMICIC11,DMA Controller Client Matrix Internal Client Interface Configuration Register 11"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2030++0x3
|
|
line.long 0x00 "DMA0_CMICIC12,DMA Controller Client Matrix Internal Client Interface Configuration Register 12"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2034++0x3
|
|
line.long 0x00 "DMA0_CMICIC13,DMA Controller Client Matrix Internal Client Interface Configuration Register 13"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2038++0x3
|
|
line.long 0x00 "DMA0_CMICIC14,DMA Controller Client Matrix Internal Client Interface Configuration Register 14"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x203C++0x3
|
|
line.long 0x00 "DMA0_CMICIC15,DMA Controller Client Matrix Internal Client Interface Configuration Register 15"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2040++0x3
|
|
line.long 0x00 "DMA0_CMICIC16,DMA Controller Client Matrix Internal Client Interface Configuration Register 16"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2044++0x3
|
|
line.long 0x00 "DMA0_CMICIC17,DMA Controller Client Matrix Internal Client Interface Configuration Register 17"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2048++0x3
|
|
line.long 0x00 "DMA0_CMICIC18,DMA Controller Client Matrix Internal Client Interface Configuration Register 18"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x204C++0x3
|
|
line.long 0x00 "DMA0_CMICIC19,DMA Controller Client Matrix Internal Client Interface Configuration Register 19"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2050++0x3
|
|
line.long 0x00 "DMA0_CMICIC20,DMA Controller Client Matrix Internal Client Interface Configuration Register 20"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2054++0x3
|
|
line.long 0x00 "DMA0_CMICIC21,DMA Controller Client Matrix Internal Client Interface Configuration Register 21"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2058++0x3
|
|
line.long 0x00 "DMA0_CMICIC22,DMA Controller Client Matrix Internal Client Interface Configuration Register 22"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x205C++0x3
|
|
line.long 0x00 "DMA0_CMICIC23,DMA Controller Client Matrix Internal Client Interface Configuration Register 23"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2060++0x3
|
|
line.long 0x00 "DMA0_CMICIC24,DMA Controller Client Matrix Internal Client Interface Configuration Register 24"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2064++0x3
|
|
line.long 0x00 "DMA0_CMICIC25,DMA Controller Client Matrix Internal Client Interface Configuration Register 25"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2068++0x3
|
|
line.long 0x00 "DMA0_CMICIC26,DMA Controller Client Matrix Internal Client Interface Configuration Register 26"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x206C++0x3
|
|
line.long 0x00 "DMA0_CMICIC27,DMA Controller Client Matrix Internal Client Interface Configuration Register 27"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2070++0x3
|
|
line.long 0x00 "DMA0_CMICIC28,DMA Controller Client Matrix Internal Client Interface Configuration Register 28"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2074++0x3
|
|
line.long 0x00 "DMA0_CMICIC29,DMA Controller Client Matrix Internal Client Interface Configuration Register 29"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2078++0x3
|
|
line.long 0x00 "DMA0_CMICIC30,DMA Controller Client Matrix Internal Client Interface Configuration Register 30"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x207C++0x3
|
|
line.long 0x00 "DMA0_CMICIC31,DMA Controller Client Matrix Internal Client Interface Configuration Register 31"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2080++0x3
|
|
line.long 0x00 "DMA0_CMICIC32,DMA Controller Client Matrix Internal Client Interface Configuration Register 32"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2084++0x3
|
|
line.long 0x00 "DMA0_CMICIC33,DMA Controller Client Matrix Internal Client Interface Configuration Register 33"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2088++0x3
|
|
line.long 0x00 "DMA0_CMICIC34,DMA Controller Client Matrix Internal Client Interface Configuration Register 34"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x208C++0x3
|
|
line.long 0x00 "DMA0_CMICIC35,DMA Controller Client Matrix Internal Client Interface Configuration Register 35"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2090++0x3
|
|
line.long 0x00 "DMA0_CMICIC36,DMA Controller Client Matrix Internal Client Interface Configuration Register 36"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2094++0x3
|
|
line.long 0x00 "DMA0_CMICIC37,DMA Controller Client Matrix Internal Client Interface Configuration Register 37"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2098++0x3
|
|
line.long 0x00 "DMA0_CMICIC38,DMA Controller Client Matrix Internal Client Interface Configuration Register 38"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x209C++0x3
|
|
line.long 0x00 "DMA0_CMICIC39,DMA Controller Client Matrix Internal Client Interface Configuration Register 39"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20A0++0x3
|
|
line.long 0x00 "DMA0_CMICIC40,DMA Controller Client Matrix Internal Client Interface Configuration Register 40"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20A4++0x3
|
|
line.long 0x00 "DMA0_CMICIC41,DMA Controller Client Matrix Internal Client Interface Configuration Register 41"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20A8++0x3
|
|
line.long 0x00 "DMA0_CMICIC42,DMA Controller Client Matrix Internal Client Interface Configuration Register 42"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20AC++0x3
|
|
line.long 0x00 "DMA0_CMICIC43,DMA Controller Client Matrix Internal Client Interface Configuration Register 43"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20B0++0x3
|
|
line.long 0x00 "DMA0_CMICIC44,DMA Controller Client Matrix Internal Client Interface Configuration Register 44"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20B4++0x3
|
|
line.long 0x00 "DMA0_CMICIC45,DMA Controller Client Matrix Internal Client Interface Configuration Register 45"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20B8++0x3
|
|
line.long 0x00 "DMA0_CMICIC46,DMA Controller Client Matrix Internal Client Interface Configuration Register 46"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20BC++0x3
|
|
line.long 0x00 "DMA0_CMICIC47,DMA Controller Client Matrix Internal Client Interface Configuration Register 47"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20C0++0x3
|
|
line.long 0x00 "DMA0_CMICIC48,DMA Controller Client Matrix Internal Client Interface Configuration Register 48"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20C4++0x3
|
|
line.long 0x00 "DMA0_CMICIC49,DMA Controller Client Matrix Internal Client Interface Configuration Register 49"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20C8++0x3
|
|
line.long 0x00 "DMA0_CMICIC50,DMA Controller Client Matrix Internal Client Interface Configuration Register 50"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20CC++0x3
|
|
line.long 0x00 "DMA0_CMICIC51,DMA Controller Client Matrix Internal Client Interface Configuration Register 51"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20D0++0x3
|
|
line.long 0x00 "DMA0_CMICIC52,DMA Controller Client Matrix Internal Client Interface Configuration Register 52"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20D4++0x3
|
|
line.long 0x00 "DMA0_CMICIC53,DMA Controller Client Matrix Internal Client Interface Configuration Register 53"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20D8++0x3
|
|
line.long 0x00 "DMA0_CMICIC54,DMA Controller Client Matrix Internal Client Interface Configuration Register 54"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20DC++0x3
|
|
line.long 0x00 "DMA0_CMICIC55,DMA Controller Client Matrix Internal Client Interface Configuration Register 55"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20E0++0x3
|
|
line.long 0x00 "DMA0_CMICIC56,DMA Controller Client Matrix Internal Client Interface Configuration Register 56"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20E4++0x3
|
|
line.long 0x00 "DMA0_CMICIC57,DMA Controller Client Matrix Internal Client Interface Configuration Register 57"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20E8++0x3
|
|
line.long 0x00 "DMA0_CMICIC58,DMA Controller Client Matrix Internal Client Interface Configuration Register 58"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20EC++0x3
|
|
line.long 0x00 "DMA0_CMICIC59,DMA Controller Client Matrix Internal Client Interface Configuration Register 59"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20F0++0x3
|
|
line.long 0x00 "DMA0_CMICIC60,DMA Controller Client Matrix Internal Client Interface Configuration Register 60"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20F4++0x3
|
|
line.long 0x00 "DMA0_CMICIC61,DMA Controller Client Matrix Internal Client Interface Configuration Register 61"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20F8++0x3
|
|
line.long 0x00 "DMA0_CMICIC62,DMA Controller Client Matrix Internal Client Interface Configuration Register 62"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20FC++0x3
|
|
line.long 0x00 "DMA0_CMICIC63,DMA Controller Client Matrix Internal Client Interface Configuration Register 63"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2100++0x3
|
|
line.long 0x00 "DMA0_CMICIC64,DMA Controller Client Matrix Internal Client Interface Configuration Register 64"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2104++0x3
|
|
line.long 0x00 "DMA0_CMICIC65,DMA Controller Client Matrix Internal Client Interface Configuration Register 65"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2108++0x3
|
|
line.long 0x00 "DMA0_CMICIC66,DMA Controller Client Matrix Internal Client Interface Configuration Register 66"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x210C++0x3
|
|
line.long 0x00 "DMA0_CMICIC67,DMA Controller Client Matrix Internal Client Interface Configuration Register 67"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2110++0x3
|
|
line.long 0x00 "DMA0_CMICIC68,DMA Controller Client Matrix Internal Client Interface Configuration Register 68"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2114++0x3
|
|
line.long 0x00 "DMA0_CMICIC69,DMA Controller Client Matrix Internal Client Interface Configuration Register 69"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2118++0x3
|
|
line.long 0x00 "DMA0_CMICIC70,DMA Controller Client Matrix Internal Client Interface Configuration Register 70"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x211C++0x3
|
|
line.long 0x00 "DMA0_CMICIC71,DMA Controller Client Matrix Internal Client Interface Configuration Register 71"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2120++0x3
|
|
line.long 0x00 "DMA0_CMICIC72,DMA Controller Client Matrix Internal Client Interface Configuration Register 72"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2124++0x3
|
|
line.long 0x00 "DMA0_CMICIC73,DMA Controller Client Matrix Internal Client Interface Configuration Register 73"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2128++0x3
|
|
line.long 0x00 "DMA0_CMICIC74,DMA Controller Client Matrix Internal Client Interface Configuration Register 74"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x212C++0x3
|
|
line.long 0x00 "DMA0_CMICIC75,DMA Controller Client Matrix Internal Client Interface Configuration Register 75"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2130++0x3
|
|
line.long 0x00 "DMA0_CMICIC76,DMA Controller Client Matrix Internal Client Interface Configuration Register 76"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2134++0x3
|
|
line.long 0x00 "DMA0_CMICIC77,DMA Controller Client Matrix Internal Client Interface Configuration Register 77"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2138++0x3
|
|
line.long 0x00 "DMA0_CMICIC78,DMA Controller Client Matrix Internal Client Interface Configuration Register 78"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x213C++0x3
|
|
line.long 0x00 "DMA0_CMICIC79,DMA Controller Client Matrix Internal Client Interface Configuration Register 79"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2140++0x3
|
|
line.long 0x00 "DMA0_CMICIC80,DMA Controller Client Matrix Internal Client Interface Configuration Register 80"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2144++0x3
|
|
line.long 0x00 "DMA0_CMICIC81,DMA Controller Client Matrix Internal Client Interface Configuration Register 81"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2148++0x3
|
|
line.long 0x00 "DMA0_CMICIC82,DMA Controller Client Matrix Internal Client Interface Configuration Register 82"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x214C++0x3
|
|
line.long 0x00 "DMA0_CMICIC83,DMA Controller Client Matrix Internal Client Interface Configuration Register 83"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2150++0x3
|
|
line.long 0x00 "DMA0_CMICIC84,DMA Controller Client Matrix Internal Client Interface Configuration Register 84"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2154++0x3
|
|
line.long 0x00 "DMA0_CMICIC85,DMA Controller Client Matrix Internal Client Interface Configuration Register 85"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2158++0x3
|
|
line.long 0x00 "DMA0_CMICIC86,DMA Controller Client Matrix Internal Client Interface Configuration Register 86"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x215C++0x3
|
|
line.long 0x00 "DMA0_CMICIC87,DMA Controller Client Matrix Internal Client Interface Configuration Register 87"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2160++0x3
|
|
line.long 0x00 "DMA0_CMICIC88,DMA Controller Client Matrix Internal Client Interface Configuration Register 88"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2164++0x3
|
|
line.long 0x00 "DMA0_CMICIC89,DMA Controller Client Matrix Internal Client Interface Configuration Register 89"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2168++0x3
|
|
line.long 0x00 "DMA0_CMICIC90,DMA Controller Client Matrix Internal Client Interface Configuration Register 90"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x216C++0x3
|
|
line.long 0x00 "DMA0_CMICIC91,DMA Controller Client Matrix Internal Client Interface Configuration Register 91"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2170++0x3
|
|
line.long 0x00 "DMA0_CMICIC92,DMA Controller Client Matrix Internal Client Interface Configuration Register 92"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2174++0x3
|
|
line.long 0x00 "DMA0_CMICIC93,DMA Controller Client Matrix Internal Client Interface Configuration Register 93"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2178++0x3
|
|
line.long 0x00 "DMA0_CMICIC94,DMA Controller Client Matrix Internal Client Interface Configuration Register 94"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x217C++0x3
|
|
line.long 0x00 "DMA0_CMICIC95,DMA Controller Client Matrix Internal Client Interface Configuration Register 95"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2180++0x3
|
|
line.long 0x00 "DMA0_CMICIC96,DMA Controller Client Matrix Internal Client Interface Configuration Register 96"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2184++0x3
|
|
line.long 0x00 "DMA0_CMICIC97,DMA Controller Client Matrix Internal Client Interface Configuration Register 97"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2188++0x3
|
|
line.long 0x00 "DMA0_CMICIC98,DMA Controller Client Matrix Internal Client Interface Configuration Register 98"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x218C++0x3
|
|
line.long 0x00 "DMA0_CMICIC99,DMA Controller Client Matrix Internal Client Interface Configuration Register 99"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2190++0x3
|
|
line.long 0x00 "DMA0_CMICIC100,DMA Controller Client Matrix Internal Client Interface Configuration Register 100"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2194++0x3
|
|
line.long 0x00 "DMA0_CMICIC101,DMA Controller Client Matrix Internal Client Interface Configuration Register 101"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2198++0x3
|
|
line.long 0x00 "DMA0_CMICIC102,DMA Controller Client Matrix Internal Client Interface Configuration Register 102"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x219C++0x3
|
|
line.long 0x00 "DMA0_CMICIC103,DMA Controller Client Matrix Internal Client Interface Configuration Register 103"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21A0++0x3
|
|
line.long 0x00 "DMA0_CMICIC104,DMA Controller Client Matrix Internal Client Interface Configuration Register 104"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21A4++0x3
|
|
line.long 0x00 "DMA0_CMICIC105,DMA Controller Client Matrix Internal Client Interface Configuration Register 105"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21A8++0x3
|
|
line.long 0x00 "DMA0_CMICIC106,DMA Controller Client Matrix Internal Client Interface Configuration Register 106"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21AC++0x3
|
|
line.long 0x00 "DMA0_CMICIC107,DMA Controller Client Matrix Internal Client Interface Configuration Register 107"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21B0++0x3
|
|
line.long 0x00 "DMA0_CMICIC108,DMA Controller Client Matrix Internal Client Interface Configuration Register 108"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21B4++0x3
|
|
line.long 0x00 "DMA0_CMICIC109,DMA Controller Client Matrix Internal Client Interface Configuration Register 109"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21B8++0x3
|
|
line.long 0x00 "DMA0_CMICIC110,DMA Controller Client Matrix Internal Client Interface Configuration Register 110"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21BC++0x3
|
|
line.long 0x00 "DMA0_CMICIC111,DMA Controller Client Matrix Internal Client Interface Configuration Register 111"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21C0++0x3
|
|
line.long 0x00 "DMA0_CMICIC112,DMA Controller Client Matrix Internal Client Interface Configuration Register 112"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21C4++0x3
|
|
line.long 0x00 "DMA0_CMICIC113,DMA Controller Client Matrix Internal Client Interface Configuration Register 113"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21C8++0x3
|
|
line.long 0x00 "DMA0_CMICIC114,DMA Controller Client Matrix Internal Client Interface Configuration Register 114"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21CC++0x3
|
|
line.long 0x00 "DMA0_CMICIC115,DMA Controller Client Matrix Internal Client Interface Configuration Register 115"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21D0++0x3
|
|
line.long 0x00 "DMA0_CMICIC116,DMA Controller Client Matrix Internal Client Interface Configuration Register 116"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21D4++0x3
|
|
line.long 0x00 "DMA0_CMICIC117,DMA Controller Client Matrix Internal Client Interface Configuration Register 117"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21D8++0x3
|
|
line.long 0x00 "DMA0_CMICIC118,DMA Controller Client Matrix Internal Client Interface Configuration Register 118"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21DC++0x3
|
|
line.long 0x00 "DMA0_CMICIC119,DMA Controller Client Matrix Internal Client Interface Configuration Register 119"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21E0++0x3
|
|
line.long 0x00 "DMA0_CMICIC120,DMA Controller Client Matrix Internal Client Interface Configuration Register 120"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21E4++0x3
|
|
line.long 0x00 "DMA0_CMICIC121,DMA Controller Client Matrix Internal Client Interface Configuration Register 121"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21E8++0x3
|
|
line.long 0x00 "DMA0_CMICIC122,DMA Controller Client Matrix Internal Client Interface Configuration Register 122"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21EC++0x3
|
|
line.long 0x00 "DMA0_CMICIC123,DMA Controller Client Matrix Internal Client Interface Configuration Register 123"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21F0++0x3
|
|
line.long 0x00 "DMA0_CMICIC124,DMA Controller Client Matrix Internal Client Interface Configuration Register 124"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21F4++0x3
|
|
line.long 0x00 "DMA0_CMICIC125,DMA Controller Client Matrix Internal Client Interface Configuration Register 125"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21F8++0x3
|
|
line.long 0x00 "DMA0_CMICIC126,DMA Controller Client Matrix Internal Client Interface Configuration Register 126"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21FC++0x3
|
|
line.long 0x00 "DMA0_CMICIC127,DMA Controller Client Matrix Internal Client Interface Configuration Register 127"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2200++0x3
|
|
line.long 0x00 "DMA0_CMICIC128,DMA Controller Client Matrix Internal Client Interface Configuration Register 128"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2204++0x3
|
|
line.long 0x00 "DMA0_CMICIC129,DMA Controller Client Matrix Internal Client Interface Configuration Register 129"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2208++0x3
|
|
line.long 0x00 "DMA0_CMICIC130,DMA Controller Client Matrix Internal Client Interface Configuration Register 130"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x220C++0x3
|
|
line.long 0x00 "DMA0_CMICIC131,DMA Controller Client Matrix Internal Client Interface Configuration Register 131"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2210++0x3
|
|
line.long 0x00 "DMA0_CMICIC132,DMA Controller Client Matrix Internal Client Interface Configuration Register 132"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2214++0x3
|
|
line.long 0x00 "DMA0_CMICIC133,DMA Controller Client Matrix Internal Client Interface Configuration Register 133"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2218++0x3
|
|
line.long 0x00 "DMA0_CMICIC134,DMA Controller Client Matrix Internal Client Interface Configuration Register 134"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x221C++0x3
|
|
line.long 0x00 "DMA0_CMICIC135,DMA Controller Client Matrix Internal Client Interface Configuration Register 135"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2220++0x3
|
|
line.long 0x00 "DMA0_CMICIC136,DMA Controller Client Matrix Internal Client Interface Configuration Register 136"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2224++0x3
|
|
line.long 0x00 "DMA0_CMICIC137,DMA Controller Client Matrix Internal Client Interface Configuration Register 137"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2228++0x3
|
|
line.long 0x00 "DMA0_CMICIC138,DMA Controller Client Matrix Internal Client Interface Configuration Register 138"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x222C++0x3
|
|
line.long 0x00 "DMA0_CMICIC139,DMA Controller Client Matrix Internal Client Interface Configuration Register 139"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2230++0x3
|
|
line.long 0x00 "DMA0_CMICIC140,DMA Controller Client Matrix Internal Client Interface Configuration Register 140"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2234++0x3
|
|
line.long 0x00 "DMA0_CMICIC141,DMA Controller Client Matrix Internal Client Interface Configuration Register 141"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2238++0x3
|
|
line.long 0x00 "DMA0_CMICIC142,DMA Controller Client Matrix Internal Client Interface Configuration Register 142"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
tree.end
|
|
tree "Client Matrix Channel Interface Configuration Registers"
|
|
group.long 0x2800++0x03
|
|
line.long 0x00 "DMA0_CMCHIC0,DMA Controller Client Matrix Internal Client Interface Configuration Register 0"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x2804++0x03
|
|
line.long 0x00 "DMA0_CMCHIC1,DMA Controller Client Matrix Internal Client Interface Configuration Register 1"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x2808++0x03
|
|
line.long 0x00 "DMA0_CMCHIC2,DMA Controller Client Matrix Internal Client Interface Configuration Register 2"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x280C++0x03
|
|
line.long 0x00 "DMA0_CMCHIC3,DMA Controller Client Matrix Internal Client Interface Configuration Register 3"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x2810++0x03
|
|
line.long 0x00 "DMA0_CMCHIC4,DMA Controller Client Matrix Internal Client Interface Configuration Register 4"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x2814++0x03
|
|
line.long 0x00 "DMA0_CMCHIC5,DMA Controller Client Matrix Internal Client Interface Configuration Register 5"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x2818++0x03
|
|
line.long 0x00 "DMA0_CMCHIC6,DMA Controller Client Matrix Internal Client Interface Configuration Register 6"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x281C++0x03
|
|
line.long 0x00 "DMA0_CMCHIC7,DMA Controller Client Matrix Internal Client Interface Configuration Register 7"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x2820++0x03
|
|
line.long 0x00 "DMA0_CMCHIC8,DMA Controller Client Matrix Internal Client Interface Configuration Register 8"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x2824++0x03
|
|
line.long 0x00 "DMA0_CMCHIC9,DMA Controller Client Matrix Internal Client Interface Configuration Register 9"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x2828++0x03
|
|
line.long 0x00 "DMA0_CMCHIC10,DMA Controller Client Matrix Internal Client Interface Configuration Register 10"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x282C++0x03
|
|
line.long 0x00 "DMA0_CMCHIC11,DMA Controller Client Matrix Internal Client Interface Configuration Register 11"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x2830++0x03
|
|
line.long 0x00 "DMA0_CMCHIC12,DMA Controller Client Matrix Internal Client Interface Configuration Register 12"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x2834++0x03
|
|
line.long 0x00 "DMA0_CMCHIC13,DMA Controller Client Matrix Internal Client Interface Configuration Register 13"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x2838++0x03
|
|
line.long 0x00 "DMA0_CMCHIC14,DMA Controller Client Matrix Internal Client Interface Configuration Register 14"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
group.long 0x283C++0x03
|
|
line.long 0x00 "DMA0_CMCHIC15,DMA Controller Client Matrix Internal Client Interface Configuration Register 15"
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "MPU (Memory Protection (AHB))"
|
|
base ad:0xB0710000
|
|
width 9.
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CTRL0,MPU AHB Control Register"
|
|
bitfld.long 0x00 24.--26. " AP ,Access permissions for background region (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MPUEN ,MPU enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged,Privileged"
|
|
newline
|
|
bitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled"
|
|
sif (!cpuis("S6J342*"))
|
|
bitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU stop feature" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " NMI ,NMI interrupt flag" "Not detected,Detected"
|
|
else
|
|
if ((per.l(ad:0xB0710000)&0x10000)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL0,MPU AHB Control Register"
|
|
bitfld.long 0x00 24.--26. " AP ,Access permissions for background region (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " MPUEN ,MPU enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged,Privileged"
|
|
newline
|
|
bitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled"
|
|
sif (!cpuis("S6J342*"))
|
|
bitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU stop feature" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "Not detected,Detected"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL0,MPU AHB Control Register"
|
|
rbitfld.long 0x00 24.--26. " AP ,Access permissions for background region (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " MPUEN ,MPU enable status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged,Privileged"
|
|
newline
|
|
rbitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled"
|
|
sif (!cpuis("S6J342*"))
|
|
bitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU stop feature" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "Not detected,Detected"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "NMIEN,MPU AHB NMI Enable Register"
|
|
bitfld.long 0x00 0. " NMIEN ,NMI interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "NMIEN,MPU AHB NMI Enable Register"
|
|
bitfld.long 0x00 0. " NMIEN ,NMI interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "MERRC,MPU AHB Memory Error Control Register"
|
|
bitfld.long 0x00 1. " HPROT ,AHB transfer privileged mode" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " HWRITE ,AHB transfer mode" "Not detected,Detected"
|
|
line.long 0x04 "MERRA,MPU AHB Memory Error Address Register"
|
|
sif (!cpuis("S6J342*"))
|
|
tree "Region 1"
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x10++0x0B
|
|
line.long 0x00 "CTRL1,MPU AHB Region 1 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR1,MPU AHB Start Address Register 1"
|
|
line.long 0x08 "EADDR1,MPU AHB End Address Register 1"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x10))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "CTRL1,MPU AHB Region 1 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR1,MPU AHB Start Address Register 1"
|
|
line.long 0x08 "EADDR1,MPU AHB End Address Register 1"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTRL1,MPU AHB Region 1 Control Register"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
rgroup.long (0x10+0x04)++0x07
|
|
line.long 0x00 "SADDR1,MPU AHB Start Address Register 1"
|
|
line.long 0x04 "EADDR1,MPU AHB End Address Register 1"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Region 2"
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "CTRL2,MPU AHB Region 2 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR2,MPU AHB Start Address Register 2"
|
|
line.long 0x08 "EADDR2,MPU AHB End Address Register 2"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x1C))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "CTRL2,MPU AHB Region 2 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR2,MPU AHB Start Address Register 2"
|
|
line.long 0x08 "EADDR2,MPU AHB End Address Register 2"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CTRL2,MPU AHB Region 2 Control Register"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
rgroup.long (0x1C+0x04)++0x07
|
|
line.long 0x00 "SADDR2,MPU AHB Start Address Register 2"
|
|
line.long 0x04 "EADDR2,MPU AHB End Address Register 2"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Region 3"
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x28++0x0B
|
|
line.long 0x00 "CTRL3,MPU AHB Region 3 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR3,MPU AHB Start Address Register 3"
|
|
line.long 0x08 "EADDR3,MPU AHB End Address Register 3"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x28))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "CTRL3,MPU AHB Region 3 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR3,MPU AHB Start Address Register 3"
|
|
line.long 0x08 "EADDR3,MPU AHB End Address Register 3"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CTRL3,MPU AHB Region 3 Control Register"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
rgroup.long (0x28+0x04)++0x07
|
|
line.long 0x00 "SADDR3,MPU AHB Start Address Register 3"
|
|
line.long 0x04 "EADDR3,MPU AHB End Address Register 3"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Region 4"
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x34++0x0B
|
|
line.long 0x00 "CTRL4,MPU AHB Region 4 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR4,MPU AHB Start Address Register 4"
|
|
line.long 0x08 "EADDR4,MPU AHB End Address Register 4"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x34))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x34++0x0B
|
|
line.long 0x00 "CTRL4,MPU AHB Region 4 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR4,MPU AHB Start Address Register 4"
|
|
line.long 0x08 "EADDR4,MPU AHB End Address Register 4"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTRL4,MPU AHB Region 4 Control Register"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
rgroup.long (0x34+0x04)++0x07
|
|
line.long 0x00 "SADDR4,MPU AHB Start Address Register 4"
|
|
line.long 0x04 "EADDR4,MPU AHB End Address Register 4"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Region 5"
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x40++0x0B
|
|
line.long 0x00 "CTRL5,MPU AHB Region 5 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR5,MPU AHB Start Address Register 5"
|
|
line.long 0x08 "EADDR5,MPU AHB End Address Register 5"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x40))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "CTRL5,MPU AHB Region 5 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR5,MPU AHB Start Address Register 5"
|
|
line.long 0x08 "EADDR5,MPU AHB End Address Register 5"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CTRL5,MPU AHB Region 5 Control Register"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
rgroup.long (0x40+0x04)++0x07
|
|
line.long 0x00 "SADDR5,MPU AHB Start Address Register 5"
|
|
line.long 0x04 "EADDR5,MPU AHB End Address Register 5"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Region 6"
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x4C++0x0B
|
|
line.long 0x00 "CTRL6,MPU AHB Region 6 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR6,MPU AHB Start Address Register 6"
|
|
line.long 0x08 "EADDR6,MPU AHB End Address Register 6"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x4C))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x4C++0x0B
|
|
line.long 0x00 "CTRL6,MPU AHB Region 6 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR6,MPU AHB Start Address Register 6"
|
|
line.long 0x08 "EADDR6,MPU AHB End Address Register 6"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CTRL6,MPU AHB Region 6 Control Register"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
rgroup.long (0x4C+0x04)++0x07
|
|
line.long 0x00 "SADDR6,MPU AHB Start Address Register 6"
|
|
line.long 0x04 "EADDR6,MPU AHB End Address Register 6"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Region 7"
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x58++0x0B
|
|
line.long 0x00 "CTRL7,MPU AHB Region 7 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR7,MPU AHB Start Address Register 7"
|
|
line.long 0x08 "EADDR7,MPU AHB End Address Register 7"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x58))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "CTRL7,MPU AHB Region 7 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR7,MPU AHB Start Address Register 7"
|
|
line.long 0x08 "EADDR7,MPU AHB End Address Register 7"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CTRL7,MPU AHB Region 7 Control Register"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
rgroup.long (0x58+0x04)++0x07
|
|
line.long 0x00 "SADDR7,MPU AHB Start Address Register 7"
|
|
line.long 0x04 "EADDR7,MPU AHB End Address Register 7"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Region 8"
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x64++0x0B
|
|
line.long 0x00 "CTRL8,MPU AHB Region 8 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR8,MPU AHB Start Address Register 8"
|
|
line.long 0x08 "EADDR8,MPU AHB End Address Register 8"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x64))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x64++0x0B
|
|
line.long 0x00 "CTRL8,MPU AHB Region 8 Control Register"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
line.long 0x04 "SADDR8,MPU AHB Start Address Register 8"
|
|
line.long 0x08 "EADDR8,MPU AHB End Address Register 8"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CTRL8,MPU AHB Region 8 Control Register"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write"
|
|
bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled"
|
|
rgroup.long (0x64+0x04)++0x07
|
|
line.long 0x00 "SADDR8,MPU AHB Start Address Register 8"
|
|
line.long 0x04 "EADDR8,MPU AHB End Address Register 8"
|
|
endif
|
|
endif
|
|
tree.end
|
|
else
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CTRL1,MPU16 AHB Region Control Register 1"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x10))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTRL1,MPU16 AHB Region Control Register 1"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTRL1,MPU16 AHB Region Control Register 1"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CTRL2,MPU16 AHB Region Control Register 2"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x1C))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CTRL2,MPU16 AHB Region Control Register 2"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CTRL2,MPU16 AHB Region Control Register 2"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "CTRL3,MPU16 AHB Region Control Register 3"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x28))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CTRL3,MPU16 AHB Region Control Register 3"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CTRL3,MPU16 AHB Region Control Register 3"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CTRL4,MPU16 AHB Region Control Register 4"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x34))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTRL4,MPU16 AHB Region Control Register 4"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTRL4,MPU16 AHB Region Control Register 4"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "CTRL5,MPU16 AHB Region Control Register 5"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x40))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CTRL5,MPU16 AHB Region Control Register 5"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CTRL5,MPU16 AHB Region Control Register 5"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "CTRL6,MPU16 AHB Region Control Register 6"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x4C))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CTRL6,MPU16 AHB Region Control Register 6"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CTRL6,MPU16 AHB Region Control Register 6"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "CTRL7,MPU16 AHB Region Control Register 7"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x58))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CTRL7,MPU16 AHB Region Control Register 7"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CTRL7,MPU16 AHB Region Control Register 7"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0xB0710000)&0x100)==0x100)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "CTRL8,MPU16 AHB Region Control Register 8"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x64))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CTRL8,MPU16 AHB Region Control Register 8"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CTRL8,MPU16 AHB Region Control Register 8"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xB0710000))&0x100)==0x100)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "CTRL9,MPU16 AHB Region Control Register 9"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x110))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CTRL9,MPU16 AHB Region Control Register 9"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CTRL9,MPU16 AHB Region Control Register 9"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xB0710000))&0x100)==0x100)
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "CTRL10,MPU16 AHB Region Control Register 10"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x11C))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CTRL10,MPU16 AHB Region Control Register 10"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CTRL10,MPU16 AHB Region Control Register 10"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xB0710000))&0x100)==0x100)
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "CTRL11,MPU16 AHB Region Control Register 11"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x128))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CTRL11,MPU16 AHB Region Control Register 11"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CTRL11,MPU16 AHB Region Control Register 11"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xB0710000))&0x100)==0x100)
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "CTRL12,MPU16 AHB Region Control Register 12"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x134))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "CTRL12,MPU16 AHB Region Control Register 12"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "CTRL12,MPU16 AHB Region Control Register 12"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xB0710000))&0x100)==0x100)
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "CTRL13,MPU16 AHB Region Control Register 13"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x140))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CTRL13,MPU16 AHB Region Control Register 13"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CTRL13,MPU16 AHB Region Control Register 13"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xB0710000))&0x100)==0x100)
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "CTRL14,MPU16 AHB Region Control Register 14"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x14C))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "CTRL14,MPU16 AHB Region Control Register 14"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "CTRL14,MPU16 AHB Region Control Register 14"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xB0710000))&0x100)==0x100)
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "CTRL15,MPU16 AHB Region Control Register 15"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x158))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "CTRL15,MPU16 AHB Region Control Register 15"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "CTRL15,MPU16 AHB Region Control Register 15"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xB0710000))&0x100)==0x100)
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "CTRL16,MPU16 AHB Region Control Register 16"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
if ((((per.l(ad:0xB0710000+0x164))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x10000)==0x0000))
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "CTRL16,MPU16 AHB Region Control Register 16"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "CTRL16,MPU16 AHB Region Control Register 16"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x14-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SADDR1,MPU16 AHB Start Address Register 1"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SADDR1,MPU16 AHB Start Address Register 1"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x20-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SADDR2,MPU16 AHB Start Address Register 2"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SADDR2,MPU16 AHB Start Address Register 2"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x2C-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SADDR3,MPU16 AHB Start Address Register 3"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SADDR3,MPU16 AHB Start Address Register 3"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x38-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SADDR4,MPU16 AHB Start Address Register 4"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SADDR4,MPU16 AHB Start Address Register 4"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x44-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SADDR5,MPU16 AHB Start Address Register 5"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SADDR5,MPU16 AHB Start Address Register 5"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x50-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SADDR6,MPU16 AHB Start Address Register 6"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "SADDR6,MPU16 AHB Start Address Register 6"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x5C-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SADDR7,MPU16 AHB Start Address Register 7"
|
|
else
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "SADDR7,MPU16 AHB Start Address Register 7"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x68-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SADDR8,MPU16 AHB Start Address Register 8"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "SADDR8,MPU16 AHB Start Address Register 8"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x114-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SADDR9,MPU16 AHB Start Address Register 9"
|
|
else
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "SADDR9,MPU16 AHB Start Address Register 9"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x120-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "SADDR10,MPU16 AHB Start Address Register 10"
|
|
else
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "SADDR10,MPU16 AHB Start Address Register 10"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x12C-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "SADDR11,MPU16 AHB Start Address Register 11"
|
|
else
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "SADDR11,MPU16 AHB Start Address Register 11"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x138-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "SADDR12,MPU16 AHB Start Address Register 12"
|
|
else
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "SADDR12,MPU16 AHB Start Address Register 12"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x144-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "SADDR13,MPU16 AHB Start Address Register 13"
|
|
else
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "SADDR13,MPU16 AHB Start Address Register 13"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x150-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "SADDR14,MPU16 AHB Start Address Register 14"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SADDR14,MPU16 AHB Start Address Register 14"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x15C-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "SADDR15,MPU16 AHB Start Address Register 15"
|
|
else
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "SADDR15,MPU16 AHB Start Address Register 15"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x168-0x04))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "SADDR16,MPU16 AHB Start Address Register 16"
|
|
else
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "SADDR16,MPU16 AHB Start Address Register 16"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x18-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "EADDR1,MPU16 AHB End Address Register 1"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "EADDR1,MPU16 AHB End Address Register 1"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x24-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "EADDR2,MPU16 AHB End Address Register 2"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "EADDR2,MPU16 AHB End Address Register 2"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x30-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "EADDR3,MPU16 AHB End Address Register 3"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "EADDR3,MPU16 AHB End Address Register 3"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x3C-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "EADDR4,MPU16 AHB End Address Register 4"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "EADDR4,MPU16 AHB End Address Register 4"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x48-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "EADDR5,MPU16 AHB End Address Register 5"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "EADDR5,MPU16 AHB End Address Register 5"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x54-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "EADDR6,MPU16 AHB End Address Register 6"
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "EADDR6,MPU16 AHB End Address Register 6"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x60-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "EADDR7,MPU16 AHB End Address Register 7"
|
|
else
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "EADDR7,MPU16 AHB End Address Register 7"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x6C-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "EADDR8,MPU16 AHB End Address Register 8"
|
|
else
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "EADDR8,MPU16 AHB End Address Register 8"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x118-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "EADDR9,MPU16 AHB End Address Register 9"
|
|
else
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "EADDR9,MPU16 AHB End Address Register 9"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x124-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "EADDR10,MPU16 AHB End Address Register 10"
|
|
else
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "EADDR10,MPU16 AHB End Address Register 10"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x130-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "EADDR11,MPU16 AHB End Address Register 11"
|
|
else
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "EADDR11,MPU16 AHB End Address Register 11"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x13C-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "EADDR12,MPU16 AHB End Address Register 12"
|
|
else
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "EADDR12,MPU16 AHB End Address Register 12"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x148-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "EADDR13,MPU16 AHB End Address Register 13"
|
|
else
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "EADDR13,MPU16 AHB End Address Register 13"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x154-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "EADDR14,MPU16 AHB End Address Register 14"
|
|
else
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "EADDR14,MPU16 AHB End Address Register 14"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x160-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "EADDR15,MPU16 AHB End Address Register 15"
|
|
else
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "EADDR15,MPU16 AHB End Address Register 15"
|
|
endif
|
|
if (((per.l(ad:0xB0710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB0710000+0x16C-0x08))&0x01)==0x00)||(((per.l(ad:0xB0710000))&0x100)==0x00)
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "EADDR16,MPU16 AHB End Address Register 16"
|
|
else
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "EADDR16,MPU16 AHB End Address Register 16"
|
|
endif
|
|
endif
|
|
newline
|
|
sif (!cpuis("S6J342*"))
|
|
wgroup.long 0x70++0x03
|
|
line.long 0x00 "UNLOCK,MPU AHB Unlock Register"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "UNLOCK,MPU AHB Unlock Register"
|
|
endif
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "MID,MPU AHB Module ID Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "TPU (Time Protection Unit)"
|
|
tree "Unit 0"
|
|
base ad:0xB0408000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UNLOCK,TPU Lock Release Register"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "LST,TPU Lock Status Register"
|
|
bitfld.long 0x00 0. " LST ,Lock status of the timing protection unit" "Unlocked,Locked"
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CFG,TPU Configuration Register"
|
|
bitfld.long 0x00 24. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " GLBPSE ,Global prescaler enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--21. " GLBPS ,Global prescaler division" "1/1,1/2,1/3,1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12,1/13,1/14,1/15,1/16,1/17,1/18,1/19,1/20,1/21,1/22,1/23,1/24,1/25,1/26,1/27,1/28,1/29,1/30,1/31,1/32,31/3,1/34,1/35,1/36,1/37,1/38,1/39,1/40,1/41,1/42,1/43,1/44,1/45,1/46,1/47,1/48,1/49,1/50,1/51,1/52,1/53,1/54,1/55,1/56,1/57,1/58,1/59,1/60,1/61,1/62,1/63,1/64"
|
|
bitfld.long 0x00 0. " INTE ,Timing protection unit interrupt enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CFG,TPU Configuration Register"
|
|
bitfld.long 0x00 24. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " GLBPSE ,Global prescaler enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--21. " GLBPS ,Global prescaler division" "1/1,1/2,1/3,1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12,1/13,1/14,1/15,1/16,1/17,1/18,1/19,1/20,1/21,1/22,1/23,1/24,1/25,1/26,1/27,1/28,1/29,1/30,1/31,1/32,31/3,1/34,1/35,1/36,1/37,1/38,1/39,1/40,1/41,1/42,1/43,1/44,1/45,1/46,1/47,1/48,1/49,1/50,1/51,1/52,1/53,1/54,1/55,1/56,1/57,1/58,1/59,1/60,1/61,1/62,1/63,1/64"
|
|
bitfld.long 0x00 0. " INTE ,Timing protection unit interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "TIR,TPU Timer Interrupt Request Register"
|
|
bitfld.long 0x00 7. " IR7 ,Timer 7 interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IR6 ,Timer 6 interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IR5 ,Timer 5 interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IR4 ,Timer 4 interrupt request" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " IR3 ,Timer 3 interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IR2 ,Timer 2 interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IR1 ,Timer 1 interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IR0 ,Timer 0 interrupt request" "No interrupt,Interrupt"
|
|
line.long 0x04 "TST,TPU Timer Status Register"
|
|
bitfld.long 0x04 7. " ST7 ,Timer 7 status" "Stopped,Running"
|
|
bitfld.long 0x04 6. " ST6 ,Timer 6 status" "Stopped,Running"
|
|
bitfld.long 0x04 5. " ST5 ,Timer 5 status" "Stopped,Running"
|
|
bitfld.long 0x04 4. " ST4 ,Timer 4 status" "Stopped,Running"
|
|
newline
|
|
bitfld.long 0x04 3. " ST3 ,Timer 3 status" "Stopped,Running"
|
|
bitfld.long 0x04 2. " ST2 ,Timer 2 status" "Stopped,Running"
|
|
bitfld.long 0x04 1. " ST1 ,Timer 1 status" "Stopped,Running"
|
|
bitfld.long 0x04 0. " ST0 ,Timer 0 status" "Stopped,Running"
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIE,TPU Timer Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " IE7 ,Timer 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IE6 ,Timer 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IE5 ,Timer 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IE4 ,Timer 4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " IE3 ,Timer 3 Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IE2 ,Timer 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE1 ,Timer 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IE0 ,Timer 0 interrupt enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TIE,TPU Timer Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " IE7 ,Timer 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IE6 ,Timer 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IE5 ,Timer 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IE4 ,Timer 4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " IE3 ,Timer 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IE2 ,Timer 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE1 ,Timer 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IE0 ,Timer 0 interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TCN00,TPU Timer 0 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TCN00,TPU Timer 0 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TCN01,TPU Timer 1 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TCN01,TPU Timer 1 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCN02,TPU Timer 2 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TCN02,TPU Timer 2 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TCN03,TPU Timer 3 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TCN03,TPU Timer 3 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TCN04,TPU Timer 4 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TCN04,TPU Timer 4 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TCN05,TPU Timer 5 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TCN05,TPU Timer 5 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TCN06,TPU Timer 6 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TCN06,TPU Timer 6 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TCN07,TPU Timer 7 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "TCN07,TPU Timer 7 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TCN10,TPU Timer 0 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "TCN10,TPU Timer 0 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TCN11,TPU Timer 1 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "TCN11,TPU Timer 1 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCN12,TPU Timer 2 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "TCN12,TPU Timer 2 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TCN13,TPU Timer 3 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TCN13,TPU Timer 3 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCN14,TPU Timer 4 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "TCN14,TPU Timer 4 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TCN15,TPU Timer 5 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "TCN15,TPU Timer 5 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TCN16,TPU Timer 6 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "TCN16,TPU Timer 6 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TCN17,TPU Timer 7 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "TCN17,TPU Timer 7 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TCC0,TPU Timer 0 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "TCC1,TPU Timer 1 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "TCC2,TPU Timer 2 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "TCC3,TPU Timer 3 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "TCC4,TPU Timer 4 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TCC5,TPU Timer 5 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "TCC6,TPU Timer 6 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "TCC7,TPU Timer 7 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 1"
|
|
base ad:0xB0409000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UNLOCK,TPU Lock Release Register"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "LST,TPU Lock Status Register"
|
|
bitfld.long 0x00 0. " LST ,Lock status of the timing protection unit" "Unlocked,Locked"
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CFG,TPU Configuration Register"
|
|
bitfld.long 0x00 24. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " GLBPSE ,Global prescaler enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--21. " GLBPS ,Global prescaler division" "1/1,1/2,1/3,1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12,1/13,1/14,1/15,1/16,1/17,1/18,1/19,1/20,1/21,1/22,1/23,1/24,1/25,1/26,1/27,1/28,1/29,1/30,1/31,1/32,31/3,1/34,1/35,1/36,1/37,1/38,1/39,1/40,1/41,1/42,1/43,1/44,1/45,1/46,1/47,1/48,1/49,1/50,1/51,1/52,1/53,1/54,1/55,1/56,1/57,1/58,1/59,1/60,1/61,1/62,1/63,1/64"
|
|
bitfld.long 0x00 0. " INTE ,Timing protection unit interrupt enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CFG,TPU Configuration Register"
|
|
bitfld.long 0x00 24. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " GLBPSE ,Global prescaler enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--21. " GLBPS ,Global prescaler division" "1/1,1/2,1/3,1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12,1/13,1/14,1/15,1/16,1/17,1/18,1/19,1/20,1/21,1/22,1/23,1/24,1/25,1/26,1/27,1/28,1/29,1/30,1/31,1/32,31/3,1/34,1/35,1/36,1/37,1/38,1/39,1/40,1/41,1/42,1/43,1/44,1/45,1/46,1/47,1/48,1/49,1/50,1/51,1/52,1/53,1/54,1/55,1/56,1/57,1/58,1/59,1/60,1/61,1/62,1/63,1/64"
|
|
bitfld.long 0x00 0. " INTE ,Timing protection unit interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "TIR,TPU Timer Interrupt Request Register"
|
|
bitfld.long 0x00 7. " IR7 ,Timer 7 interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IR6 ,Timer 6 interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IR5 ,Timer 5 interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IR4 ,Timer 4 interrupt request" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " IR3 ,Timer 3 interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IR2 ,Timer 2 interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IR1 ,Timer 1 interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IR0 ,Timer 0 interrupt request" "No interrupt,Interrupt"
|
|
line.long 0x04 "TST,TPU Timer Status Register"
|
|
bitfld.long 0x04 7. " ST7 ,Timer 7 status" "Stopped,Running"
|
|
bitfld.long 0x04 6. " ST6 ,Timer 6 status" "Stopped,Running"
|
|
bitfld.long 0x04 5. " ST5 ,Timer 5 status" "Stopped,Running"
|
|
bitfld.long 0x04 4. " ST4 ,Timer 4 status" "Stopped,Running"
|
|
newline
|
|
bitfld.long 0x04 3. " ST3 ,Timer 3 status" "Stopped,Running"
|
|
bitfld.long 0x04 2. " ST2 ,Timer 2 status" "Stopped,Running"
|
|
bitfld.long 0x04 1. " ST1 ,Timer 1 status" "Stopped,Running"
|
|
bitfld.long 0x04 0. " ST0 ,Timer 0 status" "Stopped,Running"
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIE,TPU Timer Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " IE7 ,Timer 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IE6 ,Timer 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IE5 ,Timer 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IE4 ,Timer 4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " IE3 ,Timer 3 Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IE2 ,Timer 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE1 ,Timer 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IE0 ,Timer 0 interrupt enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TIE,TPU Timer Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " IE7 ,Timer 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IE6 ,Timer 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IE5 ,Timer 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IE4 ,Timer 4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " IE3 ,Timer 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IE2 ,Timer 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE1 ,Timer 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IE0 ,Timer 0 interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TCN00,TPU Timer 0 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TCN00,TPU Timer 0 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TCN01,TPU Timer 1 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TCN01,TPU Timer 1 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCN02,TPU Timer 2 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TCN02,TPU Timer 2 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TCN03,TPU Timer 3 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TCN03,TPU Timer 3 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TCN04,TPU Timer 4 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TCN04,TPU Timer 4 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TCN05,TPU Timer 5 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TCN05,TPU Timer 5 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TCN06,TPU Timer 6 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TCN06,TPU Timer 6 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TCN07,TPU Timer 7 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "TCN07,TPU Timer 7 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart"
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TCN10,TPU Timer 0 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "TCN10,TPU Timer 0 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TCN11,TPU Timer 1 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "TCN11,TPU Timer 1 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCN12,TPU Timer 2 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "TCN12,TPU Timer 2 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TCN13,TPU Timer 3 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TCN13,TPU Timer 3 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCN14,TPU Timer 4 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "TCN14,TPU Timer 4 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TCN15,TPU Timer 5 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "TCN15,TPU Timer 5 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TCN16,TPU Timer 6 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "TCN16,TPU Timer 6 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
if (((per.l(ad:0xB0409000+0x04))&0x01)==0x00)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TCN17,TPU Timer 7 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
else
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "TCN17,TPU Timer 7 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16"
|
|
endif
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TCC0,TPU Timer 0 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "TCC1,TPU Timer 1 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "TCC2,TPU Timer 2 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "TCC3,TPU Timer 3 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "TCC4,TPU Timer 4 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TCC5,TPU Timer 5 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "TCC6,TPU Timer 6 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "TCC7,TPU Timer 7 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "IPCU (Inter-processor Communication)"
|
|
base ad:0xB0415000
|
|
width 16.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "ISTR0,IPCU CPU0 Interrupt Status Register"
|
|
bitfld.long 0x00 7. " IST7 ,Mailbox 7 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IST6 ,Mailbox 6 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IST5 ,Mailbox 5 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IST4 ,Mailbox 4 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IST3 ,Mailbox 3 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IST2 ,Mailbox 2 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IST1 ,Mailbox 1 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IST0 ,Mailbox 0 interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "ISTR1,IPCU CPU1 Interrupt Status Register"
|
|
bitfld.long 0x04 7. " IST7 ,Mailbox 7 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " IST6 ,Mailbox 6 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " IST5 ,Mailbox 5 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " IST4 ,Mailbox 4 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IST3 ,Mailbox 3 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " IST2 ,Mailbox 2 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " IST1 ,Mailbox 1 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " IST0 ,Mailbox 0 interrupt status" "No interrupt,Interrupt"
|
|
rgroup.long 0x80++0x07
|
|
line.long 0x00 "MAR0,IPCU CPU0 Mailbox Address Register"
|
|
bitfld.long 0x00 13. " ACK ,Acknowledgment indication" "Not ACK,ACK"
|
|
bitfld.long 0x00 12. " REQ ,Request indication" "Not a request,Request"
|
|
hexmask.long.word 0x00 0.--11. 1. " MAR ,Interrupt sending mailbox address indication bits"
|
|
line.long 0x04 "MAR1,IPCU CPU1 Mailbox Address Register"
|
|
bitfld.long 0x04 13. " ACK ,Acknowledgment indication bit" "Not ACK,ACK"
|
|
bitfld.long 0x04 12. " REQ ,Request indication bit" "Not a request,Request"
|
|
hexmask.long.word 0x04 0.--11. 1. " MAR ,Interrupt sending mailbox address indication bits"
|
|
tree "Mailbox 0"
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "MB0SRCR,IPCU Mailbox 0 Request Sender Setting Register"
|
|
bitfld.long 0x00 1. " SRC1 ,CPU1 request sender setting" "Not a sender,Sender"
|
|
bitfld.long 0x00 0. " SRC0 ,CPU0 request sender setting" "Not a sender,Sender"
|
|
line.long 0x04 "MB0MR,IPCU Mailbox 0 Operation Mode Setting Register"
|
|
bitfld.long 0x04 0.--2. " MODE ,Operation mode setting bits" "Manual,Manual,Auto ACK,Auto ACK,Auto clear,?..."
|
|
line.long 0x08 "MB0SR,IPCU Mailbox 0 Request Send Register"
|
|
bitfld.long 0x08 0. " SEND ,Request send" "Stopped,Started"
|
|
group.long (0x100+0x18)++0x03
|
|
line.long 0x00 "MB0DSTR,IPCU Mailbox 0 Request Recipient Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DSTST1 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DSTST0 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
group.long (0x100+0x28)++0x03
|
|
line.long 0x00 "MB0MSTR,IPCU Mailbox 0 Request Transmission Mask Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MSKS1 ,CPU1 request transmission mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MSKS0 ,CPU0 request transmission mask" "Not masked,Masked"
|
|
group.long (0x100+0x38)++0x07
|
|
line.long 0x00 "MB0ASTR,IPCU Mailbox 0 Acknowledgment Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACKST1 ,CPU1 acknowledgment" "No ACK,ACK"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACKST0 ,CPU0 acknowledgment" "No ACK,ACK"
|
|
line.long 0x04 "MB0ASRCR,IPCU Mailbox 0 Acknowledgment Sender Status Register"
|
|
bitfld.long 0x04 1. " ACKSRC1 ,CPU1 acknowledgment sender status" "Not a sender,Sender"
|
|
bitfld.long 0x04 0. " ACKSRC0 ,CPU0 acknowledgment sender status" "Not a sender,Sender"
|
|
group.long (0x100+0x40)++0x23
|
|
line.long 0x00 "MB0_DR0,IPCU Mailbox 0 Data Register 0"
|
|
line.long 0x04 "MB0_DR1,IPCU Mailbox 0 Data Register 1"
|
|
line.long 0x08 "MB0_DR2,IPCU Mailbox 0 Data Register 2"
|
|
line.long 0x0C "MB0_DR3,IPCU Mailbox 0 Data Register 3"
|
|
line.long 0x10 "MB0_DR4,IPCU Mailbox 0 Data Register 4"
|
|
line.long 0x14 "MB0_DR5,IPCU Mailbox 0 Data Register 5"
|
|
line.long 0x18 "MB0_DR6,IPCU Mailbox 0 Data Register 6"
|
|
line.long 0x1C "MB0_DR7,IPCU Mailbox 0 Data Register 7"
|
|
line.long 0x20 "MB0_DR8,IPCU Mailbox 0 Data Register 8"
|
|
tree.end
|
|
tree "Mailbox 1"
|
|
group.long 0x180++0x0B
|
|
line.long 0x00 "MB1SRCR,IPCU Mailbox 1 Request Sender Setting Register"
|
|
bitfld.long 0x00 1. " SRC1 ,CPU1 request sender setting" "Not a sender,Sender"
|
|
bitfld.long 0x00 0. " SRC0 ,CPU0 request sender setting" "Not a sender,Sender"
|
|
line.long 0x04 "MB1MR,IPCU Mailbox 1 Operation Mode Setting Register"
|
|
bitfld.long 0x04 0.--2. " MODE ,Operation mode setting bits" "Manual,Manual,Auto ACK,Auto ACK,Auto clear,?..."
|
|
line.long 0x08 "MB1SR,IPCU Mailbox 1 Request Send Register"
|
|
bitfld.long 0x08 0. " SEND ,Request send" "Stopped,Started"
|
|
group.long (0x180+0x18)++0x03
|
|
line.long 0x00 "MB1DSTR,IPCU Mailbox 1 Request Recipient Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DSTST1 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DSTST0 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
group.long (0x180+0x28)++0x03
|
|
line.long 0x00 "MB1MSTR,IPCU Mailbox 1 Request Transmission Mask Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MSKS1 ,CPU1 request transmission mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MSKS0 ,CPU0 request transmission mask" "Not masked,Masked"
|
|
group.long (0x180+0x38)++0x07
|
|
line.long 0x00 "MB1ASTR,IPCU Mailbox 1 Acknowledgment Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACKST1 ,CPU1 acknowledgment" "No ACK,ACK"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACKST0 ,CPU0 acknowledgment" "No ACK,ACK"
|
|
line.long 0x04 "MB1ASRCR,IPCU Mailbox 1 Acknowledgment Sender Status Register"
|
|
bitfld.long 0x04 1. " ACKSRC1 ,CPU1 acknowledgment sender status" "Not a sender,Sender"
|
|
bitfld.long 0x04 0. " ACKSRC0 ,CPU0 acknowledgment sender status" "Not a sender,Sender"
|
|
group.long (0x180+0x40)++0x23
|
|
line.long 0x00 "MB1_DR0,IPCU Mailbox 1 Data Register 0"
|
|
line.long 0x04 "MB1_DR1,IPCU Mailbox 1 Data Register 1"
|
|
line.long 0x08 "MB1_DR2,IPCU Mailbox 1 Data Register 2"
|
|
line.long 0x0C "MB1_DR3,IPCU Mailbox 1 Data Register 3"
|
|
line.long 0x10 "MB1_DR4,IPCU Mailbox 1 Data Register 4"
|
|
line.long 0x14 "MB1_DR5,IPCU Mailbox 1 Data Register 5"
|
|
line.long 0x18 "MB1_DR6,IPCU Mailbox 1 Data Register 6"
|
|
line.long 0x1C "MB1_DR7,IPCU Mailbox 1 Data Register 7"
|
|
line.long 0x20 "MB1_DR8,IPCU Mailbox 1 Data Register 8"
|
|
tree.end
|
|
tree "Mailbox 2"
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "MB2SRCR,IPCU Mailbox 2 Request Sender Setting Register"
|
|
bitfld.long 0x00 1. " SRC1 ,CPU1 request sender setting" "Not a sender,Sender"
|
|
bitfld.long 0x00 0. " SRC0 ,CPU0 request sender setting" "Not a sender,Sender"
|
|
line.long 0x04 "MB2MR,IPCU Mailbox 2 Operation Mode Setting Register"
|
|
bitfld.long 0x04 0.--2. " MODE ,Operation mode setting bits" "Manual,Manual,Auto ACK,Auto ACK,Auto clear,?..."
|
|
line.long 0x08 "MB2SR,IPCU Mailbox 2 Request Send Register"
|
|
bitfld.long 0x08 0. " SEND ,Request send" "Stopped,Started"
|
|
group.long (0x200+0x18)++0x03
|
|
line.long 0x00 "MB2DSTR,IPCU Mailbox 2 Request Recipient Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DSTST1 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DSTST0 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
group.long (0x200+0x28)++0x03
|
|
line.long 0x00 "MB2MSTR,IPCU Mailbox 2 Request Transmission Mask Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MSKS1 ,CPU1 request transmission mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MSKS0 ,CPU0 request transmission mask" "Not masked,Masked"
|
|
group.long (0x200+0x38)++0x07
|
|
line.long 0x00 "MB2ASTR,IPCU Mailbox 2 Acknowledgment Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACKST1 ,CPU1 acknowledgment" "No ACK,ACK"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACKST0 ,CPU0 acknowledgment" "No ACK,ACK"
|
|
line.long 0x04 "MB2ASRCR,IPCU Mailbox 2 Acknowledgment Sender Status Register"
|
|
bitfld.long 0x04 1. " ACKSRC1 ,CPU1 acknowledgment sender status" "Not a sender,Sender"
|
|
bitfld.long 0x04 0. " ACKSRC0 ,CPU0 acknowledgment sender status" "Not a sender,Sender"
|
|
group.long (0x200+0x40)++0x23
|
|
line.long 0x00 "MB2_DR0,IPCU Mailbox 2 Data Register 0"
|
|
line.long 0x04 "MB2_DR1,IPCU Mailbox 2 Data Register 1"
|
|
line.long 0x08 "MB2_DR2,IPCU Mailbox 2 Data Register 2"
|
|
line.long 0x0C "MB2_DR3,IPCU Mailbox 2 Data Register 3"
|
|
line.long 0x10 "MB2_DR4,IPCU Mailbox 2 Data Register 4"
|
|
line.long 0x14 "MB2_DR5,IPCU Mailbox 2 Data Register 5"
|
|
line.long 0x18 "MB2_DR6,IPCU Mailbox 2 Data Register 6"
|
|
line.long 0x1C "MB2_DR7,IPCU Mailbox 2 Data Register 7"
|
|
line.long 0x20 "MB2_DR8,IPCU Mailbox 2 Data Register 8"
|
|
tree.end
|
|
tree "Mailbox 3"
|
|
group.long 0x280++0x0B
|
|
line.long 0x00 "MB3SRCR,IPCU Mailbox 3 Request Sender Setting Register"
|
|
bitfld.long 0x00 1. " SRC1 ,CPU1 request sender setting" "Not a sender,Sender"
|
|
bitfld.long 0x00 0. " SRC0 ,CPU0 request sender setting" "Not a sender,Sender"
|
|
line.long 0x04 "MB3MR,IPCU Mailbox 3 Operation Mode Setting Register"
|
|
bitfld.long 0x04 0.--2. " MODE ,Operation mode setting bits" "Manual,Manual,Auto ACK,Auto ACK,Auto clear,?..."
|
|
line.long 0x08 "MB3SR,IPCU Mailbox 3 Request Send Register"
|
|
bitfld.long 0x08 0. " SEND ,Request send" "Stopped,Started"
|
|
group.long (0x280+0x18)++0x03
|
|
line.long 0x00 "MB3DSTR,IPCU Mailbox 3 Request Recipient Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DSTST1 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DSTST0 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
group.long (0x280+0x28)++0x03
|
|
line.long 0x00 "MB3MSTR,IPCU Mailbox 3 Request Transmission Mask Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MSKS1 ,CPU1 request transmission mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MSKS0 ,CPU0 request transmission mask" "Not masked,Masked"
|
|
group.long (0x280+0x38)++0x07
|
|
line.long 0x00 "MB3ASTR,IPCU Mailbox 3 Acknowledgment Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACKST1 ,CPU1 acknowledgment" "No ACK,ACK"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACKST0 ,CPU0 acknowledgment" "No ACK,ACK"
|
|
line.long 0x04 "MB3ASRCR,IPCU Mailbox 3 Acknowledgment Sender Status Register"
|
|
bitfld.long 0x04 1. " ACKSRC1 ,CPU1 acknowledgment sender status" "Not a sender,Sender"
|
|
bitfld.long 0x04 0. " ACKSRC0 ,CPU0 acknowledgment sender status" "Not a sender,Sender"
|
|
group.long (0x280+0x40)++0x23
|
|
line.long 0x00 "MB3_DR0,IPCU Mailbox 3 Data Register 0"
|
|
line.long 0x04 "MB3_DR1,IPCU Mailbox 3 Data Register 1"
|
|
line.long 0x08 "MB3_DR2,IPCU Mailbox 3 Data Register 2"
|
|
line.long 0x0C "MB3_DR3,IPCU Mailbox 3 Data Register 3"
|
|
line.long 0x10 "MB3_DR4,IPCU Mailbox 3 Data Register 4"
|
|
line.long 0x14 "MB3_DR5,IPCU Mailbox 3 Data Register 5"
|
|
line.long 0x18 "MB3_DR6,IPCU Mailbox 3 Data Register 6"
|
|
line.long 0x1C "MB3_DR7,IPCU Mailbox 3 Data Register 7"
|
|
line.long 0x20 "MB3_DR8,IPCU Mailbox 3 Data Register 8"
|
|
tree.end
|
|
tree "Mailbox 4"
|
|
group.long 0x300++0x0B
|
|
line.long 0x00 "MB4SRCR,IPCU Mailbox 4 Request Sender Setting Register"
|
|
bitfld.long 0x00 1. " SRC1 ,CPU1 request sender setting" "Not a sender,Sender"
|
|
bitfld.long 0x00 0. " SRC0 ,CPU0 request sender setting" "Not a sender,Sender"
|
|
line.long 0x04 "MB4MR,IPCU Mailbox 4 Operation Mode Setting Register"
|
|
bitfld.long 0x04 0.--2. " MODE ,Operation mode setting bits" "Manual,Manual,Auto ACK,Auto ACK,Auto clear,?..."
|
|
line.long 0x08 "MB4SR,IPCU Mailbox 4 Request Send Register"
|
|
bitfld.long 0x08 0. " SEND ,Request send" "Stopped,Started"
|
|
group.long (0x300+0x18)++0x03
|
|
line.long 0x00 "MB4DSTR,IPCU Mailbox 4 Request Recipient Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DSTST1 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DSTST0 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
group.long (0x300+0x28)++0x03
|
|
line.long 0x00 "MB4MSTR,IPCU Mailbox 4 Request Transmission Mask Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MSKS1 ,CPU1 request transmission mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MSKS0 ,CPU0 request transmission mask" "Not masked,Masked"
|
|
group.long (0x300+0x38)++0x07
|
|
line.long 0x00 "MB4ASTR,IPCU Mailbox 4 Acknowledgment Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACKST1 ,CPU1 acknowledgment" "No ACK,ACK"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACKST0 ,CPU0 acknowledgment" "No ACK,ACK"
|
|
line.long 0x04 "MB4ASRCR,IPCU Mailbox 4 Acknowledgment Sender Status Register"
|
|
bitfld.long 0x04 1. " ACKSRC1 ,CPU1 acknowledgment sender status" "Not a sender,Sender"
|
|
bitfld.long 0x04 0. " ACKSRC0 ,CPU0 acknowledgment sender status" "Not a sender,Sender"
|
|
group.long (0x300+0x40)++0x23
|
|
line.long 0x00 "MB4_DR0,IPCU Mailbox 4 Data Register 0"
|
|
line.long 0x04 "MB4_DR1,IPCU Mailbox 4 Data Register 1"
|
|
line.long 0x08 "MB4_DR2,IPCU Mailbox 4 Data Register 2"
|
|
line.long 0x0C "MB4_DR3,IPCU Mailbox 4 Data Register 3"
|
|
line.long 0x10 "MB4_DR4,IPCU Mailbox 4 Data Register 4"
|
|
line.long 0x14 "MB4_DR5,IPCU Mailbox 4 Data Register 5"
|
|
line.long 0x18 "MB4_DR6,IPCU Mailbox 4 Data Register 6"
|
|
line.long 0x1C "MB4_DR7,IPCU Mailbox 4 Data Register 7"
|
|
line.long 0x20 "MB4_DR8,IPCU Mailbox 4 Data Register 8"
|
|
tree.end
|
|
tree "Mailbox 5"
|
|
group.long 0x380++0x0B
|
|
line.long 0x00 "MB5SRCR,IPCU Mailbox 5 Request Sender Setting Register"
|
|
bitfld.long 0x00 1. " SRC1 ,CPU1 request sender setting" "Not a sender,Sender"
|
|
bitfld.long 0x00 0. " SRC0 ,CPU0 request sender setting" "Not a sender,Sender"
|
|
line.long 0x04 "MB5MR,IPCU Mailbox 5 Operation Mode Setting Register"
|
|
bitfld.long 0x04 0.--2. " MODE ,Operation mode setting bits" "Manual,Manual,Auto ACK,Auto ACK,Auto clear,?..."
|
|
line.long 0x08 "MB5SR,IPCU Mailbox 5 Request Send Register"
|
|
bitfld.long 0x08 0. " SEND ,Request send" "Stopped,Started"
|
|
group.long (0x380+0x18)++0x03
|
|
line.long 0x00 "MB5DSTR,IPCU Mailbox 5 Request Recipient Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DSTST1 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DSTST0 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
group.long (0x380+0x28)++0x03
|
|
line.long 0x00 "MB5MSTR,IPCU Mailbox 5 Request Transmission Mask Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MSKS1 ,CPU1 request transmission mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MSKS0 ,CPU0 request transmission mask" "Not masked,Masked"
|
|
group.long (0x380+0x38)++0x07
|
|
line.long 0x00 "MB5ASTR,IPCU Mailbox 5 Acknowledgment Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACKST1 ,CPU1 acknowledgment" "No ACK,ACK"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACKST0 ,CPU0 acknowledgment" "No ACK,ACK"
|
|
line.long 0x04 "MB5ASRCR,IPCU Mailbox 5 Acknowledgment Sender Status Register"
|
|
bitfld.long 0x04 1. " ACKSRC1 ,CPU1 acknowledgment sender status" "Not a sender,Sender"
|
|
bitfld.long 0x04 0. " ACKSRC0 ,CPU0 acknowledgment sender status" "Not a sender,Sender"
|
|
group.long (0x380+0x40)++0x23
|
|
line.long 0x00 "MB5_DR0,IPCU Mailbox 5 Data Register 0"
|
|
line.long 0x04 "MB5_DR1,IPCU Mailbox 5 Data Register 1"
|
|
line.long 0x08 "MB5_DR2,IPCU Mailbox 5 Data Register 2"
|
|
line.long 0x0C "MB5_DR3,IPCU Mailbox 5 Data Register 3"
|
|
line.long 0x10 "MB5_DR4,IPCU Mailbox 5 Data Register 4"
|
|
line.long 0x14 "MB5_DR5,IPCU Mailbox 5 Data Register 5"
|
|
line.long 0x18 "MB5_DR6,IPCU Mailbox 5 Data Register 6"
|
|
line.long 0x1C "MB5_DR7,IPCU Mailbox 5 Data Register 7"
|
|
line.long 0x20 "MB5_DR8,IPCU Mailbox 5 Data Register 8"
|
|
tree.end
|
|
tree "Mailbox 6"
|
|
group.long 0x400++0x0B
|
|
line.long 0x00 "MB6SRCR,IPCU Mailbox 6 Request Sender Setting Register"
|
|
bitfld.long 0x00 1. " SRC1 ,CPU1 request sender setting" "Not a sender,Sender"
|
|
bitfld.long 0x00 0. " SRC0 ,CPU0 request sender setting" "Not a sender,Sender"
|
|
line.long 0x04 "MB6MR,IPCU Mailbox 6 Operation Mode Setting Register"
|
|
bitfld.long 0x04 0.--2. " MODE ,Operation mode setting bits" "Manual,Manual,Auto ACK,Auto ACK,Auto clear,?..."
|
|
line.long 0x08 "MB6SR,IPCU Mailbox 6 Request Send Register"
|
|
bitfld.long 0x08 0. " SEND ,Request send" "Stopped,Started"
|
|
group.long (0x400+0x18)++0x03
|
|
line.long 0x00 "MB6DSTR,IPCU Mailbox 6 Request Recipient Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DSTST1 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DSTST0 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
group.long (0x400+0x28)++0x03
|
|
line.long 0x00 "MB6MSTR,IPCU Mailbox 6 Request Transmission Mask Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MSKS1 ,CPU1 request transmission mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MSKS0 ,CPU0 request transmission mask" "Not masked,Masked"
|
|
group.long (0x400+0x38)++0x07
|
|
line.long 0x00 "MB6ASTR,IPCU Mailbox 6 Acknowledgment Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACKST1 ,CPU1 acknowledgment" "No ACK,ACK"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACKST0 ,CPU0 acknowledgment" "No ACK,ACK"
|
|
line.long 0x04 "MB6ASRCR,IPCU Mailbox 6 Acknowledgment Sender Status Register"
|
|
bitfld.long 0x04 1. " ACKSRC1 ,CPU1 acknowledgment sender status" "Not a sender,Sender"
|
|
bitfld.long 0x04 0. " ACKSRC0 ,CPU0 acknowledgment sender status" "Not a sender,Sender"
|
|
group.long (0x400+0x40)++0x23
|
|
line.long 0x00 "MB6_DR0,IPCU Mailbox 6 Data Register 0"
|
|
line.long 0x04 "MB6_DR1,IPCU Mailbox 6 Data Register 1"
|
|
line.long 0x08 "MB6_DR2,IPCU Mailbox 6 Data Register 2"
|
|
line.long 0x0C "MB6_DR3,IPCU Mailbox 6 Data Register 3"
|
|
line.long 0x10 "MB6_DR4,IPCU Mailbox 6 Data Register 4"
|
|
line.long 0x14 "MB6_DR5,IPCU Mailbox 6 Data Register 5"
|
|
line.long 0x18 "MB6_DR6,IPCU Mailbox 6 Data Register 6"
|
|
line.long 0x1C "MB6_DR7,IPCU Mailbox 6 Data Register 7"
|
|
line.long 0x20 "MB6_DR8,IPCU Mailbox 6 Data Register 8"
|
|
tree.end
|
|
tree "Mailbox 7"
|
|
group.long 0x480++0x0B
|
|
line.long 0x00 "MB7SRCR,IPCU Mailbox 7 Request Sender Setting Register"
|
|
bitfld.long 0x00 1. " SRC1 ,CPU1 request sender setting" "Not a sender,Sender"
|
|
bitfld.long 0x00 0. " SRC0 ,CPU0 request sender setting" "Not a sender,Sender"
|
|
line.long 0x04 "MB7MR,IPCU Mailbox 7 Operation Mode Setting Register"
|
|
bitfld.long 0x04 0.--2. " MODE ,Operation mode setting bits" "Manual,Manual,Auto ACK,Auto ACK,Auto clear,?..."
|
|
line.long 0x08 "MB7SR,IPCU Mailbox 7 Request Send Register"
|
|
bitfld.long 0x08 0. " SEND ,Request send" "Stopped,Started"
|
|
group.long (0x480+0x18)++0x03
|
|
line.long 0x00 "MB7DSTR,IPCU Mailbox 7 Request Recipient Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DSTST1 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DSTST0 ,CPU1 request recipient set/clear" "Not a recipient,Recipient"
|
|
group.long (0x480+0x28)++0x03
|
|
line.long 0x00 "MB7MSTR,IPCU Mailbox 7 Request Transmission Mask Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MSKS1 ,CPU1 request transmission mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MSKS0 ,CPU0 request transmission mask" "Not masked,Masked"
|
|
group.long (0x480+0x38)++0x07
|
|
line.long 0x00 "MB7ASTR,IPCU Mailbox 7 Acknowledgment Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACKST1 ,CPU1 acknowledgment" "No ACK,ACK"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACKST0 ,CPU0 acknowledgment" "No ACK,ACK"
|
|
line.long 0x04 "MB7ASRCR,IPCU Mailbox 7 Acknowledgment Sender Status Register"
|
|
bitfld.long 0x04 1. " ACKSRC1 ,CPU1 acknowledgment sender status" "Not a sender,Sender"
|
|
bitfld.long 0x04 0. " ACKSRC0 ,CPU0 acknowledgment sender status" "Not a sender,Sender"
|
|
group.long (0x480+0x40)++0x23
|
|
line.long 0x00 "MB7_DR0,IPCU Mailbox 7 Data Register 0"
|
|
line.long 0x04 "MB7_DR1,IPCU Mailbox 7 Data Register 1"
|
|
line.long 0x08 "MB7_DR2,IPCU Mailbox 7 Data Register 2"
|
|
line.long 0x0C "MB7_DR3,IPCU Mailbox 7 Data Register 3"
|
|
line.long 0x10 "MB7_DR4,IPCU Mailbox 7 Data Register 4"
|
|
line.long 0x14 "MB7_DR5,IPCU Mailbox 7 Data Register 5"
|
|
line.long 0x18 "MB7_DR6,IPCU Mailbox 7 Data Register 6"
|
|
line.long 0x1C "MB7_DR7,IPCU Mailbox 7 Data Register 7"
|
|
line.long 0x20 "MB7_DR8,IPCU Mailbox 7 Data Register 8"
|
|
tree.end
|
|
textline " "
|
|
rgroup.long 0x900++0x03
|
|
line.long 0x00 "MBSTR,IPCU Mailbox Status Register"
|
|
bitfld.long 0x00 7. " MBST7 ,Mailbox 7 status " "Available,Used"
|
|
bitfld.long 0x00 6. " MBST6 ,Mailbox 6 status " "Available,Used"
|
|
bitfld.long 0x00 5. " MBST5 ,Mailbox 5 status " "Available,Used"
|
|
bitfld.long 0x00 4. " MBST4 ,Mailbox 4 status " "Available,Used"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MBST3 ,Mailbox 3 status " "Available,Used"
|
|
bitfld.long 0x00 2. " MBST2 ,Mailbox 2 status " "Available,Used"
|
|
bitfld.long 0x00 1. " MBST1 ,Mailbox 1 status " "Available,Used"
|
|
bitfld.long 0x00 0. " MBST0 ,Mailbox 0 status " "Available,Used"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "I/O port"
|
|
tree "GPIO (General Purpose I/O Port)"
|
|
base ad:0xB0738000
|
|
width 16.
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "DDR0_SET/CLR,Data Direction Set/Clear Register"
|
|
sif cpuis("MB9DF56?LAE")||cpuis("MB9DF56?LGE")
|
|
setclrfld.long 0x00 26. -0x1FC 26. -0x1F8 26. " DD26 ,Port 0 pin 26 data direction" "Input,Output"
|
|
setclrfld.long 0x00 16. -0x1FC 16. -0x1F8 16. " DD16 ,Port 0 pin 16 data direction" "Input,Output"
|
|
elif cpuis("MB9DF56?MAE")||cpuis("MB9DF56?MGE")
|
|
setclrfld.long 0x00 31. -0x1FC 31. -0x1F8 31. " DD31 ,Port 0 pin 31 data direction" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x1FC 30. -0x1F8 30. " DD30 ,Port 0 pin 30 data direction" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x1FC 26. -0x1F8 26. " DD26 ,Port 0 pin 26 data direction" "Input,Output"
|
|
setclrfld.long 0x00 16. -0x1FC 16. -0x1F8 16. " DD16 ,Port 0 pin 16 data direction" "Input,Output"
|
|
else
|
|
sif cpuis("MB9DF56?LLE")||cpuis("MB9DF56?LQE")
|
|
setclrfld.long 0x00 29. -0x1FC 29. -0x1F8 29. " DD29 ,Port 0 pin 29 data direction" "Input,Output"
|
|
setclrfld.long 0x00 28. -0x1FC 28. -0x1F8 28. " DD28 ,Port 0 pin 28 data direction" "Input,Output"
|
|
else
|
|
setclrfld.long 0x00 31. -0x1FC 31. -0x1F8 31. " DD31 ,Port 0 pin 31 data direction" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x1FC 30. -0x1F8 30. " DD30 ,Port 0 pin 30 data direction" "Input,Output"
|
|
setclrfld.long 0x00 29. -0x1FC 29. -0x1F8 29. " DD29 ,Port 0 pin 29 data direction" "Input,Output"
|
|
setclrfld.long 0x00 28. -0x1FC 28. -0x1F8 28. " DD28 ,Port 0 pin 28 data direction" "Input,Output"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x1FC 27. -0x1F8 27. " DD27 ,Port 0 pin 27 data direction" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x1FC 26. -0x1F8 26. " DD26 ,Port 0 pin 26 data direction" "Input,Output"
|
|
setclrfld.long 0x00 25. -0x1FC 25. -0x1F8 25. " DD25 ,Port 0 pin 25 data direction" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x1FC 24. -0x1F8 24. " DD24 ,Port 0 pin 24 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x1FC 23. -0x1F8 23. " DD23 ,Port 0 pin 23 data direction" "Input,Output"
|
|
setclrfld.long 0x00 22. -0x1FC 22. -0x1F8 22. " DD22 ,Port 0 pin 22 data direction" "Input,Output"
|
|
setclrfld.long 0x00 21. -0x1FC 21. -0x1F8 21. " DD21 ,Port 0 pin 21 data direction" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x1FC 20. -0x1F8 20. " DD20 ,Port 0 pin 20 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x1FC 19. -0x1F8 19. " DD19 ,Port 0 pin 19 data direction" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x1FC 18. -0x1F8 18. " DD18 ,Port 0 pin 18 data direction" "Input,Output"
|
|
setclrfld.long 0x00 17. -0x1FC 17. -0x1F8 17. " DD17 ,Port 0 pin 17 data direction" "Input,Output"
|
|
setclrfld.long 0x00 16. -0x1FC 16. -0x1F8 16. " DD16 ,Port 0 pin 16 data direction" "Input,Output"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x1FC 15. -0x1F8 15. " DD15 ,Port 0 pin 15 data direction" "Input,Output"
|
|
setclrfld.long 0x00 14. -0x1FC 14. -0x1F8 14. " DD14 ,Port 0 pin 14 data direction" "Input,Output"
|
|
setclrfld.long 0x00 13. -0x1FC 13. -0x1F8 13. " DD13 ,Port 0 pin 13 data direction" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x1FC 12. -0x1F8 12. " DD12 ,Port 0 pin 12 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x1FC 11. -0x1F8 11. " DD11 ,Port 0 pin 11 data direction" "Input,Output"
|
|
setclrfld.long 0x00 10. -0x1FC 10. -0x1F8 10. " DD10 ,Port 0 pin 10 data direction" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x1FC 9. -0x1F8 9. " DD9 ,Port 0 pin 9 data direction" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x1FC 8. -0x1F8 8. " DD8 ,Port 0 pin 8 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x1FC 7. -0x1F8 7. " DD7 ,Port 0 pin 7 data direction" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x1FC 6. -0x1F8 6. " DD6 ,Port 0 pin 6 data direction" "Input,Output"
|
|
setclrfld.long 0x00 5. -0x1FC 5. -0x1F8 5. " DD5 ,Port 0 pin 5 data direction" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x1FC 4. -0x1F8 4. " DD4 ,Port 0 pin 4 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x1FC 3. -0x1F8 3. " DD3 ,Port 0 pin 3 data direction" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x1FC 2. -0x1F8 2. " DD2 ,Port 0 pin 2 data direction" "Input,Output"
|
|
setclrfld.long 0x00 1. -0x1FC 1. -0x1F8 1. " DD1 ,Port 0 pin 1 data direction" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x1FC 0. -0x1F8 0. " DD0 ,Port 0 pin 0 data direction" "Input,Output"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "DDR1_SET/CLR,Data Direction Set/Clear Register"
|
|
sif cpuis("MB9DF56?MAE")||cpuis("MB9DF56?MGE")
|
|
setclrfld.long 0x00 31. -0x1F4 31. -0x1F0 31. " DD31 ,Port 1 pin 31 data direction" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x1F4 26. -0x1F0 26. " DD26 ,Port 1 pin 26 data direction" "Input,Output"
|
|
setclrfld.long 0x00 16. -0x1F4 16. -0x1F0 16. " DD16 ,Port 1 pin 16 data direction" "Input,Output"
|
|
elif cpuis("MB9DF56?LAE")||cpuis("MB9DF56?LGE")
|
|
setclrfld.long 0x00 26. -0x1F4 26. -0x1F0 26. " DD26 ,Port 1 pin 26 data direction" "Input,Output"
|
|
setclrfld.long 0x00 16. -0x1F4 16. -0x1F0 16. " DD16 ,Port 1 pin 16 data direction" "Input,Output"
|
|
else
|
|
sif cpuis("MB9DF56?LLE")||cpuis("MB9DF56?LQE")
|
|
setclrfld.long 0x00 29. -0x1F4 29. -0x1F0 29. " DD29 ,Port 1 pin 29 data direction" "Input,Output"
|
|
setclrfld.long 0x00 28. -0x1F4 28. -0x1F0 28. " DD28 ,Port 1 pin 28 data direction" "Input,Output"
|
|
else
|
|
setclrfld.long 0x00 31. -0x1F4 31. -0x1F0 31. " DD31 ,Port 1 pin 31 data direction" "Input,Output"
|
|
setclrfld.long 0x00 29. -0x1F4 29. -0x1F0 29. " DD29 ,Port 1 pin 29 data direction" "Input,Output"
|
|
setclrfld.long 0x00 28. -0x1F4 28. -0x1F0 28. " DD28 ,Port 1 pin 28 data direction" "Input,Output"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x1F4 27. -0x1F0 27. " DD27 ,Port 1 pin 27 data direction" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x1F4 26. -0x1F0 26. " DD26 ,Port 1 pin 26 data direction" "Input,Output"
|
|
setclrfld.long 0x00 25. -0x1F4 25. -0x1F0 25. " DD25 ,Port 1 pin 25 data direction" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x1F4 24. -0x1F0 24. " DD24 ,Port 1 pin 24 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x1F4 23. -0x1F0 23. " DD23 ,Port 1 pin 23 data direction" "Input,Output"
|
|
setclrfld.long 0x00 22. -0x1F4 22. -0x1F0 22. " DD22 ,Port 1 pin 22 data direction" "Input,Output"
|
|
setclrfld.long 0x00 21. -0x1F4 21. -0x1F0 21. " DD21 ,Port 1 pin 21 data direction" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x1F4 20. -0x1F0 20. " DD20 ,Port 1 pin 20 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x1F4 19. -0x1F0 19. " DD19 ,Port 1 pin 19 data direction" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x1F4 18. -0x1F0 18. " DD18 ,Port 1 pin 18 data direction" "Input,Output"
|
|
setclrfld.long 0x00 17. -0x1F4 17. -0x1F0 17. " DD17 ,Port 1 pin 17 data direction" "Input,Output"
|
|
setclrfld.long 0x00 16. -0x1F4 16. -0x1F0 16. " DD16 ,Port 1 pin 16 data direction" "Input,Output"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x1F4 15. -0x1F0 15. " DD15 ,Port 1 pin 15 data direction" "Input,Output"
|
|
setclrfld.long 0x00 14. -0x1F4 14. -0x1F0 14. " DD14 ,Port 1 pin 14 data direction" "Input,Output"
|
|
setclrfld.long 0x00 13. -0x1F4 13. -0x1F0 13. " DD13 ,Port 1 pin 13 data direction" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x1F4 12. -0x1F0 12. " DD12 ,Port 1 pin 12 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x1F4 11. -0x1F0 11. " DD11 ,Port 1 pin 11 data direction" "Input,Output"
|
|
setclrfld.long 0x00 10. -0x1F4 10. -0x1F0 10. " DD10 ,Port 1 pin 10 data direction" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x1F4 9. -0x1F0 9. " DD9 ,Port 1 pin 9 data direction" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x1F4 8. -0x1F0 8. " DD8 ,Port 1 pin 8 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x1F4 7. -0x1F0 7. " DD7 ,Port 1 pin 7 data direction" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x1F4 6. -0x1F0 6. " DD6 ,Port 1 pin 6 data direction" "Input,Output"
|
|
setclrfld.long 0x00 5. -0x1F4 5. -0x1F0 5. " DD5 ,Port 1 pin 5 data direction" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x1F4 4. -0x1F0 4. " DD4 ,Port 1 pin 4 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x1F4 3. -0x1F0 3. " DD3 ,Port 1 pin 3 data direction" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x1F4 2. -0x1F0 2. " DD2 ,Port 1 pin 2 data direction" "Input,Output"
|
|
setclrfld.long 0x00 1. -0x1F4 1. -0x1F0 1. " DD1 ,Port 1 pin 1 data direction" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x1F4 0. -0x1F0 0. " DD0 ,Port 1 pin 0 data direction" "Input,Output"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DDR2_SET/CLR,Data Direction Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x1EC 31. -0x1E8 31. " DD31 ,Port 2 pin 31 data direction" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x1EC 30. -0x1E8 30. " DD30 ,Port 2 pin 30 data direction" "Input,Output"
|
|
setclrfld.long 0x00 29. -0x1EC 29. -0x1E8 29. " DD29 ,Port 2 pin 29 data direction" "Input,Output"
|
|
setclrfld.long 0x00 28. -0x1EC 28. -0x1E8 28. " DD28 ,Port 2 pin 28 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x1EC 27. -0x1E8 27. " DD27 ,Port 2 pin 27 data direction" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x1EC 26. -0x1E8 26. " DD26 ,Port 2 pin 26 data direction" "Input,Output"
|
|
setclrfld.long 0x00 25. -0x1EC 25. -0x1E8 25. " DD25 ,Port 2 pin 25 data direction" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x1EC 24. -0x1E8 24. " DD24 ,Port 2 pin 24 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x1EC 23. -0x1E8 23. " DD23 ,Port 2 pin 23 data direction" "Input,Output"
|
|
setclrfld.long 0x00 22. -0x1EC 22. -0x1E8 22. " DD22 ,Port 2 pin 22 data direction" "Input,Output"
|
|
setclrfld.long 0x00 21. -0x1EC 21. -0x1E8 21. " DD21 ,Port 2 pin 21 data direction" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x1EC 20. -0x1E8 20. " DD20 ,Port 2 pin 20 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x1EC 19. -0x1E8 19. " DD19 ,Port 2 pin 19 data direction" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x1EC 18. -0x1E8 18. " DD18 ,Port 2 pin 18 data direction" "Input,Output"
|
|
setclrfld.long 0x00 17. -0x1EC 17. -0x1E8 17. " DD17 ,Port 2 pin 17 data direction" "Input,Output"
|
|
setclrfld.long 0x00 16. -0x1EC 16. -0x1E8 16. " DD16 ,Port 2 pin 16 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x1EC 15. -0x1E8 15. " DD15 ,Port 2 pin 15 data direction" "Input,Output"
|
|
setclrfld.long 0x00 14. -0x1EC 14. -0x1E8 14. " DD14 ,Port 2 pin 13 data direction" "Input,Output"
|
|
setclrfld.long 0x00 13. -0x1EC 13. -0x1E8 13. " DD13 ,Port 2 pin 13 data direction" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x1EC 12. -0x1E8 12. " DD12 ,Port 2 pin 12 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x1EC 11. -0x1E8 11. " DD11 ,Port 2 pin 11 data direction" "Input,Output"
|
|
setclrfld.long 0x00 10. -0x1EC 10. -0x1E8 10. " DD10 ,Port 2 pin 10 data direction" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x1EC 9. -0x1E8 9. " DD9 ,Port 2 pin 9 data direction" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x1EC 8. -0x1E8 8. " DD8 ,Port 2 pin 8 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x1EC 7. -0x1E8 7. " DD7 ,Port 2 pin 7 data direction" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x1EC 6. -0x1E8 6. " DD6 ,Port 2 pin 6 data direction" "Input,Output"
|
|
setclrfld.long 0x00 5. -0x1EC 5. -0x1E8 5. " DD5 ,Port 2 pin 5 data direction" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x1EC 4. -0x1E8 4. " DD4 ,Port 2 pin 4 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x1EC 3. -0x1E8 3. " DD3 ,Port 2 pin 3 data direction" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x1EC 2. -0x1E8 2. " DD2 ,Port 2 pin 2 data direction" "Input,Output"
|
|
setclrfld.long 0x00 1. -0x1EC 1. -0x1E8 1. " DD1 ,Port 2 pin 1 data direction" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x1EC 0. -0x1E8 0. " DD0 ,Port 2 pin 0 data direction" "Input,Output"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "DDR3_SET/CLR,Data Direction Set/Clear Register"
|
|
setclrfld.long 0x00 30. -0x1E4 30. -0x1E0 30. " DD30 ,Port 3 pin 30 data direction" "Input,Output"
|
|
setclrfld.long 0x00 29. -0x1E4 29. -0x1E0 29. " DD29 ,Port 3 pin 29 data direction" "Input,Output"
|
|
setclrfld.long 0x00 28. -0x1E4 28. -0x1E0 28. " DD28 ,Port 3 pin 28 data direction" "Input,Output"
|
|
setclrfld.long 0x00 27. -0x1E4 27. -0x1E0 27. " DD27 ,Port 3 pin 27 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x1E4 26. -0x1E0 26. " DD26 ,Port 3 pin 26 data direction" "Input,Output"
|
|
setclrfld.long 0x00 25. -0x1E4 25. -0x1E0 25. " DD25 ,Port 3 pin 25 data direction" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x1E4 24. -0x1E0 24. " DD24 ,Port 3 pin 24 data direction" "Input,Output"
|
|
setclrfld.long 0x00 23. -0x1E4 23. -0x1E0 23. " DD23 ,Port 3 pin 23 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x1E4 22. -0x1E0 22. " DD22 ,Port 3 pin 22 data direction" "Input,Output"
|
|
setclrfld.long 0x00 21. -0x1E4 21. -0x1E0 21. " DD21 ,Port 3 pin 21 data direction" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x1E4 20. -0x1E0 20. " DD20 ,Port 3 pin 20 data direction" "Input,Output"
|
|
setclrfld.long 0x00 19. -0x1E4 19. -0x1E0 19. " DD19 ,Port 3 pin 19 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x1E4 18. -0x1E0 18. " DD18 ,Port 3 pin 18 data direction" "Input,Output"
|
|
setclrfld.long 0x00 17. -0x1E4 17. -0x1E0 17. " DD17 ,Port 3 pin 17 data direction" "Input,Output"
|
|
setclrfld.long 0x00 16. -0x1E4 16. -0x1E0 16. " DD16 ,Port 3 pin 16 data direction" "Input,Output"
|
|
setclrfld.long 0x00 15. -0x1E4 15. -0x1E0 15. " DD15 ,Port 3 pin 15 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x1E4 14. -0x1E0 14. " DD14 ,Port 3 pin 14 data direction" "Input,Output"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x00 13. -0x1E4 13. -0x1E0 13. " DD13 ,Port 3 pin 13 data direction" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x1E4 12. -0x1E0 12. " DD12 ,Port 3 pin 12 data direction" "Input,Output"
|
|
setclrfld.long 0x00 11. -0x1E4 11. -0x1E0 11. " DD11 ,Port 3 pin 11 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x1E4 10. -0x1E0 10. " DD10 ,Port 3 pin 10 data direction" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x1E4 9. -0x1E0 9. " DD9 ,Port 3 pin 9 data direction" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x1E4 6. -0x1E0 6. " DD6 ,Port 3 pin 6 data direction" "Input,Output"
|
|
setclrfld.long 0x00 5. -0x1E4 5. -0x1E0 5. " DD5 ,Port 3 pin 5 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x1E4 4. -0x1E0 4. " DD4 ,Port 3 pin 4 data direction" "Input,Output"
|
|
setclrfld.long 0x00 3. -0x1E4 3. -0x1E0 3. " DD3 ,Port 3 pin 3 data direction" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x1E4 2. -0x1E0 2. " DD2 ,Port 3 pin 2 data direction" "Input,Output"
|
|
setclrfld.long 0x00 1. -0x1E4 1. -0x1E0 1. " DD1 ,Port 3 pin 1 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x1E4 0. -0x1E0 0. " DD0 ,Port 3 pin 0 data direction" "Input,Output"
|
|
else
|
|
setclrfld.long 0x00 0. -0x1E4 0. -0x1E0 0. " DD0 ,Port 3 pin 0 data direction" "Input,Output"
|
|
endif
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "DDR4_SET/CLR,Data Direction Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x1DC 31. -0x1D8 31. " DD31 ,Port 4 pin 31 data direction" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x1DC 30. -0x1D8 30. " DD30 ,Port 4 pin 30 data direction" "Input,Output"
|
|
setclrfld.long 0x00 29. -0x1DC 29. -0x1D8 29. " DD29 ,Port 4 pin 29 data direction" "Input,Output"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x00 28. -0x1DC 28. -0x1D8 28. " DD28 ,Port 4 pin 28 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x1DC 27. -0x1D8 27. " DD27 ,Port 4 pin 27 data direction" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x1DC 26. -0x1D8 26. " DD26 ,Port 4 pin 26 data direction" "Input,Output"
|
|
setclrfld.long 0x00 25. -0x1DC 25. -0x1D8 25. " DD25 ,Port 4 pin 25 data direction" "Input,Output"
|
|
setclrfld.long 0x00 23. -0x1DC 23. -0x1D8 23. " DD23 ,Port 4 pin 23 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x1DC 22. -0x1D8 22. " DD22 ,Port 4 pin 22 data direction" "Input,Output"
|
|
setclrfld.long 0x00 21. -0x1DC 21. -0x1D8 21. " DD21 ,Port 4 pin 21 data direction" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x1DC 20. -0x1D8 20. " DD20 ,Port 4 pin 20 data direction" "Input,Output"
|
|
setclrfld.long 0x00 19. -0x1DC 19. -0x1D8 19. " DD19 ,Port 4 pin 19 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x1DC 18. -0x1D8 18. " DD18 ,Port 4 pin 18 data direction" "Input,Output"
|
|
setclrfld.long 0x00 17. -0x1DC 17. -0x1D8 17. " DD17 ,Port 4 pin 17 data direction" "Input,Output"
|
|
setclrfld.long 0x00 16. -0x1DC 16. -0x1D8 16. " DD16 ,Port 4 pin 16 data direction" "Input,Output"
|
|
setclrfld.long 0x00 15. -0x1DC 15. -0x1D8 15. " DD15 ,Port 4 pin 15 data direction" "Input,Output"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x1DC 14. -0x1D8 14. " DD14 ,Port 4 pin 14 data direction" "Input,Output"
|
|
setclrfld.long 0x00 13. -0x1DC 13. -0x1D8 13. " DD13 ,Port 4 pin 13 data direction" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x1DC 12. -0x1D8 12. " DD12 ,Port 4 pin 12 data direction" "Input,Output"
|
|
setclrfld.long 0x00 11. -0x1DC 11. -0x1D8 11. " DD11 ,Port 4 pin 11 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x1DC 10. -0x1D8 10. " DD10 ,Port 4 pin 10 data direction" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x1DC 9. -0x1D8 9. " DD9 ,Port 4 pin 9 data direction" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x1DC 8. -0x1D8 8. " DD8 ,Port 4 pin 8 data direction" "Input,Output"
|
|
setclrfld.long 0x00 7. -0x1DC 7. -0x1D8 7. " DD7 ,Port 4 pin 7 data direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x1DC 6. -0x1D8 6. " DD6 ,Port 4 pin 6 data direction" "Input,Output"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PODR0_SET/CLR,Port Output Data Set/Clear Register"
|
|
sif cpuis("MB9DF56?LAE")||cpuis("MB9DF56?LGE")
|
|
setclrfld.long 0x00 26. -0x200 26. -0x1FC 26. " P26 ,Port 0 pin 26 output" "Low,High"
|
|
setclrfld.long 0x00 16. -0x200 16. -0x1FC 16. " P16 ,Port 0 pin 16 output" "Low,High"
|
|
elif cpuis("MB9DF56?MAE")||cpuis("MB9DF56?MGE")
|
|
setclrfld.long 0x00 31. -0x200 31. -0x1FC 31. " P31 ,Port 0 pin 31 output" "Low,High"
|
|
setclrfld.long 0x00 30. -0x200 30. -0x1FC 30. " P30 ,Port 0 pin 30 output" "Low,High"
|
|
setclrfld.long 0x00 26. -0x200 26. -0x1FC 26. " P26 ,Port 0 pin 26 output" "Low,High"
|
|
setclrfld.long 0x00 16. -0x200 16. -0x1FC 16. " P16 ,Port 0 pin 16 output" "Low,High"
|
|
else
|
|
sif cpuis("MB9DF56?LLE")||cpuis("MB9DF56?LQE")
|
|
setclrfld.long 0x00 29. -0x200 29. -0x1FC 29. " P29 ,Port 0 pin 29 output" "Low,High"
|
|
setclrfld.long 0x00 28. -0x200 28. -0x1FC 28. " P28 ,Port 0 pin 28 output" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 31. -0x200 31. -0x1FC 31. " P31 ,Port 0 pin 31 output" "Low,High"
|
|
setclrfld.long 0x00 30. -0x200 30. -0x1FC 30. " P30 ,Port 0 pin 30 output" "Low,High"
|
|
setclrfld.long 0x00 29. -0x200 29. -0x1FC 29. " P29 ,Port 0 pin 29 output" "Low,High"
|
|
setclrfld.long 0x00 28. -0x200 28. -0x1FC 28. " P28 ,Port 0 pin 28 output" "Low,High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x200 27. -0x1FC 27. " P27 ,Port 0 pin 27 output" "Low,High"
|
|
setclrfld.long 0x00 26. -0x200 26. -0x1FC 26. " P26 ,Port 0 pin 26 output" "Low,High"
|
|
setclrfld.long 0x00 25. -0x200 25. -0x1FC 25. " P25 ,Port 0 pin 25 output" "Low,High"
|
|
setclrfld.long 0x00 24. -0x200 24. -0x1FC 24. " P24 ,Port 0 pin 24 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x200 23. -0x1FC 23. " P23 ,Port 0 pin 23 output" "Low,High"
|
|
setclrfld.long 0x00 22. -0x200 22. -0x1FC 22. " P22 ,Port 0 pin 22 output" "Low,High"
|
|
setclrfld.long 0x00 21. -0x200 21. -0x1FC 21. " P21 ,Port 0 pin 21 output" "Low,High"
|
|
setclrfld.long 0x00 20. -0x200 20. -0x1FC 20. " P20 ,Port 0 pin 20 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x200 19. -0x1FC 19. " P19 ,Port 0 pin 19 output" "Low,High"
|
|
setclrfld.long 0x00 18. -0x200 18. -0x1FC 18. " P18 ,Port 0 pin 18 output" "Low,High"
|
|
setclrfld.long 0x00 17. -0x200 17. -0x1FC 17. " P17 ,Port 0 pin 17 output" "Low,High"
|
|
setclrfld.long 0x00 16. -0x200 16. -0x1FC 16. " P16 ,Port 0 pin 16 output" "Low,High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x200 15. -0x1FC 15. " P15 ,Port 0 pin 15 output" "Low,High"
|
|
setclrfld.long 0x00 14. -0x200 14. -0x1FC 14. " P14 ,Port 0 pin 14 output" "Low,High"
|
|
setclrfld.long 0x00 13. -0x200 13. -0x1FC 13. " P13 ,Port 0 pin 13 output" "Low,High"
|
|
setclrfld.long 0x00 12. -0x200 12. -0x1FC 12. " P12 ,Port 0 pin 12 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x200 11. -0x1FC 11. " P11 ,Port 0 pin 11 output" "Low,High"
|
|
setclrfld.long 0x00 10. -0x200 10. -0x1FC 10. " P10 ,Port 0 pin 10 output" "Low,High"
|
|
setclrfld.long 0x00 9. -0x200 9. -0x1FC 9. " P9 ,Port 0 pin 9 output" "Low,High"
|
|
setclrfld.long 0x00 8. -0x200 8. -0x1FC 8. " P8 ,Port 0 pin 8 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x200 7. -0x1FC 7. " P7 ,Port 0 pin 7 output" "Low,High"
|
|
setclrfld.long 0x00 6. -0x200 6. -0x1FC 6. " P6 ,Port 0 pin 6 output" "Low,High"
|
|
setclrfld.long 0x00 5. -0x200 5. -0x1FC 5. " P5 ,Port 0 pin 5 output" "Low,High"
|
|
setclrfld.long 0x00 4. -0x200 4. -0x1FC 4. " P4 ,Port 0 pin 4 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x200 3. -0x1FC 3. " P3 ,Port 0 pin 3 output" "Low,High"
|
|
setclrfld.long 0x00 2. -0x200 2. -0x1FC 2. " P2 ,Port 0 pin 2 output" "Low,High"
|
|
setclrfld.long 0x00 1. -0x200 1. -0x1FC 1. " P1 ,Port 0 pin 1 output" "Low,High"
|
|
setclrfld.long 0x00 0. -0x200 0. -0x1FC 0. " P0 ,Port 0 pin 1 output" "Low,High"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "PODR1_SET/CLR,Port Output Data Set/Clear Register"
|
|
sif cpuis("MB9DF56?MAE")||cpuis("MB9DF56?MGE")
|
|
setclrfld.long 0x00 31. -0x1F8 31. -0x1F4 31. " P31 ,Port 1 pin 31 output" "Low,High"
|
|
setclrfld.long 0x00 26. -0x1F8 26. -0x1F4 26. " P26 ,Port 1 pin 26 output" "Low,High"
|
|
setclrfld.long 0x00 16. -0x1F8 16. -0x1F4 16. " P16 ,Port 1 pin 16 output" "Low,High"
|
|
elif cpuis("MB9DF56?LAE")||cpuis("MB9DF56?LGE")
|
|
setclrfld.long 0x00 26. -0x1F8 26. -0x1F4 26. " P26 ,Port 1 pin 26 output" "Low,High"
|
|
setclrfld.long 0x00 16. -0x1F8 16. -0x1F4 16. " P16 ,Port 1 pin 16 output" "Low,High"
|
|
else
|
|
sif cpuis("MB9DF56?LLE")||cpuis("MB9DF56?LQE")
|
|
setclrfld.long 0x00 29. -0x1F8 29. -0x1F4 29. " P29 ,Port 1 pin 29 output" "Low,High"
|
|
setclrfld.long 0x00 28. -0x1F8 28. -0x1F4 28. " P28 ,Port 1 pin 28 output" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 31. -0x1F8 31. -0x1F4 31. " P31 ,Port 1 pin 31 output" "Low,High"
|
|
setclrfld.long 0x00 29. -0x1F8 29. -0x1F4 29. " P29 ,Port 1 pin 29 output" "Low,High"
|
|
setclrfld.long 0x00 28. -0x1F8 28. -0x1F4 28. " P28 ,Port 1 pin 28 output" "Low,High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x1F8 27. -0x1F4 27. " P27 ,Port 1 pin 27 output" "Low,High"
|
|
setclrfld.long 0x00 26. -0x1F8 26. -0x1F4 26. " P26 ,Port 1 pin 26 output" "Low,High"
|
|
setclrfld.long 0x00 25. -0x1F8 25. -0x1F4 25. " P25 ,Port 1 pin 25 output" "Low,High"
|
|
setclrfld.long 0x00 24. -0x1F8 24. -0x1F4 24. " P24 ,Port 1 pin 24 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x1F8 23. -0x1F4 23. " P23 ,Port 1 pin 23 output" "Low,High"
|
|
setclrfld.long 0x00 22. -0x1F8 22. -0x1F4 22. " P22 ,Port 1 pin 22 output" "Low,High"
|
|
setclrfld.long 0x00 21. -0x1F8 21. -0x1F4 21. " P21 ,Port 1 pin 21 output" "Low,High"
|
|
setclrfld.long 0x00 20. -0x1F8 20. -0x1F4 20. " P20 ,Port 1 pin 20 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x1F8 19. -0x1F4 19. " P19 ,Port 1 pin 19 output" "Low,High"
|
|
setclrfld.long 0x00 18. -0x1F8 18. -0x1F4 18. " P18 ,Port 1 pin 18 output" "Low,High"
|
|
setclrfld.long 0x00 17. -0x1F8 17. -0x1F4 17. " P17 ,Port 1 pin 17 output" "Low,High"
|
|
setclrfld.long 0x00 16. -0x1F8 16. -0x1F4 16. " P16 ,Port 1 pin 16 output" "Low,High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x1F8 15. -0x1F4 15. " P15 ,Port 1 pin 15 output" "Low,High"
|
|
setclrfld.long 0x00 14. -0x1F8 14. -0x1F4 14. " P14 ,Port 1 pin 14 output" "Low,High"
|
|
setclrfld.long 0x00 13. -0x1F8 13. -0x1F4 13. " P13 ,Port 1 pin 13 output" "Low,High"
|
|
setclrfld.long 0x00 12. -0x1F8 12. -0x1F4 12. " P12 ,Port 1 pin 12 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x1F8 11. -0x1F4 11. " P11 ,Port 1 pin 11 output" "Low,High"
|
|
setclrfld.long 0x00 10. -0x1F8 10. -0x1F4 10. " P10 ,Port 1 pin 10 output" "Low,High"
|
|
setclrfld.long 0x00 9. -0x1F8 9. -0x1F4 9. " P9 ,Port 1 pin 9 output" "Low,High"
|
|
setclrfld.long 0x00 8. -0x1F8 8. -0x1F4 8. " P8 ,Port 1 pin 8 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x1F8 7. -0x1F4 7. " P7 ,Port 1 pin 7 output" "Low,High"
|
|
setclrfld.long 0x00 6. -0x1F8 6. -0x1F4 6. " P6 ,Port 1 pin 6 output" "Low,High"
|
|
setclrfld.long 0x00 5. -0x1F8 5. -0x1F4 5. " P5 ,Port 1 pin 5 output" "Low,High"
|
|
setclrfld.long 0x00 4. -0x1F8 4. -0x1F4 4. " P4 ,Port 1 pin 4 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x1F8 3. -0x1F4 3. " P3 ,Port 1 pin 3 output" "Low,High"
|
|
setclrfld.long 0x00 2. -0x1F8 2. -0x1F4 2. " P2 ,Port 1 pin 2 output" "Low,High"
|
|
setclrfld.long 0x00 1. -0x1F8 1. -0x1F4 1. " P1 ,Port 1 pin 1 output" "Low,High"
|
|
setclrfld.long 0x00 0. -0x1F8 0. -0x1F4 0. " P0 ,Port 1 pin 0 output" "Low,High"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "PODR2_SET/CLR,Port Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x1F0 31. -0x1EC 31. " P31 ,Port 2 pin 31 output" "Low,High"
|
|
setclrfld.long 0x00 30. -0x1F0 30. -0x1EC 30. " P30 ,Port 2 pin 30 output" "Low,High"
|
|
setclrfld.long 0x00 29. -0x1F0 29. -0x1EC 29. " P29 ,Port 2 pin 29 output" "Low,High"
|
|
setclrfld.long 0x00 28. -0x1F0 28. -0x1EC 28. " P28 ,Port 2 pin 28 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x1F0 27. -0x1EC 27. " P27 ,Port 2 pin 27 output" "Low,High"
|
|
setclrfld.long 0x00 26. -0x1F0 26. -0x1EC 26. " P26 ,Port 2 pin 26 output" "Low,High"
|
|
setclrfld.long 0x00 25. -0x1F0 25. -0x1EC 25. " P25 ,Port 2 pin 25 output" "Low,High"
|
|
setclrfld.long 0x00 24. -0x1F0 24. -0x1EC 24. " P24 ,Port 2 pin 24 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x1F0 23. -0x1EC 23. " P23 ,Port 2 pin 23 output" "Low,High"
|
|
setclrfld.long 0x00 22. -0x1F0 22. -0x1EC 22. " P22 ,Port 2 pin 22 output" "Low,High"
|
|
setclrfld.long 0x00 21. -0x1F0 21. -0x1EC 21. " P21 ,Port 2 pin 21 output" "Low,High"
|
|
setclrfld.long 0x00 20. -0x1F0 20. -0x1EC 20. " P20 ,Port 2 pin 20 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x1F0 19. -0x1EC 19. " P19 ,Port 2 pin 19 output" "Low,High"
|
|
setclrfld.long 0x00 18. -0x1F0 18. -0x1EC 18. " P18 ,Port 2 pin 18 output" "Low,High"
|
|
setclrfld.long 0x00 17. -0x1F0 17. -0x1EC 17. " P17 ,Port 2 pin 17 output" "Low,High"
|
|
setclrfld.long 0x00 16. -0x1F0 16. -0x1EC 16. " P16 ,Port 2 pin 16 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x1F0 15. -0x1EC 15. " P15 ,Port 2 pin 15 output" "Low,High"
|
|
setclrfld.long 0x00 14. -0x1F0 14. -0x1EC 14. " P14 ,Port 2 pin 14 output" "Low,High"
|
|
setclrfld.long 0x00 13. -0x1F0 13. -0x1EC 13. " P13 ,Port 2 pin 13 output" "Low,High"
|
|
setclrfld.long 0x00 12. -0x1F0 12. -0x1EC 12. " P12 ,Port 2 pin 12 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x1F0 11. -0x1EC 11. " P11 ,Port 2 pin 11 output" "Low,High"
|
|
setclrfld.long 0x00 10. -0x1F0 10. -0x1EC 10. " P10 ,Port 2 pin 10 output" "Low,High"
|
|
setclrfld.long 0x00 9. -0x1F0 9. -0x1EC 9. " P9 ,Port 2 pin 9 output" "Low,High"
|
|
setclrfld.long 0x00 8. -0x1F0 8. -0x1EC 8. " P8 ,Port 2 pin 8 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x1F0 7. -0x1EC 7. " P7 ,Port 2 pin 7 output" "Low,High"
|
|
setclrfld.long 0x00 6. -0x1F0 6. -0x1EC 6. " P6 ,Port 2 pin 6 output" "Low,High"
|
|
setclrfld.long 0x00 5. -0x1F0 5. -0x1EC 5. " P5 ,Port 2 pin 5 output" "Low,High"
|
|
setclrfld.long 0x00 4. -0x1F0 4. -0x1EC 4. " P4 ,Port 2 pin 4 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x1F0 3. -0x1EC 3. " P3 ,Port 2 pin 3 output" "Low,High"
|
|
setclrfld.long 0x00 2. -0x1F0 2. -0x1EC 2. " P2 ,Port 2 pin 2 output" "Low,High"
|
|
setclrfld.long 0x00 1. -0x1F0 1. -0x1EC 1. " P1 ,Port 2 pin 1 output" "Low,High"
|
|
setclrfld.long 0x00 0. -0x1F0 0. -0x1EC 0. " P0 ,Port 2 pin 0 output" "Low,High"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "PODR3_SET/CLR,Port Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 30. -0x1E8 30. -0x1E4 30. " P30 ,Port 3 pin 30 output" "Low,High"
|
|
setclrfld.long 0x00 29. -0x1E8 29. -0x1E4 29. " P29 ,Port 3 pin 29 output" "Low,High"
|
|
setclrfld.long 0x00 28. -0x1E8 28. -0x1E4 28. " P28 ,Port 3 pin 28 output" "Low,High"
|
|
setclrfld.long 0x00 27. -0x1E8 27. -0x1E4 27. " P27 ,Port 3 pin 27 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x1E8 26. -0x1E4 26. " P26 ,Port 3 pin 26 output" "Low,High"
|
|
setclrfld.long 0x00 25. -0x1E8 25. -0x1E4 25. " P25 ,Port 3 pin 25 output" "Low,High"
|
|
setclrfld.long 0x00 24. -0x1E8 24. -0x1E4 24. " P24 ,Port 3 pin 24 output" "Low,High"
|
|
setclrfld.long 0x00 23. -0x1E8 23. -0x1E4 23. " P23 ,Port 3 pin 23 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x1E8 22. -0x1E4 22. " P22 ,Port 3 pin 22 output" "Low,High"
|
|
setclrfld.long 0x00 21. -0x1E8 21. -0x1E4 21. " P21 ,Port 3 pin 21 output" "Low,High"
|
|
setclrfld.long 0x00 20. -0x1E8 20. -0x1E4 20. " P20 ,Port 3 pin 20 output" "Low,High"
|
|
setclrfld.long 0x00 19. -0x1E8 19. -0x1E4 19. " P19 ,Port 3 pin 19 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x1E8 18. -0x1E4 18. " P18 ,Port 3 pin 18 output" "Low,High"
|
|
setclrfld.long 0x00 17. -0x1E8 17. -0x1E4 17. " P17 ,Port 3 pin 17 output" "Low,High"
|
|
setclrfld.long 0x00 16. -0x1E8 16. -0x1E4 16. " P16 ,Port 3 pin 16 output" "Low,High"
|
|
setclrfld.long 0x00 15. -0x1E8 15. -0x1E4 15. " P15 ,Port 3 pin 15 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x1E8 14. -0x1E4 14. " P14 ,Port 3 pin 14 output" "Low,High"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x00 13. -0x1E8 13. -0x1E4 13. " P13 ,Port 3 pin 13 output" "Low,High"
|
|
setclrfld.long 0x00 12. -0x1E8 12. -0x1E4 12. " P12 ,Port 3 pin 12 output" "Low,High"
|
|
setclrfld.long 0x00 11. -0x1E8 11. -0x1E4 11. " P11 ,Port 3 pin 11 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x1E8 10. -0x1E4 10. " P10 ,Port 3 pin 10 output" "Low,High"
|
|
setclrfld.long 0x00 9. -0x1E8 9. -0x1E4 9. " P9 ,Port 3 pin 9 output" "Low,High"
|
|
setclrfld.long 0x00 6. -0x1E8 6. -0x1E4 6. " P6 ,Port 3 pin 6 output" "Low,High"
|
|
setclrfld.long 0x00 5. -0x1E8 5. -0x1E4 5. " P5 ,Port 3 pin 5 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x1E8 4. -0x1E4 4. " P4 ,Port 3 pin 4 output" "Low,High"
|
|
setclrfld.long 0x00 3. -0x1E8 3. -0x1E4 3. " P3 ,Port 3 pin 3 output" "Low,High"
|
|
setclrfld.long 0x00 2. -0x1E8 2. -0x1E4 2. " P2 ,Port 3 pin 2 output" "Low,High"
|
|
setclrfld.long 0x00 1. -0x1E8 1. -0x1E4 1. " P1 ,Port 3 pin 1 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x1E8 0. -0x1E4 0. " P0 ,Port 3 pin 0 output" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 0. -0x1E8 0. -0x1E4 0. " P0 ,Port 3 pin 0 output" "Low,High"
|
|
endif
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "PODR4_SET/CLR,Port Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x1E0 31. -0x1DC 31. " P31 ,Port 4 pin 31 output" "Low,High"
|
|
setclrfld.long 0x00 30. -0x1E0 30. -0x1DC 30. " P30 ,Port 4 pin 30 output" "Low,High"
|
|
setclrfld.long 0x00 29. -0x1E0 29. -0x1DC 29. " P29 ,Port 4 pin 29 output" "Low,High"
|
|
sif cpuis("MB9DF56?M*")
|
|
setclrfld.long 0x00 28. -0x1E0 28. -0x1DC 28. " P28 ,Port 4 pin 28 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x1E0 27. -0x1DC 27. " P27 ,Port 4 pin 27 output" "Low,High"
|
|
setclrfld.long 0x00 26. -0x1E0 26. -0x1DC 26. " P26 ,Port 4 pin 26 output" "Low,High"
|
|
setclrfld.long 0x00 25. -0x1E0 25. -0x1DC 25. " P25 ,Port 4 pin 25 output" "Low,High"
|
|
setclrfld.long 0x00 23. -0x1E0 23. -0x1DC 23. " P23 ,Port 4 pin 23 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x1E0 22. -0x1DC 22. " P22 ,Port 4 pin 22 output" "Low,High"
|
|
setclrfld.long 0x00 21. -0x1E0 21. -0x1DC 21. " P21 ,Port 4 pin 21 output" "Low,High"
|
|
setclrfld.long 0x00 20. -0x1E0 20. -0x1DC 20. " P20 ,Port 4 pin 20 output" "Low,High"
|
|
setclrfld.long 0x00 19. -0x1E0 19. -0x1DC 19. " P19 ,Port 4 pin 19 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x1E0 18. -0x1DC 18. " P18 ,Port 4 pin 18 output" "Low,High"
|
|
setclrfld.long 0x00 17. -0x1E0 17. -0x1DC 17. " P17 ,Port 4 pin 17 output" "Low,High"
|
|
setclrfld.long 0x00 16. -0x1E0 16. -0x1DC 16. " P16 ,Port 4 pin 16 output" "Low,High"
|
|
setclrfld.long 0x00 15. -0x1E0 15. -0x1DC 15. " P15 ,Port 4 pin 15 output" "Low,High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x1E0 14. -0x1DC 14. " P14 ,Port 4 pin 14 output" "Low,High"
|
|
setclrfld.long 0x00 13. -0x1E0 13. -0x1DC 13. " P13 ,Port 4 pin 13 output" "Low,High"
|
|
setclrfld.long 0x00 12. -0x1E0 12. -0x1DC 12. " P12 ,Port 4 pin 12 output" "Low,High"
|
|
setclrfld.long 0x00 11. -0x1E0 11. -0x1DC 11. " P11 ,Port 4 pin 11 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x1E0 10. -0x1DC 10. " P10 ,Port 4 pin 10 output" "Low,High"
|
|
setclrfld.long 0x00 9. -0x1E0 9. -0x1DC 9. " P9 ,Port 4 pin 9 output" "Low,High"
|
|
setclrfld.long 0x00 8. -0x1E0 8. -0x1DC 8. " P8 ,Port 4 pin 8 output" "Low,High"
|
|
setclrfld.long 0x00 7. -0x1E0 7. -0x1DC 7. " P7 ,Port 4 pin 7 output" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x1E0 6. -0x1DC 6. " P6 ,Port 4 pin 6 output" "Low,High"
|
|
group.long 0x300++0x13
|
|
line.long 0x00 "PIDR0,Port Input Data Register 0"
|
|
sif cpuis("MB9DF56?LAE")||cpuis("MB9DF56?LGE")
|
|
bitfld.long 0x00 26. " PID26 ,Port 0 pin 26 input data" "Low,High"
|
|
bitfld.long 0x00 16. " PID16 ,Port 0 pin 16 input data" "Low,High"
|
|
elif cpuis("MB9DF56?MAE")||cpuis("MB9DF56?MGE")
|
|
bitfld.long 0x00 31. " PID31 ,Port 0 pin 31 input data" "Low,High"
|
|
bitfld.long 0x00 30. " PID30 ,Port 0 pin 30 input data" "Low,High"
|
|
bitfld.long 0x00 26. " PID26 ,Port 0 pin 26 input data" "Low,High"
|
|
bitfld.long 0x00 16. " PID16 ,Port 0 pin 16 input data" "Low,High"
|
|
else
|
|
sif cpuis("MB9DF56?LLE")||cpuis("MB9DF56?LQE")
|
|
bitfld.long 0x00 29. " PID29 ,Port 0 pin 29 input data" "Low,High"
|
|
bitfld.long 0x00 28. " PID28 ,Port 0 pin 28 input data" "Low,High"
|
|
else
|
|
bitfld.long 0x00 31. " PID31 ,Port 0 pin 31 input data" "Low,High"
|
|
bitfld.long 0x00 30. " PID30 ,Port 0 pin 30 input data" "Low,High"
|
|
bitfld.long 0x00 29. " PID29 ,Port 0 pin 29 input data" "Low,High"
|
|
bitfld.long 0x00 28. " PID28 ,Port 0 pin 28 input data" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 27. " PID27 ,Port 0 pin 27 input data" "Low,High"
|
|
bitfld.long 0x00 26. " PID26 ,Port 0 pin 26 input data" "Low,High"
|
|
bitfld.long 0x00 25. " PID25 ,Port 0 pin 25 input data" "Low,High"
|
|
bitfld.long 0x00 24. " PID24 ,Port 0 pin 24 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PID23 ,Port 0 pin 23 input data" "Low,High"
|
|
bitfld.long 0x00 22. " PID22 ,Port 0 pin 22 input data" "Low,High"
|
|
bitfld.long 0x00 21. " PID21 ,Port 0 pin 21 input data" "Low,High"
|
|
bitfld.long 0x00 20. " PID20 ,Port 0 pin 20 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PID19 ,Port 0 pin 19 input data" "Low,High"
|
|
bitfld.long 0x00 18. " PID18 ,Port 0 pin 18 input data" "Low,High"
|
|
bitfld.long 0x00 17. " PID17 ,Port 0 pin 17 input data" "Low,High"
|
|
bitfld.long 0x00 16. " PID16 ,Port 0 pin 16 input data" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " PID15 ,Port 0 pin 15 input data" "Low,High"
|
|
bitfld.long 0x00 14. " PID14 ,Port 0 pin 14 input data" "Low,High"
|
|
bitfld.long 0x00 13. " PID13 ,Port 0 pin 13 input data" "Low,High"
|
|
bitfld.long 0x00 12. " PID12 ,Port 0 pin 12 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PID11 ,Port 0 pin 11 input data" "Low,High"
|
|
bitfld.long 0x00 10. " PID10 ,Port 0 pin 10 input data" "Low,High"
|
|
bitfld.long 0x00 9. " PID9 ,Port 0 pin 9 input data" "Low,High"
|
|
bitfld.long 0x00 8. " PID8 ,Port 0 pin 8 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PID7 ,Port 0 pin 7 input data" "Low,High"
|
|
bitfld.long 0x00 6. " PID6 ,Port 0 pin 6 input data" "Low,High"
|
|
bitfld.long 0x00 5. " PID5 ,Port 0 pin 5 input data" "Low,High"
|
|
bitfld.long 0x00 4. " PID4 ,Port 0 pin 4 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PID3 ,Port 0 pin 3 input data" "Low,High"
|
|
bitfld.long 0x00 2. " PID2 ,Port 0 pin 2 input data" "Low,High"
|
|
bitfld.long 0x00 1. " PID1 ,Port 0 pin 1 input data" "Low,High"
|
|
bitfld.long 0x00 0. " PID0 ,Port 0 pin 0 input data" "Low,High"
|
|
line.long 0x04 "PIDR1,Port Input Data Register 1"
|
|
sif cpuis("MB9DF56?MAE")||cpuis("MB9DF56?MGE")
|
|
bitfld.long 0x04 31. " PID31 ,Port 1 pin 31 input data" "Low,High"
|
|
bitfld.long 0x04 26. " PID26 ,Port 1 pin 26 input data" "Low,High"
|
|
bitfld.long 0x04 16. " PID16 ,Port 1 pin 16 input data" "Low,High"
|
|
elif cpuis("MB9DF56?LAE")||cpuis("MB9DF56?LGE")
|
|
bitfld.long 0x04 26. " PID26 ,Port 1 pin 26 input data" "Low,High"
|
|
bitfld.long 0x04 16. " PID16 ,Port 1 pin 16 input data" "Low,High"
|
|
else
|
|
sif cpuis("MB9DF56?LLE")||cpuis("MB9DF56?LQE")
|
|
bitfld.long 0x04 29. " PID29 ,Port 1 pin 29 input data" "Low,High"
|
|
bitfld.long 0x04 28. " PID28 ,Port 1 pin 28 input data" "Low,High"
|
|
else
|
|
bitfld.long 0x04 31. " PID31 ,Port 1 pin 31 input data" "Low,High"
|
|
bitfld.long 0x04 29. " PID29 ,Port 1 pin 29 input data" "Low,High"
|
|
bitfld.long 0x04 28. " PID28 ,Port 1 pin 28 input data" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 27. " PID27 ,Port 1 pin 27 input data" "Low,High"
|
|
bitfld.long 0x04 26. " PID26 ,Port 1 pin 26 input data" "Low,High"
|
|
bitfld.long 0x04 25. " PID25 ,Port 1 pin 25 input data" "Low,High"
|
|
bitfld.long 0x04 24. " PID24 ,Port 1 pin 24 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PID23 ,Port 1 pin 23 input data" "Low,High"
|
|
bitfld.long 0x04 22. " PID22 ,Port 1 pin 22 input data" "Low,High"
|
|
bitfld.long 0x04 21. " PID21 ,Port 1 pin 21 input data" "Low,High"
|
|
bitfld.long 0x04 20. " PID20 ,Port 1 pin 20 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PID19 ,Port 1 pin 19 input data" "Low,High"
|
|
bitfld.long 0x04 18. " PID18 ,Port 1 pin 18 input data" "Low,High"
|
|
bitfld.long 0x04 17. " PID17 ,Port 1 pin 17 input data" "Low,High"
|
|
bitfld.long 0x04 16. " PID16 ,Port 1 pin 16 input data" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 15. " PID15 ,Port 1 pin 15 input data" "Low,High"
|
|
bitfld.long 0x04 14. " PID14 ,Port 1 pin 14 input data" "Low,High"
|
|
bitfld.long 0x04 13. " PID13 ,Port 1 pin 13 input data" "Low,High"
|
|
bitfld.long 0x04 12. " PID12 ,Port 1 pin 12 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PID11 ,Port 1 pin 11 input data" "Low,High"
|
|
bitfld.long 0x04 10. " PID10 ,Port 1 pin 10 input data" "Low,High"
|
|
bitfld.long 0x04 9. " PID9 ,Port 1 pin 9 input data" "Low,High"
|
|
bitfld.long 0x04 8. " PID8 ,Port 1 pin 8 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PID7 ,Port 1 pin 7 input data" "Low,High"
|
|
bitfld.long 0x04 6. " PID6 ,Port 1 pin 6 input data" "Low,High"
|
|
bitfld.long 0x04 5. " PID5 ,Port 1 pin 5 input data" "Low,High"
|
|
bitfld.long 0x04 4. " PID4 ,Port 1 pin 4 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PID3 ,Port 1 pin 3 input data" "Low,High"
|
|
bitfld.long 0x04 2. " PID2 ,Port 1 pin 2 input data" "Low,High"
|
|
bitfld.long 0x04 1. " PID1 ,Port 1 pin 1 input data" "Low,High"
|
|
bitfld.long 0x04 0. " PID0 ,Port 1 pin 0 input data" "Low,High"
|
|
line.long 0x08 "PIDR2,Port Input Data Register 2"
|
|
bitfld.long 0x08 31. " PID31 ,Port 2 pin 31 input data" "Low,High"
|
|
bitfld.long 0x08 30. " PID30 ,Port 2 pin 30 input data" "Low,High"
|
|
bitfld.long 0x08 29. " PID29 ,Port 2 pin 29 input data" "Low,High"
|
|
bitfld.long 0x08 28. " PID28 ,Port 2 pin 28 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 27. " PID27 ,Port 2 pin 27 input data" "Low,High"
|
|
bitfld.long 0x08 26. " PID26 ,Port 2 pin 26 input data" "Low,High"
|
|
bitfld.long 0x08 25. " PID25 ,Port 2 pin 25 input data" "Low,High"
|
|
bitfld.long 0x08 24. " PID24 ,Port 2 pin 24 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 23. " PID23 ,Port 2 pin 23 input data" "Low,High"
|
|
bitfld.long 0x08 22. " PID22 ,Port 2 pin 22 input data" "Low,High"
|
|
bitfld.long 0x08 21. " PID21 ,Port 2 pin 21 input data" "Low,High"
|
|
bitfld.long 0x08 20. " PID20 ,Port 2 pin 20 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PID19 ,Port 2 pin 19 input data" "Low,High"
|
|
bitfld.long 0x08 18. " PID18 ,Port 2 pin 18 input data" "Low,High"
|
|
bitfld.long 0x08 17. " PID17 ,Port 2 pin 17 input data" "Low,High"
|
|
bitfld.long 0x08 16. " PID16 ,Port 2 pin 16 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 15. " PID15 ,Port 2 pin 15 input data" "Low,High"
|
|
bitfld.long 0x08 14. " PID14 ,Port 2 pin 14 input data" "Low,High"
|
|
bitfld.long 0x08 13. " PID13 ,Port 2 pin 13 input data" "Low,High"
|
|
bitfld.long 0x08 12. " PID12 ,Port 2 pin 12 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 11. " PID11 ,Port 2 pin 11 input data" "Low,High"
|
|
bitfld.long 0x08 10. " PID10 ,Port 2 pin 10 input data" "Low,High"
|
|
bitfld.long 0x08 9. " PID9 ,Port 2 pin 9 input data" "Low,High"
|
|
bitfld.long 0x08 8. " PID8 ,Port 2 pin 8 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 7. " PID7 ,Port 2 pin 7 input data" "Low,High"
|
|
bitfld.long 0x08 6. " PID6 ,Port 2 pin 6 input data" "Low,High"
|
|
bitfld.long 0x08 5. " PID5 ,Port 2 pin 5 input data" "Low,High"
|
|
bitfld.long 0x08 4. " PID4 ,Port 2 pin 4 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PID3 ,Port 2 pin 3 input data" "Low,High"
|
|
bitfld.long 0x08 2. " PID2 ,Port 2 pin 2 input data" "Low,High"
|
|
bitfld.long 0x08 1. " PID1 ,Port 2 pin 1 input data" "Low,High"
|
|
bitfld.long 0x08 0. " PID0 ,Port 2 pin 0 input data" "Low,High"
|
|
line.long 0x0C "PIDR3,Port Input Data Register 3"
|
|
bitfld.long 0x0C 30. " PID30 ,Port 3 pin 30 input data" "Low,High"
|
|
bitfld.long 0x0C 29. " PID29 ,Port 3 pin 29 input data" "Low,High"
|
|
bitfld.long 0x0C 28. " PID28 ,Port 3 pin 28 input data" "Low,High"
|
|
bitfld.long 0x0C 27. " PID27 ,Port 3 pin 27 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " PID26 ,Port 3 pin 26 input data" "Low,High"
|
|
bitfld.long 0x0C 25. " PID25 ,Port 3 pin 25 input data" "Low,High"
|
|
bitfld.long 0x0C 24. " PID24 ,Port 3 pin 24 input data" "Low,High"
|
|
bitfld.long 0x0C 23. " PID23 ,Port 3 pin 23 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " PID22 ,Port 3 pin 22 input data" "Low,High"
|
|
bitfld.long 0x0C 21. " PID21 ,Port 3 pin 21 input data" "Low,High"
|
|
bitfld.long 0x0C 20. " PID20 ,Port 3 pin 20 input data" "Low,High"
|
|
bitfld.long 0x0C 19. " PID19 ,Port 3 pin 19 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " PID18 ,Port 3 pin 18 input data" "Low,High"
|
|
bitfld.long 0x0C 17. " PID17 ,Port 3 pin 17 input data" "Low,High"
|
|
bitfld.long 0x0C 16. " PID16 ,Port 3 pin 16 input data" "Low,High"
|
|
bitfld.long 0x0C 15. " PID15 ,Port 3 pin 15 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " PID14 ,Port 3 pin 14 input data" "Low,High"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x0C 13. " PID13 ,Port 3 pin 13 input data" "Low,High"
|
|
bitfld.long 0x0C 12. " PID12 ,Port 3 pin 12 input data" "Low,High"
|
|
bitfld.long 0x0C 11. " PID11 ,Port 3 pin 11 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " PID10 ,Port 3 pin 10 input data" "Low,High"
|
|
bitfld.long 0x0C 9. " PID9 ,Port 3 pin 9 input data" "Low,High"
|
|
bitfld.long 0x0C 6. " PID6 ,Port 3 pin 6 input data" "Low,High"
|
|
bitfld.long 0x0C 5. " PID5 ,Port 3 pin 5 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " PID4 ,Port 3 pin 4 input data" "Low,High"
|
|
bitfld.long 0x0C 3. " PID3 ,Port 3 pin 3 input data" "Low,High"
|
|
bitfld.long 0x0C 2. " PID2 ,Port 3 pin 2 input data" "Low,High"
|
|
bitfld.long 0x0C 1. " PID1 ,Port 3 pin 1 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " PID0 ,Port 3 pin 0 input data" "Low,High"
|
|
else
|
|
bitfld.long 0x0C 0. " PID0 ,Port 3 pin 0 input data" "Low,High"
|
|
endif
|
|
line.long 0x10 "PIDR4,Port Input Data Register 4"
|
|
bitfld.long 0x10 31. " PID31 ,Port 4 pin 31 input data" "Low,High"
|
|
bitfld.long 0x10 30. " PID30 ,Port 4 pin 30 input data" "Low,High"
|
|
bitfld.long 0x10 29. " PID29 ,Port 4 pin 29 input data" "Low,High"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x10 28. " PID28 ,Port 4 pin 28 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 27. " PID27 ,Port 4 pin 27 input data" "Low,High"
|
|
bitfld.long 0x10 26. " PID26 ,Port 4 pin 26 input data" "Low,High"
|
|
bitfld.long 0x10 25. " PID25 ,Port 4 pin 25 input data" "Low,High"
|
|
bitfld.long 0x10 23. " PID23 ,Port 4 pin 23 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 22. " PID22 ,Port 4 pin 22 input data" "Low,High"
|
|
bitfld.long 0x10 21. " PID21 ,Port 4 pin 21 input data" "Low,High"
|
|
bitfld.long 0x10 20. " PID20 ,Port 4 pin 20 input data" "Low,High"
|
|
bitfld.long 0x10 19. " PID19 ,Port 4 pin 19 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 18. " PID18 ,Port 4 pin 18 input data" "Low,High"
|
|
bitfld.long 0x10 17. " PID17 ,Port 4 pin 17 input data" "Low,High"
|
|
bitfld.long 0x10 16. " PID16 ,Port 4 pin 16 input data" "Low,High"
|
|
bitfld.long 0x10 15. " PID15 ,Port 4 pin 15 input data" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 14. " PID14 ,Port 4 pin 14 input data" "Low,High"
|
|
bitfld.long 0x10 13. " PID13 ,Port 4 pin 13 input data" "Low,High"
|
|
bitfld.long 0x10 12. " PID12 ,Port 4 pin 12 input data" "Low,High"
|
|
bitfld.long 0x10 11. " PID11 ,Port 4 pin 11 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 10. " PID10 ,Port 4 pin 10 input data" "Low,High"
|
|
bitfld.long 0x10 9. " PID9 ,Port 4 pin 9 input data" "Low,High"
|
|
bitfld.long 0x10 8. " PID8 ,Port 4 pin 8 input data" "Low,High"
|
|
bitfld.long 0x10 7. " PID7 ,Port 4 pin 7 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 6. " PID6 ,Port 4 pin 6 input data" "Low,High"
|
|
textline " "
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PORTEN,Port Input Enable Register"
|
|
bitfld.long 0x00 1. " CPORTEN ,Serial write pin input enable bit" "No effect,Enable"
|
|
bitfld.long 0x00 0. " GPORTEN ,Global input enable bit" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PPC (Port Configuration)"
|
|
base ad:0xB0740000
|
|
width 16.
|
|
group.word 0x00++0x21
|
|
line.word 0x00 "PPC_PCFGR000,Port 0 Pin 0 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P000,?..."
|
|
line.word 0x02 "PPC_PCFGR001,Port 0 Pin 1 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P001,RTO0,?..."
|
|
line.word 0x04 "PPC_PCFGR002,Port 0 Pin 2 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P002,RTO1,,?..."
|
|
line.word 0x06 "PPC_PCFGR003,Port 0 Pin 3 Setting Register"
|
|
rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x06 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "GPIO_P003,RTO2,?..."
|
|
line.word 0x08 "PPC_PCFGR004,Port 0 Pin 4 Setting Register"
|
|
rbitfld.word 0x08 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x08 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x08 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x08 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x08 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x08 0.--2. " POF ,Port output function selection bit" "GPIO_P004,RTO3,?..."
|
|
line.word 0x0A "PPC_PCFGR005,Port 0 Pin 5 Setting Register"
|
|
rbitfld.word 0x0A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0A 0.--2. " POF ,Port output function selection bit" "GPIO_P005,RTO4,?..."
|
|
line.word 0x0C "PPC_PCFGR006,Port 0 Pin 6 Setting Register"
|
|
rbitfld.word 0x0C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0C 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0C 0.--2. " POF ,Port output function selection bit" "GPIO_P006,RTO5,?..."
|
|
line.word 0x0E "PPC_PCFGR007,Port 0 Pin 7 Setting Register"
|
|
rbitfld.word 0x0E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0E 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0E 0.--2. " POF ,Port output function selection bit" "GPIO_P007,?..."
|
|
line.word 0x10 "PPC_PCFGR008,Port 0 Pin 8 Setting Register"
|
|
rbitfld.word 0x10 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x10 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x10 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x10 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x10 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x10 0.--2. " POF ,Port output function selection bit" "GPIO_P008,?..."
|
|
line.word 0x12 "PPC_PCFGR009,Port 0 Pin 9 Setting Register"
|
|
rbitfld.word 0x12 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x12 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x12 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x12 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x12 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x12 0.--2. " POF ,Port output function selection bit" "GPIO_P009,?..."
|
|
line.word 0x14 "PPC_PCFGR010,Port 0 Pin 10 Setting Register"
|
|
rbitfld.word 0x14 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x14 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x14 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x14 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x14 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x14 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x14 0.--2. " POF ,Port output function selection bit" "GPIO_P010,?..."
|
|
line.word 0x16 "PPC_PCFGR011,Port 0 Pin 11 Setting Register"
|
|
rbitfld.word 0x16 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x16 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x16 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x16 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x16 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x16 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.word 0x16 0.--2. " POF ,Port output function selection bit" "GPIO_P011,RDC_W0,?..."
|
|
else
|
|
bitfld.word 0x16 0.--2. " POF ,Port output function selection bit" "GPIO_P011,?..."
|
|
endif
|
|
line.word 0x18 "PPC_PCFGR012,Port 0 Pin 12 Setting Register"
|
|
rbitfld.word 0x18 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x18 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x18 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x18 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x18 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x18 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.word 0x18 0.--2. " POF ,Port output function selection bit" "GPIO_P012,RDC_V0,?..."
|
|
else
|
|
bitfld.word 0x18 0.--2. " POF ,Port output function selection bit" "GPIO_P012,?..."
|
|
endif
|
|
line.word 0x1A "PPC_PCFGR013,Port 0 Pin 13 Setting Register"
|
|
rbitfld.word 0x1A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x1A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x1A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x1A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x1A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x1A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.word 0x1A 0.--2. " POF ,Port output function selection bit" "GPIO_P013,RDC_U0,?..."
|
|
else
|
|
bitfld.word 0x1A 0.--2. " POF ,Port output function selection bit" "GPIO_P013,?..."
|
|
endif
|
|
line.word 0x1C "PPC_PCFGR014,Port 0 Pin 14 Setting Register"
|
|
rbitfld.word 0x1C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x1C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x1C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x1C 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x1C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x1C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.word 0x1C 0.--2. " POF ,Port output function selection bit" "GPIO_P014,RDC_Z0,?..."
|
|
else
|
|
bitfld.word 0x1C 0.--2. " POF ,Port output function selection bit" "GPIO_P014,?..."
|
|
endif
|
|
line.word 0x1E "PPC_PCFGR015,Port 0 Pin 15 Setting Register"
|
|
rbitfld.word 0x1E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x1E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x1E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x1E 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x1E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x1E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.word 0x1E 0.--2. " POF ,Port output function selection bit" "GPIO_P015,RDC_B0,?..."
|
|
else
|
|
bitfld.word 0x1E 0.--2. " POF ,Port output function selection bit" "GPIO_P015,?..."
|
|
endif
|
|
line.word 0x20 "PPC_PCFGR016,Port 0 Pin 16 Setting Register"
|
|
rbitfld.word 0x20 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x20 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x20 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x20 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x20 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x20 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.word 0x20 0.--2. " POF ,Port output function selection bit" "GPIO_P016,RDC_A0,?..."
|
|
else
|
|
bitfld.word 0x20 0.--2. " POF ,Port output function selection bit" "GPIO_P016,?..."
|
|
endif
|
|
sif cpuis("MB9DF56??LE")||cpuis("MB9DF56??QE")
|
|
group.word 0x22++0x13
|
|
line.word 0x00 "PPC_PCFGR017,Port 0 Pin 17 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P017,?..."
|
|
line.word 0x02 "PPC_PCFGR018,Port 0 Pin 18 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P018,?..."
|
|
line.word 0x04 "PPC_PCFGR019,Port 0 Pin 19 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P019,?..."
|
|
line.word 0x06 "PPC_PCFGR020,Port 0 Pin 20 Setting Register"
|
|
rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x06 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "GPIO_P020,?..."
|
|
line.word 0x08 "PPC_PCFGR021,Port 0 Pin 21 Setting Register"
|
|
rbitfld.word 0x08 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x08 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x08 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x08 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x08 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x08 0.--2. " POF ,Port output function selection bit" "GPIO_P21,?..."
|
|
line.word 0x0A "PPC_PCFGR022,Port 0 Pin 22 Setting Register"
|
|
rbitfld.word 0x0A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0A 0.--2. " POF ,Port output function selection bit" "GPIO_P22,?..."
|
|
line.word 0x0C "PPC_PCFGR023,Port 0 Pin 23 Setting Register"
|
|
rbitfld.word 0x0C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0C 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0C 0.--2. " POF ,Port output function selection bit" "GPIO_P23,?..."
|
|
line.word 0x0E "PPC_PCFGR024,Port 0 Pin 24 Setting Register"
|
|
rbitfld.word 0x0E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0E 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0E 0.--2. " POF ,Port output function selection bit" "GPIO_P24,?..."
|
|
line.word 0x10 "PPC_PCFGR025,Port 0 Pin 25 Setting Register"
|
|
rbitfld.word 0x10 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x10 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x10 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x10 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x10 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x10 0.--2. " POF ,Port output function selection bit" "GPIO_P25,?..."
|
|
endif
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "PPC_PCFGR026,Port 0 Pin 26 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
sif cpuis("MB9FD56??AE")||cpuis("MB9FD56??GE")
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "RDC_ACT0,GPIO_P026,?..."
|
|
else
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P026,?..."
|
|
endif
|
|
sif cpuis("MB9DF56??LE")||cpuis("MB9DF56??QE")
|
|
group.word 0x36++0x05
|
|
line.word 0x00 "PPC_PCFGR027,Port 0 Pin 27 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P07,?..."
|
|
line.word 0x02 "PPC_PCFGR028,Port 0 Pin 28 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P08,?..."
|
|
line.word 0x04 "PPC_PCFGR029,Port 0 Pin 29 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P029,?..."
|
|
endif
|
|
sif cpuis("MB9DF56?M*")
|
|
group.word 0x3C++0x03
|
|
line.word 0x00 "PPC_PCFGR030,Port 0 Pin 30 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P030,?..."
|
|
line.word 0x02 "PPC_PCFGR031,Port 0 Pin 31 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P031,RTO12,?..."
|
|
endif
|
|
group.word 0x40++0x21
|
|
line.word 0x00 "PPC_PCFGR100,Port 1 Pin 0 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P100,?..."
|
|
line.word 0x02 "PPC_PCFGR101,Port 1 Pin 1 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P101,RTO6,?..."
|
|
line.word 0x04 "PPC_PCFGR102,Port 1 Pin 2 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P102,RTO7,?..."
|
|
line.word 0x06 "PPC_PCFGR103,Port 1 Pin 3 Setting Register"
|
|
rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x06 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "GPIO_P103,RTO8,?..."
|
|
line.word 0x08 "PPC_PCFGR104,Port 1 Pin 4 Setting Register"
|
|
rbitfld.word 0x08 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x08 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x08 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x08 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x08 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x08 0.--2. " POF ,Port output function selection bit" "GPIO_P104,RTO9,?..."
|
|
line.word 0x0A "PPC_PCFGR105,Port 1 Pin 5 Setting Register"
|
|
rbitfld.word 0x0A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0A 0.--2. " POF ,Port output function selection bit" "GPIO_P105,?..."
|
|
line.word 0x0C "PPC_PCFGR106,Port 1 Pin 6 Setting Register"
|
|
rbitfld.word 0x0C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0C 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0C 0.--2. " POF ,Port output function selection bit" "GPIO_P106,RTO11,?..."
|
|
line.word 0x0E "PPC_PCFGR107,Port 1 Pin 7 Setting Register"
|
|
rbitfld.word 0x0E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0E 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0E 0.--2. " POF ,Port output function selection bit" "GPIO_P107,?..."
|
|
line.word 0x10 "PPC_PCFGR108,Port 1 Pin 8 Setting Register"
|
|
rbitfld.word 0x10 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x10 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x10 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x10 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x10 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x10 0.--2. " POF ,Port output function selection bit" "GPIO_P108,?..."
|
|
line.word 0x12 "PPC_PCFGR109,Port 1 Pin 9 Setting Register"
|
|
rbitfld.word 0x12 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x12 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x12 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x12 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x12 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x12 0.--2. " POF ,Port output function selection bit" "GPIO_P109,?..."
|
|
line.word 0x14 "PPC_PCFGR110,Port 1 Pin 10 Setting Register"
|
|
rbitfld.word 0x14 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x14 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x14 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x14 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x14 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x14 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x14 0.--2. " POF ,Port output function selection bit" "GPIO_P110,?..."
|
|
line.word 0x16 "PPC_PCFGR111,Port 1 Pin 11 Setting Register"
|
|
rbitfld.word 0x16 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x16 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x16 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x16 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x16 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x16 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.word 0x16 0.--2. " POF ,Port output function selection bit" "GPIO_P111,RDC_W1,?..."
|
|
else
|
|
bitfld.word 0x16 0.--2. " POF ,Port output function selection bit" "GPIO_P111,?..."
|
|
endif
|
|
line.word 0x18 "PPC_PCFGR112,Port 1 Pin 12 Setting Register"
|
|
rbitfld.word 0x18 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x18 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x18 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x18 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x18 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x18 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.word 0x18 0.--2. " POF ,Port output function selection bit" "GPIO_P112,RDC_V1,?..."
|
|
else
|
|
bitfld.word 0x18 0.--2. " POF ,Port output function selection bit" "GPIO_P112,?..."
|
|
endif
|
|
line.word 0x1A "PPC_PCFGR113,Port 1 Pin 13 Setting Register"
|
|
rbitfld.word 0x1A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x1A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x1A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x1A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x1A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x1A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,4mA,?..."
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.word 0x1A 0.--2. " POF ,Port output function selection bit" "GPIO_P113,RDC_U1,?..."
|
|
else
|
|
bitfld.word 0x1A 0.--2. " POF ,Port output function selection bit" "GPIO_P113,?..."
|
|
endif
|
|
line.word 0x1C "PPC_PCFGR114,Port 1 Pin 14 Setting Register"
|
|
rbitfld.word 0x1C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x1C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x1C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x1C 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x1C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x1C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,4mA,?..."
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.word 0x1C 0.--2. " POF ,Port output function selection bit" "GPIO_P114,RDC_Z1,?..."
|
|
else
|
|
bitfld.word 0x1C 0.--2. " POF ,Port output function selection bit" "GPIO_P114,?..."
|
|
endif
|
|
line.word 0x1E "PPC_PCFGR115,Port 1 Pin 15 Setting Register"
|
|
rbitfld.word 0x1E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x1E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x1E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x1E 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x1E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x1E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,4mA,?..."
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.word 0x1E 0.--2. " POF ,Port output function selection bit" "GPIO_P115,RDC_B1,?..."
|
|
else
|
|
bitfld.word 0x1E 0.--2. " POF ,Port output function selection bit" "GPIO_P115,?..."
|
|
endif
|
|
line.word 0x20 "PPC_PCFGR116,Port 1 Pin 16 Setting Register"
|
|
rbitfld.word 0x20 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x20 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x20 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x20 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x20 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x20 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,4mA,?..."
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.word 0x20 0.--2. " POF ,Port output function selection bit" "GPIO_P116,RDC_A1,?..."
|
|
else
|
|
bitfld.word 0x20 0.--2. " POF ,Port output function selection bit" "GPIO_P116,?..."
|
|
endif
|
|
sif cpuis("MB9DF56??LE")||cpuis("MB9DF56??QE")
|
|
group.word 0x62++0x13
|
|
line.word 0x00 "PPC_PCFGR117,Port 1 Pin 17 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P117,?..."
|
|
line.word 0x02 "PPC_PCFGR118,Port 1 Pin 18 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P118,?..."
|
|
line.word 0x04 "PPC_PCFGR119,Port 1 Pin 19 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P119,?..."
|
|
line.word 0x06 "PPC_PCFGR120,Port 1 Pin 20 Setting Register"
|
|
rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x06 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "GPIO_P120,?..."
|
|
line.word 0x08 "PPC_PCFGR121,Port 1 Pin 21 Setting Register"
|
|
rbitfld.word 0x08 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x08 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x08 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x08 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x08 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x08 0.--2. " POF ,Port output function selection bit" "GPIO_P121,?..."
|
|
line.word 0x0A "PPC_PCFGR122,Port 1 Pin 22 Setting Register"
|
|
rbitfld.word 0x0A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0A 0.--2. " POF ,Port output function selection bit" "GPIO_P122,?..."
|
|
line.word 0x0C "PPC_PCFGR123,Port 1 Pin 23 Setting Register"
|
|
rbitfld.word 0x0C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0C 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0C 0.--2. " POF ,Port output function selection bit" "GPIO_P123,?..."
|
|
line.word 0x0E "PPC_PCFGR124,Port 1 Pin 24 Setting Register"
|
|
rbitfld.word 0x0E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0E 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0E 0.--2. " POF ,Port output function selection bit" "GPIO_P124,?..."
|
|
line.word 0x10 "PPC_PCFGR125,Port 1 Pin 25 Setting Register"
|
|
rbitfld.word 0x10 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x10 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x10 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x10 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x10 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x10 0.--2. " POF ,Port output function selection bit" "GPIO_P125,?..."
|
|
endif
|
|
group.word 0x74++0x01
|
|
line.word 0x00 "PPC_PCFGR126,Port 1 Pin 26 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "RDC_ACT1,GPIO_P126,?..."
|
|
else
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P126,?..."
|
|
endif
|
|
sif cpuis("MB9DF56??LE")||cpuis("MB9DF56??QE")
|
|
group.word 0x76++0x05
|
|
line.word 0x00 "PPC_PCFGR127,Port 1 Pin 27 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P127,?..."
|
|
line.word 0x02 "PPC_PCFGR128,Port 1 Pin 28 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P128,?..."
|
|
line.word 0x04 "PPC_PCFGR129,Port 1 Pin 29 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P129,?..."
|
|
endif
|
|
sif cpuis("MB9DF56?M*")
|
|
group.word 0x7E++0x03
|
|
line.word 0x00 "PPC_PCFGR131,Port 1 Pin 31 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P131,SCK2,?..."
|
|
endif
|
|
group.word 0x80++0x3F
|
|
line.word 0x00 "PPC_PCFGR200,Port 2 Pin 0 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P200,?..."
|
|
line.word 0x02 "PPC_PCFGR201,Port 2 Pin 1 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P201,?..."
|
|
line.word 0x04 "PPC_PCFGR202,Port 2 Pin 2 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P202,?..."
|
|
line.word 0x06 "PPC_PCFGR203,Port 2 Pin 3 Setting Register"
|
|
rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x06 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "GPIO_P203,?..."
|
|
line.word 0x08 "PPC_PCFGR204,Port 2 Pin 4 Setting Register"
|
|
rbitfld.word 0x08 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x08 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x08 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x08 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x08 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x08 0.--2. " POF ,Port output function selection bit" "GPIO_P204,?..."
|
|
line.word 0x0A "PPC_PCFGR205,Port 2 Pin 5 Setting Register"
|
|
rbitfld.word 0x0A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0A 0.--2. " POF ,Port output function selection bit" "GPIO_P205,?..."
|
|
line.word 0x0C "PPC_PCFGR206,Port 2 Pin 6 Setting Register"
|
|
rbitfld.word 0x0C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0C 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0C 0.--2. " POF ,Port output function selection bit" "GPIO_P206,?..."
|
|
line.word 0x0E "PPC_PCFGR207,Port 2 Pin 7 Setting Register"
|
|
rbitfld.word 0x0E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0E 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0E 0.--2. " POF ,Port output function selection bit" "GPIO_P207,?..."
|
|
line.word 0x10 "PPC_PCFGR208,Port 2 Pin 8 Setting Register"
|
|
rbitfld.word 0x10 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x10 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x10 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x10 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x10 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x10 0.--2. " POF ,Port output function selection bit" "GPIO_P208,?..."
|
|
line.word 0x12 "PPC_PCFGR209,Port 2 Pin 9 Setting Register"
|
|
rbitfld.word 0x12 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x12 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x12 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x12 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x12 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x12 0.--2. " POF ,Port output function selection bit" "GPIO_P209,?..."
|
|
line.word 0x14 "PPC_PCFGR210,Port 2 Pin 10 Setting Register"
|
|
rbitfld.word 0x14 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x14 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x14 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x14 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x14 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x14 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x14 0.--2. " POF ,Port output function selection bit" "GPIO_P210,?..."
|
|
line.word 0x16 "PPC_PCFGR211,Port 2 Pin 11 Setting Register"
|
|
rbitfld.word 0x16 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x16 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x16 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x16 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x16 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x16 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x16 0.--2. " POF ,Port output function selection bit" "GPIO_P211,?..."
|
|
line.word 0x18 "PPC_PCFGR212,Port 2 Pin 12 Setting Register"
|
|
rbitfld.word 0x18 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x18 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x18 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x18 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x18 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x18 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x18 0.--2. " POF ,Port output function selection bit" "GPIO_P212,?..."
|
|
line.word 0x1A "PPC_PCFGR213,Port 2 Pin 13 Setting Register"
|
|
rbitfld.word 0x1A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x1A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x1A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x1A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x1A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x1A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x1A 0.--2. " POF ,Port output function selection bit" "GPIO_P213,?..."
|
|
line.word 0x1C "PPC_PCFGR214,Port 2 Pin 14 Setting Register"
|
|
rbitfld.word 0x1C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x1C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x1C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x1C 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x1C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x1C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x1C 0.--2. " POF ,Port output function selection bit" "GPIO_P214,?..."
|
|
line.word 0x1E "PPC_PCFGR215,Port 2 Pin 15 Setting Register"
|
|
rbitfld.word 0x1E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x1E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x1E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x1E 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x1E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x1E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x1E 0.--2. " POF ,Port output function selection bit" "GPIO_P215,?..."
|
|
line.word 0x20 "PPC_PCFGR216,Port 2 Pin 16 Setting Register"
|
|
rbitfld.word 0x20 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x20 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x20 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x20 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x20 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x20 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x20 0.--2. " POF ,Port output function selection bit" "GPIO_P216,?..."
|
|
line.word 0x22 "PPC_PCFGR217,Port 2 Pin 17 Setting Register"
|
|
rbitfld.word 0x22 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x22 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x22 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x22 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x22 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x22 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x22 0.--2. " POF ,Port output function selection bit" "GPIO_P217,?..."
|
|
line.word 0x24 "PPC_PCFGR218,Port 2 Pin 18 Setting Register"
|
|
rbitfld.word 0x24 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x24 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x24 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x24 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x24 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x24 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x24 0.--2. " POF ,Port output function selection bit" "GPIO_P218,?..."
|
|
line.word 0x26 "PPC_PCFGR219,Port 2 Pin 19 Setting Register"
|
|
rbitfld.word 0x26 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x26 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x26 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x26 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x26 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x26 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x26 0.--2. " POF ,Port output function selection bit" "GPIO_P219,?..."
|
|
line.word 0x28 "PPC_PCFGR220,Port 2 Pin 20 Setting Register"
|
|
rbitfld.word 0x28 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x28 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x28 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x28 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x28 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x28 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x28 0.--2. " POF ,Port output function selection bit" "GPIO_P220,TIOA6,?..."
|
|
line.word 0x2A "PPC_PCFGR221,Port 2 Pin 21 Setting Register"
|
|
rbitfld.word 0x2A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x2A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x2A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x2A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x2A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x2A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x2A 0.--2. " POF ,Port output function selection bit" "GPIO_P221,?..."
|
|
line.word 0x2C "PPC_PCFGR222,Port 2 Pin 22 Setting Register"
|
|
rbitfld.word 0x2C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x2C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x2C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x2C 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x2C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x2C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x2C 0.--2. " POF ,Port output function selection bit" "GPIO_P222,TIOA7,?..."
|
|
line.word 0x2E "PPC_PCFGR223,Port 2 Pin 23 Setting Register"
|
|
rbitfld.word 0x2E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x2E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x2E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x2E 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x2E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x2E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x2E 0.--2. " POF ,Port output function selection bit" "GPIO_P223,?..."
|
|
line.word 0x30 "PPC_PCFGR224,Port 2 Pin 24 Setting Register"
|
|
rbitfld.word 0x30 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x30 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x30 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x30 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x30 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x30 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x30 0.--2. " POF ,Port output function selection bit" "GPIO_P224,?..."
|
|
line.word 0x32 "PPC_PCFGR225,Port 2 Pin 25 Setting Register"
|
|
rbitfld.word 0x32 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x32 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x32 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x32 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x32 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x32 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x32 0.--2. " POF ,Port output function selection bit" "GPIO_P225,?..."
|
|
line.word 0x34 "PPC_PCFGR226,Port 2 Pin 26 Setting Register"
|
|
rbitfld.word 0x34 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x34 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x34 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x34 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x34 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x34 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x34 0.--2. " POF ,Port output function selection bit" "GPIO_P226,SOT4,?..."
|
|
line.word 0x36 "PPC_PCFGR227,Port 2 Pin 27 Setting Register"
|
|
rbitfld.word 0x36 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x36 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x36 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x36 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x36 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x36 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x36 0.--2. " POF ,Port output function selection bit" "GPIO_P227,SCK4,?..."
|
|
line.word 0x38 "PPC_PCFGR228,Port 2 Pin 28 Setting Register"
|
|
rbitfld.word 0x38 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x38 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x38 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x38 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x38 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x38 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x38 0.--2. " POF ,Port output function selection bit" "GPIO_P228,SCS40,?..."
|
|
line.word 0x3A "PPC_PCFGR229,Port 2 Pin 29 Setting Register"
|
|
rbitfld.word 0x3A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x3A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x3A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x3A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x3A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x3A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x3A 0.--2. " POF ,Port output function selection bit" "GPIO_P229,SCS41,?..."
|
|
line.word 0x3C "PPC_PCFGR230,Port 2 Pin 30 Setting Register"
|
|
rbitfld.word 0x3C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x3C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x3C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x3C 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x3C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x3C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x3C 0.--2. " POF ,Port output function selection bit" "GPIO_P230,SCS42,?..."
|
|
line.word 0x3E "PPC_PCFGR231,Port 2 Pin 31 Setting Register"
|
|
rbitfld.word 0x3E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x3E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x3E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x3E 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x3E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x3E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x3E 0.--2. " POF ,Port output function selection bit" "GPIO_P231,SCS43,?..."
|
|
group.word 0xC0++0x01
|
|
line.word 0x00 "PPC_PCFGR300,Port 3 Pin 0 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P300,?..."
|
|
sif cpuis("MB9DF56?M*")
|
|
group.word 0xC2++0x0B
|
|
line.word 0x00 "PPC_PCFGR301,Port 3 Pin 1 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P301,TIOA10,?..."
|
|
line.word 0x02 "PPC_PCFGR302,Port 3 Pin 2 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P302,?..."
|
|
line.word 0x04 "PPC_PCFGR303,Port 3 Pin 3 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P303,TIOA11,?..."
|
|
line.word 0x06 "PPC_PCFGR304,Port 3 Pin 4 Setting Register"
|
|
rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x06 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "GPIO_P304,?..."
|
|
line.word 0x08 "PPC_PCFGR305,Port 3 Pin 5 Setting Register"
|
|
rbitfld.word 0x08 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x08 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x08 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x08 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x08 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x08 0.--2. " POF ,Port output function selection bit" "GPIO_P305,?..."
|
|
line.word 0x0A "PPC_PCFGR306,Port 3 Pin 6 Setting Register"
|
|
rbitfld.word 0x0A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0A 0.--2. " POF ,Port output function selection bit" "GPIO_P306,?..."
|
|
group.word 0xD2++0x09
|
|
line.word 0x00 "PPC_PCFGR309,Port 3 Pin 9 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P309,RTO13,?..."
|
|
line.word 0x02 "PPC_PCFGR310,Port 3 Pin 10 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P310,RTO14,?..."
|
|
line.word 0x04 "PPC_PCFGR311,Port 3 Pin 11 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P311,RTO15,?..."
|
|
line.word 0x06 "PPC_PCFGR312,Port 3 Pin 12 Setting Register"
|
|
rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x06 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "GPIO_P312,RTO16,?..."
|
|
line.word 0x08 "PPC_PCFGR313,Port 3 Pin 13 Setting Register"
|
|
rbitfld.word 0x08 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x08 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x08 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x08 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x08 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x08 0.--2. " POF ,Port output function selection bit" "GPIO_P313,RTO17,?..."
|
|
endif
|
|
group.word 0xDC++0x21
|
|
line.word 0x00 "PPC_PCFGR314,Port 3 Pin 14 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P314,TIOA0,?..."
|
|
line.word 0x02 "PPC_PCFGR315,Port 3 Pin 15 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P315,RTO18,?..."
|
|
line.word 0x04 "PPC_PCFGR316,Port 3 Pin 16 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P316,RTO19,TIOA1,?..."
|
|
line.word 0x06 "PPC_PCFGR317,Port 3 Pin 17 Setting Register"
|
|
rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x06 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "GPIO_P317,RTO20,?..."
|
|
line.word 0x08 "PPC_PCFGR318,Port 3 Pin 18 Setting Register"
|
|
rbitfld.word 0x08 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x08 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x08 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x08 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x08 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x08 0.--2. " POF ,Port output function selection bit" "GPIO_P318,RTO21,TIOA2,?..."
|
|
line.word 0x0A "PPC_PCFGR319,Port 3 Pin 19 Setting Register"
|
|
rbitfld.word 0x0A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0A 0.--2. " POF ,Port output function selection bit" "GPIO_P319,RTO22,?..."
|
|
line.word 0x0C "PPC_PCFGR320,Port 3 Pin 20 Setting Register"
|
|
rbitfld.word 0x0C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0C 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0C 0.--2. " POF ,Port output function selection bit" "GPIO_P320,RTO23,TIOA3,?..."
|
|
line.word 0x0E "PPC_PCFGR321,Port 3 Pin 21 Setting Register"
|
|
rbitfld.word 0x0E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0E 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0E 0.--2. " POF ,Port output function selection bit" "GPIO_P321,?..."
|
|
line.word 0x10 "PPC_PCFGR322,Port 3 Pin 22 Setting Register"
|
|
rbitfld.word 0x10 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x10 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x10 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x10 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x10 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x10 0.--2. " POF ,Port output function selection bit" "GPIO_P322,SOT0,?..."
|
|
line.word 0x12 "PPC_PCFGR323,Port 3 Pin 23 Setting Register"
|
|
rbitfld.word 0x12 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x12 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x12 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x12 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x12 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x12 0.--2. " POF ,Port output function selection bit" "GPIO_P323,SCK0,?..."
|
|
line.word 0x14 "PPC_PCFGR324,Port 3 Pin 24 Setting Register"
|
|
rbitfld.word 0x14 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x14 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x14 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x14 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x14 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x14 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x14 0.--2. " POF ,Port output function selection bit" "GPIO_P324,?..."
|
|
line.word 0x16 "PPC_PCFGR325,Port 3 Pin 25 Setting Register"
|
|
rbitfld.word 0x16 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x16 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x16 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x16 10.--11. " PIL ,Input level bit" "Automotive input,FlexRay input,?..."
|
|
textline " "
|
|
bitfld.word 0x16 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x16 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,4mA,?..."
|
|
bitfld.word 0x16 0.--2. " POF ,Port output function selection bit" "GPIO_P325,?..."
|
|
line.word 0x18 "PPC_PCFGR326,Port 3 Pin 26 Setting Register"
|
|
rbitfld.word 0x18 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x18 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x18 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x18 10.--11. " PIL ,Input level bit" "Automotive input,FlexRay input,?..."
|
|
textline " "
|
|
bitfld.word 0x18 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x18 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,4mA,?..."
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
bitfld.word 0x18 0.--2. " POF ,Port output function selection bit" "GPIO_P326,TXDA,?..."
|
|
else
|
|
bitfld.word 0x18 0.--2. " POF ,Port output function selection bit" "GPIO_P326,?..."
|
|
endif
|
|
line.word 0x1A "PPC_PCFGR327,Port 3 Pin 27 Setting Register"
|
|
rbitfld.word 0x1A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x1A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x1A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x1A 10.--11. " PIL ,Input level bit" "Automotive input,FlexRay input,?..."
|
|
textline " "
|
|
bitfld.word 0x1A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x1A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,4mA,?..."
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
bitfld.word 0x1A 0.--2. " POF ,Port output function selection bit" "GPIO_P327,TXENA,?..."
|
|
else
|
|
bitfld.word 0x1A 0.--2. " POF ,Port output function selection bit" "GPIO_P327,?..."
|
|
endif
|
|
line.word 0x1C "PPC_PCFGR328,Port 3 Pin 28 Setting Register"
|
|
rbitfld.word 0x1C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x1C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x1C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x1C 10.--11. " PIL ,Input level bit" "Automotive input,FlexRay input,?..."
|
|
textline " "
|
|
bitfld.word 0x1C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x1C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,4mA,?..."
|
|
bitfld.word 0x1C 0.--2. " POF ,Port output function selection bit" "GPIO_P328,?..."
|
|
line.word 0x1E "PPC_PCFGR329,Port 3 Pin 29 Setting Register"
|
|
rbitfld.word 0x1E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x1E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x1E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x1E 10.--11. " PIL ,Input level bit" "Automotive input,FlexRay input,?..."
|
|
textline " "
|
|
bitfld.word 0x1E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x1E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,4mA,?..."
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
bitfld.word 0x1E 0.--2. " POF ,Port output function selection bit" "GPIO_P329,TXDB,?..."
|
|
else
|
|
bitfld.word 0x1E 0.--2. " POF ,Port output function selection bit" "GPIO_P329,?..."
|
|
endif
|
|
line.word 0x20 "PPC_PCFGR330,Port 3 Pin 30 Setting Register"
|
|
rbitfld.word 0x20 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x20 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x20 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x20 10.--11. " PIL ,Input level bit" "Automotive input,FlexRay input,?..."
|
|
textline " "
|
|
bitfld.word 0x20 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x20 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,4mA,?..."
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
bitfld.word 0x20 0.--2. " POF ,Port output function selection bit" "GPIO_P330,TXENB,?..."
|
|
else
|
|
bitfld.word 0x20 0.--2. " POF ,Port output function selection bit" "GPIO_P330,?..."
|
|
endif
|
|
group.word 0x10C++0x11
|
|
line.word 0x00 "PPC_PCFGR406,Port 4 Pin 6 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P406,?..."
|
|
line.word 0x02 "PPC_PCFGR407,Port 4 Pin 7 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P407,SOT1,?..."
|
|
line.word 0x04 "PPC_PCFGR408,Port 4 Pin 8 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P408,SCK1,?..."
|
|
line.word 0x06 "PPC_PCFGR409,Port 4 Pin 9 Setting Register"
|
|
rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x06 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "GPIO_P409,?..."
|
|
line.word 0x08 "PPC_PCFGR410,Port 4 Pin 10 Setting Register"
|
|
rbitfld.word 0x08 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x08 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x08 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x08 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x08 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x08 0.--2. " POF ,Port output function selection bit" "GPIO_P410,TX0,?..."
|
|
line.word 0x0A "PPC_PCFGR411,Port 4 Pin 11 Setting Register"
|
|
rbitfld.word 0x0A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0A 0.--2. " POF ,Port output function selection bit" "GPIO_P411,?..."
|
|
line.word 0x0C "PPC_PCFGR412,Port 4 Pin 12 Setting Register"
|
|
rbitfld.word 0x0C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0C 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0C 0.--2. " POF ,Port output function selection bit" "GPIO_P412,TX1,?..."
|
|
line.word 0x0E "PPC_PCFGR413,Port 4 Pin 13 Setting Register"
|
|
rbitfld.word 0x0E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0E 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0E 0.--2. " POF ,Port output function selection bit" "GPIO_P413,?..."
|
|
line.word 0x10 "PPC_PCFGR414,Port 4 Pin 14 Setting Register"
|
|
rbitfld.word 0x10 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x10 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x10 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x10 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x10 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x10 0.--2. " POF ,Port output function selection bit" "GPIO_P414,TX2,?..."
|
|
sif cpuis("MB9DF56?M*")
|
|
group.word 0x11E++0x11
|
|
line.word 0x00 "PPC_PCFGR415,Port 4 Pin 15 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P415,TIOA4,?..."
|
|
line.word 0x02 "PPC_PCFGR416,Port 4 Pin 16 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P416,?..."
|
|
line.word 0x04 "PPC_PCFGR417,Port 4 Pin 17 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P417,TIOA5,?..."
|
|
line.word 0x06 "PPC_PCFGR418,Port 4 Pin 18 Setting Register"
|
|
rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x06 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "GPIO_P418,?..."
|
|
line.word 0x08 "PPC_PCFGR419,Port 4 Pin 19 Setting Register"
|
|
rbitfld.word 0x08 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x08 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x08 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x08 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x08 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x08 0.--2. " POF ,Port output function selection bit" "GPIO_P419,?..."
|
|
line.word 0x0A "PPC_PCFGR420,Port 4 Pin 20 Setting Register"
|
|
rbitfld.word 0x0A 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0A 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0A 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0A 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0A 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,4mA,?..."
|
|
bitfld.word 0x0A 0.--2. " POF ,Port output function selection bit" "GPIO_P420,SOT2,?..."
|
|
line.word 0x0C "PPC_PCFGR421,Port 4 Pin 21 Setting Register"
|
|
rbitfld.word 0x0C 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0C 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0C 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0C 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0C 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0C 0.--2. " POF ,Port output function selection bit" "GPIO_P421,?..."
|
|
line.word 0x0E "PPC_PCFGR422,Port 4 Pin 22 Setting Register"
|
|
rbitfld.word 0x0E 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x0E 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x0E 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x0E 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x0E 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x0E 0.--2. " POF ,Port output function selection bit" "GPIO_P422,SOT3,?..."
|
|
line.word 0x10 "PPC_PCFGR423,Port 4 Pin 23 Setting Register"
|
|
rbitfld.word 0x10 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x10 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x10 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x10 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x10 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x10 0.--2. " POF ,Port output function selection bit" "GPIO_P423,SCK3,?..."
|
|
group.word 0x132++0x07
|
|
line.word 0x00 "PPC_PCFGR425,Port 4 Pin 25 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P425,TIOA8,?..."
|
|
line.word 0x02 "PPC_PCFGR426,Port 4 Pin 26 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P426,?..."
|
|
line.word 0x04 "PPC_PCFGR427,Port 4 Pin 27 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P427,TIOA9,?..."
|
|
line.word 0x06 "PPC_PCFGR428,Port 4 Pin 28 Setting Register"
|
|
rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x06 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "GPIO_P428,?..."
|
|
endif
|
|
group.word 0x13A++0x05
|
|
line.word 0x00 "PPC_PCFGR429,Port 4 Pin 29 Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "GPIO_P429,MONCLK,MM,?..."
|
|
line.word 0x02 "PPC_PCFGR430,Port 4 Pin 30 Setting Register"
|
|
rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x02 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "GPIO_P430,ERDS0,?..."
|
|
line.word 0x04 "PPC_PCFGR431,Port 4 Pin 31 Setting Register"
|
|
rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x04 10.--11. " PIL ,Input level bit" "Automotive input,CMOS hysteresis input,?..."
|
|
textline " "
|
|
bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,?..."
|
|
bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "GPIO_P431,ERDS1,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "RIC (Resource Input Configuration)"
|
|
base ad:0xB0748000
|
|
width 16.
|
|
group.word 0x00++0x17
|
|
line.word 0x00 "RIC_RESIN0,Resource Input Setting Register 0"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,32-bit input capture ch.0 timer value input resource select" "32-bit free-run timer ch.0 32-bit timer counter output,32-bit free-run timer ch.1 32-bit timer counter output,32-bit free-run timer ch.2 32-bit timer counter output,32-bit free-run timer ch.3 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output"
|
|
line.word 0x02 "RIC_RESIN1,Resource Input Setting Register 1"
|
|
bitfld.word 0x02 0.--3. " RESSEL ,32-bit input capture ch.1 timer value input resource select" "32-bit free-run timer ch.0 32-bit timer counter output,32-bit free-run timer ch.1 32-bit timer counter output,32-bit free-run timer ch.2 32-bit timer counter output,32-bit free-run timer ch.3 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output"
|
|
line.word 0x04 "RIC_RESIN2,Resource Input Setting Register 2"
|
|
bitfld.word 0x04 0.--3. " RESSEL ,32-bit input capture ch.0 external input signal resource select" "External pin IN16,Multi-function serial interface ch.0 LIN sync detection signal,External pin IN16,External pin IN16,External pin IN16,External pin IN16,External pin IN16,External pin IN16,External pin IN16,External pin IN16,External pin IN16,External pin IN16,External pin IN16,External pin IN16,External pin IN16,External pin IN16"
|
|
line.word 0x06 "RIC_RESIN3,Resource Input Setting Register 3"
|
|
bitfld.word 0x06 0.--3. " RESSEL ,32-bit input capture ch.1 external input signal resource select" "External pin IN17,Multi-function serial interface ch.1 LIN sync detection signal,External pin IN17,External pin IN17,External pin IN17,External pin IN17,External pin IN17,External pin IN17,External pin IN17,External pin IN17,External pin IN17,External pin IN17,External pin IN17,External pin IN17,External pin IN17,External pin IN17"
|
|
line.word 0x08 "RIC_RESIN4,Resource Input Setting Register 4"
|
|
bitfld.word 0x08 0.--3. " RESSEL ,32-bit input capture ch.2. timer value input resource select" "32-bit free-run timer ch.0 32-bit timer counter output,32-bit free-run timer ch.1 32-bit timer counter output,32-bit free-run timer ch.2 32-bit timer counter output,32-bit free-run timer ch.3 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output"
|
|
line.word 0x0A "RIC_RESIN5,Resource Input Setting Register 5"
|
|
bitfld.word 0x0A 0.--3. " RESSEL ,32-bit input capture ch.3 timer value input resource select" "32-bit free-run timer ch.0 32-bit timer counter output,32-bit free-run timer ch.1 32-bit timer counter output,32-bit free-run timer ch.2 32-bit timer counter output,32-bit free-run timer ch.3 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output"
|
|
line.word 0x0C "RIC_RESIN6,Resource Input Setting Register 6"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.word 0x0C 0.--3. " RESSEL ,32-bit input capture ch.2 external input signal resource select" "External pin IN18,Multi-function serial interface ch.2 LIN sync detection signal,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18"
|
|
else
|
|
bitfld.word 0x0C 0.--3. " RESSEL ,32-bit input capture ch.2 external input signal resource select" "External pin IN18,,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18,External pin IN18"
|
|
endif
|
|
line.word 0x0E "RIC_RESIN7,Resource Input Setting Register 7"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.word 0x0E 0.--3. " RESSEL ,32-bit input capture ch.3 external input signal resource select" "External pin IN19,Multi-function serial interface ch.3 LIN sync detection signal,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19"
|
|
else
|
|
bitfld.word 0x0E 0.--3. " RESSEL ,32-bit input capture ch.3 external input signal resource select" "External pin IN19,,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19,External pin IN19"
|
|
endif
|
|
line.word 0x10 "RIC_RESIN8,Resource Input Setting Register 8"
|
|
bitfld.word 0x10 0.--3. " RESSEL ,32-bit input capture ch.4 timer value input resource select" "32-bit free-run timer ch.0 32-bit timer counter output,32-bit free-run timer ch.1 32-bit timer counter output,32-bit free-run timer ch.2 32-bit timer counter output,32-bit free-run timer ch.3 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output"
|
|
line.word 0x12 "RIC_RESIN9,Resource Input Setting Register 9"
|
|
bitfld.word 0x12 0.--3. " RESSEL ,32-bit input capture ch.5 timer value input resource select" "32-bit free-run timer ch.0 32-bit timer counter output,32-bit free-run timer ch.1 32-bit timer counter output,32-bit free-run timer ch.2 32-bit timer counter output,32-bit free-run timer ch.3 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output,32-bit free-run timer ch.4 32-bit timer counter output"
|
|
line.word 0x14 "RIC_RESIN10,Resource Input Setting Register 10"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.word 0x14 8. " PORTSEL ,External activation triggeer factor of base timer ch.0/2/4" "External pin input,Waveform generator 0 output"
|
|
else
|
|
bitfld.word 0x14 8. " PORTSEL ,External activation triggeer factor of base timer ch.0/2" "External pin input,Waveform generator 0 output"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x14 0.--3. " RESSEL ,32-bit input capture ch.4 external input signal resource select" "External pin IN20,Multi-function serial interface ch.4 LIN sync detection signal,External pin IN20,External pin IN20,External pin IN20,External pin IN20,External pin IN20,External pin IN20,External pin IN20,External pin IN20,External pin IN20,External pin IN20,External pin IN20,External pin IN20,External pin IN20,External pin IN20"
|
|
line.word 0x16 "RIC_RESIN11,Resource Input Setting Register 10"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.word 0x16 8. " PORTSEL ,External activation triggeer factor of base timer ch.6/8/10" "External pin input,Waveform generator 1 output"
|
|
else
|
|
bitfld.word 0x16 8. " PORTSEL ,External activation triggeer factor of base timer ch.6" "External pin input,Waveform generator 1 output"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x16 0.--3. " RESSEL ,32-bit input capture ch.5 external input signal resource select" "External pin IN21,External pin IN21,External pin IN21,External pin IN21,External pin IN21,External pin IN21,External pin IN21,External pin IN21,External pin IN21,External pin IN21,External pin IN21,External pin IN21,External pin IN21,External pin IN21,External pin IN21,External pin IN21"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "CR Calibration"
|
|
base ad:0xB0730000
|
|
width 8.
|
|
group.word 0x00++0x03
|
|
line.word 0x00 "CUCR1,Correction Unit Control Register 1"
|
|
bitfld.word 0x00 4. " STRT ,Calibration start" "Aborted,Started"
|
|
bitfld.word 0x00 1. " INT ,Calibration interrupt" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INTEN ,Calibration interrupt enable" "Disabled,Enabled"
|
|
line.word 0x02 "CUTD1,CR Clock Timer Data Register 1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CUTR1,Main Oscillation Timer Data Register 1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TDR ,Timer data"
|
|
group.long 0x08++0x03
|
|
line.long 0x0 "CUCRC1,Correction Unit Control Clear Register 1"
|
|
bitfld.long 0x00 1. " INTC ,Interrupt clear" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "CRC (Cyclic Redundancy Check)"
|
|
tree "Channel 0"
|
|
base ad:0xB0718000
|
|
width 9.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CRCCR,CRC Control Register"
|
|
bitfld.byte 0x00 6. " FXOR ,Final XOR control" "None,Available"
|
|
bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting" "MSB,LSB"
|
|
bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting" "Big,Little"
|
|
bitfld.byte 0x00 3. " LSBFST ,Bit order setting" "MSB,LSB"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LTLEND ,Byte order setting" "Big,Little"
|
|
bitfld.byte 0x00 1. " CRC32 ,CRC mode selection" "CRC16,CRC32"
|
|
bitfld.byte 0x00 0. " INIT ,Initialization" "No effect,Initialize"
|
|
if (((per.b(ad:0xB0718000))&0x02)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRCINIT,Initial Value Register"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRCINIT,Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value"
|
|
endif
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "CRCIN,Input Data Register"
|
|
if (((per.b(ad:0xB0718000))&0x12)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,CRC calculation result"
|
|
elif (((per.b(ad:0xB0718000))&0x12)==0x10)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " D ,CRC calculation result"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xB0718400
|
|
width 9.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CRCCR,CRC Control Register"
|
|
bitfld.byte 0x00 6. " FXOR ,Final XOR control" "None,Available"
|
|
bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting" "MSB,LSB"
|
|
bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting" "Big,Little"
|
|
bitfld.byte 0x00 3. " LSBFST ,Bit order setting" "MSB,LSB"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LTLEND ,Byte order setting" "Big,Little"
|
|
bitfld.byte 0x00 1. " CRC32 ,CRC mode selection" "CRC16,CRC32"
|
|
bitfld.byte 0x00 0. " INIT ,Initialization" "No effect,Initialize"
|
|
if (((per.b(ad:0xB0718400))&0x02)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRCINIT,Initial Value Register"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRCINIT,Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value"
|
|
endif
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "CRCIN,Input Data Register"
|
|
if (((per.b(ad:0xB0718400))&0x12)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,CRC calculation result"
|
|
elif (((per.b(ad:0xB0718400))&0x12)==0x10)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " D ,CRC calculation result"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "CAN"
|
|
tree "Channel 0"
|
|
base ad:0xB0720000
|
|
width 7.
|
|
rgroup.byte 0x0D0++0x00
|
|
line.byte 0x00 "CIRRR,CAN Interrupt Request Batch Read Register"
|
|
bitfld.byte 0x00 2. " ECCSEI ,Single-bit error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " ECCDEI ,Double-bit error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " CANINT ,CAN interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xB0720400
|
|
width 7.
|
|
rgroup.byte 0x0D0++0x00
|
|
line.byte 0x00 "CIRRR,CAN Interrupt Request Batch Read Register"
|
|
bitfld.byte 0x00 2. " ECCSEI ,Single-bit error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " ECCDEI ,Double-bit error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " CANINT ,CAN interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xB0720800
|
|
width 7.
|
|
rgroup.byte 0x0D0++0x00
|
|
line.byte 0x00 "CIRRR,CAN Interrupt Request Batch Read Register"
|
|
bitfld.byte 0x00 2. " ECCSEI ,Single-bit error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " ECCDEI ,Double-bit error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " CANINT ,CAN interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "CAN Controller"
|
|
tree "Channel 0"
|
|
base ad:0xB0720000
|
|
width 9.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CTRLR,CAN Control Register"
|
|
bitfld.word 0x00 7. " Test ,Test mode enable" "Normal,Test"
|
|
bitfld.word 0x00 6. " CCE ,Bit timing register write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " DAR ,Automatic retransmission disable" "No,Yes"
|
|
bitfld.word 0x00 3. " EIE ,Error interrupt code enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SIE ,Status interrupt code enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " INIT ,Initialization" "Operated,Initialization"
|
|
hgroup.word 0x02++0x01
|
|
hide.word 0x00 "STATR,CAN Status Register"
|
|
in
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "ERRCNT,CAN Error Counter"
|
|
bitfld.word 0x00 15. " RP ,Receive error passive indication" "Not passive,Passive"
|
|
hexmask.word.byte 0x00 8.--14. 1. " REC ,Receive error counter"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TEC ,Send error counter"
|
|
if (((per.l(ad:0xB0720000))&0x41)==0x41)
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "BTR,CAN Bit Timing Register"
|
|
bitfld.word 0x00 12.--14. " TSEG2 ,Time segment 2 setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--11. " TSEG1 ,Time segment 1 setting" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 6.--7. " SJW ,Resynchronization jump width setting" "0,1,2,3"
|
|
bitfld.word 0x00 0.--5. " BRP ,Baud rate prescaler setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.word 0x06++0x01
|
|
line.word 0x00 "BTR,CAN Bit Timing Register"
|
|
bitfld.word 0x00 12.--14. " TSEG2 ,Time segment 2 setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--11. " TSEG1 ,Time segment 1 setting" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 6.--7. " SJW ,Resynchronization jump width setting" "0,1,2,3"
|
|
bitfld.word 0x00 0.--5. " BRP ,Baud rate prescaler setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "INTR,CAN Interrupt Register"
|
|
group.word 0x0A++0x01
|
|
line.word 0x00 "TESTR,CAN Test Register"
|
|
bitfld.word 0x00 7. " RX ,RX pin monitor" "Dominant,Recessive"
|
|
bitfld.word 0x00 5.--6. " TX ,TX pin control" "Normal,Sampling,Dominant,Recessive"
|
|
bitfld.word 0x00 4. " LBACK ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BASIC ,Basic mode" "Disabled,Enabled"
|
|
if (((per.l(ad:0xB0720000))&0x41)==0x41)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "BRPER,CAN Prescaler Extended Register"
|
|
bitfld.word 0x00 0.--3. " BRPE ,Baud rate prescaler extension bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "BRPER,CAN Prescaler Extended Register"
|
|
bitfld.word 0x00 0.--3. " BRPE ,Baud rate prescaler extension bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "IF1CREQ,IF1 Command Request Register"
|
|
bitfld.word 0x00 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ,Message number (64 message objects)"
|
|
if (((per.w(ad:0xB0720000+0x10+0x02))&0x80)==0x80)
|
|
group.word (0x10+0x02)++0x01
|
|
line.word 0x00 "IF1CMSK,IF1 Command Mask Register"
|
|
bitfld.word 0x00 7. " WR/RD ,Writing or reading control" "Read,Written"
|
|
bitfld.word 0x00 6. " MASK ,Mask data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " ARB ,Arbitration data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " CONTROL ,Control data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CIP ,Interrupt clear bit" "0,1"
|
|
bitfld.word 0x00 2. " TXRQST/NEWDAT ,Message transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " DATAA ,Data0-Data3 update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " DATAB ,Data4-Data7 update" "Not updated,Updated"
|
|
else
|
|
group.word (0x10+0x02)++0x01
|
|
line.word 0x00 "IF1CMSK,IF1 Command Mask Register"
|
|
bitfld.word 0x00 7. " WR/RD ,Writing or reading control" "Read,Written"
|
|
bitfld.word 0x00 6. " MASK ,Mask data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " ARB ,Arbitration data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " CONTROL ,Control data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CIP ,Interrupt clear" "Not cleared,Cleared"
|
|
bitfld.word 0x00 2. " TXRQST/NEWDAT ,Message transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " DATAA ,Data0-Data3 update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " DATAB ,Data4-Data7 update" "Not updated,Updated"
|
|
endif
|
|
group.word (0x10+0x04)++0x09
|
|
line.word 0x00 "IF1MSK1,IF1 Mask Register 1"
|
|
line.word 0x02 "IF1MSK2,IF1 Mask Register 2"
|
|
bitfld.word 0x02 15. " MXTD ,Extension ID mask" "Masked,Not masked"
|
|
bitfld.word 0x02 14. " MDIR ,Message direction mask" "Masked,Not masked"
|
|
hexmask.word 0x02 0.--12. 1. " MSK ,ID mask"
|
|
line.word 0x04 "IF1ARB1,IF1 Arbitration Register 1"
|
|
line.word 0x06 "IF1ARB2,IF1 Arbitration Register 2"
|
|
bitfld.word 0x06 15. " MSGVAL ,Valid message" "Invalid,Valid"
|
|
bitfld.word 0x06 14. " XTD ,Extension ID enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 13. " DIR ,Message direction" "Rx,Tx"
|
|
hexmask.word 0x06 0.--12. 1. " ID ,Message ID"
|
|
line.word 0x08 "IF1MCTR,IF1 Message Control Register"
|
|
bitfld.word 0x08 15. " NEWDAT ,Data update" "Not updated,Updated"
|
|
bitfld.word 0x08 14. " MSGLST ,Message lost" "Not occurred,Occurred"
|
|
bitfld.word 0x08 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x08 12. " UMASK ,Acceptance mask enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x08 11. " TXIE ,Transmission interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 10. " RXIE ,Receiving interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 8. " TXRQST ,Transmission request" "Idle,Busy"
|
|
textline " "
|
|
bitfld.word 0x08 7. " EOB ,End of buffer" "Not last,Last"
|
|
bitfld.word 0x08 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.word (0x10+0x10)++0x07
|
|
line.word 0x00 "IF1DTA1,IF1 Data A Register 1"
|
|
line.word 0x02 "IF1DTA2,IF1 Data A Register 2"
|
|
line.word 0x04 "IF1DTB1,IF1 Data B Register 1"
|
|
line.word 0x06 "IF1DTB2,IF1 Data B Register 2"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "IF2CREQ,IF2 Command Request Register"
|
|
bitfld.word 0x00 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ,Message number (64 message objects)"
|
|
if (((per.w(ad:0xB0720000+0x40+0x02))&0x80)==0x80)
|
|
group.word (0x40+0x02)++0x01
|
|
line.word 0x00 "IF2CMSK,IF2 Command Mask Register"
|
|
bitfld.word 0x00 7. " WR/RD ,Writing or reading control" "Read,Written"
|
|
bitfld.word 0x00 6. " MASK ,Mask data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " ARB ,Arbitration data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " CONTROL ,Control data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CIP ,Interrupt clear bit" "0,1"
|
|
bitfld.word 0x00 2. " TXRQST/NEWDAT ,Message transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " DATAA ,Data0-Data3 update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " DATAB ,Data4-Data7 update" "Not updated,Updated"
|
|
else
|
|
group.word (0x40+0x02)++0x01
|
|
line.word 0x00 "IF2CMSK,IF2 Command Mask Register"
|
|
bitfld.word 0x00 7. " WR/RD ,Writing or reading control" "Read,Written"
|
|
bitfld.word 0x00 6. " MASK ,Mask data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " ARB ,Arbitration data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " CONTROL ,Control data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CIP ,Interrupt clear" "Not cleared,Cleared"
|
|
bitfld.word 0x00 2. " TXRQST/NEWDAT ,Message transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " DATAA ,Data0-Data3 update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " DATAB ,Data4-Data7 update" "Not updated,Updated"
|
|
endif
|
|
group.word (0x40+0x04)++0x09
|
|
line.word 0x00 "IF2MSK1,IF2 Mask Register 1"
|
|
line.word 0x02 "IF2MSK2,IF2 Mask Register 2"
|
|
bitfld.word 0x02 15. " MXTD ,Extension ID mask" "Masked,Not masked"
|
|
bitfld.word 0x02 14. " MDIR ,Message direction mask" "Masked,Not masked"
|
|
hexmask.word 0x02 0.--12. 1. " MSK ,ID mask"
|
|
line.word 0x04 "IF2ARB1,IF2 Arbitration Register 1"
|
|
line.word 0x06 "IF2ARB2,IF2 Arbitration Register 2"
|
|
bitfld.word 0x06 15. " MSGVAL ,Valid message" "Invalid,Valid"
|
|
bitfld.word 0x06 14. " XTD ,Extension ID enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 13. " DIR ,Message direction" "Rx,Tx"
|
|
hexmask.word 0x06 0.--12. 1. " ID ,Message ID"
|
|
line.word 0x08 "IF2MCTR,IF2 Message Control Register"
|
|
bitfld.word 0x08 15. " NEWDAT ,Data update" "Not updated,Updated"
|
|
bitfld.word 0x08 14. " MSGLST ,Message lost" "Not occurred,Occurred"
|
|
bitfld.word 0x08 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x08 12. " UMASK ,Acceptance mask enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x08 11. " TXIE ,Transmission interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 10. " RXIE ,Receiving interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 8. " TXRQST ,Transmission request" "Idle,Busy"
|
|
textline " "
|
|
bitfld.word 0x08 7. " EOB ,End of buffer" "Not last,Last"
|
|
bitfld.word 0x08 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.word (0x40+0x10)++0x07
|
|
line.word 0x00 "IF2DTA1,IF2 Data A Register 1"
|
|
line.word 0x02 "IF2DTA2,IF2 Data A Register 2"
|
|
line.word 0x04 "IF2DTB1,IF2 Data B Register 1"
|
|
line.word 0x06 "IF2DTB2,IF2 Data B Register 2"
|
|
textline " "
|
|
rgroup.word 0x80++0x07
|
|
line.word 0x00 "TREQ1,CAN Transmit Request Register 1"
|
|
bitfld.word 0x00 15. " TXRQST16 ,Message object 16 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 14. " TXRQST15 ,Message object 15 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 13. " TXRQST14 ,Message object 14 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " TXRQST13 ,Message object 13 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 11. " TXRQST12 ,Message object 12 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 10. " TXRQST11 ,Message object 11 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 9. " TXRQST10 ,Message object 10 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 8. " TXRQST9 ,Message object 9 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXRQST8 ,Message object 8 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 6. " TXRQST7 ,Message object 7 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 5. " TXRQST6 ,Message object 6 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " TXRQST5 ,Message object 5 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TXRQST4 ,Message object 4 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 2. " TXRQST3 ,Message object 3 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " TXRQST2 ,Message object 2 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 0. " TXRQST1 ,Message object 1 transmission request" "Not requested,Requested"
|
|
line.word 0x02 "TREQ2,CAN Transmit Request Register 2"
|
|
bitfld.word 0x02 15. " TXRQST32 ,Message object 32 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 14. " TXRQST31 ,Message object 31 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 13. " TXRQST30 ,Message object 30 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 12. " TXRQST29 ,Message object 29 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x02 11. " TXRQST28 ,Message object 28 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 10. " TXRQST27 ,Message object 27 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 9. " TXRQST26 ,Message object 26 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 8. " TXRQST25 ,Message object 25 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXRQST24 ,Message object 24 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 6. " TXRQST23 ,Message object 23 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 5. " TXRQST22 ,Message object 22 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 4. " TXRQST21 ,Message object 21 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x02 3. " TXRQST20 ,Message object 20 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 2. " TXRQST19 ,Message object 19 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 1. " TXRQST18 ,Message object 18 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 0. " TXRQST17 ,Message object 17 transmission request" "Not requested,Requested"
|
|
line.word 0x04 "TREQ3,CAN Transmit Request Register 3"
|
|
bitfld.word 0x04 15. " TXRQST48 ,Message object 48 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 14. " TXRQST47 ,Message object 47 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 13. " TXRQST46 ,Message object 46 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 12. " TXRQST45 ,Message object 45 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x04 11. " TXRQST44 ,Message object 44 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 10. " TXRQST43 ,Message object 43 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 9. " TXRQST42 ,Message object 42 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 8. " TXRQST41 ,Message object 41 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x04 7. " TXRQST40 ,Message object 40 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 6. " TXRQST39 ,Message object 39 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 5. " TXRQST38 ,Message object 38 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 4. " TXRQST37 ,Message object 37 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x04 3. " TXRQST36 ,Message object 36 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 2. " TXRQST35 ,Message object 35 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 1. " TXRQST34 ,Message object 34 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 0. " TXRQST33 ,Message object 33 transmission request" "Not requested,Requested"
|
|
line.word 0x06 "TREQ3,CAN Transmit Request Register 3"
|
|
bitfld.word 0x06 15. " TXRQST63 ,Message object 63 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 14. " TXRQST62 ,Message object 62 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 13. " TXRQST61 ,Message object 61 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 12. " TXRQST60 ,Message object 60 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x06 11. " TXRQST59 ,Message object 59 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 10. " TXRQST58 ,Message object 58 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 9. " TXRQST57 ,Message object 57 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 8. " TXRQST56 ,Message object 56 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x06 7. " TXRQST55 , Message object 55 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 6. " TXRQST54 ,Message object 54 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 5. " TXRQST53 ,Message object 53 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 4. " TXRQST52 ,Message object 52 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x06 3. " TXRQST51 ,Message object 51 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 2. " TXRQST50 ,Message object 50 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 1. " TXRQST49 ,Message object 49 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 0. " TXRQST48 ,Message object 48 transmission request" "Not requested,Requested"
|
|
rgroup.word (0x80+0x10)++0x07
|
|
line.word 0x00 "NEWDT1,CAN New Data Register 1"
|
|
bitfld.word 0x00 15. " NEWDAT16 ,Message object 16 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 14. " NEWDAT15 ,Message object 15 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 13. " NEWDAT14 ,Message object 14 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 12. " NEWDAT13 ,Message object 13 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 11. " NEWDAT12 ,Message object 12 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 10. " NEWDAT11 ,Message object 11 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 9. " NEWDAT10 ,Message object 10 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 8. " NEWDAT9 ,Message object 9 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NEWDAT8 ,Message object 8 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 6. " NEWDAT7 ,Message object 7 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " NEWDAT6 ,Message object 6 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " NEWDAT5 ,Message object 5 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NEWDAT4 ,Message object 4 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 2. " NEWDAT3 ,Message object 3 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 1. " NEWDAT2 ,Message object 2 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " NEWDAT1 ,Message object 1 data update" "Not updated,Updated"
|
|
line.word 0x02 "NEWDT2,CAN New Data Register 2"
|
|
bitfld.word 0x02 15. " NEWDAT32 ,Message object 32 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 14. " NEWDAT31 ,Message object 31 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 13. " NEWDAT30 ,Message object 30 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 12. " NEWDAT29 ,Message object 29 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x02 11. " NEWDAT28 ,Message object 28 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 10. " NEWDAT27 ,Message object 27 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 9. " NEWDAT26 ,Message object 26 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 8. " NEWDAT25 ,Message object 25 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x02 7. " NEWDAT24 ,Message object 24 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 6. " NEWDAT23 ,Message object 23 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 5. " NEWDAT22 ,Message object 22 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 4. " NEWDAT21 ,Message object 21 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x02 3. " NEWDAT20 ,Message object 20 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 2. " NEWDAT19 ,Message object 19 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 1. " NEWDAT18 ,Message object 18 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 0. " NEWDAT17 ,Message object 17 data update" "Not updated,Updated"
|
|
line.word 0x04 "NEWDT3,CAN New Data Register 3"
|
|
bitfld.word 0x04 15. " NEWDAT48 ,Message object 48 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 14. " NEWDAT47 ,Message object 47 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 13. " NEWDAT46 ,Message object 46 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 12. " NEWDAT45 ,Message object 45 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x04 11. " NEWDAT44 ,Message object 44 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 10. " NEWDAT43 ,Message object 43 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 9. " NEWDAT42 ,Message object 42 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 8. " NEWDAT41 ,Message object 41 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x04 7. " NEWDAT40 ,Message object 40 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 6. " NEWDAT39 ,Message object 39 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 5. " NEWDAT38 ,Message object 38 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 4. " NEWDAT37 ,Message object 37 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x04 3. " NEWDAT36 ,Message object 36 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 2. " NEWDAT35 ,Message object 35 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 1. " NEWDAT34 ,Message object 34 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 0. " NEWDAT33 ,Message object 33 data update" "Not updated,Updated"
|
|
line.word 0x06 "NEWDT4,CAN New Data Register 4"
|
|
bitfld.word 0x06 15. " NEWDAT63 ,Message object 63 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 14. " NEWDAT62 ,Message object 62 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 13. " NEWDAT61 ,Message object 61 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 12. " NEWDAT60 ,Message object 60 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x06 11. " NEWDAT59 ,Message object 59 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 10. " NEWDAT58 ,Message object 58 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 9. " NEWDAT57 ,Message object 57 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 8. " NEWDAT56 ,Message object 56 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x06 7. " NEWDAT55 ,Message object 55 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 6. " NEWDAT54 ,Message object 54 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 5. " NEWDAT53 ,Message object 53 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 4. " NEWDAT52 ,Message object 52 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x06 3. " NEWDAT51 ,Message object 51 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 2. " NEWDAT50 ,Message object 50 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 1. " NEWDAT49 ,Message object 49 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 0. " NEWDAT48 ,Message object 48 data update" "Not updated,Updated"
|
|
rgroup.word (0x80+0x20)++0x07
|
|
line.word 0x00 "INTPND1,CAN Interrupt Pending Register 1"
|
|
bitfld.word 0x00 15. " INTPND16 ,Message object 16 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 14. " INTPND15 ,Message object 15 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTPND14 ,Message object 14 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 12. " INTPND13 ,Message object 13 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 11. " INTPND12 ,Message object 12 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 10. " INTPND11 ,Message object 11 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 9. " INTPND10 ,Message object 10 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 8. " INTPND9 ,Message object 9 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " INTPND8 ,Message object 8 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " INTPND7 ,Message object 7 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " INTPND6 ,Message object 6 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 4. " INTPND5 ,Message object 5 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 3. " INTPND4 ,Message object 4 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 2. " INTPND3 ,Message object 3 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1. " INTPND2 ,Message object 2 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INTPND1 ,Message object 1 interrupt pending" "No interrupt,Interrupt"
|
|
line.word 0x02 "INTPND2,CAN Interrupt Pending Register 2"
|
|
bitfld.word 0x02 15. " INTPND32 ,Message object 32 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 14. " INTPND31 ,Message object 31 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 13. " INTPND30 ,Message object 30 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 12. " INTPND29 ,Message object 29 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x02 11. " INTPND28 ,Message object 28 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 10. " INTPND27 ,Message object 27 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 9. " INTPND26 ,Message object 26 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 8. " INTPND25 ,Message object 25 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x02 7. " INTPND24 ,Message object 24 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 6. " INTPND23 ,Message object 23 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 5. " INTPND22 ,Message object 22 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 4. " INTPND21 ,Message object 21 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x02 3. " INTPND20 ,Message object 20 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 2. " INTPND19 ,Message object 19 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 1. " INTPND18 ,Message object 18 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 0. " INTPND17 ,Message object 17 interrupt pending" "No interrupt,Interrupt"
|
|
line.word 0x04 "INTPND3,CAN Interrupt Pending Register 3"
|
|
bitfld.word 0x04 15. " INTPND48 ,Message object 48 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 14. " INTPND47 ,Message object 47 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 13. " INTPND46 ,Message object 46 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 12. " INTPND45 ,Message object 45 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 11. " INTPND44 ,Message object 44 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 10. " INTPND43 ,Message object 43 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 9. " INTPND42 ,Message object 42 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 8. " INTPND41 ,Message object 41 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 7. " INTPND40 ,Message object 40 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 6. " INTPND39 ,Message object 39 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 5. " INTPND38 ,Message object 38 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 4. " INTPND37 ,Message object 37 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 3. " INTPND36 ,Message object 36 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 2. " INTPND35 ,Message object 35 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 1. " INTPND34 ,Message object 34 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 0. " INTPND33 ,Message object 33 interrupt pending" "No interrupt,Interrupt"
|
|
line.word 0x06 "INTPND4,CAN Interrupt Pending Register 4"
|
|
bitfld.word 0x06 15. " INTPND64 ,Message object 64 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 14. " INTPND63 ,Message object 63 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 13. " INTPND62 ,Message object 62 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 12. " INTPND61 ,Message object 61 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x06 11. " INTPND60 ,Message object 60 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 10. " INTPND59 ,Message object 59 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 9. " INTPND58 ,Message object 58 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 8. " INTPND57 ,Message object 57 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x06 7. " INTPND56 ,Message object 56 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 6. " INTPND55 ,Message object 55 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 5. " INTPND54 ,Message object 54 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 4. " INTPND53 ,Message object 53 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x06 3. " INTPND52 ,Message object 52 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 2. " INTPND51 ,Message object 51 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 1. " INTPND50 ,Message object 50 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 0. " INTPND49 ,Message object 49 interrupt pending" "No interrupt,Interrupt"
|
|
rgroup.word (0x80+0x30)++0x07
|
|
line.word 0x00 "MSGVAL1,CAN Message Valid Register 1"
|
|
bitfld.word 0x00 15. " MSGVAL16 ,Message object 16 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 14. " MSGVAL15 ,Message object 15 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 13. " MSGVAL14 ,Message object 14 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 12. " MSGVAL13 ,Message object 13 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MSGVAL12 ,Message object 12 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 10. " MSGVAL11 ,Message object 11 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 9. " MSGVAL10 ,Message object 10 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 8. " MSGVAL9 ,Message object 9 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSGVAL8 ,Message object 8 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 6. " MSGVAL7 ,Message object 7 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 5. " MSGVAL6 ,Message object 6 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 4. " MSGVAL5 ,Message object 5 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MSGVAL4 ,Message object 4 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 2. " MSGVAL3 ,Message object 3 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 1. " MSGVAL2 ,Message object 2 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 0. " MSGVAL1 ,Message object 1 valid" "Invalid,Valid"
|
|
line.word 0x02 "MSGVAL2,CAN Message Valid Register 2"
|
|
bitfld.word 0x02 15. " MSGVAL32 ,Message object 32 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 14. " MSGVAL31 ,Message object 31 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 13. " MSGVAL30 ,Message object 30 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 12. " MSGVAL29 ,Message object 29 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x02 11. " MSGVAL28 ,Message object 28 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 10. " MSGVAL27 ,Message object 27 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 9. " MSGVAL26 ,Message object 26 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 8. " MSGVAL25 ,Message object 25 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x02 7. " MSGVAL24 ,Message object 24 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 6. " MSGVAl23 ,Message object 23 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 5. " MSGVAl22 ,Message object 22 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 4. " MSGVAl21 ,Message object 21 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x02 3. " MSGVAL20 ,Message object 20 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 2. " MSGVAL19 ,Message object 19 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 1. " MSGVAL18 ,Message object 18 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 0. " MSGVAL17 ,Message object 17 valid" "Invalid,Valid"
|
|
line.word 0x04 "MSGVAL3,CAN Message Valid Register 3"
|
|
bitfld.word 0x04 15. " MSGVAL48 ,Message object valid" "Invalid,Valid"
|
|
bitfld.word 0x04 14. " MSGVAL47 ,Message object 47 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 13. " MSGVAL46 ,Message object 46 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 12. " MSGVAL45 ,Message object 45 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x04 11. " MSGVAL44 ,Message object 44 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 10. " MSGVAL43 ,Message object 43 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 9. " MSGVAL42 ,Message object 42 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 8. " MSGVAL41 ,Message object 41 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x04 7. " MSGVAL40 ,Message object 40 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 6. " MSGVAL39 ,Message object 39 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 5. " MSGVAL38 ,Message object 38 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 4. " MSGVAL37 ,Message object 37 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x04 3. " MSGVAL36 ,Message object 36 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 2. " MSGVAL35 ,Message object 35 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 1. " MSGVAL34 ,Message object 34 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 0. " MSGVAL33 ,Message object 33 valid" "Invalid,Valid"
|
|
line.word 0x06 "MSGVAL4,CAN Message Valid Register 4"
|
|
bitfld.word 0x06 15. " MSGVAL64 ,Message object 64 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 14. " MSGVAL63 ,Message object 63 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 13. " MSGVAL62 ,Message object 62 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 12. " MSGVAL61 ,Message object 61 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x06 11. " MSGVAL60 ,Message object 60 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 10. " MSGVAL59 ,Message object 59 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 9. " MSGVAL58 ,Message object 58 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 8. " MSGVAL57 ,Message object 57 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x06 7. " MSGVAL56 ,Message object 56 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 6. " MSGVAL55 ,Message object 55 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 5. " MSGVAL54 ,Message object 54 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 4. " MSGVAL53 ,Message object 53 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x06 3. " MSGVAL52 ,Message object 52 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 2. " MSGVAL51 ,Message object 51 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 1. " MSGVAL50 ,Message object 50 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 0. " MSGVAL49 ,Message object 49 valid" "Invalid,Valid"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xB0720400
|
|
width 9.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CTRLR,CAN Control Register"
|
|
bitfld.word 0x00 7. " Test ,Test mode enable" "Normal,Test"
|
|
bitfld.word 0x00 6. " CCE ,Bit timing register write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " DAR ,Automatic retransmission disable" "No,Yes"
|
|
bitfld.word 0x00 3. " EIE ,Error interrupt code enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SIE ,Status interrupt code enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " INIT ,Initialization" "Operated,Initialization"
|
|
hgroup.word 0x02++0x01
|
|
hide.word 0x00 "STATR,CAN Status Register"
|
|
in
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "ERRCNT,CAN Error Counter"
|
|
bitfld.word 0x00 15. " RP ,Receive error passive indication" "Not passive,Passive"
|
|
hexmask.word.byte 0x00 8.--14. 1. " REC ,Receive error counter"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TEC ,Send error counter"
|
|
if (((per.l(ad:0xB0720400))&0x41)==0x41)
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "BTR,CAN Bit Timing Register"
|
|
bitfld.word 0x00 12.--14. " TSEG2 ,Time segment 2 setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--11. " TSEG1 ,Time segment 1 setting" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 6.--7. " SJW ,Resynchronization jump width setting" "0,1,2,3"
|
|
bitfld.word 0x00 0.--5. " BRP ,Baud rate prescaler setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.word 0x06++0x01
|
|
line.word 0x00 "BTR,CAN Bit Timing Register"
|
|
bitfld.word 0x00 12.--14. " TSEG2 ,Time segment 2 setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--11. " TSEG1 ,Time segment 1 setting" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 6.--7. " SJW ,Resynchronization jump width setting" "0,1,2,3"
|
|
bitfld.word 0x00 0.--5. " BRP ,Baud rate prescaler setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "INTR,CAN Interrupt Register"
|
|
group.word 0x0A++0x01
|
|
line.word 0x00 "TESTR,CAN Test Register"
|
|
bitfld.word 0x00 7. " RX ,RX pin monitor" "Dominant,Recessive"
|
|
bitfld.word 0x00 5.--6. " TX ,TX pin control" "Normal,Sampling,Dominant,Recessive"
|
|
bitfld.word 0x00 4. " LBACK ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BASIC ,Basic mode" "Disabled,Enabled"
|
|
if (((per.l(ad:0xB0720400))&0x41)==0x41)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "BRPER,CAN Prescaler Extended Register"
|
|
bitfld.word 0x00 0.--3. " BRPE ,Baud rate prescaler extension bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "BRPER,CAN Prescaler Extended Register"
|
|
bitfld.word 0x00 0.--3. " BRPE ,Baud rate prescaler extension bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "IF1CREQ,IF1 Command Request Register"
|
|
bitfld.word 0x00 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ,Message number (64 message objects)"
|
|
if (((per.w(ad:0xB0720400+0x10+0x02))&0x80)==0x80)
|
|
group.word (0x10+0x02)++0x01
|
|
line.word 0x00 "IF1CMSK,IF1 Command Mask Register"
|
|
bitfld.word 0x00 7. " WR/RD ,Writing or reading control" "Read,Written"
|
|
bitfld.word 0x00 6. " MASK ,Mask data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " ARB ,Arbitration data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " CONTROL ,Control data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CIP ,Interrupt clear bit" "0,1"
|
|
bitfld.word 0x00 2. " TXRQST/NEWDAT ,Message transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " DATAA ,Data0-Data3 update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " DATAB ,Data4-Data7 update" "Not updated,Updated"
|
|
else
|
|
group.word (0x10+0x02)++0x01
|
|
line.word 0x00 "IF1CMSK,IF1 Command Mask Register"
|
|
bitfld.word 0x00 7. " WR/RD ,Writing or reading control" "Read,Written"
|
|
bitfld.word 0x00 6. " MASK ,Mask data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " ARB ,Arbitration data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " CONTROL ,Control data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CIP ,Interrupt clear" "Not cleared,Cleared"
|
|
bitfld.word 0x00 2. " TXRQST/NEWDAT ,Message transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " DATAA ,Data0-Data3 update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " DATAB ,Data4-Data7 update" "Not updated,Updated"
|
|
endif
|
|
group.word (0x10+0x04)++0x09
|
|
line.word 0x00 "IF1MSK1,IF1 Mask Register 1"
|
|
line.word 0x02 "IF1MSK2,IF1 Mask Register 2"
|
|
bitfld.word 0x02 15. " MXTD ,Extension ID mask" "Masked,Not masked"
|
|
bitfld.word 0x02 14. " MDIR ,Message direction mask" "Masked,Not masked"
|
|
hexmask.word 0x02 0.--12. 1. " MSK ,ID mask"
|
|
line.word 0x04 "IF1ARB1,IF1 Arbitration Register 1"
|
|
line.word 0x06 "IF1ARB2,IF1 Arbitration Register 2"
|
|
bitfld.word 0x06 15. " MSGVAL ,Valid message" "Invalid,Valid"
|
|
bitfld.word 0x06 14. " XTD ,Extension ID enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 13. " DIR ,Message direction" "Rx,Tx"
|
|
hexmask.word 0x06 0.--12. 1. " ID ,Message ID"
|
|
line.word 0x08 "IF1MCTR,IF1 Message Control Register"
|
|
bitfld.word 0x08 15. " NEWDAT ,Data update" "Not updated,Updated"
|
|
bitfld.word 0x08 14. " MSGLST ,Message lost" "Not occurred,Occurred"
|
|
bitfld.word 0x08 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x08 12. " UMASK ,Acceptance mask enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x08 11. " TXIE ,Transmission interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 10. " RXIE ,Receiving interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 8. " TXRQST ,Transmission request" "Idle,Busy"
|
|
textline " "
|
|
bitfld.word 0x08 7. " EOB ,End of buffer" "Not last,Last"
|
|
bitfld.word 0x08 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.word (0x10+0x10)++0x07
|
|
line.word 0x00 "IF1DTA1,IF1 Data A Register 1"
|
|
line.word 0x02 "IF1DTA2,IF1 Data A Register 2"
|
|
line.word 0x04 "IF1DTB1,IF1 Data B Register 1"
|
|
line.word 0x06 "IF1DTB2,IF1 Data B Register 2"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "IF2CREQ,IF2 Command Request Register"
|
|
bitfld.word 0x00 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ,Message number (64 message objects)"
|
|
if (((per.w(ad:0xB0720400+0x40+0x02))&0x80)==0x80)
|
|
group.word (0x40+0x02)++0x01
|
|
line.word 0x00 "IF2CMSK,IF2 Command Mask Register"
|
|
bitfld.word 0x00 7. " WR/RD ,Writing or reading control" "Read,Written"
|
|
bitfld.word 0x00 6. " MASK ,Mask data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " ARB ,Arbitration data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " CONTROL ,Control data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CIP ,Interrupt clear bit" "0,1"
|
|
bitfld.word 0x00 2. " TXRQST/NEWDAT ,Message transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " DATAA ,Data0-Data3 update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " DATAB ,Data4-Data7 update" "Not updated,Updated"
|
|
else
|
|
group.word (0x40+0x02)++0x01
|
|
line.word 0x00 "IF2CMSK,IF2 Command Mask Register"
|
|
bitfld.word 0x00 7. " WR/RD ,Writing or reading control" "Read,Written"
|
|
bitfld.word 0x00 6. " MASK ,Mask data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " ARB ,Arbitration data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " CONTROL ,Control data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CIP ,Interrupt clear" "Not cleared,Cleared"
|
|
bitfld.word 0x00 2. " TXRQST/NEWDAT ,Message transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " DATAA ,Data0-Data3 update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " DATAB ,Data4-Data7 update" "Not updated,Updated"
|
|
endif
|
|
group.word (0x40+0x04)++0x09
|
|
line.word 0x00 "IF2MSK1,IF2 Mask Register 1"
|
|
line.word 0x02 "IF2MSK2,IF2 Mask Register 2"
|
|
bitfld.word 0x02 15. " MXTD ,Extension ID mask" "Masked,Not masked"
|
|
bitfld.word 0x02 14. " MDIR ,Message direction mask" "Masked,Not masked"
|
|
hexmask.word 0x02 0.--12. 1. " MSK ,ID mask"
|
|
line.word 0x04 "IF2ARB1,IF2 Arbitration Register 1"
|
|
line.word 0x06 "IF2ARB2,IF2 Arbitration Register 2"
|
|
bitfld.word 0x06 15. " MSGVAL ,Valid message" "Invalid,Valid"
|
|
bitfld.word 0x06 14. " XTD ,Extension ID enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 13. " DIR ,Message direction" "Rx,Tx"
|
|
hexmask.word 0x06 0.--12. 1. " ID ,Message ID"
|
|
line.word 0x08 "IF2MCTR,IF2 Message Control Register"
|
|
bitfld.word 0x08 15. " NEWDAT ,Data update" "Not updated,Updated"
|
|
bitfld.word 0x08 14. " MSGLST ,Message lost" "Not occurred,Occurred"
|
|
bitfld.word 0x08 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x08 12. " UMASK ,Acceptance mask enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x08 11. " TXIE ,Transmission interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 10. " RXIE ,Receiving interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 8. " TXRQST ,Transmission request" "Idle,Busy"
|
|
textline " "
|
|
bitfld.word 0x08 7. " EOB ,End of buffer" "Not last,Last"
|
|
bitfld.word 0x08 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.word (0x40+0x10)++0x07
|
|
line.word 0x00 "IF2DTA1,IF2 Data A Register 1"
|
|
line.word 0x02 "IF2DTA2,IF2 Data A Register 2"
|
|
line.word 0x04 "IF2DTB1,IF2 Data B Register 1"
|
|
line.word 0x06 "IF2DTB2,IF2 Data B Register 2"
|
|
textline " "
|
|
rgroup.word 0x80++0x07
|
|
line.word 0x00 "TREQ1,CAN Transmit Request Register 1"
|
|
bitfld.word 0x00 15. " TXRQST16 ,Message object 16 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 14. " TXRQST15 ,Message object 15 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 13. " TXRQST14 ,Message object 14 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " TXRQST13 ,Message object 13 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 11. " TXRQST12 ,Message object 12 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 10. " TXRQST11 ,Message object 11 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 9. " TXRQST10 ,Message object 10 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 8. " TXRQST9 ,Message object 9 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXRQST8 ,Message object 8 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 6. " TXRQST7 ,Message object 7 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 5. " TXRQST6 ,Message object 6 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " TXRQST5 ,Message object 5 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TXRQST4 ,Message object 4 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 2. " TXRQST3 ,Message object 3 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " TXRQST2 ,Message object 2 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 0. " TXRQST1 ,Message object 1 transmission request" "Not requested,Requested"
|
|
line.word 0x02 "TREQ2,CAN Transmit Request Register 2"
|
|
bitfld.word 0x02 15. " TXRQST32 ,Message object 32 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 14. " TXRQST31 ,Message object 31 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 13. " TXRQST30 ,Message object 30 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 12. " TXRQST29 ,Message object 29 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x02 11. " TXRQST28 ,Message object 28 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 10. " TXRQST27 ,Message object 27 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 9. " TXRQST26 ,Message object 26 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 8. " TXRQST25 ,Message object 25 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXRQST24 ,Message object 24 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 6. " TXRQST23 ,Message object 23 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 5. " TXRQST22 ,Message object 22 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 4. " TXRQST21 ,Message object 21 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x02 3. " TXRQST20 ,Message object 20 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 2. " TXRQST19 ,Message object 19 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 1. " TXRQST18 ,Message object 18 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 0. " TXRQST17 ,Message object 17 transmission request" "Not requested,Requested"
|
|
line.word 0x04 "TREQ3,CAN Transmit Request Register 3"
|
|
bitfld.word 0x04 15. " TXRQST48 ,Message object 48 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 14. " TXRQST47 ,Message object 47 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 13. " TXRQST46 ,Message object 46 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 12. " TXRQST45 ,Message object 45 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x04 11. " TXRQST44 ,Message object 44 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 10. " TXRQST43 ,Message object 43 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 9. " TXRQST42 ,Message object 42 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 8. " TXRQST41 ,Message object 41 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x04 7. " TXRQST40 ,Message object 40 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 6. " TXRQST39 ,Message object 39 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 5. " TXRQST38 ,Message object 38 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 4. " TXRQST37 ,Message object 37 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x04 3. " TXRQST36 ,Message object 36 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 2. " TXRQST35 ,Message object 35 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 1. " TXRQST34 ,Message object 34 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 0. " TXRQST33 ,Message object 33 transmission request" "Not requested,Requested"
|
|
line.word 0x06 "TREQ3,CAN Transmit Request Register 3"
|
|
bitfld.word 0x06 15. " TXRQST63 ,Message object 63 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 14. " TXRQST62 ,Message object 62 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 13. " TXRQST61 ,Message object 61 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 12. " TXRQST60 ,Message object 60 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x06 11. " TXRQST59 ,Message object 59 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 10. " TXRQST58 ,Message object 58 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 9. " TXRQST57 ,Message object 57 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 8. " TXRQST56 ,Message object 56 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x06 7. " TXRQST55 , Message object 55 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 6. " TXRQST54 ,Message object 54 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 5. " TXRQST53 ,Message object 53 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 4. " TXRQST52 ,Message object 52 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x06 3. " TXRQST51 ,Message object 51 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 2. " TXRQST50 ,Message object 50 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 1. " TXRQST49 ,Message object 49 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 0. " TXRQST48 ,Message object 48 transmission request" "Not requested,Requested"
|
|
rgroup.word (0x80+0x10)++0x07
|
|
line.word 0x00 "NEWDT1,CAN New Data Register 1"
|
|
bitfld.word 0x00 15. " NEWDAT16 ,Message object 16 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 14. " NEWDAT15 ,Message object 15 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 13. " NEWDAT14 ,Message object 14 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 12. " NEWDAT13 ,Message object 13 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 11. " NEWDAT12 ,Message object 12 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 10. " NEWDAT11 ,Message object 11 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 9. " NEWDAT10 ,Message object 10 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 8. " NEWDAT9 ,Message object 9 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NEWDAT8 ,Message object 8 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 6. " NEWDAT7 ,Message object 7 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " NEWDAT6 ,Message object 6 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " NEWDAT5 ,Message object 5 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NEWDAT4 ,Message object 4 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 2. " NEWDAT3 ,Message object 3 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 1. " NEWDAT2 ,Message object 2 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " NEWDAT1 ,Message object 1 data update" "Not updated,Updated"
|
|
line.word 0x02 "NEWDT2,CAN New Data Register 2"
|
|
bitfld.word 0x02 15. " NEWDAT32 ,Message object 32 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 14. " NEWDAT31 ,Message object 31 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 13. " NEWDAT30 ,Message object 30 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 12. " NEWDAT29 ,Message object 29 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x02 11. " NEWDAT28 ,Message object 28 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 10. " NEWDAT27 ,Message object 27 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 9. " NEWDAT26 ,Message object 26 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 8. " NEWDAT25 ,Message object 25 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x02 7. " NEWDAT24 ,Message object 24 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 6. " NEWDAT23 ,Message object 23 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 5. " NEWDAT22 ,Message object 22 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 4. " NEWDAT21 ,Message object 21 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x02 3. " NEWDAT20 ,Message object 20 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 2. " NEWDAT19 ,Message object 19 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 1. " NEWDAT18 ,Message object 18 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 0. " NEWDAT17 ,Message object 17 data update" "Not updated,Updated"
|
|
line.word 0x04 "NEWDT3,CAN New Data Register 3"
|
|
bitfld.word 0x04 15. " NEWDAT48 ,Message object 48 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 14. " NEWDAT47 ,Message object 47 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 13. " NEWDAT46 ,Message object 46 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 12. " NEWDAT45 ,Message object 45 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x04 11. " NEWDAT44 ,Message object 44 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 10. " NEWDAT43 ,Message object 43 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 9. " NEWDAT42 ,Message object 42 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 8. " NEWDAT41 ,Message object 41 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x04 7. " NEWDAT40 ,Message object 40 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 6. " NEWDAT39 ,Message object 39 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 5. " NEWDAT38 ,Message object 38 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 4. " NEWDAT37 ,Message object 37 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x04 3. " NEWDAT36 ,Message object 36 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 2. " NEWDAT35 ,Message object 35 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 1. " NEWDAT34 ,Message object 34 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 0. " NEWDAT33 ,Message object 33 data update" "Not updated,Updated"
|
|
line.word 0x06 "NEWDT4,CAN New Data Register 4"
|
|
bitfld.word 0x06 15. " NEWDAT63 ,Message object 63 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 14. " NEWDAT62 ,Message object 62 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 13. " NEWDAT61 ,Message object 61 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 12. " NEWDAT60 ,Message object 60 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x06 11. " NEWDAT59 ,Message object 59 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 10. " NEWDAT58 ,Message object 58 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 9. " NEWDAT57 ,Message object 57 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 8. " NEWDAT56 ,Message object 56 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x06 7. " NEWDAT55 ,Message object 55 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 6. " NEWDAT54 ,Message object 54 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 5. " NEWDAT53 ,Message object 53 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 4. " NEWDAT52 ,Message object 52 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x06 3. " NEWDAT51 ,Message object 51 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 2. " NEWDAT50 ,Message object 50 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 1. " NEWDAT49 ,Message object 49 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 0. " NEWDAT48 ,Message object 48 data update" "Not updated,Updated"
|
|
rgroup.word (0x80+0x20)++0x07
|
|
line.word 0x00 "INTPND1,CAN Interrupt Pending Register 1"
|
|
bitfld.word 0x00 15. " INTPND16 ,Message object 16 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 14. " INTPND15 ,Message object 15 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTPND14 ,Message object 14 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 12. " INTPND13 ,Message object 13 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 11. " INTPND12 ,Message object 12 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 10. " INTPND11 ,Message object 11 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 9. " INTPND10 ,Message object 10 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 8. " INTPND9 ,Message object 9 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " INTPND8 ,Message object 8 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " INTPND7 ,Message object 7 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " INTPND6 ,Message object 6 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 4. " INTPND5 ,Message object 5 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 3. " INTPND4 ,Message object 4 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 2. " INTPND3 ,Message object 3 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1. " INTPND2 ,Message object 2 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INTPND1 ,Message object 1 interrupt pending" "No interrupt,Interrupt"
|
|
line.word 0x02 "INTPND2,CAN Interrupt Pending Register 2"
|
|
bitfld.word 0x02 15. " INTPND32 ,Message object 32 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 14. " INTPND31 ,Message object 31 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 13. " INTPND30 ,Message object 30 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 12. " INTPND29 ,Message object 29 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x02 11. " INTPND28 ,Message object 28 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 10. " INTPND27 ,Message object 27 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 9. " INTPND26 ,Message object 26 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 8. " INTPND25 ,Message object 25 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x02 7. " INTPND24 ,Message object 24 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 6. " INTPND23 ,Message object 23 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 5. " INTPND22 ,Message object 22 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 4. " INTPND21 ,Message object 21 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x02 3. " INTPND20 ,Message object 20 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 2. " INTPND19 ,Message object 19 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 1. " INTPND18 ,Message object 18 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 0. " INTPND17 ,Message object 17 interrupt pending" "No interrupt,Interrupt"
|
|
line.word 0x04 "INTPND3,CAN Interrupt Pending Register 3"
|
|
bitfld.word 0x04 15. " INTPND48 ,Message object 48 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 14. " INTPND47 ,Message object 47 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 13. " INTPND46 ,Message object 46 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 12. " INTPND45 ,Message object 45 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 11. " INTPND44 ,Message object 44 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 10. " INTPND43 ,Message object 43 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 9. " INTPND42 ,Message object 42 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 8. " INTPND41 ,Message object 41 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 7. " INTPND40 ,Message object 40 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 6. " INTPND39 ,Message object 39 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 5. " INTPND38 ,Message object 38 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 4. " INTPND37 ,Message object 37 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 3. " INTPND36 ,Message object 36 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 2. " INTPND35 ,Message object 35 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 1. " INTPND34 ,Message object 34 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 0. " INTPND33 ,Message object 33 interrupt pending" "No interrupt,Interrupt"
|
|
line.word 0x06 "INTPND4,CAN Interrupt Pending Register 4"
|
|
bitfld.word 0x06 15. " INTPND64 ,Message object 64 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 14. " INTPND63 ,Message object 63 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 13. " INTPND62 ,Message object 62 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 12. " INTPND61 ,Message object 61 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x06 11. " INTPND60 ,Message object 60 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 10. " INTPND59 ,Message object 59 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 9. " INTPND58 ,Message object 58 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 8. " INTPND57 ,Message object 57 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x06 7. " INTPND56 ,Message object 56 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 6. " INTPND55 ,Message object 55 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 5. " INTPND54 ,Message object 54 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 4. " INTPND53 ,Message object 53 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x06 3. " INTPND52 ,Message object 52 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 2. " INTPND51 ,Message object 51 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 1. " INTPND50 ,Message object 50 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 0. " INTPND49 ,Message object 49 interrupt pending" "No interrupt,Interrupt"
|
|
rgroup.word (0x80+0x30)++0x07
|
|
line.word 0x00 "MSGVAL1,CAN Message Valid Register 1"
|
|
bitfld.word 0x00 15. " MSGVAL16 ,Message object 16 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 14. " MSGVAL15 ,Message object 15 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 13. " MSGVAL14 ,Message object 14 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 12. " MSGVAL13 ,Message object 13 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MSGVAL12 ,Message object 12 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 10. " MSGVAL11 ,Message object 11 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 9. " MSGVAL10 ,Message object 10 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 8. " MSGVAL9 ,Message object 9 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSGVAL8 ,Message object 8 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 6. " MSGVAL7 ,Message object 7 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 5. " MSGVAL6 ,Message object 6 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 4. " MSGVAL5 ,Message object 5 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MSGVAL4 ,Message object 4 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 2. " MSGVAL3 ,Message object 3 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 1. " MSGVAL2 ,Message object 2 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 0. " MSGVAL1 ,Message object 1 valid" "Invalid,Valid"
|
|
line.word 0x02 "MSGVAL2,CAN Message Valid Register 2"
|
|
bitfld.word 0x02 15. " MSGVAL32 ,Message object 32 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 14. " MSGVAL31 ,Message object 31 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 13. " MSGVAL30 ,Message object 30 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 12. " MSGVAL29 ,Message object 29 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x02 11. " MSGVAL28 ,Message object 28 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 10. " MSGVAL27 ,Message object 27 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 9. " MSGVAL26 ,Message object 26 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 8. " MSGVAL25 ,Message object 25 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x02 7. " MSGVAL24 ,Message object 24 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 6. " MSGVAl23 ,Message object 23 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 5. " MSGVAl22 ,Message object 22 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 4. " MSGVAl21 ,Message object 21 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x02 3. " MSGVAL20 ,Message object 20 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 2. " MSGVAL19 ,Message object 19 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 1. " MSGVAL18 ,Message object 18 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 0. " MSGVAL17 ,Message object 17 valid" "Invalid,Valid"
|
|
line.word 0x04 "MSGVAL3,CAN Message Valid Register 3"
|
|
bitfld.word 0x04 15. " MSGVAL48 ,Message object valid" "Invalid,Valid"
|
|
bitfld.word 0x04 14. " MSGVAL47 ,Message object 47 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 13. " MSGVAL46 ,Message object 46 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 12. " MSGVAL45 ,Message object 45 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x04 11. " MSGVAL44 ,Message object 44 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 10. " MSGVAL43 ,Message object 43 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 9. " MSGVAL42 ,Message object 42 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 8. " MSGVAL41 ,Message object 41 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x04 7. " MSGVAL40 ,Message object 40 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 6. " MSGVAL39 ,Message object 39 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 5. " MSGVAL38 ,Message object 38 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 4. " MSGVAL37 ,Message object 37 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x04 3. " MSGVAL36 ,Message object 36 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 2. " MSGVAL35 ,Message object 35 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 1. " MSGVAL34 ,Message object 34 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 0. " MSGVAL33 ,Message object 33 valid" "Invalid,Valid"
|
|
line.word 0x06 "MSGVAL4,CAN Message Valid Register 4"
|
|
bitfld.word 0x06 15. " MSGVAL64 ,Message object 64 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 14. " MSGVAL63 ,Message object 63 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 13. " MSGVAL62 ,Message object 62 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 12. " MSGVAL61 ,Message object 61 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x06 11. " MSGVAL60 ,Message object 60 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 10. " MSGVAL59 ,Message object 59 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 9. " MSGVAL58 ,Message object 58 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 8. " MSGVAL57 ,Message object 57 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x06 7. " MSGVAL56 ,Message object 56 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 6. " MSGVAL55 ,Message object 55 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 5. " MSGVAL54 ,Message object 54 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 4. " MSGVAL53 ,Message object 53 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x06 3. " MSGVAL52 ,Message object 52 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 2. " MSGVAL51 ,Message object 51 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 1. " MSGVAL50 ,Message object 50 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 0. " MSGVAL49 ,Message object 49 valid" "Invalid,Valid"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xB0720800
|
|
width 9.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CTRLR,CAN Control Register"
|
|
bitfld.word 0x00 7. " Test ,Test mode enable" "Normal,Test"
|
|
bitfld.word 0x00 6. " CCE ,Bit timing register write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " DAR ,Automatic retransmission disable" "No,Yes"
|
|
bitfld.word 0x00 3. " EIE ,Error interrupt code enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SIE ,Status interrupt code enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " INIT ,Initialization" "Operated,Initialization"
|
|
hgroup.word 0x02++0x01
|
|
hide.word 0x00 "STATR,CAN Status Register"
|
|
in
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "ERRCNT,CAN Error Counter"
|
|
bitfld.word 0x00 15. " RP ,Receive error passive indication" "Not passive,Passive"
|
|
hexmask.word.byte 0x00 8.--14. 1. " REC ,Receive error counter"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TEC ,Send error counter"
|
|
if (((per.l(ad:0xB0720800))&0x41)==0x41)
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "BTR,CAN Bit Timing Register"
|
|
bitfld.word 0x00 12.--14. " TSEG2 ,Time segment 2 setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--11. " TSEG1 ,Time segment 1 setting" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 6.--7. " SJW ,Resynchronization jump width setting" "0,1,2,3"
|
|
bitfld.word 0x00 0.--5. " BRP ,Baud rate prescaler setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.word 0x06++0x01
|
|
line.word 0x00 "BTR,CAN Bit Timing Register"
|
|
bitfld.word 0x00 12.--14. " TSEG2 ,Time segment 2 setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--11. " TSEG1 ,Time segment 1 setting" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 6.--7. " SJW ,Resynchronization jump width setting" "0,1,2,3"
|
|
bitfld.word 0x00 0.--5. " BRP ,Baud rate prescaler setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "INTR,CAN Interrupt Register"
|
|
group.word 0x0A++0x01
|
|
line.word 0x00 "TESTR,CAN Test Register"
|
|
bitfld.word 0x00 7. " RX ,RX pin monitor" "Dominant,Recessive"
|
|
bitfld.word 0x00 5.--6. " TX ,TX pin control" "Normal,Sampling,Dominant,Recessive"
|
|
bitfld.word 0x00 4. " LBACK ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BASIC ,Basic mode" "Disabled,Enabled"
|
|
if (((per.l(ad:0xB0720800))&0x41)==0x41)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "BRPER,CAN Prescaler Extended Register"
|
|
bitfld.word 0x00 0.--3. " BRPE ,Baud rate prescaler extension bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "BRPER,CAN Prescaler Extended Register"
|
|
bitfld.word 0x00 0.--3. " BRPE ,Baud rate prescaler extension bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "IF1CREQ,IF1 Command Request Register"
|
|
bitfld.word 0x00 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ,Message number (64 message objects)"
|
|
if (((per.w(ad:0xB0720800+0x10+0x02))&0x80)==0x80)
|
|
group.word (0x10+0x02)++0x01
|
|
line.word 0x00 "IF1CMSK,IF1 Command Mask Register"
|
|
bitfld.word 0x00 7. " WR/RD ,Writing or reading control" "Read,Written"
|
|
bitfld.word 0x00 6. " MASK ,Mask data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " ARB ,Arbitration data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " CONTROL ,Control data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CIP ,Interrupt clear bit" "0,1"
|
|
bitfld.word 0x00 2. " TXRQST/NEWDAT ,Message transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " DATAA ,Data0-Data3 update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " DATAB ,Data4-Data7 update" "Not updated,Updated"
|
|
else
|
|
group.word (0x10+0x02)++0x01
|
|
line.word 0x00 "IF1CMSK,IF1 Command Mask Register"
|
|
bitfld.word 0x00 7. " WR/RD ,Writing or reading control" "Read,Written"
|
|
bitfld.word 0x00 6. " MASK ,Mask data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " ARB ,Arbitration data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " CONTROL ,Control data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CIP ,Interrupt clear" "Not cleared,Cleared"
|
|
bitfld.word 0x00 2. " TXRQST/NEWDAT ,Message transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " DATAA ,Data0-Data3 update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " DATAB ,Data4-Data7 update" "Not updated,Updated"
|
|
endif
|
|
group.word (0x10+0x04)++0x09
|
|
line.word 0x00 "IF1MSK1,IF1 Mask Register 1"
|
|
line.word 0x02 "IF1MSK2,IF1 Mask Register 2"
|
|
bitfld.word 0x02 15. " MXTD ,Extension ID mask" "Masked,Not masked"
|
|
bitfld.word 0x02 14. " MDIR ,Message direction mask" "Masked,Not masked"
|
|
hexmask.word 0x02 0.--12. 1. " MSK ,ID mask"
|
|
line.word 0x04 "IF1ARB1,IF1 Arbitration Register 1"
|
|
line.word 0x06 "IF1ARB2,IF1 Arbitration Register 2"
|
|
bitfld.word 0x06 15. " MSGVAL ,Valid message" "Invalid,Valid"
|
|
bitfld.word 0x06 14. " XTD ,Extension ID enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 13. " DIR ,Message direction" "Rx,Tx"
|
|
hexmask.word 0x06 0.--12. 1. " ID ,Message ID"
|
|
line.word 0x08 "IF1MCTR,IF1 Message Control Register"
|
|
bitfld.word 0x08 15. " NEWDAT ,Data update" "Not updated,Updated"
|
|
bitfld.word 0x08 14. " MSGLST ,Message lost" "Not occurred,Occurred"
|
|
bitfld.word 0x08 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x08 12. " UMASK ,Acceptance mask enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x08 11. " TXIE ,Transmission interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 10. " RXIE ,Receiving interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 8. " TXRQST ,Transmission request" "Idle,Busy"
|
|
textline " "
|
|
bitfld.word 0x08 7. " EOB ,End of buffer" "Not last,Last"
|
|
bitfld.word 0x08 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.word (0x10+0x10)++0x07
|
|
line.word 0x00 "IF1DTA1,IF1 Data A Register 1"
|
|
line.word 0x02 "IF1DTA2,IF1 Data A Register 2"
|
|
line.word 0x04 "IF1DTB1,IF1 Data B Register 1"
|
|
line.word 0x06 "IF1DTB2,IF1 Data B Register 2"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "IF2CREQ,IF2 Command Request Register"
|
|
bitfld.word 0x00 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ,Message number (64 message objects)"
|
|
if (((per.w(ad:0xB0720800+0x40+0x02))&0x80)==0x80)
|
|
group.word (0x40+0x02)++0x01
|
|
line.word 0x00 "IF2CMSK,IF2 Command Mask Register"
|
|
bitfld.word 0x00 7. " WR/RD ,Writing or reading control" "Read,Written"
|
|
bitfld.word 0x00 6. " MASK ,Mask data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " ARB ,Arbitration data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " CONTROL ,Control data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CIP ,Interrupt clear bit" "0,1"
|
|
bitfld.word 0x00 2. " TXRQST/NEWDAT ,Message transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " DATAA ,Data0-Data3 update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " DATAB ,Data4-Data7 update" "Not updated,Updated"
|
|
else
|
|
group.word (0x40+0x02)++0x01
|
|
line.word 0x00 "IF2CMSK,IF2 Command Mask Register"
|
|
bitfld.word 0x00 7. " WR/RD ,Writing or reading control" "Read,Written"
|
|
bitfld.word 0x00 6. " MASK ,Mask data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " ARB ,Arbitration data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " CONTROL ,Control data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CIP ,Interrupt clear" "Not cleared,Cleared"
|
|
bitfld.word 0x00 2. " TXRQST/NEWDAT ,Message transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " DATAA ,Data0-Data3 update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " DATAB ,Data4-Data7 update" "Not updated,Updated"
|
|
endif
|
|
group.word (0x40+0x04)++0x09
|
|
line.word 0x00 "IF2MSK1,IF2 Mask Register 1"
|
|
line.word 0x02 "IF2MSK2,IF2 Mask Register 2"
|
|
bitfld.word 0x02 15. " MXTD ,Extension ID mask" "Masked,Not masked"
|
|
bitfld.word 0x02 14. " MDIR ,Message direction mask" "Masked,Not masked"
|
|
hexmask.word 0x02 0.--12. 1. " MSK ,ID mask"
|
|
line.word 0x04 "IF2ARB1,IF2 Arbitration Register 1"
|
|
line.word 0x06 "IF2ARB2,IF2 Arbitration Register 2"
|
|
bitfld.word 0x06 15. " MSGVAL ,Valid message" "Invalid,Valid"
|
|
bitfld.word 0x06 14. " XTD ,Extension ID enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 13. " DIR ,Message direction" "Rx,Tx"
|
|
hexmask.word 0x06 0.--12. 1. " ID ,Message ID"
|
|
line.word 0x08 "IF2MCTR,IF2 Message Control Register"
|
|
bitfld.word 0x08 15. " NEWDAT ,Data update" "Not updated,Updated"
|
|
bitfld.word 0x08 14. " MSGLST ,Message lost" "Not occurred,Occurred"
|
|
bitfld.word 0x08 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x08 12. " UMASK ,Acceptance mask enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x08 11. " TXIE ,Transmission interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 10. " RXIE ,Receiving interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 8. " TXRQST ,Transmission request" "Idle,Busy"
|
|
textline " "
|
|
bitfld.word 0x08 7. " EOB ,End of buffer" "Not last,Last"
|
|
bitfld.word 0x08 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.word (0x40+0x10)++0x07
|
|
line.word 0x00 "IF2DTA1,IF2 Data A Register 1"
|
|
line.word 0x02 "IF2DTA2,IF2 Data A Register 2"
|
|
line.word 0x04 "IF2DTB1,IF2 Data B Register 1"
|
|
line.word 0x06 "IF2DTB2,IF2 Data B Register 2"
|
|
textline " "
|
|
rgroup.word 0x80++0x07
|
|
line.word 0x00 "TREQ1,CAN Transmit Request Register 1"
|
|
bitfld.word 0x00 15. " TXRQST16 ,Message object 16 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 14. " TXRQST15 ,Message object 15 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 13. " TXRQST14 ,Message object 14 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " TXRQST13 ,Message object 13 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 11. " TXRQST12 ,Message object 12 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 10. " TXRQST11 ,Message object 11 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 9. " TXRQST10 ,Message object 10 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 8. " TXRQST9 ,Message object 9 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXRQST8 ,Message object 8 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 6. " TXRQST7 ,Message object 7 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 5. " TXRQST6 ,Message object 6 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " TXRQST5 ,Message object 5 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TXRQST4 ,Message object 4 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 2. " TXRQST3 ,Message object 3 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 1. " TXRQST2 ,Message object 2 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x00 0. " TXRQST1 ,Message object 1 transmission request" "Not requested,Requested"
|
|
line.word 0x02 "TREQ2,CAN Transmit Request Register 2"
|
|
bitfld.word 0x02 15. " TXRQST32 ,Message object 32 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 14. " TXRQST31 ,Message object 31 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 13. " TXRQST30 ,Message object 30 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 12. " TXRQST29 ,Message object 29 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x02 11. " TXRQST28 ,Message object 28 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 10. " TXRQST27 ,Message object 27 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 9. " TXRQST26 ,Message object 26 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 8. " TXRQST25 ,Message object 25 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXRQST24 ,Message object 24 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 6. " TXRQST23 ,Message object 23 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 5. " TXRQST22 ,Message object 22 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 4. " TXRQST21 ,Message object 21 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x02 3. " TXRQST20 ,Message object 20 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 2. " TXRQST19 ,Message object 19 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 1. " TXRQST18 ,Message object 18 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x02 0. " TXRQST17 ,Message object 17 transmission request" "Not requested,Requested"
|
|
line.word 0x04 "TREQ3,CAN Transmit Request Register 3"
|
|
bitfld.word 0x04 15. " TXRQST48 ,Message object 48 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 14. " TXRQST47 ,Message object 47 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 13. " TXRQST46 ,Message object 46 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 12. " TXRQST45 ,Message object 45 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x04 11. " TXRQST44 ,Message object 44 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 10. " TXRQST43 ,Message object 43 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 9. " TXRQST42 ,Message object 42 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 8. " TXRQST41 ,Message object 41 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x04 7. " TXRQST40 ,Message object 40 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 6. " TXRQST39 ,Message object 39 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 5. " TXRQST38 ,Message object 38 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 4. " TXRQST37 ,Message object 37 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x04 3. " TXRQST36 ,Message object 36 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 2. " TXRQST35 ,Message object 35 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 1. " TXRQST34 ,Message object 34 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x04 0. " TXRQST33 ,Message object 33 transmission request" "Not requested,Requested"
|
|
line.word 0x06 "TREQ3,CAN Transmit Request Register 3"
|
|
bitfld.word 0x06 15. " TXRQST63 ,Message object 63 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 14. " TXRQST62 ,Message object 62 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 13. " TXRQST61 ,Message object 61 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 12. " TXRQST60 ,Message object 60 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x06 11. " TXRQST59 ,Message object 59 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 10. " TXRQST58 ,Message object 58 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 9. " TXRQST57 ,Message object 57 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 8. " TXRQST56 ,Message object 56 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x06 7. " TXRQST55 , Message object 55 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 6. " TXRQST54 ,Message object 54 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 5. " TXRQST53 ,Message object 53 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 4. " TXRQST52 ,Message object 52 transmission request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x06 3. " TXRQST51 ,Message object 51 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 2. " TXRQST50 ,Message object 50 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 1. " TXRQST49 ,Message object 49 transmission request" "Not requested,Requested"
|
|
bitfld.word 0x06 0. " TXRQST48 ,Message object 48 transmission request" "Not requested,Requested"
|
|
rgroup.word (0x80+0x10)++0x07
|
|
line.word 0x00 "NEWDT1,CAN New Data Register 1"
|
|
bitfld.word 0x00 15. " NEWDAT16 ,Message object 16 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 14. " NEWDAT15 ,Message object 15 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 13. " NEWDAT14 ,Message object 14 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 12. " NEWDAT13 ,Message object 13 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 11. " NEWDAT12 ,Message object 12 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 10. " NEWDAT11 ,Message object 11 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 9. " NEWDAT10 ,Message object 10 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 8. " NEWDAT9 ,Message object 9 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NEWDAT8 ,Message object 8 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 6. " NEWDAT7 ,Message object 7 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 5. " NEWDAT6 ,Message object 6 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 4. " NEWDAT5 ,Message object 5 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NEWDAT4 ,Message object 4 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 2. " NEWDAT3 ,Message object 3 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 1. " NEWDAT2 ,Message object 2 data update" "Not updated,Updated"
|
|
bitfld.word 0x00 0. " NEWDAT1 ,Message object 1 data update" "Not updated,Updated"
|
|
line.word 0x02 "NEWDT2,CAN New Data Register 2"
|
|
bitfld.word 0x02 15. " NEWDAT32 ,Message object 32 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 14. " NEWDAT31 ,Message object 31 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 13. " NEWDAT30 ,Message object 30 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 12. " NEWDAT29 ,Message object 29 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x02 11. " NEWDAT28 ,Message object 28 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 10. " NEWDAT27 ,Message object 27 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 9. " NEWDAT26 ,Message object 26 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 8. " NEWDAT25 ,Message object 25 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x02 7. " NEWDAT24 ,Message object 24 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 6. " NEWDAT23 ,Message object 23 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 5. " NEWDAT22 ,Message object 22 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 4. " NEWDAT21 ,Message object 21 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x02 3. " NEWDAT20 ,Message object 20 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 2. " NEWDAT19 ,Message object 19 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 1. " NEWDAT18 ,Message object 18 data update" "Not updated,Updated"
|
|
bitfld.word 0x02 0. " NEWDAT17 ,Message object 17 data update" "Not updated,Updated"
|
|
line.word 0x04 "NEWDT3,CAN New Data Register 3"
|
|
bitfld.word 0x04 15. " NEWDAT48 ,Message object 48 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 14. " NEWDAT47 ,Message object 47 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 13. " NEWDAT46 ,Message object 46 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 12. " NEWDAT45 ,Message object 45 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x04 11. " NEWDAT44 ,Message object 44 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 10. " NEWDAT43 ,Message object 43 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 9. " NEWDAT42 ,Message object 42 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 8. " NEWDAT41 ,Message object 41 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x04 7. " NEWDAT40 ,Message object 40 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 6. " NEWDAT39 ,Message object 39 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 5. " NEWDAT38 ,Message object 38 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 4. " NEWDAT37 ,Message object 37 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x04 3. " NEWDAT36 ,Message object 36 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 2. " NEWDAT35 ,Message object 35 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 1. " NEWDAT34 ,Message object 34 data update" "Not updated,Updated"
|
|
bitfld.word 0x04 0. " NEWDAT33 ,Message object 33 data update" "Not updated,Updated"
|
|
line.word 0x06 "NEWDT4,CAN New Data Register 4"
|
|
bitfld.word 0x06 15. " NEWDAT63 ,Message object 63 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 14. " NEWDAT62 ,Message object 62 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 13. " NEWDAT61 ,Message object 61 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 12. " NEWDAT60 ,Message object 60 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x06 11. " NEWDAT59 ,Message object 59 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 10. " NEWDAT58 ,Message object 58 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 9. " NEWDAT57 ,Message object 57 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 8. " NEWDAT56 ,Message object 56 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x06 7. " NEWDAT55 ,Message object 55 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 6. " NEWDAT54 ,Message object 54 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 5. " NEWDAT53 ,Message object 53 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 4. " NEWDAT52 ,Message object 52 data update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.word 0x06 3. " NEWDAT51 ,Message object 51 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 2. " NEWDAT50 ,Message object 50 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 1. " NEWDAT49 ,Message object 49 data update" "Not updated,Updated"
|
|
bitfld.word 0x06 0. " NEWDAT48 ,Message object 48 data update" "Not updated,Updated"
|
|
rgroup.word (0x80+0x20)++0x07
|
|
line.word 0x00 "INTPND1,CAN Interrupt Pending Register 1"
|
|
bitfld.word 0x00 15. " INTPND16 ,Message object 16 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 14. " INTPND15 ,Message object 15 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTPND14 ,Message object 14 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 12. " INTPND13 ,Message object 13 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 11. " INTPND12 ,Message object 12 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 10. " INTPND11 ,Message object 11 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 9. " INTPND10 ,Message object 10 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 8. " INTPND9 ,Message object 9 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " INTPND8 ,Message object 8 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " INTPND7 ,Message object 7 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " INTPND6 ,Message object 6 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 4. " INTPND5 ,Message object 5 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 3. " INTPND4 ,Message object 4 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 2. " INTPND3 ,Message object 3 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1. " INTPND2 ,Message object 2 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INTPND1 ,Message object 1 interrupt pending" "No interrupt,Interrupt"
|
|
line.word 0x02 "INTPND2,CAN Interrupt Pending Register 2"
|
|
bitfld.word 0x02 15. " INTPND32 ,Message object 32 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 14. " INTPND31 ,Message object 31 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 13. " INTPND30 ,Message object 30 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 12. " INTPND29 ,Message object 29 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x02 11. " INTPND28 ,Message object 28 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 10. " INTPND27 ,Message object 27 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 9. " INTPND26 ,Message object 26 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 8. " INTPND25 ,Message object 25 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x02 7. " INTPND24 ,Message object 24 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 6. " INTPND23 ,Message object 23 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 5. " INTPND22 ,Message object 22 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 4. " INTPND21 ,Message object 21 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x02 3. " INTPND20 ,Message object 20 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 2. " INTPND19 ,Message object 19 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 1. " INTPND18 ,Message object 18 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 0. " INTPND17 ,Message object 17 interrupt pending" "No interrupt,Interrupt"
|
|
line.word 0x04 "INTPND3,CAN Interrupt Pending Register 3"
|
|
bitfld.word 0x04 15. " INTPND48 ,Message object 48 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 14. " INTPND47 ,Message object 47 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 13. " INTPND46 ,Message object 46 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 12. " INTPND45 ,Message object 45 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 11. " INTPND44 ,Message object 44 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 10. " INTPND43 ,Message object 43 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 9. " INTPND42 ,Message object 42 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 8. " INTPND41 ,Message object 41 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 7. " INTPND40 ,Message object 40 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 6. " INTPND39 ,Message object 39 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 5. " INTPND38 ,Message object 38 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 4. " INTPND37 ,Message object 37 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 3. " INTPND36 ,Message object 36 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 2. " INTPND35 ,Message object 35 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 1. " INTPND34 ,Message object 34 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 0. " INTPND33 ,Message object 33 interrupt pending" "No interrupt,Interrupt"
|
|
line.word 0x06 "INTPND4,CAN Interrupt Pending Register 4"
|
|
bitfld.word 0x06 15. " INTPND64 ,Message object 64 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 14. " INTPND63 ,Message object 63 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 13. " INTPND62 ,Message object 62 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 12. " INTPND61 ,Message object 61 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x06 11. " INTPND60 ,Message object 60 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 10. " INTPND59 ,Message object 59 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 9. " INTPND58 ,Message object 58 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 8. " INTPND57 ,Message object 57 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x06 7. " INTPND56 ,Message object 56 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 6. " INTPND55 ,Message object 55 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 5. " INTPND54 ,Message object 54 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 4. " INTPND53 ,Message object 53 interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x06 3. " INTPND52 ,Message object 52 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 2. " INTPND51 ,Message object 51 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 1. " INTPND50 ,Message object 50 interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.word 0x06 0. " INTPND49 ,Message object 49 interrupt pending" "No interrupt,Interrupt"
|
|
rgroup.word (0x80+0x30)++0x07
|
|
line.word 0x00 "MSGVAL1,CAN Message Valid Register 1"
|
|
bitfld.word 0x00 15. " MSGVAL16 ,Message object 16 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 14. " MSGVAL15 ,Message object 15 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 13. " MSGVAL14 ,Message object 14 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 12. " MSGVAL13 ,Message object 13 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MSGVAL12 ,Message object 12 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 10. " MSGVAL11 ,Message object 11 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 9. " MSGVAL10 ,Message object 10 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 8. " MSGVAL9 ,Message object 9 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSGVAL8 ,Message object 8 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 6. " MSGVAL7 ,Message object 7 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 5. " MSGVAL6 ,Message object 6 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 4. " MSGVAL5 ,Message object 5 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MSGVAL4 ,Message object 4 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 2. " MSGVAL3 ,Message object 3 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 1. " MSGVAL2 ,Message object 2 valid" "Invalid,Valid"
|
|
bitfld.word 0x00 0. " MSGVAL1 ,Message object 1 valid" "Invalid,Valid"
|
|
line.word 0x02 "MSGVAL2,CAN Message Valid Register 2"
|
|
bitfld.word 0x02 15. " MSGVAL32 ,Message object 32 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 14. " MSGVAL31 ,Message object 31 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 13. " MSGVAL30 ,Message object 30 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 12. " MSGVAL29 ,Message object 29 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x02 11. " MSGVAL28 ,Message object 28 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 10. " MSGVAL27 ,Message object 27 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 9. " MSGVAL26 ,Message object 26 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 8. " MSGVAL25 ,Message object 25 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x02 7. " MSGVAL24 ,Message object 24 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 6. " MSGVAl23 ,Message object 23 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 5. " MSGVAl22 ,Message object 22 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 4. " MSGVAl21 ,Message object 21 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x02 3. " MSGVAL20 ,Message object 20 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 2. " MSGVAL19 ,Message object 19 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 1. " MSGVAL18 ,Message object 18 valid" "Invalid,Valid"
|
|
bitfld.word 0x02 0. " MSGVAL17 ,Message object 17 valid" "Invalid,Valid"
|
|
line.word 0x04 "MSGVAL3,CAN Message Valid Register 3"
|
|
bitfld.word 0x04 15. " MSGVAL48 ,Message object valid" "Invalid,Valid"
|
|
bitfld.word 0x04 14. " MSGVAL47 ,Message object 47 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 13. " MSGVAL46 ,Message object 46 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 12. " MSGVAL45 ,Message object 45 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x04 11. " MSGVAL44 ,Message object 44 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 10. " MSGVAL43 ,Message object 43 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 9. " MSGVAL42 ,Message object 42 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 8. " MSGVAL41 ,Message object 41 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x04 7. " MSGVAL40 ,Message object 40 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 6. " MSGVAL39 ,Message object 39 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 5. " MSGVAL38 ,Message object 38 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 4. " MSGVAL37 ,Message object 37 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x04 3. " MSGVAL36 ,Message object 36 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 2. " MSGVAL35 ,Message object 35 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 1. " MSGVAL34 ,Message object 34 valid" "Invalid,Valid"
|
|
bitfld.word 0x04 0. " MSGVAL33 ,Message object 33 valid" "Invalid,Valid"
|
|
line.word 0x06 "MSGVAL4,CAN Message Valid Register 4"
|
|
bitfld.word 0x06 15. " MSGVAL64 ,Message object 64 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 14. " MSGVAL63 ,Message object 63 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 13. " MSGVAL62 ,Message object 62 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 12. " MSGVAL61 ,Message object 61 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x06 11. " MSGVAL60 ,Message object 60 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 10. " MSGVAL59 ,Message object 59 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 9. " MSGVAL58 ,Message object 58 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 8. " MSGVAL57 ,Message object 57 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x06 7. " MSGVAL56 ,Message object 56 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 6. " MSGVAL55 ,Message object 55 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 5. " MSGVAL54 ,Message object 54 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 4. " MSGVAL53 ,Message object 53 valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x06 3. " MSGVAL52 ,Message object 52 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 2. " MSGVAL51 ,Message object 51 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 1. " MSGVAL50 ,Message object 50 valid" "Invalid,Valid"
|
|
bitfld.word 0x06 0. " MSGVAL49 ,Message object 49 valid" "Invalid,Valid"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "CAN Message RAM ECC"
|
|
tree "Channel 0"
|
|
base ad:0xB0720000
|
|
width 17.
|
|
group.byte 0xC0++0x0
|
|
line.byte 0x00 "CANEECR,CAN ECC Error Control Register"
|
|
bitfld.byte 0x00 4. " CEIVEN ,ECC test disable allow" "No,Yes"
|
|
bitfld.byte 0x00 3. " DEIXS ,Double-bit error CAN stop" "Continued,Stopped"
|
|
bitfld.byte 0x00 2. " SEIXS ,Single-bit error CAN stop" "Continued,Stopped"
|
|
bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled"
|
|
rgroup.byte 0xC1++0x00
|
|
line.byte 0x00 "CANEESR,CAN ECC Error Status Register"
|
|
bitfld.byte 0x00 1. " DEI ,Double-bit error" "No error,Error"
|
|
bitfld.byte 0x00 0. " SEI ,Single-bit error" "No error,Error"
|
|
wgroup.byte 0xC5++0x00
|
|
line.byte 0x00 "CANEESCR,CAN ECC Error Status Clear Register"
|
|
bitfld.byte 0x00 1. " DEIC ,Double-bit error clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " SEIC ,Single-bit error clear" "No effect,Clear"
|
|
if (((per.l(ad:0xB0720000+0xC1))&0x02)==0x02)
|
|
rgroup.word 0xC6++0x01
|
|
line.word 0x00 "CANDEEAR,CAN ECC Double-bit Error Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " DMN ,Double error message number"
|
|
else
|
|
hgroup.word 0xC6++0x01
|
|
hide.word 0x00 "CANDEEAR,CAN ECC Double-bit Error Address Register"
|
|
endif
|
|
if (((per.l(ad:0xB0720000+0xC1))&0x01)==0x01)
|
|
rgroup.word 0xC2++0x01
|
|
line.word 0x00 "CANSEEAR,CAN ECC Single-bit Error Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " SMN ,Single error message number"
|
|
else
|
|
hgroup.word 0xC2++0x01
|
|
hide.word 0x00 "CANSEEAR,CAN ECC Single-bit Error Address Register"
|
|
endif
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CANEFECR,CAN ECC Error Insertion Control Register"
|
|
bitfld.long 0x00 31. " FERR ,Error insertion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " EY[9] ,Error byte specification bit 136-151" "No error,Error"
|
|
bitfld.long 0x00 24. " EY[8] ,Error byte specification bit 128-135" "No error,Error"
|
|
bitfld.long 0x00 23. " EY[7] ,Error byte specification bit 112-127" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EY[6] ,Error byte specification bit 96-111" "No error,Error"
|
|
bitfld.long 0x00 21. " EY[5] ,Error byte specification bit 80-95" "No error,Error"
|
|
bitfld.long 0x00 20. " EY[4] ,Error byte specification bit 64-79" "No error,Error"
|
|
bitfld.long 0x00 19. " EY[3] ,Error byte specification bit 48-63" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EY[2] ,Error byte specification bit 32-47" "No error,Error"
|
|
bitfld.long 0x00 17. " EY[1] ,Error byte specification bit 16-31" "No error,Error"
|
|
bitfld.long 0x00 16. " EY[0] ,Error byte specification bit 0-15" "No error,Error"
|
|
bitfld.long 0x00 15. " EI[15] ,Error bit specification bit 15" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EI[14] ,Error bit specification bit 14" "No error,Error"
|
|
bitfld.long 0x00 13. " EI[13] ,Error bit specification bit 13" "No error,Error"
|
|
bitfld.long 0x00 12. " EI[12] ,Error bit specification bit 12" "No error,Error"
|
|
bitfld.long 0x00 11. " EI[11] ,Error bit specification bit 11" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EI[10] ,Error bit specification bit 10" "No error,Error"
|
|
bitfld.long 0x00 9. " EI[9] ,Error bit specification bit 9" "No error,Error"
|
|
bitfld.long 0x00 8. " EI[8] ,Error bit specification bit 8" "No error,Error"
|
|
bitfld.long 0x00 7. " EI[7] ,Error bit specification bit 7" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EI[6] ,Error bit specification bit 6" "No error,Error"
|
|
bitfld.long 0x00 5. " EI[5] ,Error bit specification bit 5" "No error,Error"
|
|
bitfld.long 0x00 4. " EI[4] ,Error bit specification bit 4" "No error,Error"
|
|
bitfld.long 0x00 3. " EI[3] ,Error bit specification bit 3" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EI[2] ,Error bit specification bit 2" "No error,Error"
|
|
bitfld.long 0x00 1. " EI[1] ,Error bit specification bit 1" "No error,Error"
|
|
bitfld.long 0x00 0. " EI[0] ,Error bit specification bit 0" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xB0720400
|
|
width 17.
|
|
group.byte 0xC0++0x0
|
|
line.byte 0x00 "CANEECR,CAN ECC Error Control Register"
|
|
bitfld.byte 0x00 4. " CEIVEN ,ECC test disable allow" "No,Yes"
|
|
bitfld.byte 0x00 3. " DEIXS ,Double-bit error CAN stop" "Continued,Stopped"
|
|
bitfld.byte 0x00 2. " SEIXS ,Single-bit error CAN stop" "Continued,Stopped"
|
|
bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled"
|
|
rgroup.byte 0xC1++0x00
|
|
line.byte 0x00 "CANEESR,CAN ECC Error Status Register"
|
|
bitfld.byte 0x00 1. " DEI ,Double-bit error" "No error,Error"
|
|
bitfld.byte 0x00 0. " SEI ,Single-bit error" "No error,Error"
|
|
wgroup.byte 0xC5++0x00
|
|
line.byte 0x00 "CANEESCR,CAN ECC Error Status Clear Register"
|
|
bitfld.byte 0x00 1. " DEIC ,Double-bit error clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " SEIC ,Single-bit error clear" "No effect,Clear"
|
|
if (((per.l(ad:0xB0720400+0xC1))&0x02)==0x02)
|
|
rgroup.word 0xC6++0x01
|
|
line.word 0x00 "CANDEEAR,CAN ECC Double-bit Error Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " DMN ,Double error message number"
|
|
else
|
|
hgroup.word 0xC6++0x01
|
|
hide.word 0x00 "CANDEEAR,CAN ECC Double-bit Error Address Register"
|
|
endif
|
|
if (((per.l(ad:0xB0720400+0xC1))&0x01)==0x01)
|
|
rgroup.word 0xC2++0x01
|
|
line.word 0x00 "CANSEEAR,CAN ECC Single-bit Error Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " SMN ,Single error message number"
|
|
else
|
|
hgroup.word 0xC2++0x01
|
|
hide.word 0x00 "CANSEEAR,CAN ECC Single-bit Error Address Register"
|
|
endif
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CANEFECR,CAN ECC Error Insertion Control Register"
|
|
bitfld.long 0x00 31. " FERR ,Error insertion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " EY[9] ,Error byte specification bit 136-151" "No error,Error"
|
|
bitfld.long 0x00 24. " EY[8] ,Error byte specification bit 128-135" "No error,Error"
|
|
bitfld.long 0x00 23. " EY[7] ,Error byte specification bit 112-127" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EY[6] ,Error byte specification bit 96-111" "No error,Error"
|
|
bitfld.long 0x00 21. " EY[5] ,Error byte specification bit 80-95" "No error,Error"
|
|
bitfld.long 0x00 20. " EY[4] ,Error byte specification bit 64-79" "No error,Error"
|
|
bitfld.long 0x00 19. " EY[3] ,Error byte specification bit 48-63" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EY[2] ,Error byte specification bit 32-47" "No error,Error"
|
|
bitfld.long 0x00 17. " EY[1] ,Error byte specification bit 16-31" "No error,Error"
|
|
bitfld.long 0x00 16. " EY[0] ,Error byte specification bit 0-15" "No error,Error"
|
|
bitfld.long 0x00 15. " EI[15] ,Error bit specification bit 15" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EI[14] ,Error bit specification bit 14" "No error,Error"
|
|
bitfld.long 0x00 13. " EI[13] ,Error bit specification bit 13" "No error,Error"
|
|
bitfld.long 0x00 12. " EI[12] ,Error bit specification bit 12" "No error,Error"
|
|
bitfld.long 0x00 11. " EI[11] ,Error bit specification bit 11" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EI[10] ,Error bit specification bit 10" "No error,Error"
|
|
bitfld.long 0x00 9. " EI[9] ,Error bit specification bit 9" "No error,Error"
|
|
bitfld.long 0x00 8. " EI[8] ,Error bit specification bit 8" "No error,Error"
|
|
bitfld.long 0x00 7. " EI[7] ,Error bit specification bit 7" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EI[6] ,Error bit specification bit 6" "No error,Error"
|
|
bitfld.long 0x00 5. " EI[5] ,Error bit specification bit 5" "No error,Error"
|
|
bitfld.long 0x00 4. " EI[4] ,Error bit specification bit 4" "No error,Error"
|
|
bitfld.long 0x00 3. " EI[3] ,Error bit specification bit 3" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EI[2] ,Error bit specification bit 2" "No error,Error"
|
|
bitfld.long 0x00 1. " EI[1] ,Error bit specification bit 1" "No error,Error"
|
|
bitfld.long 0x00 0. " EI[0] ,Error bit specification bit 0" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xB0720800
|
|
width 17.
|
|
group.byte 0xC0++0x0
|
|
line.byte 0x00 "CANEECR,CAN ECC Error Control Register"
|
|
bitfld.byte 0x00 4. " CEIVEN ,ECC test disable allow" "No,Yes"
|
|
bitfld.byte 0x00 3. " DEIXS ,Double-bit error CAN stop" "Continued,Stopped"
|
|
bitfld.byte 0x00 2. " SEIXS ,Single-bit error CAN stop" "Continued,Stopped"
|
|
bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled"
|
|
rgroup.byte 0xC1++0x00
|
|
line.byte 0x00 "CANEESR,CAN ECC Error Status Register"
|
|
bitfld.byte 0x00 1. " DEI ,Double-bit error" "No error,Error"
|
|
bitfld.byte 0x00 0. " SEI ,Single-bit error" "No error,Error"
|
|
wgroup.byte 0xC5++0x00
|
|
line.byte 0x00 "CANEESCR,CAN ECC Error Status Clear Register"
|
|
bitfld.byte 0x00 1. " DEIC ,Double-bit error clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " SEIC ,Single-bit error clear" "No effect,Clear"
|
|
if (((per.l(ad:0xB0720800+0xC1))&0x02)==0x02)
|
|
rgroup.word 0xC6++0x01
|
|
line.word 0x00 "CANDEEAR,CAN ECC Double-bit Error Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " DMN ,Double error message number"
|
|
else
|
|
hgroup.word 0xC6++0x01
|
|
hide.word 0x00 "CANDEEAR,CAN ECC Double-bit Error Address Register"
|
|
endif
|
|
if (((per.l(ad:0xB0720800+0xC1))&0x01)==0x01)
|
|
rgroup.word 0xC2++0x01
|
|
line.word 0x00 "CANSEEAR,CAN ECC Single-bit Error Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " SMN ,Single error message number"
|
|
else
|
|
hgroup.word 0xC2++0x01
|
|
hide.word 0x00 "CANSEEAR,CAN ECC Single-bit Error Address Register"
|
|
endif
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CANEFECR,CAN ECC Error Insertion Control Register"
|
|
bitfld.long 0x00 31. " FERR ,Error insertion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " EY[9] ,Error byte specification bit 136-151" "No error,Error"
|
|
bitfld.long 0x00 24. " EY[8] ,Error byte specification bit 128-135" "No error,Error"
|
|
bitfld.long 0x00 23. " EY[7] ,Error byte specification bit 112-127" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EY[6] ,Error byte specification bit 96-111" "No error,Error"
|
|
bitfld.long 0x00 21. " EY[5] ,Error byte specification bit 80-95" "No error,Error"
|
|
bitfld.long 0x00 20. " EY[4] ,Error byte specification bit 64-79" "No error,Error"
|
|
bitfld.long 0x00 19. " EY[3] ,Error byte specification bit 48-63" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EY[2] ,Error byte specification bit 32-47" "No error,Error"
|
|
bitfld.long 0x00 17. " EY[1] ,Error byte specification bit 16-31" "No error,Error"
|
|
bitfld.long 0x00 16. " EY[0] ,Error byte specification bit 0-15" "No error,Error"
|
|
bitfld.long 0x00 15. " EI[15] ,Error bit specification bit 15" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EI[14] ,Error bit specification bit 14" "No error,Error"
|
|
bitfld.long 0x00 13. " EI[13] ,Error bit specification bit 13" "No error,Error"
|
|
bitfld.long 0x00 12. " EI[12] ,Error bit specification bit 12" "No error,Error"
|
|
bitfld.long 0x00 11. " EI[11] ,Error bit specification bit 11" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EI[10] ,Error bit specification bit 10" "No error,Error"
|
|
bitfld.long 0x00 9. " EI[9] ,Error bit specification bit 9" "No error,Error"
|
|
bitfld.long 0x00 8. " EI[8] ,Error bit specification bit 8" "No error,Error"
|
|
bitfld.long 0x00 7. " EI[7] ,Error bit specification bit 7" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EI[6] ,Error bit specification bit 6" "No error,Error"
|
|
bitfld.long 0x00 5. " EI[5] ,Error bit specification bit 5" "No error,Error"
|
|
bitfld.long 0x00 4. " EI[4] ,Error bit specification bit 4" "No error,Error"
|
|
bitfld.long 0x00 3. " EI[3] ,Error bit specification bit 3" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EI[2] ,Error bit specification bit 2" "No error,Error"
|
|
bitfld.long 0x00 1. " EI[1] ,Error bit specification bit 1" "No error,Error"
|
|
bitfld.long 0x00 0. " EI[0] ,Error bit specification bit 0" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "CAN Prescaler"
|
|
base ad:0xB0728000
|
|
width 8.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CANPRE,CAN Prescaler Control Register"
|
|
bitfld.long 0x00 4. " CPCKS ,CAN prescaler clock selection" "CANPLL clock,Main clock"
|
|
bitfld.long 0x00 0.--3. " CANPRE ,CAN prescaler setting" "/1,/2,/4,/4,/8,/8,/8,/8,2/3,/3,/6,/12,/5,/5,/10,/10"
|
|
line.long 0x04 "CANPCK,CAN PLL Clock Control Register"
|
|
bitfld.long 0x04 0.--4. " CANPCK ,Prescaler clock selections" "Disabled,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "MFS (Multi-function Serial Interface)"
|
|
tree "Channel 0"
|
|
base ad:0xB0800000
|
|
width 5.
|
|
if (((per.w(ad:0xB0800000))&0xE0)==((0x00||0x20)))
|
|
width 9.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
if (((per.b(ad:0xB0800000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.b(ad:0xB0800000+0x01))&0x03)==0x02)
|
|
if (((per.b(ad:0xB0800000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800000)&0xE0))==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0800000)&0xE0))==0x00)
|
|
if (((per.b(ad:0xB0800000+0x01))&0x01)==0x00)
|
|
if (((per.b(ad:0xB0800000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800000+0x01))&0x01)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,,,7-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,,,7-bit,?..."
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800000+0x03))&0x04)==0x04)
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.word 0x04++0x01
|
|
line.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800000+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800000+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800000+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0800000+0x01))&0x03)!=0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0800000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
if (((per.b(ad:0xB0800000+0x21))&0x04)==0x00)&&(((per.b(ad:0xB0800000+0x20))&0x03)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FE2_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FE1_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data number indication"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data number indication"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set the FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
elif (((per.w(ad:0xB0800000))&0xE0)==0x40)
|
|
width 9.
|
|
if (((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 6. " MS ,Master/slave function selection" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800000))&0x02)==0x00)
|
|
if (((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting " "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800000+0x01))&0x03)==0x00)&&(((per.b(ad:0xB0800000+0x03))&0x06)==0x02)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0800000+0x01))&0x40)==0x40)||(((per.w(ad:0xB0800000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set" "No effect,Set"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB0800000+0x03))&0x14)==0x04)
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
elif (((per.b(ad:0xB0800000+0x03))&0x14)==0x00)
|
|
wgroup.word 0x04++0x01
|
|
line.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
elif (((per.b(ad:0xB0800000+0x03))&0x14)==0x14)
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
textline " "
|
|
if (((per.w(ad:0xB0800000+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x38 13. 0x24 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800000+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x38 13. 0x24 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800000+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0800000+0x01))&0x03)!=0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0800000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention" "Not retained,Retained"
|
|
textline " "
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select 3 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select 1 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention" "Not retained,Retained"
|
|
textline " "
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select 3 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select 1 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SED ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800000+0x01))&0x43)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CSDS ,Serial chip deselect"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay"
|
|
elif (((per.b(ad:0xB0800000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CSDS ,Serial chip deselect"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay"
|
|
else
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800000+0x01))&0x40)==0x40)||(((per.b(ad:0xB0800000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB0800000+0x02))&0x20)==0x00)
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
else
|
|
if (((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS0CSLVL ,Chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS0SCINV ,Inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS0SPI ,Serial chip select pin 0 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS0BDS ,Transfer direction of chip select pin 0" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS0L ,Data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Serial chip select pin 1 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction of chip select pin 1" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,Serial chip select pin 2 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction of chip select pin 2" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS0CSLVL ,Chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS0SCINV ,Inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS0SPI ,Serial chip select pin 0 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS0BDS ,Transfer direction of chip select pin 0" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS0L ,Data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
rgroup.byte 0x15++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Serial chip select pin 1 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction of chip select pin 1" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
rgroup.byte 0x16++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,Serial chip select pin 2 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction of chip select pin 2" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800000+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x03
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
line.byte 0x01 "TBYTE1,Transfer Byte Register 1"
|
|
line.byte 0x02 "TBYTE2,Transfer Byte Register 2"
|
|
line.byte 0x03 "TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x03
|
|
hide.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
hide.byte 0x01 "TBYTE1,Transfer Byte Register 1"
|
|
hide.byte 0x02 "TBYTE2,Transfer Byte Register 2"
|
|
hide.byte 0x03 "TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag" "Not lost,lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving" "No effect,Save"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FE2_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FE1_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,Number of data items in FIFO2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,Number of data items in FIFO1"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,Number of data items in FIFO2"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,Number of data items in FIFO1"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clear the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
elif (((per.w(ad:0xB0800000))&0xE0)==0x60)
|
|
width 9.
|
|
if (((per.b(ad:0xB0800000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function select" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting" "No effect,Generate"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function select" "Master,Slave"
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800000+0x02))&0x40)==0x00)&&(((per.b(ad:0xB0800000+0x01))&0x01)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800000+0x02))&0x40)==0x40)&&(((per.b(ad:0xB0800000+0x01))&0x01)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800000+0x02))&0x40)==0x00)&&(((per.b(ad:0xB0800000+0x01))&0x01)==0x01)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " LBD ,LIN break field detection flag" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
if (((per.b(ad:0xB0800000+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB0800000+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. 5. " LBL ,LIN break field length selection" "13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection" "1-bit,2-bit,3-bit,4-bit"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. 5. " LBL ,LIN break field length selection" "13-bit,14-bit,15-bit,16-bit,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection" "1-bit,2-bit,3-bit,4-bit"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break Field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800000+0x03))&0x04)==0x04)
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.byte 0x04++0x00
|
|
line.byte 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800000+0x08))&0x2000)==0x2000)
|
|
if (((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
if (((per.w(ad:0xB0800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB0800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
if (((per.w(ad:0xB0800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB0800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0800000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800000+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit"
|
|
line.word 0x02 "SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit"
|
|
line.word 0x02 "SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
textline " "
|
|
if (((per.b(ad:0xB0800000+0x12))&0x01)==0x01)
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "LAMSR,LIN Assist Mode Status Register"
|
|
rbitfld.byte 0x00 7. " LER ,LIN representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 6. " SER ,Serial interface representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 5. " RDRF ,Reception data full flag" "Not full,Full"
|
|
rbitfld.byte 0x00 4. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag" "Not detected,Detected"
|
|
else
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "LAMSR,LIN Assist Mode Status Register"
|
|
rbitfld.byte 0x00 6. " SER ,Serial interface representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 5. " RDRF ,Reception data full flag" "Not full,Full"
|
|
rbitfld.byte 0x00 4. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 3. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0800000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800000+0x01))&0x40)==0x40)
|
|
if (((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting " "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "RDR,LAMTID"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting " "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "RDR,LAMTID"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800000+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "TDR,LAMTID"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "TDR,LAMTID"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
endif
|
|
endif
|
|
group.byte 0x19++0x0
|
|
line.byte 0x00 "LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xB0800000+0x12))&0x01)==0x01)
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800000+0x12))&0x01)==0x01)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800000+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Framing error pseudo error setting" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800000+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x20++0x0
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 , FIFO1 data number indication"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 , FIFO1 data number indication"
|
|
wgroup.byte 0x29++0x00
|
|
line.byte 0x00 "SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clear the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clear the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clear the transmission interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TBIEC ,Clear the transmission bus idle interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXEC ,Clear the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clear the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x28++0x00
|
|
line.byte 0x00 "SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 3. " SBLC ,Clear the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clear the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2B++0x00
|
|
line.byte 0x00 "SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clear the LIN break field detection flag bit" ",Clear"
|
|
wgroup.byte 0x2A++0x00
|
|
line.byte 0x00 "ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clear the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clear the LIN break field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clear the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clear the sync field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clear the sync field detection interrupt enable" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clear the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clear the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clear the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x33++0x00
|
|
line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clear the LIN checksum calculation completion flag bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clear the LIN auto header completion flag bit" ",Clear"
|
|
wgroup.byte 0x32++0x00
|
|
line.byte 0x00 "LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clear the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clear the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clear the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x35++0x00
|
|
line.byte 0x00 "LAMIERC,LIN Assist Mode Interrupt Enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clear the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clear the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clear the LIN sync data error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clear the LIN bus error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clear the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clear the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clear the LIN checksum error flag bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clear the LIN ID parity error flag bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clear the LIN Sync Data error flag bit" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clear the LIN bus error flag bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clear the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clear the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
bitfld.byte 0x00 1. " FTIEC ,Clear the transmission FIFO interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x38++0x00
|
|
line.byte 0x00 "FCR0C,FIFO Control Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clear the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clear the FIFO1 operation enable bit" ",Clear"
|
|
if (((per.b(ad:0xB0800000+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Set the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Set the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Set the LIN break field setting bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Set the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Set the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Set the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Set the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Set the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Set the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Set the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Set the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Set the transmission interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIES ,Set the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Set the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Set the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 3. " SBLS ,Set the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Set the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x3F++0x00
|
|
line.byte 0x00 "SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Set the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x3E++0x00
|
|
line.byte 0x00 "ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Set the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Set the LIN break field detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x40++0x01
|
|
line.word 0x00 "SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Set the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Set the sync field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Set the auto baud rate adjustment bit" ",Set"
|
|
bitfld.word 0x00 7. " TINTES ,Set the timer interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGES ,Set the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Set the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Set the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Set the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Set the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Set the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x49++0x00
|
|
line.byte 0x00 "LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERS ,Set the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERS ,Set the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERS ,Set the LIN sync data error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " LBSERS ,Set the LIN bus error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIES ,Set the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Set the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x4D++0x00
|
|
line.byte 0x00 "FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Set the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Set the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Set the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Set the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set the FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set the FIFO1 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FE2S ,Set the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Set the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMR,Serial Mode Register"
|
|
bitfld.word 0x00 5.--7. " MD ,Operation mode" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xB0800400
|
|
width 5.
|
|
if (((per.w(ad:0xB0800400))&0xE0)==((0x00||0x20)))
|
|
width 9.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
if (((per.b(ad:0xB0800400+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.b(ad:0xB0800400+0x01))&0x03)==0x02)
|
|
if (((per.b(ad:0xB0800400+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800400+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800400)&0xE0))==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0800400)&0xE0))==0x00)
|
|
if (((per.b(ad:0xB0800400+0x01))&0x01)==0x00)
|
|
if (((per.b(ad:0xB0800400+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800400+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800400+0x01))&0x01)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,,,7-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,,,7-bit,?..."
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800400+0x03))&0x04)==0x04)
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.word 0x04++0x01
|
|
line.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800400+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800400+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800400+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0800400+0x01))&0x03)!=0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0800400+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
if (((per.b(ad:0xB0800400+0x21))&0x04)==0x00)&&(((per.b(ad:0xB0800400+0x20))&0x03)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FE2_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FE1_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data number indication"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data number indication"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set the FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
elif (((per.w(ad:0xB0800400))&0xE0)==0x40)
|
|
width 9.
|
|
if (((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 6. " MS ,Master/slave function selection" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800400))&0x02)==0x00)
|
|
if (((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting " "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800400+0x01))&0x03)==0x00)&&(((per.b(ad:0xB0800400+0x03))&0x06)==0x02)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0800400+0x01))&0x40)==0x40)||(((per.w(ad:0xB0800400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set" "No effect,Set"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB0800400+0x03))&0x14)==0x04)
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
elif (((per.b(ad:0xB0800400+0x03))&0x14)==0x00)
|
|
wgroup.word 0x04++0x01
|
|
line.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
elif (((per.b(ad:0xB0800400+0x03))&0x14)==0x14)
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
textline " "
|
|
if (((per.w(ad:0xB0800400+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x38 13. 0x24 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800400+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x38 13. 0x24 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800400+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0800400+0x01))&0x03)!=0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0800400+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention" "Not retained,Retained"
|
|
textline " "
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select 3 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select 1 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention" "Not retained,Retained"
|
|
textline " "
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select 3 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select 1 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SED ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800400+0x01))&0x43)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CSDS ,Serial chip deselect"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay"
|
|
elif (((per.b(ad:0xB0800400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CSDS ,Serial chip deselect"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay"
|
|
else
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800400+0x01))&0x40)==0x40)||(((per.b(ad:0xB0800400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB0800400+0x02))&0x20)==0x00)
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
else
|
|
if (((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS0CSLVL ,Chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS0SCINV ,Inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS0SPI ,Serial chip select pin 0 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS0BDS ,Transfer direction of chip select pin 0" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS0L ,Data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Serial chip select pin 1 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction of chip select pin 1" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,Serial chip select pin 2 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction of chip select pin 2" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS0CSLVL ,Chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS0SCINV ,Inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS0SPI ,Serial chip select pin 0 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS0BDS ,Transfer direction of chip select pin 0" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS0L ,Data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
rgroup.byte 0x15++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Serial chip select pin 1 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction of chip select pin 1" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
rgroup.byte 0x16++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,Serial chip select pin 2 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction of chip select pin 2" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800400+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x03
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
line.byte 0x01 "TBYTE1,Transfer Byte Register 1"
|
|
line.byte 0x02 "TBYTE2,Transfer Byte Register 2"
|
|
line.byte 0x03 "TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x03
|
|
hide.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
hide.byte 0x01 "TBYTE1,Transfer Byte Register 1"
|
|
hide.byte 0x02 "TBYTE2,Transfer Byte Register 2"
|
|
hide.byte 0x03 "TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag" "Not lost,lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving" "No effect,Save"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FE2_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FE1_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,Number of data items in FIFO2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,Number of data items in FIFO1"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,Number of data items in FIFO2"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,Number of data items in FIFO1"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clear the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
elif (((per.w(ad:0xB0800400))&0xE0)==0x60)
|
|
width 9.
|
|
if (((per.b(ad:0xB0800400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function select" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting" "No effect,Generate"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function select" "Master,Slave"
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800400+0x02))&0x40)==0x00)&&(((per.b(ad:0xB0800400+0x01))&0x01)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800400+0x02))&0x40)==0x40)&&(((per.b(ad:0xB0800400+0x01))&0x01)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800400+0x02))&0x40)==0x00)&&(((per.b(ad:0xB0800400+0x01))&0x01)==0x01)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " LBD ,LIN break field detection flag" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
if (((per.b(ad:0xB0800400+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB0800400+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. 5. " LBL ,LIN break field length selection" "13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection" "1-bit,2-bit,3-bit,4-bit"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. 5. " LBL ,LIN break field length selection" "13-bit,14-bit,15-bit,16-bit,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection" "1-bit,2-bit,3-bit,4-bit"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break Field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800400+0x03))&0x04)==0x04)
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.byte 0x04++0x00
|
|
line.byte 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800400+0x08))&0x2000)==0x2000)
|
|
if (((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
if (((per.w(ad:0xB0800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB0800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
if (((per.w(ad:0xB0800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB0800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0800400+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800400+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit"
|
|
line.word 0x02 "SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit"
|
|
line.word 0x02 "SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
textline " "
|
|
if (((per.b(ad:0xB0800400+0x12))&0x01)==0x01)
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "LAMSR,LIN Assist Mode Status Register"
|
|
rbitfld.byte 0x00 7. " LER ,LIN representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 6. " SER ,Serial interface representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 5. " RDRF ,Reception data full flag" "Not full,Full"
|
|
rbitfld.byte 0x00 4. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag" "Not detected,Detected"
|
|
else
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "LAMSR,LIN Assist Mode Status Register"
|
|
rbitfld.byte 0x00 6. " SER ,Serial interface representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 5. " RDRF ,Reception data full flag" "Not full,Full"
|
|
rbitfld.byte 0x00 4. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 3. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0800400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800400+0x01))&0x40)==0x40)
|
|
if (((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting " "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "RDR,LAMTID"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting " "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "RDR,LAMTID"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800400+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "TDR,LAMTID"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "TDR,LAMTID"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
endif
|
|
endif
|
|
group.byte 0x19++0x0
|
|
line.byte 0x00 "LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xB0800400+0x12))&0x01)==0x01)
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800400+0x12))&0x01)==0x01)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800400+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Framing error pseudo error setting" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800400+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x20++0x0
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 , FIFO1 data number indication"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 , FIFO1 data number indication"
|
|
wgroup.byte 0x29++0x00
|
|
line.byte 0x00 "SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clear the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clear the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clear the transmission interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TBIEC ,Clear the transmission bus idle interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXEC ,Clear the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clear the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x28++0x00
|
|
line.byte 0x00 "SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 3. " SBLC ,Clear the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clear the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2B++0x00
|
|
line.byte 0x00 "SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clear the LIN break field detection flag bit" ",Clear"
|
|
wgroup.byte 0x2A++0x00
|
|
line.byte 0x00 "ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clear the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clear the LIN break field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clear the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clear the sync field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clear the sync field detection interrupt enable" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clear the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clear the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clear the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x33++0x00
|
|
line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clear the LIN checksum calculation completion flag bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clear the LIN auto header completion flag bit" ",Clear"
|
|
wgroup.byte 0x32++0x00
|
|
line.byte 0x00 "LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clear the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clear the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clear the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x35++0x00
|
|
line.byte 0x00 "LAMIERC,LIN Assist Mode Interrupt Enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clear the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clear the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clear the LIN sync data error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clear the LIN bus error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clear the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clear the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clear the LIN checksum error flag bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clear the LIN ID parity error flag bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clear the LIN Sync Data error flag bit" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clear the LIN bus error flag bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clear the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clear the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
bitfld.byte 0x00 1. " FTIEC ,Clear the transmission FIFO interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x38++0x00
|
|
line.byte 0x00 "FCR0C,FIFO Control Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clear the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clear the FIFO1 operation enable bit" ",Clear"
|
|
if (((per.b(ad:0xB0800400+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Set the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Set the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Set the LIN break field setting bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Set the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Set the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Set the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Set the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Set the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Set the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Set the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Set the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Set the transmission interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIES ,Set the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Set the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Set the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 3. " SBLS ,Set the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Set the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x3F++0x00
|
|
line.byte 0x00 "SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Set the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x3E++0x00
|
|
line.byte 0x00 "ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Set the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Set the LIN break field detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x40++0x01
|
|
line.word 0x00 "SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Set the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Set the sync field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Set the auto baud rate adjustment bit" ",Set"
|
|
bitfld.word 0x00 7. " TINTES ,Set the timer interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGES ,Set the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Set the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Set the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Set the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Set the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Set the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x49++0x00
|
|
line.byte 0x00 "LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERS ,Set the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERS ,Set the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERS ,Set the LIN sync data error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " LBSERS ,Set the LIN bus error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIES ,Set the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Set the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x4D++0x00
|
|
line.byte 0x00 "FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Set the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Set the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Set the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Set the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set the FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set the FIFO1 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FE2S ,Set the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Set the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMR,Serial Mode Register"
|
|
bitfld.word 0x00 5.--7. " MD ,Operation mode" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("MB9DF56?L*")
|
|
tree "Channel 2"
|
|
base ad:0xB0800800
|
|
width 5.
|
|
if (((per.w(ad:0xB0800800))&0xE0)==((0x00||0x20)))
|
|
width 9.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
if (((per.b(ad:0xB0800800+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.b(ad:0xB0800800+0x01))&0x03)==0x02)
|
|
if (((per.b(ad:0xB0800800+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800800+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800800)&0xE0))==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0800800)&0xE0))==0x00)
|
|
if (((per.b(ad:0xB0800800+0x01))&0x01)==0x00)
|
|
if (((per.b(ad:0xB0800800+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800800+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800800+0x01))&0x01)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,,,7-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,,,7-bit,?..."
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800800+0x03))&0x04)==0x04)
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.word 0x04++0x01
|
|
line.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800800+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800800+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800800+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0800800+0x01))&0x03)!=0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0800800+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
if (((per.b(ad:0xB0800800+0x21))&0x04)==0x00)&&(((per.b(ad:0xB0800800+0x20))&0x03)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FE2_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FE1_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data number indication"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data number indication"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set the FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
elif (((per.w(ad:0xB0800800))&0xE0)==0x40)
|
|
width 9.
|
|
if (((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 6. " MS ,Master/slave function selection" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800800))&0x02)==0x00)
|
|
if (((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting " "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800800+0x01))&0x03)==0x00)&&(((per.b(ad:0xB0800800+0x03))&0x06)==0x02)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0800800+0x01))&0x40)==0x40)||(((per.w(ad:0xB0800800+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set" "No effect,Set"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB0800800+0x03))&0x14)==0x04)
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
elif (((per.b(ad:0xB0800800+0x03))&0x14)==0x00)
|
|
wgroup.word 0x04++0x01
|
|
line.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
elif (((per.b(ad:0xB0800800+0x03))&0x14)==0x14)
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
textline " "
|
|
if (((per.w(ad:0xB0800800+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x38 13. 0x24 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800800+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x38 13. 0x24 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800800+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0800800+0x01))&0x03)!=0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0800800+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800800+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention" "Not retained,Retained"
|
|
textline " "
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select 3 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select 1 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention" "Not retained,Retained"
|
|
textline " "
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select 3 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select 1 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800800+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SED ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800800+0x01))&0x43)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CSDS ,Serial chip deselect"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay"
|
|
elif (((per.b(ad:0xB0800800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CSDS ,Serial chip deselect"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay"
|
|
else
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800800+0x01))&0x40)==0x40)||(((per.b(ad:0xB0800800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB0800800+0x02))&0x20)==0x00)
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
else
|
|
if (((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS0CSLVL ,Chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS0SCINV ,Inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS0SPI ,Serial chip select pin 0 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS0BDS ,Transfer direction of chip select pin 0" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS0L ,Data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Serial chip select pin 1 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction of chip select pin 1" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,Serial chip select pin 2 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction of chip select pin 2" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS0CSLVL ,Chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS0SCINV ,Inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS0SPI ,Serial chip select pin 0 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS0BDS ,Transfer direction of chip select pin 0" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS0L ,Data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
rgroup.byte 0x15++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Serial chip select pin 1 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction of chip select pin 1" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
rgroup.byte 0x16++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,Serial chip select pin 2 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction of chip select pin 2" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800800+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x03
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
line.byte 0x01 "TBYTE1,Transfer Byte Register 1"
|
|
line.byte 0x02 "TBYTE2,Transfer Byte Register 2"
|
|
line.byte 0x03 "TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x03
|
|
hide.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
hide.byte 0x01 "TBYTE1,Transfer Byte Register 1"
|
|
hide.byte 0x02 "TBYTE2,Transfer Byte Register 2"
|
|
hide.byte 0x03 "TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag" "Not lost,lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving" "No effect,Save"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FE2_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FE1_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,Number of data items in FIFO2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,Number of data items in FIFO1"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,Number of data items in FIFO2"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,Number of data items in FIFO1"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clear the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
elif (((per.w(ad:0xB0800800))&0xE0)==0x60)
|
|
width 9.
|
|
if (((per.b(ad:0xB0800800+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function select" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting" "No effect,Generate"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function select" "Master,Slave"
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800800+0x02))&0x40)==0x00)&&(((per.b(ad:0xB0800800+0x01))&0x01)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800800+0x02))&0x40)==0x40)&&(((per.b(ad:0xB0800800+0x01))&0x01)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800800+0x02))&0x40)==0x00)&&(((per.b(ad:0xB0800800+0x01))&0x01)==0x01)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " LBD ,LIN break field detection flag" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
if (((per.b(ad:0xB0800800+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB0800800+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. 5. " LBL ,LIN break field length selection" "13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection" "1-bit,2-bit,3-bit,4-bit"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. 5. " LBL ,LIN break field length selection" "13-bit,14-bit,15-bit,16-bit,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection" "1-bit,2-bit,3-bit,4-bit"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break Field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800800+0x03))&0x04)==0x04)
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.byte 0x04++0x00
|
|
line.byte 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800800+0x08))&0x2000)==0x2000)
|
|
if (((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
if (((per.w(ad:0xB0800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB0800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
if (((per.w(ad:0xB0800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB0800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0800800+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800800+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit"
|
|
line.word 0x02 "SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit"
|
|
line.word 0x02 "SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
textline " "
|
|
if (((per.b(ad:0xB0800800+0x12))&0x01)==0x01)
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "LAMSR,LIN Assist Mode Status Register"
|
|
rbitfld.byte 0x00 7. " LER ,LIN representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 6. " SER ,Serial interface representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 5. " RDRF ,Reception data full flag" "Not full,Full"
|
|
rbitfld.byte 0x00 4. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag" "Not detected,Detected"
|
|
else
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "LAMSR,LIN Assist Mode Status Register"
|
|
rbitfld.byte 0x00 6. " SER ,Serial interface representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 5. " RDRF ,Reception data full flag" "Not full,Full"
|
|
rbitfld.byte 0x00 4. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 3. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0800800+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800800+0x01))&0x40)==0x40)
|
|
if (((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting " "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "RDR,LAMTID"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting " "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "RDR,LAMTID"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800800+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "TDR,LAMTID"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "TDR,LAMTID"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
endif
|
|
endif
|
|
group.byte 0x19++0x0
|
|
line.byte 0x00 "LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xB0800800+0x12))&0x01)==0x01)
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800800+0x12))&0x01)==0x01)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800800+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Framing error pseudo error setting" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800800+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x20++0x0
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 , FIFO1 data number indication"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 , FIFO1 data number indication"
|
|
wgroup.byte 0x29++0x00
|
|
line.byte 0x00 "SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clear the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clear the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clear the transmission interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TBIEC ,Clear the transmission bus idle interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXEC ,Clear the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clear the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x28++0x00
|
|
line.byte 0x00 "SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 3. " SBLC ,Clear the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clear the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2B++0x00
|
|
line.byte 0x00 "SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clear the LIN break field detection flag bit" ",Clear"
|
|
wgroup.byte 0x2A++0x00
|
|
line.byte 0x00 "ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clear the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clear the LIN break field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clear the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clear the sync field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clear the sync field detection interrupt enable" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clear the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clear the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clear the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x33++0x00
|
|
line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clear the LIN checksum calculation completion flag bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clear the LIN auto header completion flag bit" ",Clear"
|
|
wgroup.byte 0x32++0x00
|
|
line.byte 0x00 "LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clear the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clear the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clear the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x35++0x00
|
|
line.byte 0x00 "LAMIERC,LIN Assist Mode Interrupt Enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clear the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clear the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clear the LIN sync data error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clear the LIN bus error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clear the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clear the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clear the LIN checksum error flag bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clear the LIN ID parity error flag bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clear the LIN Sync Data error flag bit" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clear the LIN bus error flag bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clear the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clear the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
bitfld.byte 0x00 1. " FTIEC ,Clear the transmission FIFO interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x38++0x00
|
|
line.byte 0x00 "FCR0C,FIFO Control Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clear the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clear the FIFO1 operation enable bit" ",Clear"
|
|
if (((per.b(ad:0xB0800800+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Set the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Set the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Set the LIN break field setting bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Set the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Set the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Set the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Set the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Set the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Set the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Set the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Set the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Set the transmission interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIES ,Set the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Set the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Set the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 3. " SBLS ,Set the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Set the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x3F++0x00
|
|
line.byte 0x00 "SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Set the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x3E++0x00
|
|
line.byte 0x00 "ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Set the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Set the LIN break field detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x40++0x01
|
|
line.word 0x00 "SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Set the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Set the sync field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Set the auto baud rate adjustment bit" ",Set"
|
|
bitfld.word 0x00 7. " TINTES ,Set the timer interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGES ,Set the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Set the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Set the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Set the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Set the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Set the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x49++0x00
|
|
line.byte 0x00 "LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERS ,Set the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERS ,Set the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERS ,Set the LIN sync data error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " LBSERS ,Set the LIN bus error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIES ,Set the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Set the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x4D++0x00
|
|
line.byte 0x00 "FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Set the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Set the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Set the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Set the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set the FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set the FIFO1 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FE2S ,Set the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Set the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMR,Serial Mode Register"
|
|
bitfld.word 0x00 5.--7. " MD ,Operation mode" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0xB0800C00
|
|
width 5.
|
|
if (((per.w(ad:0xB0800C00))&0xE0)==((0x00||0x20)))
|
|
width 9.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
if (((per.b(ad:0xB0800C00+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.b(ad:0xB0800C00+0x01))&0x03)==0x02)
|
|
if (((per.b(ad:0xB0800C00+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800C00+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800C00)&0xE0))==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0800C00)&0xE0))==0x00)
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x01)==0x00)
|
|
if (((per.b(ad:0xB0800C00+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800C00+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x01)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,,,7-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,,,7-bit,?..."
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800C00+0x03))&0x04)==0x04)
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.word 0x04++0x01
|
|
line.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800C00+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800C00+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800C00+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0800C00+0x01))&0x03)!=0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0800C00+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
if (((per.b(ad:0xB0800C00+0x21))&0x04)==0x00)&&(((per.b(ad:0xB0800C00+0x20))&0x03)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FE2_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FE1_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data number indication"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data number indication"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set the FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
elif (((per.w(ad:0xB0800C00))&0xE0)==0x40)
|
|
width 9.
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 6. " MS ,Master/slave function selection" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800C00))&0x02)==0x00)
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting " "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)&&(((per.b(ad:0xB0800C00+0x03))&0x06)==0x02)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB0800C00+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set" "No effect,Set"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB0800C00+0x03))&0x14)==0x04)
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
elif (((per.b(ad:0xB0800C00+0x03))&0x14)==0x00)
|
|
wgroup.word 0x04++0x01
|
|
line.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
elif (((per.b(ad:0xB0800C00+0x03))&0x14)==0x14)
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
textline " "
|
|
if (((per.w(ad:0xB0800C00+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x38 13. 0x24 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800C00+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x38 13. 0x24 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0800C00+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0800C00+0x01))&0x03)!=0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0800C00+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention" "Not retained,Retained"
|
|
textline " "
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select 3 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select 1 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention" "Not retained,Retained"
|
|
textline " "
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select 3 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select 1 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800C00+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SED ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x43)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CSDS ,Serial chip deselect"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay"
|
|
elif (((per.b(ad:0xB0800C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CSDS ,Serial chip deselect"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay"
|
|
else
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x40)==0x40)||(((per.b(ad:0xB0800C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB0800C00+0x02))&0x20)==0x00)
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
else
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS0CSLVL ,Chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS0SCINV ,Inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS0SPI ,Serial chip select pin 0 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS0BDS ,Transfer direction of chip select pin 0" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS0L ,Data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Serial chip select pin 1 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction of chip select pin 1" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,Serial chip select pin 2 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction of chip select pin 2" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS0CSLVL ,Chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS0SCINV ,Inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS0SPI ,Serial chip select pin 0 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS0BDS ,Transfer direction of chip select pin 0" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS0L ,Data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
rgroup.byte 0x15++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Serial chip select pin 1 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction of chip select pin 1" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
rgroup.byte 0x16++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,Serial chip select pin 2 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction of chip select pin 2" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x03
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
line.byte 0x01 "TBYTE1,Transfer Byte Register 1"
|
|
line.byte 0x02 "TBYTE2,Transfer Byte Register 2"
|
|
line.byte 0x03 "TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x03
|
|
hide.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
hide.byte 0x01 "TBYTE1,Transfer Byte Register 1"
|
|
hide.byte 0x02 "TBYTE2,Transfer Byte Register 2"
|
|
hide.byte 0x03 "TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag" "Not lost,lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving" "No effect,Save"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FE2_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FE1_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,Number of data items in FIFO2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,Number of data items in FIFO1"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,Number of data items in FIFO2"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,Number of data items in FIFO1"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clear the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
elif (((per.w(ad:0xB0800C00))&0xE0)==0x60)
|
|
width 9.
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function select" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting" "No effect,Generate"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function select" "Master,Slave"
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800C00+0x02))&0x40)==0x00)&&(((per.b(ad:0xB0800C00+0x01))&0x01)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800C00+0x02))&0x40)==0x40)&&(((per.b(ad:0xB0800C00+0x01))&0x01)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0800C00+0x02))&0x40)==0x00)&&(((per.b(ad:0xB0800C00+0x01))&0x01)==0x01)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " LBD ,LIN break field detection flag" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB0800C00+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. 5. " LBL ,LIN break field length selection" "13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection" "1-bit,2-bit,3-bit,4-bit"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. 5. " LBL ,LIN break field length selection" "13-bit,14-bit,15-bit,16-bit,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection" "1-bit,2-bit,3-bit,4-bit"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break Field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0800C00+0x03))&0x04)==0x04)
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.byte 0x04++0x00
|
|
line.byte 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800C00+0x08))&0x2000)==0x2000)
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
if (((per.w(ad:0xB0800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB0800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
if (((per.w(ad:0xB0800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB0800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0800C00+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800C00+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit"
|
|
line.word 0x02 "SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit"
|
|
line.word 0x02 "SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
textline " "
|
|
if (((per.b(ad:0xB0800C00+0x12))&0x01)==0x01)
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "LAMSR,LIN Assist Mode Status Register"
|
|
rbitfld.byte 0x00 7. " LER ,LIN representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 6. " SER ,Serial interface representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 5. " RDRF ,Reception data full flag" "Not full,Full"
|
|
rbitfld.byte 0x00 4. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag" "Not detected,Detected"
|
|
else
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "LAMSR,LIN Assist Mode Status Register"
|
|
rbitfld.byte 0x00 6. " SER ,Serial interface representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 5. " RDRF ,Reception data full flag" "Not full,Full"
|
|
rbitfld.byte 0x00 4. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 3. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0800C00+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x40)==0x40)
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting " "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "RDR,LAMTID"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting " "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "RDR,LAMTID"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "TDR,LAMTID"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "TDR,LAMTID"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
endif
|
|
endif
|
|
group.byte 0x19++0x0
|
|
line.byte 0x00 "LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xB0800C00+0x12))&0x01)==0x01)
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
if (((per.w(ad:0xB0800C00+0x12))&0x01)==0x01)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800C00+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Framing error pseudo error setting" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
if (((per.b(ad:0xB0800C00+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x20++0x0
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 , FIFO1 data number indication"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 , FIFO1 data number indication"
|
|
wgroup.byte 0x29++0x00
|
|
line.byte 0x00 "SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clear the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clear the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clear the transmission interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TBIEC ,Clear the transmission bus idle interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXEC ,Clear the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clear the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x28++0x00
|
|
line.byte 0x00 "SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 3. " SBLC ,Clear the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clear the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2B++0x00
|
|
line.byte 0x00 "SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clear the LIN break field detection flag bit" ",Clear"
|
|
wgroup.byte 0x2A++0x00
|
|
line.byte 0x00 "ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clear the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clear the LIN break field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clear the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clear the sync field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clear the sync field detection interrupt enable" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clear the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clear the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clear the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x33++0x00
|
|
line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clear the LIN checksum calculation completion flag bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clear the LIN auto header completion flag bit" ",Clear"
|
|
wgroup.byte 0x32++0x00
|
|
line.byte 0x00 "LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clear the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clear the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clear the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x35++0x00
|
|
line.byte 0x00 "LAMIERC,LIN Assist Mode Interrupt Enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clear the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clear the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clear the LIN sync data error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clear the LIN bus error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clear the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clear the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clear the LIN checksum error flag bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clear the LIN ID parity error flag bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clear the LIN Sync Data error flag bit" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clear the LIN bus error flag bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clear the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clear the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
bitfld.byte 0x00 1. " FTIEC ,Clear the transmission FIFO interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x38++0x00
|
|
line.byte 0x00 "FCR0C,FIFO Control Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clear the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clear the FIFO1 operation enable bit" ",Clear"
|
|
if (((per.b(ad:0xB0800C00+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Set the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Set the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Set the LIN break field setting bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Set the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Set the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Set the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Set the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Set the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Set the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Set the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Set the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Set the transmission interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIES ,Set the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Set the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Set the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 3. " SBLS ,Set the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Set the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x3F++0x00
|
|
line.byte 0x00 "SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Set the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x3E++0x00
|
|
line.byte 0x00 "ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Set the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Set the LIN break field detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x40++0x01
|
|
line.word 0x00 "SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Set the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Set the sync field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Set the auto baud rate adjustment bit" ",Set"
|
|
bitfld.word 0x00 7. " TINTES ,Set the timer interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGES ,Set the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Set the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Set the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Set the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Set the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Set the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x49++0x00
|
|
line.byte 0x00 "LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERS ,Set the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERS ,Set the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERS ,Set the LIN sync data error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " LBSERS ,Set the LIN bus error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIES ,Set the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Set the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x4D++0x00
|
|
line.byte 0x00 "FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Set the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Set the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Set the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Set the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set the FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set the FIFO1 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FE2S ,Set the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Set the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMR,Serial Mode Register"
|
|
bitfld.word 0x00 5.--7. " MD ,Operation mode" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "Channel 4"
|
|
base ad:0xB0801000
|
|
width 5.
|
|
if (((per.w(ad:0xB0801000))&0xE0)==((0x00||0x20)))
|
|
width 9.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
if (((per.b(ad:0xB0801000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.b(ad:0xB0801000+0x01))&0x03)==0x02)
|
|
if (((per.b(ad:0xB0801000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0801000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0801000)&0xE0))==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0801000)&0xE0))==0x00)
|
|
if (((per.b(ad:0xB0801000+0x01))&0x01)==0x00)
|
|
if (((per.b(ad:0xB0801000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0801000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0801000+0x01))&0x01)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,,,7-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format" "NRZ,Inverted"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection" "8-bit,,,7-bit,?..."
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0801000+0x03))&0x04)==0x04)
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.word 0x04++0x01
|
|
line.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
if (((per.w(ad:0xB0801000+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0801000+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0801000+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0801000+0x01))&0x03)!=0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0801000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
if (((per.b(ad:0xB0801000+0x21))&0x04)==0x00)&&(((per.b(ad:0xB0801000+0x20))&0x03)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FE2_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FE1_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data number indication"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data number indication"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set the FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
elif (((per.w(ad:0xB0801000))&0xE0)==0x40)
|
|
width 9.
|
|
if (((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 6. " MS ,Master/slave function selection" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0801000))&0x02)==0x00)
|
|
if (((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting " "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SCINV ,Serial clock invert" "High,Low"
|
|
rbitfld.byte 0x00 2. " BDS ,Transfer direction selection" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0801000+0x01))&0x03)==0x00)&&(((per.b(ad:0xB0801000+0x03))&0x06)==0x02)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0801000+0x01))&0x40)==0x40)||(((per.w(ad:0xB0801000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set" "No effect,Set"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length selection" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB0801000+0x03))&0x14)==0x04)
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
elif (((per.b(ad:0xB0801000+0x03))&0x14)==0x00)
|
|
wgroup.word 0x04++0x01
|
|
line.word 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
elif (((per.b(ad:0xB0801000+0x03))&0x14)==0x14)
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
textline " "
|
|
if (((per.w(ad:0xB0801000+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x38 13. 0x24 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0801000+0x08))&0x01)==0x00)&&(((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x38 15. 0x24 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x38 13. 0x24 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0xB0801000+0x08))&0x01)==0x01)&&(((per.b(ad:0xB0801000+0x01))&0x03)!=0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " TBEEN_set/clr ,Transfer byte error enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x38 12. 0x24 12. " CSEIE_set/clr ,Chip select error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x38 7. 0x24 7. " TINTE_set/clr ,Timer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x38 6. 0x24 6. " TSYNE_set/clr ,Synchronous transmission enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x38 0. 0x24 0. " TMRE_set/clr ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0801000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
if (((per.b(ad:0xB0801000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention" "Not retained,Retained"
|
|
textline " "
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select 3 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select 1 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0801000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention" "Not retained,Retained"
|
|
textline " "
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select 3 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select 1 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0801000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.word 0x0E++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SED ,Serial chip select display" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select 0 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0801000+0x01))&0x43)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CSDS ,Serial chip deselect"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay"
|
|
elif (((per.b(ad:0xB0801000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CSDS ,Serial chip deselect"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay"
|
|
else
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SCSTR,Serial Chip Select Timing Register"
|
|
endif
|
|
if (((per.b(ad:0xB0801000+0x01))&0x40)==0x40)||(((per.b(ad:0xB0801000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB0801000+0x02))&0x20)==0x00)
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
else
|
|
if (((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS0CSLVL ,Chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS0SCINV ,Inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS0SPI ,Serial chip select pin 0 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS0BDS ,Transfer direction of chip select pin 0" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS0L ,Data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Serial chip select pin 1 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction of chip select pin 1" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,Serial chip select pin 2 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction of chip select pin 2" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS0CSLVL ,Chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS0SCINV ,Inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS0SPI ,Serial chip select pin 0 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS0BDS ,Transfer direction of chip select pin 0" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS0L ,Data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
rgroup.byte 0x15++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Serial chip select pin 1 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction of chip select pin 1" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
rgroup.byte 0x16++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,Serial chip select pin 2 SPI support" "Normal,SPI"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction of chip select pin 2" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB0801000+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x03
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
line.byte 0x01 "TBYTE1,Transfer Byte Register 1"
|
|
line.byte 0x02 "TBYTE2,Transfer Byte Register 2"
|
|
line.byte 0x03 "TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x03
|
|
hide.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
hide.byte 0x01 "TBYTE1,Transfer Byte Register 1"
|
|
hide.byte 0x02 "TBYTE2,Transfer Byte Register 2"
|
|
hide.byte 0x03 "TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x2C 4. 0x18 4. " FLSTE_set/clr ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x2C 3. 0x18 3. " FRIIE_set/clr ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FTIE_set/clr ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag" "Not lost,lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving" "No effect,Save"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x2C 1. 0x18 1. " FE2_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x2C 0. 0x18 0. " FE1_set/clr ,FIFO2 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,Number of data items in FIFO2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,Number of data items in FIFO1"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,Number of data items in FIFO2"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,Number of data items in FIFO1"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clear the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
elif (((per.w(ad:0xB0801000))&0xE0)==0x60)
|
|
width 9.
|
|
if (((per.b(ad:0xB0801000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function select" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting" "No effect,Generate"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function select" "Master,Slave"
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0801000+0x02))&0x40)==0x00)&&(((per.b(ad:0xB0801000+0x01))&0x01)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0801000+0x02))&0x40)==0x40)&&(((per.b(ad:0xB0801000+0x01))&0x01)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB0801000+0x02))&0x40)==0x00)&&(((per.b(ad:0xB0801000+0x01))&0x01)==0x01)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
rbitfld.byte 0x00 3. " SBL ,Stop bit length selection" "3 bits,4 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " LBD ,LIN break field detection flag" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
if (((per.b(ad:0xB0801000+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB0801000+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. 5. " LBL ,LIN break field length selection" "13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection" "1-bit,2-bit,3-bit,4-bit"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. 5. " LBL ,LIN break field length selection" "13-bit,14-bit,15-bit,16-bit,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection" "1-bit,2-bit,3-bit,4-bit"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break Field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB0801000+0x03))&0x04)==0x04)
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
in
|
|
else
|
|
wgroup.byte 0x04++0x00
|
|
line.byte 0x00 "RDR/TDR,Reception Data Register/Transmission Data Register"
|
|
endif
|
|
if (((per.w(ad:0xB0801000+0x08))&0x2000)==0x2000)
|
|
if (((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
if (((per.w(ad:0xB0801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB0801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
if (((per.w(ad:0xB0801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB0801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SACSR,Serial Auxiliary Control Status Register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial timer enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB0801000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
if (((per.w(ad:0xB0801000+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit"
|
|
line.word 0x02 "SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit"
|
|
line.word 0x02 "SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
textline " "
|
|
if (((per.b(ad:0xB0801000+0x12))&0x01)==0x01)
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "LAMSR,LIN Assist Mode Status Register"
|
|
rbitfld.byte 0x00 7. " LER ,LIN representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 6. " SER ,Serial interface representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 5. " RDRF ,Reception data full flag" "Not full,Full"
|
|
rbitfld.byte 0x00 4. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag" "Not detected,Detected"
|
|
else
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "LAMSR,LIN Assist Mode Status Register"
|
|
rbitfld.byte 0x00 6. " SER ,Serial interface representative error flag" "No error,Error"
|
|
rbitfld.byte 0x00 5. " RDRF ,Reception data full flag" "Not full,Full"
|
|
rbitfld.byte 0x00 4. " TDRE ,Transmission data empty flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 3. " TBI ,Transmission bus idle flag" "Busy,Idle"
|
|
endif
|
|
if (((per.b(ad:0xB0801000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0801000+0x01))&0x40)==0x40)
|
|
if (((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting " "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "RDR,LAMTID"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting " "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "RDR,LAMTID"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB0801000+0x01))&0x03)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "TDR,LAMTID"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "LAMCR,LIN Assist Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection" "Standard,Extended"
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable" "TDR,LAMTID"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable" "Manual,Assist"
|
|
endif
|
|
endif
|
|
endif
|
|
group.byte 0x19++0x0
|
|
line.byte 0x00 "LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xB0801000+0x12))&0x01)==0x01)
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
if (((per.w(ad:0xB0801000+0x12))&0x01)==0x01)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
if (((per.b(ad:0xB0801000+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Framing error pseudo error setting" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
if (((per.b(ad:0xB0801000+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x20++0x0
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 , FIFO1 data number indication"
|
|
line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data number indication"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 , FIFO1 data number indication"
|
|
wgroup.byte 0x29++0x00
|
|
line.byte 0x00 "SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clear the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clear the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clear the transmission interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TBIEC ,Clear the transmission bus idle interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXEC ,Clear the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clear the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x28++0x00
|
|
line.byte 0x00 "SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 3. " SBLC ,Clear the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clear the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2B++0x00
|
|
line.byte 0x00 "SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clear the LIN break field detection flag bit" ",Clear"
|
|
wgroup.byte 0x2A++0x00
|
|
line.byte 0x00 "ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clear the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clear the LIN break field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clear the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clear the sync field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clear the sync field detection interrupt enable" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clear the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clear the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clear the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clear the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x33++0x00
|
|
line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clear the LIN checksum calculation completion flag bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clear the LIN auto header completion flag bit" ",Clear"
|
|
wgroup.byte 0x32++0x00
|
|
line.byte 0x00 "LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clear the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clear the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clear the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x35++0x00
|
|
line.byte 0x00 "LAMIERC,LIN Assist Mode Interrupt Enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clear the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clear the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clear the LIN sync data error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clear the LIN bus error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clear the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clear the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clear the LIN checksum error flag bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clear the LIN ID parity error flag bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clear the LIN Sync Data error flag bit" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clear the LIN bus error flag bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clear the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clear the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clear the transmission FIFO data request bit" ",Clear"
|
|
bitfld.byte 0x00 1. " FTIEC ,Clear the transmission FIFO interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x38++0x00
|
|
line.byte 0x00 "FCR0C,FIFO Control Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clear the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clear the FIFO1 operation enable bit" ",Clear"
|
|
if (((per.b(ad:0xB0801000+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Set the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Set the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Set the LIN break field setting bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Set the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Set the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Set the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Set the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Set the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Set the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Set the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Set the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Set the transmission interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIES ,Set the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Set the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Set the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 3. " SBLS ,Set the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Set the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x3F++0x00
|
|
line.byte 0x00 "SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Set the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x3E++0x00
|
|
line.byte 0x00 "ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Set the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Set the LIN break field detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x40++0x01
|
|
line.word 0x00 "SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Set the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Set the sync field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Set the auto baud rate adjustment bit" ",Set"
|
|
bitfld.word 0x00 7. " TINTES ,Set the timer interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGES ,Set the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Set the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Set the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Set the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Set the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Set the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x49++0x00
|
|
line.byte 0x00 "LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERS ,Set the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERS ,Set the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERS ,Set the LIN sync data error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " LBSERS ,Set the LIN bus error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LCSCIES ,Set the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Set the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x4D++0x00
|
|
line.byte 0x00 "FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Set the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Set the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Set the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Set the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Set the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Set the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Set the FIFO2 reset bit" ",Set"
|
|
bitfld.byte 0x00 2. " FCL1S ,Set the FIFO1 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FE2S ,Set the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Set the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMR,Serial Mode Register"
|
|
bitfld.word 0x00 5.--7. " MD ,Operation mode" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "Base Timer"
|
|
tree "Channel 0"
|
|
base ad:0xB0808000
|
|
width 7.
|
|
if (((per.w(ad:0xB0808000+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0xB0808000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0808000+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0xB0808000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0808000+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0xB0808000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0808000+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0xB0808000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xB0808400
|
|
width 7.
|
|
if (((per.w(ad:0xB0808400+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0xB0808400+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0808400+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0xB0808400+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0808400+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0xB0808400+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0808400+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0xB0808400+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xB0808800
|
|
width 7.
|
|
if (((per.w(ad:0xB0808800+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0xB0808800+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0808800+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0xB0808800+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0808800+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0xB0808800+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0808800+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0xB0808800+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0xB0808C00
|
|
width 7.
|
|
if (((per.w(ad:0xB0808C00+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0xB0808C00+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0808C00+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0xB0808C00+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0808C00+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0xB0808C00+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0808C00+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0xB0808C00+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0808C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0808C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("MB9DF56?L*")
|
|
tree "Channel 4"
|
|
base ad:0xB0809000
|
|
width 7.
|
|
if (((per.w(ad:0xB0809000+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0xB0809000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0809000+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0xB0809000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0809000+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0xB0809000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0809000+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0xB0809000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 5"
|
|
base ad:0xB0809400
|
|
width 7.
|
|
if (((per.w(ad:0xB0809400+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0xB0809400+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0809400+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0xB0809400+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0809400+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0xB0809400+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0809400+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0xB0809400+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "Channel 6"
|
|
base ad:0xB0809800
|
|
width 7.
|
|
if (((per.w(ad:0xB0809800+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0xB0809800+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0809800+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0xB0809800+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0809800+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0xB0809800+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0809800+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0xB0809800+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 7"
|
|
base ad:0xB0809C00
|
|
width 7.
|
|
if (((per.w(ad:0xB0809C00+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0xB0809C00+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0809C00+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0xB0809C00+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0809C00+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0xB0809C00+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB0809C00+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0xB0809C00+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB0809C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB0809C00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("MB9DF56?L*")
|
|
tree "Channel 8"
|
|
base ad:0xB080A000
|
|
width 7.
|
|
if (((per.w(ad:0xB080A000+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0xB080A000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080A000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080A000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB080A000+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0xB080A000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080A000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080A000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB080A000+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0xB080A000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080A000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080A000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB080A000+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0xB080A000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080A000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080A000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 9"
|
|
base ad:0xB080A400
|
|
width 7.
|
|
if (((per.w(ad:0xB080A400+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0xB080A400+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080A400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080A400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB080A400+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0xB080A400+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080A400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080A400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB080A400+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0xB080A400+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080A400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080A400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB080A400+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0xB080A400+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080A400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080A400+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 10"
|
|
base ad:0xB080A800
|
|
width 7.
|
|
if (((per.w(ad:0xB080A800+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0xB080A800+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080A800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080A800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB080A800+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0xB080A800+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080A800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080A800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB080A800+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0xB080A800+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080A800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080A800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB080A800+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0xB080A800+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080A800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080A800+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 11"
|
|
base ad:0xB080AC00
|
|
width 7.
|
|
if (((per.w(ad:0xB080AC00+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0xB080AC00+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080AC00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080AC00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB080AC00+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0xB080AC00+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080AC00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080AC00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB080AC00+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0xB080AC00+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080AC00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080AC00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0xB080AC00+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0xB080AC00+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0xB080AC00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0xB080AC00+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "Base Timer I/O Selection Function"
|
|
tree "Channels 0-1"
|
|
base ad:0xB0808030
|
|
width 13.
|
|
group.byte 0x00++0x00
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
line.byte 0x00 "BTSEL01,I/O Selection Register"
|
|
bitfld.byte 0x00 4.--7. " BTSEL0 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
bitfld.byte 0x00 0.--3. " BTSEL0 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
else
|
|
line.byte 0x00 "BTSEL01,I/O Selection Register"
|
|
bitfld.byte 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Timer start/stop and simultaneous soft start,Timer start,?..."
|
|
endif
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
else
|
|
textline " "
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "BTSSSR,Simultaneous Soft Start Register"
|
|
sif !cpuis("MB9DF56?L*")
|
|
bitfld.word 0x00 11. " SSSR11 ,Simultaneous soft start channel 11" "No effect,Started"
|
|
bitfld.word 0x00 10. " SSSR10 ,Simultaneous soft start channel 10" "No effect,Started"
|
|
bitfld.word 0x00 9. " SSSR9 ,Simultaneous soft start channel 9" "No effect,Started"
|
|
bitfld.word 0x00 8. " SSSR8 ,Simultaneous soft start channel 8" "No effect,Started"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " SSSR7 ,Simultaneous soft start channel 7" "No effect,Started"
|
|
bitfld.word 0x00 6. " SSSR6 ,Simultaneous soft start channel 6" "No effect,Started"
|
|
sif !cpuis("MB9DF56?L*")
|
|
bitfld.word 0x00 5. " SSSR5 ,Simultaneous soft start channel 5" "No effect,Started"
|
|
bitfld.word 0x00 4. " SSSR4 ,Simultaneous soft start channel 4" "No effect,Started"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 3. " SSSR3 ,Simultaneous soft start channel 3" "No effect,Started"
|
|
bitfld.word 0x00 2. " SSSR2 ,Simultaneous soft start channel 2" "No effect,Started"
|
|
bitfld.word 0x00 1. " SSSR1 ,Simultaneous soft start channel 1" "No effect,Started"
|
|
bitfld.word 0x00 0. " SSSR0 ,Simultaneous soft start channel 0" "No effect,Started"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channels 2-3"
|
|
base ad:0xB0808830
|
|
width 13.
|
|
group.byte 0x00++0x00
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
line.byte 0x00 "BTSEL23,I/O Selection Register"
|
|
bitfld.byte 0x00 4.--7. " BTSEL0 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
bitfld.byte 0x00 0.--3. " BTSEL0 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
else
|
|
line.byte 0x00 "BTSEL23,I/O Selection Register"
|
|
bitfld.byte 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Timer start/stop and simultaneous soft start,Timer start,?..."
|
|
endif
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
else
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("MB9DF56?L*")
|
|
tree "Channels 4-5"
|
|
base ad:0xB0809030
|
|
width 13.
|
|
group.byte 0x00++0x00
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
line.byte 0x00 "BTSEL45,I/O Selection Register"
|
|
bitfld.byte 0x00 4.--7. " BTSEL0 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
bitfld.byte 0x00 0.--3. " BTSEL0 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
else
|
|
line.byte 0x00 "BTSEL45,I/O Selection Register"
|
|
bitfld.byte 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Timer start/stop and simultaneous soft start,Timer start,?..."
|
|
endif
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
else
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "Channels 6-7"
|
|
base ad:0xB0809830
|
|
width 13.
|
|
group.byte 0x00++0x00
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
line.byte 0x00 "BTSEL67,I/O Selection Register"
|
|
bitfld.byte 0x00 4.--7. " BTSEL0 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
bitfld.byte 0x00 0.--3. " BTSEL0 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
else
|
|
line.byte 0x00 "BTSEL67,I/O Selection Register"
|
|
bitfld.byte 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Timer start/stop and simultaneous soft start,Timer start,?..."
|
|
endif
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
else
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("MB9DF56?L*")
|
|
tree "Channels 8-9"
|
|
base ad:0xB080A030
|
|
width 13.
|
|
group.byte 0x00++0x00
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
line.byte 0x00 "BTSEL89,I/O Selection Register"
|
|
bitfld.byte 0x00 4.--7. " BTSEL0 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
bitfld.byte 0x00 0.--3. " BTSEL0 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
else
|
|
line.byte 0x00 "BTSEL89,I/O Selection Register"
|
|
bitfld.byte 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Timer start/stop and simultaneous soft start,Timer start,?..."
|
|
endif
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
else
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channels 10-11"
|
|
base ad:0xB080A830
|
|
width 13.
|
|
group.byte 0x00++0x00
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
line.byte 0x00 "BTSEL1011,I/O Selection Register"
|
|
bitfld.byte 0x00 4.--7. " BTSEL0 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
bitfld.byte 0x00 0.--3. " BTSEL0 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
else
|
|
line.byte 0x00 "BTSEL1011,I/O Selection Register"
|
|
bitfld.byte 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Timer start/stop and simultaneous soft start,Timer start,?..."
|
|
endif
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
else
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "FRT (32-bit Free-run Timer)"
|
|
tree "Channel 0"
|
|
base ad:0xB0820000
|
|
width 8.
|
|
if (((per.l(ad:0xB0820000+0x08))&0x80)==0x80)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
if (((per.l(ad:0xB0820000+0x08))&0x40)==0x40)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE ,0 detection request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
bitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode" "Up,Up/Down"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
if (((per.l(ad:0xB0820000+0x08))&0x20)==0x20)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..."
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
endif
|
|
wgroup.long 0x10++0x07
|
|
line.long 0x00 "TCCSC,Timer State Control Clear Register"
|
|
bitfld.long 0x00 14. " IRQZFC ,IRQZF clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " IRQZEC ,IRQZE clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Control Set Register"
|
|
bitfld.long 0x04 4. " SCLRS ,SCLR set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xB0820400
|
|
width 8.
|
|
if (((per.l(ad:0xB0820400+0x08))&0x80)==0x80)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
if (((per.l(ad:0xB0820400+0x08))&0x40)==0x40)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE ,0 detection request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
bitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode" "Up,Up/Down"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
if (((per.l(ad:0xB0820400+0x08))&0x20)==0x20)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..."
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
endif
|
|
wgroup.long 0x10++0x07
|
|
line.long 0x00 "TCCSC,Timer State Control Clear Register"
|
|
bitfld.long 0x00 14. " IRQZFC ,IRQZF clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " IRQZEC ,IRQZE clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Control Set Register"
|
|
bitfld.long 0x04 4. " SCLRS ,SCLR set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xB0820800
|
|
width 8.
|
|
if (((per.l(ad:0xB0820800+0x08))&0x80)==0x80)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
if (((per.l(ad:0xB0820800+0x08))&0x40)==0x40)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE ,0 detection request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
bitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode" "Up,Up/Down"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
if (((per.l(ad:0xB0820800+0x08))&0x20)==0x20)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..."
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
endif
|
|
wgroup.long 0x10++0x07
|
|
line.long 0x00 "TCCSC,Timer State Control Clear Register"
|
|
bitfld.long 0x00 14. " IRQZFC ,IRQZF clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " IRQZEC ,IRQZE clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Control Set Register"
|
|
bitfld.long 0x04 4. " SCLRS ,SCLR set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0xB0820C00
|
|
width 8.
|
|
if (((per.l(ad:0xB0820C00+0x08))&0x80)==0x80)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
if (((per.l(ad:0xB0820C00+0x08))&0x40)==0x40)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE ,0 detection request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
bitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode" "Up,Up/Down"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
if (((per.l(ad:0xB0820C00+0x08))&0x20)==0x20)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..."
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
endif
|
|
wgroup.long 0x10++0x07
|
|
line.long 0x00 "TCCSC,Timer State Control Clear Register"
|
|
bitfld.long 0x00 14. " IRQZFC ,IRQZF clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " IRQZEC ,IRQZE clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Control Set Register"
|
|
bitfld.long 0x04 4. " SCLRS ,SCLR set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 4"
|
|
base ad:0xB0821000
|
|
width 8.
|
|
if (((per.l(ad:0xB0821000+0x08))&0x80)==0x80)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
if (((per.l(ad:0xB0821000+0x08))&0x40)==0x40)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE ,0 detection request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
bitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode" "Up,Up/Down"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
if (((per.l(ad:0xB0821000+0x08))&0x20)==0x20)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..."
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
endif
|
|
wgroup.long 0x10++0x07
|
|
line.long 0x00 "TCCSC,Timer State Control Clear Register"
|
|
bitfld.long 0x00 14. " IRQZFC ,IRQZF clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " IRQZEC ,IRQZE clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Control Set Register"
|
|
bitfld.long 0x04 4. " SCLRS ,SCLR set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "ICU (32-bit Input Capture)"
|
|
tree "Unit 0"
|
|
base ad:0xB0828000
|
|
width 7.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "IPCP0,Input Capture Data Registers 0"
|
|
line.long 0x04 "IPCP1,Input Capture Data Registers 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICS,Input Capture State Control Register"
|
|
rbitfld.long 0x00 9. " IEI1 ,Input capture 1 valid edge indication" "Falling,Rising"
|
|
rbitfld.long 0x00 8. " IEI0 ,Input capture 0 valid edge indication" "Falling,Rising"
|
|
rbitfld.long 0x00 7. " ICP1 ,Input capture 1 interrupt request flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 6. " ICP0 ,Input capture 0 interrupt request flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_set/clr ,Input capture 1 interrupt request enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_set/clr ,Input capture 0 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " EG1 ,Input capture 1 edge selection" "None,Rising,Falling,Both"
|
|
bitfld.long 0x00 0.--1. " EG0 ,Input capture 0 edge selection" "None,Rising,Falling,Both"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICSC,Input Capture State Control Clear Register"
|
|
bitfld.long 0x00 7. " ICP1C ,ICP1 clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ICP0C ,ICP0 clear" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 1"
|
|
base ad:0xB0828400
|
|
width 7.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "IPCP0,Input Capture Data Registers 0"
|
|
line.long 0x04 "IPCP1,Input Capture Data Registers 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICS,Input Capture State Control Register"
|
|
rbitfld.long 0x00 9. " IEI1 ,Input capture 1 valid edge indication" "Falling,Rising"
|
|
rbitfld.long 0x00 8. " IEI0 ,Input capture 0 valid edge indication" "Falling,Rising"
|
|
rbitfld.long 0x00 7. " ICP1 ,Input capture 1 interrupt request flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 6. " ICP0 ,Input capture 0 interrupt request flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_set/clr ,Input capture 1 interrupt request enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_set/clr ,Input capture 0 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " EG1 ,Input capture 1 edge selection" "None,Rising,Falling,Both"
|
|
bitfld.long 0x00 0.--1. " EG0 ,Input capture 0 edge selection" "None,Rising,Falling,Both"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICSC,Input Capture State Control Clear Register"
|
|
bitfld.long 0x00 7. " ICP1C ,ICP1 clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ICP0C ,ICP0 clear" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 2"
|
|
base ad:0xB0828800
|
|
width 7.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "IPCP0,Input Capture Data Registers 0"
|
|
line.long 0x04 "IPCP1,Input Capture Data Registers 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICS,Input Capture State Control Register"
|
|
rbitfld.long 0x00 9. " IEI1 ,Input capture 1 valid edge indication" "Falling,Rising"
|
|
rbitfld.long 0x00 8. " IEI0 ,Input capture 0 valid edge indication" "Falling,Rising"
|
|
rbitfld.long 0x00 7. " ICP1 ,Input capture 1 interrupt request flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 6. " ICP0 ,Input capture 0 interrupt request flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_set/clr ,Input capture 1 interrupt request enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_set/clr ,Input capture 0 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " EG1 ,Input capture 1 edge selection" "None,Rising,Falling,Both"
|
|
bitfld.long 0x00 0.--1. " EG0 ,Input capture 0 edge selection" "None,Rising,Falling,Both"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICSC,Input Capture State Control Clear Register"
|
|
bitfld.long 0x00 7. " ICP1C ,ICP1 clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ICP0C ,ICP0 clear" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif cpuis("MB9DF56??AE")||cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
tree "ERAYP (FlexRay/RDC Dedicated Clock)"
|
|
base ad:0xB1010000
|
|
width 17.
|
|
group.byte 0x3020++0x00
|
|
line.byte 0x00 "ERAYP_CSVR,FlexRay/RDC PLL CSV Control Register"
|
|
bitfld.byte 0x00 1. " CSVSEL ,CSV selection" "NMI,Reset"
|
|
bitfld.byte 0x00 0. " CSVEN ,CSV enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0xB1010000+0x1000005))&0x03)==0x02)
|
|
rgroup.byte 0x1000003++0x00
|
|
line.byte 0x00 "ERAYP_PLL2DIVM,FlexRay/RDC PLL Multiplication Rate (M Division) Selection Register"
|
|
bitfld.byte 0x00 0.--3. " DVM ,CLKVCO M division selection" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
rgroup.byte 0x1000002++0x00
|
|
line.byte 0x00 "ERAYP_PLL2DIVN,FlexRay/RDC PLL Multiplication Rate (N Division) Selection Register"
|
|
hexmask.byte 0x00 0.--6. 1. " DVN ,N division selection for main clock"
|
|
rgroup.byte 0x1000001++0x00
|
|
line.byte 0x00 "ERAYP_PLL2DIVG,FlexRay/RDC PLL Automatic Gear Multiplication Rate (G Division) Selection Register"
|
|
bitfld.byte 0x00 0.--3. " DVG ,G division selection for PLL automatic gear start/end" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
rgroup.byte 0x1000000++0x00
|
|
line.byte 0x00 "ERAYP_PLL2MULG,FlexRay/RDC PLL Step Multiplication Rate (G division) Selection Register"
|
|
else
|
|
group.byte 0x1000003++0x00
|
|
line.byte 0x00 "ERAYP_PLL2DIVM,FlexRay/RDC PLL Multiplication Rate (M Division) Selection Register"
|
|
bitfld.byte 0x00 0.--3. " DVM ,CLKVCO M division selection" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
group.byte 0x1000002++0x00
|
|
line.byte 0x00 "ERAYP_PLL2DIVN,FlexRay/RDC PLL Multiplication Rate (N Division) Selection Register"
|
|
hexmask.byte 0x00 0.--6. 1. " DVN ,N division selection for main clock"
|
|
group.byte 0x1000001++0x00
|
|
line.byte 0x00 "ERAYP_PLL2DIVG,FlexRay/RDC PLL Automatic Gear Multiplication Rate (G Division) Selection Register"
|
|
bitfld.byte 0x00 0.--3. " DVG ,G division selection for PLL automatic gear start/end" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
group.byte 0x1000000++0x00
|
|
line.byte 0x00 "ERAYP_PLL2MULG,FlexRay/RDC PLL Step Multiplication Rate (G division) Selection Register"
|
|
endif
|
|
group.byte 0x1000007++0x00
|
|
line.byte 0x00 "ERAYP_PLL2CTRL,Automatic Gear Control Register"
|
|
bitfld.byte 0x00 3. " IEDN ,Interrupt enable gear down" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " IEUP ,Interrupt enable gear up" "Disabled,Enabled"
|
|
if (((per.l(ad:0xB1010000+0x1000005))&0x03)==0x02)
|
|
rgroup.byte 0x1000006++0x00
|
|
line.byte 0x00 "ERAYP_PLL2DIVK,FlexRay/RDC PLL Multiplication Rate (K Division) Selection Register"
|
|
bitfld.byte 0x00 0. " DVK ,K division selection for main clock" "No division,/2"
|
|
group.byte 0x1000005++0x00
|
|
line.byte 0x00 "ERAYP_CLKR2,FlexRay/RDC PLL Clock Output Control Register"
|
|
rbitfld.byte 0x00 7. " FPOVF ,FlexRay/RDC PLL alarm flag" "Ordinary lock,Deadlock"
|
|
bitfld.byte 0x00 5. " FPOVIE ,FlexRay/RDC PLL alarm interrupt request enabled" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " PLL2EN ,FlexRay/RDC PLL selection enabled" "No division,/2"
|
|
bitfld.byte 0x00 0.--1. " CLKS ,SCLK output selection" "CLK_PERI7,,CLKPLL,?..."
|
|
else
|
|
group.byte 0x1000006++0x00
|
|
line.byte 0x00 "ERAYP_PLL2DIVK,FlexRay/RDC PLL Multiplication Rate (K Division) Selection Register"
|
|
bitfld.byte 0x00 0. " DVK ,K division selection for main clock" "No division,/2"
|
|
group.byte 0x1000005++0x00
|
|
line.byte 0x00 "ERAYP_CLKR2,FlexRay/RDC PLL Clock Output Control Register"
|
|
rbitfld.byte 0x00 7. " FPOVF ,FlexRay/RDC PLL alarm flag" "Ordinary lock,Deadlock"
|
|
bitfld.byte 0x00 5. " FPOVIE ,FlexRay/RDC PLL alarm interrupt request enabled" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " PLL2EN ,FlexRay/RDC PLL selection enabled" "No division,/2"
|
|
bitfld.byte 0x00 0.--1. " CLKS ,SCLK output selection" "CLK_PERI7,,CLKPLL,?..."
|
|
endif
|
|
rgroup.byte 0x100000B++0x00
|
|
line.byte 0x00 "ERAYP_PLL2CTRLF,Automatic Gear Control Flag Register"
|
|
bitfld.byte 0x00 2. " GRDN ,Interrupt flag gear down" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " IEUP ,Interrupt flag gear up" "No interrupt,Interrupt"
|
|
rgroup.byte 0x1000009++0x00
|
|
line.byte 0x00 "ERAYP_CLKR2F,FlexRay/RDC PLL Clock Output Control Flag Register"
|
|
bitfld.byte 0x00 6. " FPOVIR ,FlexRay/RDC PLL alarm interrupt request flag" "Ordinary lock,Deadlock"
|
|
wgroup.byte 0x100000F++0x00
|
|
line.byte 0x00 "ERAYP_PLL2CTRLC,Automatic Gear Control Clear Register"
|
|
bitfld.byte 0x00 2. " GRDNC ,Interrupt flag gear down clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " GRUPC ,Interrupt flag gear up clear" "No effect,Clear"
|
|
wgroup.byte 0x100000D++0x00
|
|
line.byte 0x00 "ERAYP_CLKR2C,FlexRay/RDC PLL Clock Output Control Clear Register"
|
|
bitfld.byte 0x00 6. " FPOVIRC ,FlexRay/RDC PLL alarm interrupt request flag clear" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "CLKMN (Clock Monitor)"
|
|
base ad:0xB2010100
|
|
width 13.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "CLKMN_CMCFG,Clock Monitor Control Register"
|
|
bitfld.byte 0x00 4.--7. " CMPRE ,Output frequency prescaler bits" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.byte 0x00 0.--3. " CMSEL ,Output source clock selection bits" "MONCLK output disabled,Output clock of clock output function,CLK_CPU0,CLK_CPU1,CLK_SYSC_PD1,CLK_MEMC,CLK_PERI0,CLK_PERI1,CLK_PERI4,CLK_PERI5,CLK_PERI6,CLK_PERI7,PLL output after CAN prescaler,SCLK for FlexRay,PLL output for FlexRay,PLL automatic gear output for FlexRay"
|
|
line.byte 0x01 "CLKMN_CSCFG,Clock Control Register"
|
|
bitfld.byte 0x01 4. " MONCKI ,Clock monitor MONCLK inverter" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("MB9DF56??GE")||cpuis("MB9DF56??QE")
|
|
tree "FLXRY (FlexRay Controller)"
|
|
base ad:0xB2001000
|
|
width 13.
|
|
tree "Customer Registers"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CIF0,Version Information Register"
|
|
if (((per.l(ad:0xB2001000+0x04))&0x22000000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CIF1,Control Register"
|
|
bitfld.long 0x00 30. " DLVLO ,DMA level selection bit for output buffer" "Normal,Inverted"
|
|
bitfld.long 0x00 29. " DMODO ,DMA trigger mode selection bit for output buffer" "Level,Edge"
|
|
bitfld.long 0x00 28. " DENBO ,DMA request output enable bit for output buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " DLVLI ,DMA level selection bit for input buffer host" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DMODI ,DMA trigger mode selection bit for input buffer host" "Level,Edge"
|
|
bitfld.long 0x00 24. " DENBI ,DMA request output enable bit for input buffer host" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " RESET ,FlexRay reset bits" "0,1,2,3"
|
|
bitfld.long 0x00 12. " SWAP ,Buffer data SWAP enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TENB1 ,Timer 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TENB0 ,Timer 0 interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB2001000+0x04))&0x22000000)==0x02000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CIF1,Control Register"
|
|
bitfld.long 0x00 30. " DLVLO ,DMA level selection bit for output buffer" "Normal,Inverted"
|
|
bitfld.long 0x00 29. " DMODO ,DMA trigger mode selection bit for output buffer" "Level,Edge"
|
|
bitfld.long 0x00 28. " DENBO ,DMA request output enable bit for output buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " DLVLI ,DMA edge selection bit for input buffer host" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DMODI ,DMA trigger mode selection bit for input buffer host" "Level,Edge"
|
|
bitfld.long 0x00 24. " DENBI ,DMA request output enable bit for input buffer host" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " RESET ,FlexRay reset bits" "0,1,2,3"
|
|
bitfld.long 0x00 12. " SWAP ,Buffer data SWAP enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TENB1 ,Timer 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TENB0 ,Timer 0 interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB2001000+0x04))&0x22000000)==0x20000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CIF1,Control Register"
|
|
bitfld.long 0x00 30. " DLVLO ,DMA edge selection bit for output buffer" "Falling,Rising"
|
|
bitfld.long 0x00 29. " DMODO ,DMA trigger mode selection bit for output buffer" "Level,Edge"
|
|
bitfld.long 0x00 28. " DENBO ,DMA request output enable bit for output buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " DLVLI ,DMA level selection bit for input buffer host" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DMODI ,DMA trigger mode selection bit for input buffer host" "Level,Edge"
|
|
bitfld.long 0x00 24. " DENBI ,DMA request output enable bit for input buffer host" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " RESET ,FlexRay reset bits" "0,1,2,3"
|
|
bitfld.long 0x00 12. " SWAP ,Buffer data SWAP enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TENB1 ,Timer 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TENB0 ,Timer 0 interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CIF1,Control Register"
|
|
bitfld.long 0x00 30. " DLVLO ,DMA edge selection bit for output buffer" "Falling,Rising"
|
|
bitfld.long 0x00 29. " DMODO ,DMA trigger mode selection bit for output buffer" "Level,Edge"
|
|
bitfld.long 0x00 28. " DENBO ,DMA request output enable bit for output buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " DLVLI ,DMA edge selection bit for input buffer host" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DMODI ,DMA trigger mode selection bit for input buffer host" "Level,Edge"
|
|
bitfld.long 0x00 24. " DENBI ,DMA request output enable bit for input buffer host" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " RESET ,FlexRay reset bits" "0,1,2,3"
|
|
bitfld.long 0x00 12. " SWAP ,Buffer data SWAP enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TENB1 ,Timer 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TENB0 ,Timer 0 interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CIF1F,Flag Register"
|
|
bitfld.long 0x00 3. " DREQO ,DMA request flag bit for output buffer" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " DREQI ,DMA request flag bit for input buffer host" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " TREQ1 ,Timer 1 interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " TREQ0 ,Timer 0 interrupt request" "No interrupt,Interrupt"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CIF1C,Flag Clear Register"
|
|
bitfld.long 0x00 3. " DREQOC ,DMA request clear bit for output buffer" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DREQIC ,DMA request clear bit for input buffer host" "No effect,Clear"
|
|
bitfld.long 0x00 1. " TREQ1C ,Timer 1 interrupt request clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " TREQ0C ,Timer 0 interrupt request clear" "No effect,Clear"
|
|
tree.end
|
|
tree "Special Register"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "LCK,Lock Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLK ,Configuration lock key"
|
|
tree.end
|
|
tree "Interrupt-related Registers"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "EIR,Error Interrupt Register"
|
|
eventfld.long 0x00 26. " TABB ,Transmission across channel B slot boundary" "Not detected,Detected"
|
|
eventfld.long 0x00 25. " LTVB ,Channel B transmission failure" "Not detected,Detected"
|
|
eventfld.long 0x00 24. " EDB ,Error detected on channel B" "Not detected,Detected"
|
|
eventfld.long 0x00 18. " TABA ,Transmission across channel A slot boundary" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 17. " LTVA ,Channel A transmission failure" "Not detected,Detected"
|
|
eventfld.long 0x00 16. " EDA ,Error detected on channel A" "Not detected,Detected"
|
|
eventfld.long 0x00 11. " MHF ,Message handler constraints" "Not detected,Detected"
|
|
eventfld.long 0x00 10. " IOBA ,Illegal output buffer access" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IIBA ,Illegal input buffer access" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " EFA ,Empty FIFO access" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " RFO ,Reception FIFO overrun" "Not detected,Detected"
|
|
eventfld.long 0x00 6. " PERR ,Parity error" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 5. " CCL ,CHI command locked" "Accepted,Not accepted"
|
|
eventfld.long 0x00 4. " CCF ,Clock correction failure" "No error,Error"
|
|
eventfld.long 0x00 3. " SFO ,Synchronization frame overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " SFBM ,Synchronization frames below minimum" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CNA ,Invalid command notification" "Accepted,Not accepted"
|
|
eventfld.long 0x00 0. " PEMC ,POC error mode changed" "Not changed,Changed"
|
|
line.long 0x04 "SIR,Status Interrupt Register"
|
|
eventfld.long 0x04 25. " MTSB ,MTS received on channel B (vSS!ValidMTSB)" "No MTS,MTS"
|
|
eventfld.long 0x04 24. " WUPB ,Channel B wakeup pattern reception" "No wakeup,Wakeup"
|
|
eventfld.long 0x04 17. " MTSA ,MTS received on channel A (vSS!ValidMTSA)" "No MTS,MTS"
|
|
eventfld.long 0x04 16. " WUPA ,Channel A wakeup pattern reception" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x04 15. " SDS ,Start of dynamic segment" "Not started,Started"
|
|
eventfld.long 0x04 14. " MBSI ,Message buffer status changed" "Not changed,Changed"
|
|
eventfld.long 0x04 13. " SUCS ,Startup completed successfully" "Not completed,Completed"
|
|
eventfld.long 0x04 12. " SWE ,Stop watch event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 11. " TOBC ,Transfer output buffer completed" "Not completed,Completed"
|
|
eventfld.long 0x04 10. " TIBC ,Transfer input buffer completed" "Not completed,Completed"
|
|
eventfld.long 0x04 9. " TI1 ,Timer 1 flag" "Not matched,Matched"
|
|
eventfld.long 0x04 8. " TI0 ,Timer 0 flag" "Not matched,Matched"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NMVC ,Network management vector changed" "Not changed,Changed"
|
|
eventfld.long 0x04 6. " RFCL ,Receive FIFO full" "Below,Equal or above"
|
|
eventfld.long 0x04 5. " RFNE ,Receive FIFO not empty" "Empty,Not empty"
|
|
eventfld.long 0x04 4. " RXI ,Reception completion flag" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x04 3. " TXI ,Transmission completion flag" "Not completed,Completed"
|
|
eventfld.long 0x04 2. " CYCS ,Communication cycle start" "Not started,Started"
|
|
eventfld.long 0x04 1. " CAS ,Collision avoidance symbol" "Not received,Received"
|
|
eventfld.long 0x04 0. " WST ,Wakeup status" "No wakeup,Wakeup"
|
|
line.long 0x08 "EILS,Error Interrupt Line Selection Register"
|
|
bitfld.long 0x08 26. " TABBL ,Transmission across channel B slot boundary detected interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x08 25. " LTVBL ,Channel B transmission failure detected interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x08 24. " EDBL ,Error detected on channel B interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x08 18. " TABAL ,Transmission across channel A slot boundary detected interrupt line selection" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x08 17. " LTVAL ,Channel A transmission failure detected interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x08 16. " EDAL ,Error detected on channel A interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x08 11. " MHFL ,Message handler constraints flag interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x08 10. " IOBAL ,Illegal output buffer access interrupt line selection" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x08 9. " IIBAL ,Illegal input buffer access interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x08 8. " EFAL ,Empty FIFO access interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x08 7. " RFOL ,Reception FIFO overrun interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x08 6. " PERRL ,Parity error interrupt line selection" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " CCLLCHI ,Command locked interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x08 4. " CCFL ,Clock correction failure interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x08 3. " SFOL ,Sync frame overflow interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x08 2. " SFBML ,Sync frames below minimum interrupt line selection" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CNAL ,Invalid command notification interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x08 0. " PEMCLPOC ,Error mode changed interrupt line selection" "INT0,INT1"
|
|
line.long 0x0C "SILS,Status Interrupt Line Selection Register"
|
|
bitfld.long 0x0C 25. " MTSBL ,Channel B MTS received interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 24. " WUPBL ,Channel B wakeup pattern received interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 17. " MTSAL ,Channel A MTS received interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 16. " WUPAL ,Channel A wakeup pattern received interrupt line selection" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " SDSL ,Start of dynamic segment interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 14. " MBSIL ,Message buffer status changed interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 13. " SUCSL ,Startup completed successfully interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 12. " SWEL ,Stop watch event interrupt line selection" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " TOBCL ,Transfer output buffer completed interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 10. " TIBCL ,Transfer input buffer completed interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 9. " TI1L ,Timer 1 interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 8. " TI0L ,Timer 0 interrupt line selection" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " NMVCL ,Network management vector changed interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 6. " RFCLL ,Reception FIFO critical level interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 5. " RFNEL ,Reception FIFO interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 4. " RXIL ,Reception completed interrupt line selection" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " TXIL ,Transmission completed interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 2. " CYCSL ,Communication cycle start interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 1. " CASL ,Collision avoidance symbol interrupt line selection" "INT0,INT1"
|
|
bitfld.long 0x0C 0. " WSTL ,Wakeup status interrupt line selection" "INT0,INT1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "EIE_SET/CLR,Error Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 26. -0x04 26. 0x00 26. " TABBE ,Transmission across channel B slot boundary detected interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x04 25. 0x00 25. " LTVBE ,Channel B transmission failure detected interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x04 24. 0x00 24. " EDBE ,Error detected on channel B interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x04 18. 0x00 18. " TABAE ,Transmission across channel A slot boundary detected interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. 0x00 17. " LTVAE ,Channel A transmission failure detected interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x04 16. 0x00 16. " EDAE ,Error detected on channel A interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x04 11. 0x00 11. " MHFE ,Message handler constraints flag interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x04 10. 0x00 10. " IOBAE ,Illegal output buffer access interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. 0x00 9. " IIBAE ,Illegal input buffer access interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x04 8. 0x00 8. " EFAE ,Empty FIFO access interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x04 7. 0x00 7. " RFOE ,Reception FIFO overrun interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x04 6. 0x00 6. " PERRE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. 0x00 5. " CCLECHI ,Command locked interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x04 4. 0x00 4. " CCFE ,Clock correction failure interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x04 3. 0x00 3. " SFOE ,Sync frame overflow interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x04 2. 0x00 2. " SFBME ,Sync frames below minimum interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. 0x00 1. " CNAE ,Invalid command notification interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x04 0. 0x00 0. " PEMCEPOC ,Error mode changed interrupt enable" "Disabled,Enabled"
|
|
group.long 0x3C++0x0F
|
|
line.long 0x00 "SIE_SET/CLR,Status Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 25. -0x04 25. 0x00 25. " MTSBE ,MTS received on channel B interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x04 24. 0x00 24. " WUPBE ,Channel B wakeup pattern received interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x04 17. 0x00 17. " MTSAE ,MTS received on channel A interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x04 16. 0x00 16. " WUPAE ,Channel A wakeup pattern received interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. 0x00 15. " SDSE ,Start of dynamic segment interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x04 14. 0x00 14. " MBSIE ,Message buffer status changed interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x04 13. 0x00 13. " SUCSE ,Startup completed successfully interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x04 12. 0x00 12. " SWEE ,Stop watch event interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. 0x00 11. " TOBCE ,Transfer output buffer completed interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x04 10. 0x00 10. " TIBCE ,Transfer input buffer completed interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x04 9. 0x00 9. " TI1E ,Timer 1 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x04 8. 0x00 8. " TI0E ,Timer 0 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. 0x00 7. " NMVCE ,Network management vector changed interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x04 6. 0x00 6. " RFCLE ,Reception FIFO critical level interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x04 5. 0x00 5. " RFNEE ,Reception FIFO interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x04 4. 0x00 4. " RXIE ,Reception completed interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. 0x00 3. " TXIE ,Transmission completed interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x04 2. 0x00 2. " CYCSE ,Communication cycle start interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x04 1. 0x00 1. " CASE ,Collision avoidance symbol interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x04 0. 0x00 0. " WSTE ,Wakeup status interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "ILE,Interrupt Line Enable Register"
|
|
bitfld.long 0x04 1. " EINT1 ,Interrupt line INT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EINT0 ,Interrupt line INT0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "T0C,Timer 0 Configuration Register"
|
|
hexmask.long.word 0x08 16.--29. 1. " T0MO ,Timer 0 macrotick offset configuration"
|
|
hexmask.long.byte 0x08 8.--14. 1. " T0CC ,Timer 0 cycle code configuration"
|
|
bitfld.long 0x08 1. " T0MS ,Timer 0 mode select" "Single-shot,Continuous"
|
|
bitfld.long 0x08 0. " T0RC ,Timer 0 run control" "Stopped,Running"
|
|
line.long 0x0C "T1C,Timer 1 Configuration Register"
|
|
hexmask.long.word 0x0C 16.--29. 1. " T1MC ,Timer 1 macrotick count"
|
|
bitfld.long 0x0C 1. " T1MS ,Timer 1 mode select" "Single-shot,Continuous"
|
|
bitfld.long 0x0C 0. " T1RC ,Timer 1 run control" "Stopped,Running"
|
|
if (((per.l(ad:0xB2001000+0x4C))&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "STPW1,Stop Watch Register 1"
|
|
hexmask.long.word 0x00 16.--29. 1. " SMTV ,Stop watch event occurrence macrotick value"
|
|
rbitfld.long 0x00 8.--13. " SCCV ,Stop watch event occurrence cycle counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6. " EINT1 ,Enable interrupt 1 trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EINT0 ,Enable interrupt 0 trigger" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EETP ,Enable external trigger pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSWT ,Software stop watch trigger" "Cleared,Activated"
|
|
bitfld.long 0x00 2. " EDGE ,Stop watch trigger edge select" "Falling,Rising"
|
|
bitfld.long 0x00 1. " SWMS ,Stop watch mode select" "Single,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ESWT ,Enable stop watch trigger" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "STPW1,Stop Watch Register 1"
|
|
hexmask.long.word 0x00 16.--29. 1. " SMTV ,Stop watch event occurrence macrotick value"
|
|
rbitfld.long 0x00 8.--13. " SCCV ,Stop watch event occurrence cycle counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6. " EINT1 ,Enable interrupt 1 trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EINT0 ,Enable interrupt 0 trigger" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EETP ,Enable external trigger pin" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " SSWT ,Software stop watch trigger" "Cleared,Activated"
|
|
bitfld.long 0x00 2. " EDGE ,Stop watch trigger edge select" "Falling,Rising"
|
|
bitfld.long 0x00 1. " SWMS ,Stop watch mode select" "Single,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ESWT ,Enable stop watch trigger" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "STPW2,Stop Watch Register 2"
|
|
hexmask.long.word 0x00 16.--26. 1. " SSCVB ,Channel B stop watch counter value"
|
|
hexmask.long.word 0x00 0.--10. 1. " SSCVA ,Channel A stop watch counter value"
|
|
tree.end
|
|
tree "Communication Controller Control Registers"
|
|
if (((per.l(ad:0xB2001000+0x80))&0x80)==0x00)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SUCC1,SUC Configuration Register 1"
|
|
bitfld.long 0x00 27. " CCHB ,Connected to channel B (pChannels)" "Not connected,Connected"
|
|
bitfld.long 0x00 26. " CCHA ,Connected to channel A (pChannels)" "Not connected,Connected"
|
|
bitfld.long 0x00 25. " MTSB ,Select channel B for MTS symbol transmission" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " MTSA ,Select channel A for MTS symbol transmission" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " HCSE ,Halt due to clock sync error (pAllowHaltDueToClock)" "NORMAL_PASSIVE,HALT"
|
|
bitfld.long 0x00 22. " TSM ,Transmission slot mode selection (pSingleSlotEnabled)" "ALL,SINGLE"
|
|
bitfld.long 0x00 21. " WUCS ,Wakeup pattern transmission channel selection (pWakeupChannel)" "Channel A,Channel B"
|
|
bitfld.long 0x00 16.--20. " PTA ,Required cycle pairs for state transition between passive and active (pAllowPassiveToActive)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " CSA ,Cold start attempts (gColdStartAttempts)" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. " TXSY ,Synchronization frame transmission in key slot (pKeySlotUsedForSync)" "Not used,Used"
|
|
bitfld.long 0x00 8. " TXST ,Startup frame transmission in key slot (pKeySlotUsedForStartup)" "Not used,Used"
|
|
rbitfld.long 0x00 7. " PBSY ,POC busy" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CMD ,CHI command vector" "COMMAND_NOT_ACCEPTED,CONFIG,READY,WAKEUP,RUN,ALL_SLOTS,HALT,FREEZE,SEND_MTS,ALLOW_COLDSTART,RESET_STATUS_INDICATORS,MONITOR_MODE,CLEAR_RAMS,?..."
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SUCC1,SUC Configuration Register 1"
|
|
bitfld.long 0x00 27. " CCHB ,Connected to channel B" "Not connected,Connected"
|
|
bitfld.long 0x00 26. " CCHA ,Connected to channel A" "Not connected,Connected"
|
|
bitfld.long 0x00 25. " MTSB ,Select channel B for MTS symbol transmission" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " MTSA ,Select channel A for MTS symbol transmission" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " HCSE ,Halt due to clock sync error" "NORMAL_PASSIVE,HALT"
|
|
bitfld.long 0x00 22. " TSM ,Transmission slot mode selection" "ALL,SINGLE"
|
|
bitfld.long 0x00 21. " WUCS ,Wakeup pattern transmission channel selection" "Channel A,Channel B"
|
|
bitfld.long 0x00 16.--20. " PTA ,Required cycle pairs for state transition between passive and active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " CSA ,Cold start attempts" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. " TXSY ,Synchronization frame transmission in key slot (pKeySlotUsedForSync)" "Not used,Used"
|
|
bitfld.long 0x00 8. " TXST ,Startup frame transmission in key slot (pKeySlotUsedForStartup)" "Not used,Used"
|
|
rbitfld.long 0x00 7. " PBSY ,POC busy" "Idle,Busy"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--3. " CMD ,CHI command vector" "COMMAND_NOT_ACCEPTED,CONFIG,READY,WAKEUP,RUN,ALL_SLOTS,HALT,FREEZE,SEND_MTS,ALLOW_COLDSTART,RESET_STATUS_INDICATORS,MONITOR_MODE,CLEAR_RAMS,?..."
|
|
endif
|
|
if (((per.l(ad:0xB2001000+0x100))&0x3F)==(0x00||0x0F))
|
|
group.long 0x84++0x17
|
|
line.long 0x00 "SUCC2,SUC Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. " LTN ,Listen timeout noise value (gListenNoise-1)" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " LT ,Listen timeout value (pdListenTimeout)"
|
|
line.long 0x04 "SUCC3,SUC Configuration Register 3"
|
|
bitfld.long 0x04 4.--7. " WCF ,Maximum HALT transition time without clock correction (gMaxWithoutClockCorrectionFatal)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " WCP ,Maximum PASSIVE transition time without clock correction (gMaxWithoutClockCorrectionPassive)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "NEMC,NEM Configuration Register"
|
|
bitfld.long 0x08 0.--3. " NML ,Network management vector length (gNetworkManagementVectorLength)" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
line.long 0x0C "PRTC1,PRT Configuration Register 1"
|
|
bitfld.long 0x0C 26.--31. " RWP ,Wakeup pattern transmission count (pWakeupPattern)" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x0C 16.--24. 1. " RXW ,Wakeup symbol reception window length (gdWakeupSymbolRxWindow)"
|
|
bitfld.long 0x0C 14.--15. " BRP ,Baud rate prescaler (gdSampleClockPeriod, pSamplePerMicrotick)" "1/SCLK(s),2/SCLK(s),4/SCLK(s),4/SCLK(s)"
|
|
bitfld.long 0x0C 12.--13. " SPP ,Strobe point position" "5,4,6,5"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 4.--10. 1. " CASM ,Collision avoidance symbol upper limit (gdCASRxLowMax)"
|
|
bitfld.long 0x0C 0.--3. " TSST ,Transmission start sequence time (gdTSSTransmitter)" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "PRTC2,PRT Configuration Register 2"
|
|
bitfld.long 0x10 24.--29. " TXL ,Wakeup symbol transmission low time (gdWakeupSymbolTxLow)" ",,,,,,,,,,,,,,,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,?..."
|
|
hexmask.long.byte 0x10 16.--23. 1. " TXI ,Wakeup symbol transmission idle phase time (gdWakeupSymbolTxIdle)"
|
|
bitfld.long 0x10 8.--13. " RXL ,Wakeup reception low time (gdWakeupSymbolRxLow)" ",,,,,,,,,,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,?..."
|
|
bitfld.long 0x10 0.--5. " RXI ,Wakeup reception idle phase time (gdWakeupSymbolRxIdle)" ",,,,,,,,,,,,,,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
line.long 0x14 "MHDC,MHD Configuration Register"
|
|
hexmask.long.word 0x14 16.--28. 1. " SLT ,Transmission end minislot value (pLatestTx)"
|
|
hexmask.long.byte 0x14 0.--6. 1. " SFDL ,Static frame data length (gPayloadLengthStatic)"
|
|
group.long 0xA0++0x02B
|
|
line.long 0x00 "GTUC1,GTU Configuration Register 1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " UT ,Microtick per cycle (pMicroPerCycle)"
|
|
line.long 0x04 "GTUC2,GTU Configuration Register 2"
|
|
bitfld.long 0x04 16.--19. " SNM ,Maximum sync node (gSyncNodeMax)" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--13. 1. " MPC ,Macrotick per cycle (gMacroPerCycle)"
|
|
line.long 0x08 "GTUC3,GTU Configuration Register 3"
|
|
hexmask.long.byte 0x08 24.--30. 1. " MIOB ,Channel B macrotick initial offset (pMacroInitialOffset[B])"
|
|
hexmask.long.byte 0x08 16.--22. 1. " MIOA ,Channel A macrotick initial offset (pMacroInitialOffset[A])"
|
|
hexmask.long.byte 0x08 8.--15. 1. " UIOB ,Channel B microtick initial offset (pMicroInitialOffset[B])"
|
|
hexmask.long.byte 0x08 0.--7. 1. " UIOA ,Channel A microtick initial offset (pMicroInitialOffset[A])"
|
|
line.long 0x0C "GTUC4,GTU Configuration Register 4"
|
|
hexmask.long.word 0x0C 16.--29. 1. " OCS ,Offset correction start (gOffsetCorrectionStart - 1)"
|
|
hexmask.long.word 0x0C 0.--13. 1. " NIT ,Network idle time start (gMacroPerCycle - gdNIT - 1)"
|
|
line.long 0x10 "GTUC5,GTU Configuration Register 5"
|
|
hexmask.long.byte 0x10 24.--31. 1. " DEC ,Decoding correction value (pDecodingCorrection)"
|
|
bitfld.long 0x10 16.--20. " CDD ,Cluster drift damping (pClusterDriftDamping)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,?..."
|
|
hexmask.long.byte 0x10 0.--7. 1. " DCB ,Channel B reception delay compensation (pDelayCompensation[B])"
|
|
hexmask.long.byte 0x10 8.--15. 1. " DCA ,Channel A reception delay compensation (pDelayCompensation[A])"
|
|
line.long 0x14 "GTUC6,GTU Configuration Register 6"
|
|
hexmask.long.word 0x14 16.--26. 1. " MOD ,Maximum oscillator drift (pdMaxDrift)"
|
|
hexmask.long.word 0x14 0.--10. 1. " ASR ,Acceptance startup range (pdAcceptedStartupRange)"
|
|
line.long 0x18 "GTUC7,GTU Configuration Register 7"
|
|
hexmask.long.word 0x18 16.--25. 1. " NSS ,Number of static slots (gNumberOfStaticSlots)"
|
|
hexmask.long.word 0x18 0.--9. 1. " SSL ,Static slot length (gdStaticSlot)"
|
|
line.long 0x1C "GTUC8,GTU Configuration Register 8"
|
|
hexmask.long.word 0x1C 16.--28. 1. " NMS ,Number of minislots (gNumberOfMinislots)"
|
|
bitfld.long 0x1C 0.--5. " MSL ,Minislot length (gdMinislot)" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x20 "GTUC9,GTU Configuration Register 9"
|
|
bitfld.long 0x20 16.--17. " DSI ,Dynamic slot idle phase (gdDynamicSlotIdlePhase)" "0,1,2,?..."
|
|
bitfld.long 0x20 8.--12. " MAPO ,Minislot action point offset (gdMinislotActionPointOffset)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x20 0.--5. " APO ,Action point offset (gdActionPointOffset)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x24 "GTUC10,GTU Configuration Register 10"
|
|
hexmask.long.word 0x24 16.--26. 1. " MRC ,Maximum rate correction value (pRateCorrectionOut)"
|
|
hexmask.long.word 0x24 0.--13. 1. " MOC ,Maximum offset correction value (pOffsetCorrectionOut)"
|
|
line.long 0x28 "GTUC11,GTU Configuration Register 11"
|
|
bitfld.long 0x28 24.--26. " ERC ,External rate correction (pExternRateCorrection)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 16.--18. " EOC ,External offset correction (pExternOffsetCorrection)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 8.--9. " ERCC ,External rate correction control (vExternRateControl)" "No correction,No correction,Subtract,Add"
|
|
bitfld.long 0x28 0.--1. " EOCC ,External offset correction control (vExternOffsetControl)" "No correction,No correction,Subtract,Add"
|
|
else
|
|
rgroup.long 0x84++0x17
|
|
line.long 0x00 "SUCC2,SUC Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. " LTN ,Listen timeout noise value (gListenNoise-1)" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " LT ,Listen timeout value (pdListenTimeout)"
|
|
line.long 0x04 "SUCC3,SUC Configuration Register 3"
|
|
bitfld.long 0x04 4.--7. " WCF ,Maximum HALT transition time without clock correction (gMaxWithoutClockCorrectionFatal)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " WCP ,Maximum PASSIVE transition time without clock correction (gMaxWithoutClockCorrectionPassive)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "NEMC,NEM Configuration Register"
|
|
bitfld.long 0x08 0.--3. " NML ,Network management vector length (gNetworkManagementVectorLength)" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
line.long 0x0C "PRTC1,PRT Configuration Register 1"
|
|
bitfld.long 0x0C 26.--31. " RWP ,Wakeup pattern transmission count (pWakeupPattern)" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x0C 16.--24. 1. " RXW ,Wakeup symbol reception window length (gdWakeupSymbolRxWindow)"
|
|
bitfld.long 0x0C 14.--15. " BRP ,Baud rate prescaler (gdSampleClockPeriod, pSamplePerMicrotick)" "1/SCLK(s),2/SCLK(s),4/SCLK(s),4/SCLK(s)"
|
|
bitfld.long 0x0C 12.--13. " SPP ,Strobe point position" "5,4,6,5"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 4.--10. 1. " CASM ,Collision avoidance symbol upper limit (gdCASRxLowMax)"
|
|
bitfld.long 0x0C 0.--3. " TSST ,Transmission start sequence time (gdTSSTransmitter)" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "PRTC2,PRT Configuration Register 2"
|
|
bitfld.long 0x10 24.--29. " TXL ,Wakeup symbol transmission low time (gdWakeupSymbolTxLow)" ",,,,,,,,,,,,,,,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,?..."
|
|
hexmask.long.byte 0x10 16.--23. 1. " TXI ,Wakeup symbol transmission idle phase time (gdWakeupSymbolTxIdle)"
|
|
bitfld.long 0x10 8.--13. " RXL ,Wakeup reception low time (gdWakeupSymbolRxLow)" ",,,,,,,,,,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,?..."
|
|
bitfld.long 0x10 0.--5. " RXI ,Wakeup reception idle phase time (gdWakeupSymbolRxIdle)" ",,,,,,,,,,,,,,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
line.long 0x14 "MHDC,MHD Configuration Register"
|
|
hexmask.long.word 0x14 16.--28. 1. " SLT ,Transmission end minislot value (pLatestTx)"
|
|
hexmask.long.byte 0x14 0.--6. 1. " SFDL ,Static frame data length (gPayloadLengthStatic)"
|
|
rgroup.long 0xA0++0x02B
|
|
line.long 0x00 "GTUC1,GTU Configuration Register 1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " UT ,Microtick per cycle (pMicroPerCycle)"
|
|
line.long 0x04 "GTUC2,GTU Configuration Register 2"
|
|
bitfld.long 0x04 16.--19. " SNM ,Maximum sync node (gSyncNodeMax)" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--13. 1. " MPC ,Macrotick per cycle (gMacroPerCycle)"
|
|
line.long 0x08 "GTUC3,GTU Configuration Register 3"
|
|
hexmask.long.byte 0x08 24.--30. 1. " MIOB ,Channel B macrotick initial offset (pMacroInitialOffset[B])"
|
|
hexmask.long.byte 0x08 16.--22. 1. " MIOA ,Channel A macrotick initial offset (pMacroInitialOffset[A])"
|
|
hexmask.long.byte 0x08 8.--15. 1. " UIOB ,Channel B microtick initial offset (pMicroInitialOffset[B])"
|
|
hexmask.long.byte 0x08 0.--7. 1. " UIOA ,Channel A microtick initial offset (pMicroInitialOffset [A])"
|
|
line.long 0x0C "GTUC4,GTU Configuration Register 4"
|
|
hexmask.long.word 0x0C 16.--29. 1. " OCS ,Offset correction start (gOffsetCorrectionStart - 1)"
|
|
hexmask.long.word 0x0C 0.--13. 1. " NIT ,Network idle time start (gMacroPerCycle - gdNIT - 1)"
|
|
line.long 0x10 "GTUC5,GTU Configuration Register 5"
|
|
hexmask.long.byte 0x10 24.--31. 1. " DEC ,Decoding correction value (pDecodingCorrection)"
|
|
bitfld.long 0x10 16.--20. " CDD ,Cluster drift damping (pClusterDriftDamping)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,?..."
|
|
hexmask.long.byte 0x10 0.--7. 1. " DCB ,Channel B reception delay compensation (pDelayCompensation[B])"
|
|
hexmask.long.byte 0x10 8.--15. 1. " DCA ,Channel A reception delay compensation (pDelayCompensation[A])"
|
|
line.long 0x14 "GTUC6,GTU Configuration Register 6"
|
|
hexmask.long.word 0x14 16.--26. 1. " MOD ,Maximum oscillator drift (pdMaxDrift)"
|
|
hexmask.long.word 0x14 0.--10. 1. " ASR ,Acceptance startup range (pdAcceptedStartupRange)"
|
|
line.long 0x18 "GTUC7,GTU Configuration Register 7"
|
|
hexmask.long.word 0x18 16.--25. 1. " NSS ,Number of static slots (gNumberOfStaticSlots)"
|
|
hexmask.long.word 0x18 0.--9. 1. " SSL ,Static slot length (gdStaticSlot)"
|
|
line.long 0x1C "GTUC8,GTU Configuration Register 8"
|
|
hexmask.long.word 0x1C 16.--28. 1. " NMS ,Number of minislots (gNumberOfMinislots)"
|
|
bitfld.long 0x1C 0.--5. " MSL ,Minislot length (gdMinislot)" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x20 "GTUC9,GTU Configuration Register 9"
|
|
bitfld.long 0x20 16.--17. " DSI ,Dynamic slot idle phase (gdDynamicSlotIdlePhase)" "0,1,2,?..."
|
|
bitfld.long 0x20 8.--12. " MAPO ,Minislot action point offset (gdMinislotActionPointOffset)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x20 0.--5. " APO ,Action point offset (gdActionPointOffset)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x24 "GTUC10,GTU Configuration Register 10"
|
|
hexmask.long.word 0x24 16.--26. 1. " MRC ,Maximum rate correction value (pRateCorrectionOut)"
|
|
hexmask.long.word 0x24 0.--13. 1. " MOC ,Maximum offset correction value (pOffsetCorrectionOut)"
|
|
line.long 0x28 "GTUC11,GTU Configuration Register 11"
|
|
bitfld.long 0x28 24.--26. " ERC ,External rate correction (pExternRateCorrection)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 16.--18. " EOC ,External offset correction (pExternOffsetCorrection)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 8.--9. " ERCC ,External rate correction control (vExternRateControl)" "No correction,No correction,Subtract,Add"
|
|
bitfld.long 0x28 0.--1. " EOCC ,External offset correction control (vExternOffsetControl)" "No correction,No correction,Subtract,Add"
|
|
endif
|
|
tree.end
|
|
tree "Communication Controller Status Registers"
|
|
rgroup.long 0x100++0x07
|
|
line.long 0x00 "CCSV,CC Status Vector Register"
|
|
bitfld.long 0x00 24.--29. " PSL ,POC status log" "DEFAULT_CONFIG,READY,NORMAL_ACTIVE,NORMAL_PASSIVE,HALT,MONITOR_MODE,,,,,,,,,,CONFIG,WAKEUP_STANDBY,WAKEUP_LISTEN,WAKEUP_SEND,WAKEUP_DETECT,,,,,,,,,,,,,STARTUP_PREPARE,COLDSTART_LISTEN,COLDSTART_COLLISION_RESOLUTION,COLDSTART_CONSISTENCY_CHECK,COLDSTART_GAP,COLDSTART_JOIN,INTEGRATION_COLDSTART_CHECK,INTEGRATION_LISTEN,INTEGRATION_CONSISTENCY_CHECK,INITIALIZE_SCHEDULE,ABORT_STARTUP,STARTUP_SUCCESS,?..."
|
|
bitfld.long 0x00 19.--23. " RCA ,Remaining cold start attempts (vRemainingColdstartAttempts)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " WSV ,Wakeup status (vPOC!WakeupStatus)" "UNDEFINED,RECEIVED_HEADER,RECEIVED_WUP,A COLLISION_HEADER,COLLISION_WUP,COLLISION_UNKNOWN,TRANSMITTED,?..."
|
|
bitfld.long 0x00 14. " CSI ,Cold start inhibit (vColdStartInhibit)" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CSAI ,Cold start abort indicator" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " CSNI ,Cold start noise indicator (vColdStartNoise)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8.--9. " SLM ,Slot mode (vPOC!SlotMode)" "SINGLE,,ALL_PENDING,ALL"
|
|
bitfld.long 0x00 7. " HRQ ,Halt request (vPOC!CHIHaltRequest)" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSI ,Freeze status indicator (vPOC!Freeze)" "Not frozen,Frozen"
|
|
bitfld.long 0x00 0.--5. " POCS ,POC state (Protocol Operation Control Status)" "DEFAULT_CONFIG,READY,NORMAL_ACTIVE,NORMAL_PASSIVE,HALT,MONITOR_MODE,,,,,,,,,,CONFIG,WAKEUP_STANDBY,WAKEUP_LISTEN,WAKEUP_SEND,WAKEUP_DETECT,,,,,,,,,,,,,STARTUP_PREPARE,COLDSTART_LISTEN,COLDSTART_COLLISION_RESOLUTION,COLDSTART_CONSISTENCY_CHECK,COLDSTART_GAP,COLDSTART_JOIN,INTEGRATION_COLDSTART_CHECK,INTEGRATION_LISTEN,INTEGRATION_CONSISTENCY_CHECK,INITIALIZE_SCHEDULE,ABORT_STARTUP,STARTUP_SUCCESS,?..."
|
|
line.long 0x04 "CCEV,CC Error Vector Register"
|
|
bitfld.long 0x04 8.--12. " PTAC ,Counter for cycle pair number required for state transition from passive to active (vAllowPassiveToActive)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 6.--7. " ERRM ,Error mode (vPOC!ErrorMode)" "ACTIVE,PASSIVE,COMM_HALT,?..."
|
|
bitfld.long 0x04 0.--3. " CCFC ,Clock correction failed counter (vClockCorrectionFailed)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x110++0x17
|
|
line.long 0x00 "SCV,Slot Counter Value Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " SCCB ,Channel B slot counter (vSlotCounter[B])"
|
|
hexmask.long.word 0x00 0.--10. 1. " SCCA ,Channel A slot counter (vSlotCounter[A])"
|
|
line.long 0x04 "MTCCV,Macrotick And Cycle Counter Value Register"
|
|
bitfld.long 0x04 16.--21. " CCV ,Cycle counter value (vCycleCounter)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x04 0.--13. 1. " MTV ,Macrotick value (vMacrotick)"
|
|
line.long 0x08 "RCV,Rate Correction Value Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " RCV ,Rate correction value (vRateCorrection)"
|
|
line.long 0x0C "OCV,Offset Correction Value Register"
|
|
hexmask.long.tbyte 0x0C 0.--18. 1. " OCV ,Offset correction value (vOffsetCorrection)"
|
|
line.long 0x10 "SFS,Sync Frame Status Register"
|
|
bitfld.long 0x10 19. " RCLR ,Rate correction limit reached" "Not exceeded,Exceeded"
|
|
bitfld.long 0x10 18. " MRCS ,Missing rate correction signal" "Enabled,Missing"
|
|
bitfld.long 0x10 17. " OCLR ,Offset correction limit reached" "Not exceeded,Exceeded"
|
|
bitfld.long 0x10 16. " MOCS ,Missing offset correction signal" "Enabled,Missing"
|
|
textline " "
|
|
bitfld.long 0x10 12.--15. " VSBO ,Channel B valid sync frames, odd communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. " VSBE ,Channel B valid sync frames, even communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 4.--7. " VSAO ,Channel A valid sync frames, odd communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " VSAE ,Channel A valid sync frames, even communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "SWNIT,Symbol Window And NIT Status Register"
|
|
bitfld.long 0x14 11. " SBNB ,Channel B slot boundary violation during NIT (vSS!BViolationB)" "Not detected,Detected"
|
|
bitfld.long 0x14 10. " SENB ,Channel B syntax error during NIT (vSS!SyntaxErrorB)" "Not detected,Detected"
|
|
bitfld.long 0x14 9. " SBNA ,Channel A slot boundary violation during NIT (vSS!BViolationA)" "Not detected,Detected"
|
|
bitfld.long 0x14 8. " SENA ,Channel A syntax error during NIT (vSS!SyntaxErrorA)" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x14 7. " MTSB ,Channel B media access test symbol detection (vSS!ValidMTSB)" "Not detected,Detected"
|
|
bitfld.long 0x14 6. " MTSA ,Channel A media access test symbol detection (vSS!ValidMTSA)" "Not detected,Detected"
|
|
bitfld.long 0x14 5. " TCSB ,Channel B symbol window transmission collision detection (vSS!TxConflictB)" "Not detected,Detected"
|
|
bitfld.long 0x14 4. " SBSB ,Channel B symbol window slot boundary violation (vSS!BViolationB)" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x14 3. " SESB ,Channel B symbol window syntax error (vSS!SyntaxErrorB)" "Not detected,Detected"
|
|
bitfld.long 0x14 2. " TCSA ,Channel A symbol window transmission collision detection (vSS!TxConflictA)" "Not detected,Detected"
|
|
bitfld.long 0x14 1. " SBSA ,Channel A symbol window slot boundary violation (vSS!BViolationA)" "Not detected,Detected"
|
|
bitfld.long 0x14 0. " SESA ,Channel A symbol window syntax error (vSS!SyntaxErrorA)" "Not detected,Detected"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "ACS,Aggregated Channel Status Register"
|
|
eventfld.long 0x00 12. " SBVB ,Channel B slot boundary violation (vSS!BViolationB)" "Not observed,Observed"
|
|
eventfld.long 0x00 11. " CIB ,Channel B additional communication detection" "Not received,Received"
|
|
eventfld.long 0x00 10. " CEDB ,Channel B content error detection (vSS!ContentErrorB)" "Not detected,Detected"
|
|
eventfld.long 0x00 9. " SEDB ,Channel B syntax error detection (vSS!SyntaxErrorB)" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 8. " VFRB ,Channel B valid frame reception (vSS!ValidFrameB)" "Not received,Received"
|
|
eventfld.long 0x00 4. " SBVA ,Channel A slot boundary violation (vSS!BViolationA)" "Not observed,Observed"
|
|
eventfld.long 0x00 3. " CIA ,Channel A additional communication detection" "Not received,Received"
|
|
eventfld.long 0x00 2. " CEDA ,Channel A content error detection (vSS!ContentErrorA)" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " SEDA ,Channel A syntax error detection (vSS!SyntaxErrorA)" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " VFRA ,Channel A valid frame reception (vSS!ValidFrameA)" "Not received,Received"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "ESID1,Even Cycle Sync Frame ID Register 1"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "ESID2,Even Cycle Sync Frame ID Register 2"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "ESID3,Even Cycle Sync Frame ID Register 3"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "ESID4,Even Cycle Sync Frame ID Register 4"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "ESID5,Even Cycle Sync Frame ID Register 5"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "ESID6,Even Cycle Sync Frame ID Register 6"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "ESID7,Even Cycle Sync Frame ID Register 7"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "ESID8,Even Cycle Sync Frame ID Register 8"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "ESID9,Even Cycle Sync Frame ID Register 9"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "ESID10,Even Cycle Sync Frame ID Register 10"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "ESID11,Even Cycle Sync Frame ID Register 11"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "ESID12,Even Cycle Sync Frame ID Register 12"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "ESID13,Even Cycle Sync Frame ID Register 13"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "ESID14,Even Cycle Sync Frame ID Register 14"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "ESID15,Even Cycle Sync Frame ID Register 15"
|
|
bitfld.long 0x00 15. " RXEB ,Even cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Even cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID ,Even cycle sync frame ID (vsSyncIDListA,B even)"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "OSID1,Odd Cycle Sync Frame ID Register 1"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "OSID2,Odd Cycle Sync Frame ID Register 2"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "OSID3,Odd Cycle Sync Frame ID Register 3"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "OSID4,Odd Cycle Sync Frame ID Register 4"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "OSID5,Odd Cycle Sync Frame ID Register 5"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "OSID6,Odd Cycle Sync Frame ID Register 6"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "OSID7,Odd Cycle Sync Frame ID Register 7"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "OSID8,Odd Cycle Sync Frame ID Register 8"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "OSID9,Odd Cycle Sync Frame ID Register 9"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "OSID10,Odd Cycle Sync Frame ID Register 10"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "OSID11,Odd Cycle Sync Frame ID Register 11"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "OSID12,Odd Cycle Sync Frame ID Register 12"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "OSID13,Odd Cycle Sync Frame ID Register 13"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "OSID14,Odd Cycle Sync Frame ID Register 14"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "OSID15,Odd Cycle Sync Frame ID Register 15"
|
|
bitfld.long 0x00 15. " RXOB ,Odd cycle sync frame channel B reception" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXOA ,Odd cycle sync frame channel A reception" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID ,Odd cycle sync frame ID (vsSyncIDListA,B odd)"
|
|
rgroup.long 0x1B0++0x0B
|
|
line.long 0x00 "NMV1,Network Management Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,NM vector 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,NM vector 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,NM vector 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,NM vector 0"
|
|
line.long 0x04 "NMV2,Network Management Register 2"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,NM vector 7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,NM vector 6"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,NM vector 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,NM vector 4"
|
|
line.long 0x08 "NMV3,Network Management Register 3"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA11 ,NM vector 11"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA10 ,NM vector 10"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA9 ,NM vector 9"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA8 ,NM vector 8"
|
|
tree.end
|
|
tree "Message Buffer Control Registers"
|
|
if (((per.l(ad:0xB2001000+0x100))&0x3F)==(0x00||0x0F))
|
|
group.long 0x300++0x0F
|
|
line.long 0x00 "MRC,Message RAM Configuration Register"
|
|
bitfld.long 0x00 26. " SPLM ,Sync frame payload multiplex" "Buffers 0 and 1,Buffer 0"
|
|
bitfld.long 0x00 24.--25. " SEC ,Secure buffer" "Enabled for buffers with number <=FFB,Locked for buffers with number <=FDB,Locked for all buffers,Locked for all buffers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCB ,Last message buffer number"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FFB ,First FIFO buffer number"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " FDB ,First dynamic buffer number"
|
|
line.long 0x04 "FRF,FIFO Rejection Filter Register"
|
|
bitfld.long 0x04 24. " RNF ,Null frame rejection" "Not rejected,Rejected"
|
|
bitfld.long 0x04 23. " RSS ,Message rejection in static segment" "Not rejected,Rejected"
|
|
hexmask.long.byte 0x04 16.--22. 1. " CYF ,Cycle code filter"
|
|
hexmask.long.word 0x04 2.--12. 1. " FID ,Frame ID filter"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CH ,Channel filter" "Both channels,Channel B,Channel A,Not possible"
|
|
line.long 0x08 "FRFM,FIFO Rejection Filter Mask Register"
|
|
hexmask.long.word 0x08 2.--12. 1. " MFID ,Mask frame ID filter"
|
|
line.long 0x0C "FCL,FIFO Critical Level Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CL ,Critical level"
|
|
else
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "MRC,Message RAM Configuration Register"
|
|
bitfld.long 0x00 26. " SPLM ,Sync frame payload multiplex" "Buffers 0 and 1,Buffer 0"
|
|
bitfld.long 0x00 24.--25. " SEC ,Secure buffer" "Enabled for buffers with number <=FFB,Locked for buffers with number <=FDB,Locked for all buffers,Locked for all buffers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCB ,Last message buffer number"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FFB ,First FIFO buffer number"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " FDB ,First dynamic buffer number"
|
|
line.long 0x04 "FRF,FIFO Rejection Filter Register"
|
|
bitfld.long 0x04 24. " RNF ,Null frame rejection" "Not rejected,Rejected"
|
|
bitfld.long 0x04 23. " RSS ,Message rejection in static segment" "Not rejected,Rejected"
|
|
hexmask.long.byte 0x04 16.--22. 1. " CYF ,Cycle code filter"
|
|
hexmask.long.word 0x04 2.--12. 1. " FID ,Frame ID filter"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CH ,Channel filter" "Both channels,Channel B,Channel A,Not possible"
|
|
line.long 0x08 "FRFM,FIFO Rejection Filter Mask Register"
|
|
hexmask.long.word 0x08 2.--12. 1. " MFID ,Mask frame ID filter"
|
|
line.long 0x0C "FCL,FIFO Critical Level Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CL ,Critical level"
|
|
endif
|
|
tree.end
|
|
tree "Message Buffer Status Registers"
|
|
group.long 0x310++0x0F
|
|
line.long 0x00 "MHDS,Message Handler Status Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " MBU ,Updated message buffer number"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBT ,Transmission message buffer number"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FMB ,Faulty message error"
|
|
bitfld.long 0x00 7. " CRAM ,Clear of all internal RAM" "Not running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MFMB ,Multiple faulty message buffers detected" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " FMBD ,Faulty message buffer detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " PTBF2 ,Parity error detection at read of transient buffer RAM B" "No error,Error"
|
|
bitfld.long 0x00 3. " PTBF1 ,Parity error detection at read of transient buffer RAM A" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PMR ,Parity error detection at read of message RAM" "No error,Error"
|
|
bitfld.long 0x00 1. " POBF ,Parity error detection at read of output buffer RAM 1 and 2" "No error,Error"
|
|
bitfld.long 0x00 0. " PIBF ,Parity error detection at read of input buffer RAM 1 and 2" "No error,Error"
|
|
line.long 0x04 "LDTS,Last Dynamic Transmission Slot Register"
|
|
hexmask.long.word 0x04 16.--26. 1. " LDTB ,Last dynamic transmission channel B"
|
|
hexmask.long.word 0x04 0.--10. 1. " LDTA ,Last dynamic transmission channel A"
|
|
line.long 0x08 "FSR,FIFO Status Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " RFFL ,Reception FIFO fill level"
|
|
bitfld.long 0x08 2. " RFO ,Reception FIFO overrun" "No overrun,Overrun"
|
|
bitfld.long 0x08 1. " RFCL ,Reception FIFO critical level" "Below critical,At critical"
|
|
bitfld.long 0x08 0. " RFNE ,Reception FIFO not empty" "Empty,Not empty"
|
|
line.long 0x0C "MHDF,Message Handler Constraints Flags"
|
|
eventfld.long 0x0C 8. " WAHP ,Header partition write" "Not written,Written"
|
|
eventfld.long 0x0C 7. " TNSB ,Channel B transmission not started" "Started,Not started"
|
|
eventfld.long 0x0C 6. " TNSA ,Channel A transmission not started" "Started,Not started"
|
|
eventfld.long 0x0C 5. " TBFB ,Channel B transient buffer access failure" "No failure,Failure"
|
|
textline " "
|
|
eventfld.long 0x0C 4. " TBFA ,Channel A transient buffer access failure" "No failure,Failure"
|
|
eventfld.long 0x0C 3. " FNFB ,Channel B sequence not finished" "Not detected,Detected"
|
|
eventfld.long 0x0C 2. " FNFA ,Channel A sequence not finished" "Not detected,Detected"
|
|
eventfld.long 0x0C 1. " SNUB ,Channel B status not updated" "Updated,Not updated"
|
|
textline " "
|
|
eventfld.long 0x0C 0. " SNUA ,Channel A status not updated" "Updated,Not updated"
|
|
rgroup.long 0x320++0x2F
|
|
line.long 0x00 "TXRQ1,Transmission Request Register 1"
|
|
bitfld.long 0x00 31. " TXR31 ,Transmission request flag 31" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " TXR30 ,Transmission request flag 30" "Not requested,Requested"
|
|
bitfld.long 0x00 29. " TXR29 ,Transmission request flag 29" "Not requested,Requested"
|
|
bitfld.long 0x00 28. " TXR28 ,Transmission request flag 28" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 27. " TXR27 ,Transmission request flag 27" "Not requested,Requested"
|
|
bitfld.long 0x00 26. " TXR26 ,Transmission request flag 26" "Not requested,Requested"
|
|
bitfld.long 0x00 25. " TXR25 ,Transmission request flag 25" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " TXR24 ,Transmission request flag 24" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TXR23 ,Transmission request flag 23" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " TXR22 ,Transmission request flag 22" "Not requested,Requested"
|
|
bitfld.long 0x00 21. " TXR21 ,Transmission request flag 21" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " TXR20 ,Transmission request flag 20" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXR19 ,Transmission request flag 19" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " TXR18 ,Transmission request flag 18" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " TXR17 ,Transmission request flag 17" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " TXR16 ,Transmission request flag 16" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TXR15 ,Transmission request flag 15" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " TXR14 ,Transmission request flag 14" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " TXR13 ,Transmission request flag 13" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " TXR12 ,Transmission request flag 12" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXR11 ,Transmission request flag 11" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " TXR10 ,Transmission request flag 10" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " TXR9 ,Transmission request flag 9" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " TXR8 ,Transmission request flag 8" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXR7 ,Transmission request flag 7" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " TXR6 ,Transmission request flag 6" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " TXR5 ,Transmission request flag 5" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " TXR4 ,Transmission request flag 4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TXR3 ,Transmission request flag 3" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " TXR2 ,Transmission request flag 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " TXR1 ,Transmission request flag 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " TXR0 ,Transmission request flag 0" "Not requested,Requested"
|
|
line.long 0x04 "TXRQ2,Transmission Request Register 2"
|
|
bitfld.long 0x04 31. " TXR63 ,Transmission request flag 63" "Not requested,Requested"
|
|
bitfld.long 0x04 30. " TXR62 ,Transmission request flag 62" "Not requested,Requested"
|
|
bitfld.long 0x04 29. " TXR61 ,Transmission request flag 61" "Not requested,Requested"
|
|
bitfld.long 0x04 28. " TXR60 ,Transmission request flag 60" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 27. " TXR59 ,Transmission request flag 59" "Not requested,Requested"
|
|
bitfld.long 0x04 26. " TXR58 ,Transmission request flag 58" "Not requested,Requested"
|
|
bitfld.long 0x04 25. " TXR57 ,Transmission request flag 57" "Not requested,Requested"
|
|
bitfld.long 0x04 24. " TXR56 ,Transmission request flag 56" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 23. " TXR55 ,Transmission request flag 55" "Not requested,Requested"
|
|
bitfld.long 0x04 22. " TXR54 ,Transmission request flag 54" "Not requested,Requested"
|
|
bitfld.long 0x04 21. " TXR53 ,Transmission request flag 53" "Not requested,Requested"
|
|
bitfld.long 0x04 20. " TXR52 ,Transmission request flag 52" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 19. " TXR51 ,Transmission request flag 51" "Not requested,Requested"
|
|
bitfld.long 0x04 18. " TXR50 ,Transmission request flag 50" "Not requested,Requested"
|
|
bitfld.long 0x04 17. " TXR49 ,Transmission request flag 49" "Not requested,Requested"
|
|
bitfld.long 0x04 16. " TXR48 ,Transmission request flag 48" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 15. " TXR47 ,Transmission request flag 47" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " TXR46 ,Transmission request flag 46" "Not requested,Requested"
|
|
bitfld.long 0x04 13. " TXR45 ,Transmission request flag 45" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " TXR44 ,Transmission request flag 44" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 11. " TXR43 ,Transmission request flag 43" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " TXR42 ,Transmission request flag 42" "Not requested,Requested"
|
|
bitfld.long 0x04 9. " TXR41 ,Transmission request flag 41" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " TXR40 ,Transmission request flag 40" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 7. " TXR39 ,Transmission request flag 39" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " TXR38 ,Transmission request flag 38" "Not requested,Requested"
|
|
bitfld.long 0x04 5. " TXR37 ,Transmission request flag 37" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " TXR36 ,Transmission request flag 36" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TXR35 ,Transmission request flag 35" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " TXR34 ,Transmission request flag 34" "Not requested,Requested"
|
|
bitfld.long 0x04 1. " TXR33 ,Transmission request flag 33" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " TXR32 ,Transmission request flag 32" "Not requested,Requested"
|
|
line.long 0x08 "TXRQ3,Transmission Request Register 3"
|
|
bitfld.long 0x08 31. " TXR95 ,Transmission request flag 95" "Not requested,Requested"
|
|
bitfld.long 0x08 30. " TXR94 ,Transmission request flag 94" "Not requested,Requested"
|
|
bitfld.long 0x08 29. " TXR93 ,Transmission request flag 93" "Not requested,Requested"
|
|
bitfld.long 0x08 28. " TXR92 ,Transmission request flag 92" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 27. " TXR91 ,Transmission request flag 91" "Not requested,Requested"
|
|
bitfld.long 0x08 26. " TXR90 ,Transmission request flag 90" "Not requested,Requested"
|
|
bitfld.long 0x08 25. " TXR89 ,Transmission request flag 89" "Not requested,Requested"
|
|
bitfld.long 0x08 24. " TXR88 ,Transmission request flag 88" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 23. " TXR87 ,Transmission request flag 87" "Not requested,Requested"
|
|
bitfld.long 0x08 22. " TXR86 ,Transmission request flag 86" "Not requested,Requested"
|
|
bitfld.long 0x08 21. " TXR85 ,Transmission request flag 85" "Not requested,Requested"
|
|
bitfld.long 0x08 20. " TXR84 ,Transmission request flag 84" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 19. " TXR83 ,Transmission request flag 83" "Not requested,Requested"
|
|
bitfld.long 0x08 18. " TXR82 ,Transmission request flag 82" "Not requested,Requested"
|
|
bitfld.long 0x08 17. " TXR81 ,Transmission request flag 81" "Not requested,Requested"
|
|
bitfld.long 0x08 16. " TXR80 ,Transmission request flag 80" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 15. " TXR79 ,Transmission request flag 79" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " TXR78 ,Transmission request flag 78" "Not requested,Requested"
|
|
bitfld.long 0x08 13. " TXR77 ,Transmission request flag 77" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " TXR76 ,Transmission request flag 76" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 11. " TXR75 ,Transmission request flag 75" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " TXR74 ,Transmission request flag 74" "Not requested,Requested"
|
|
bitfld.long 0x08 9. " TXR73 ,Transmission request flag 73" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " TXR72 ,Transmission request flag 72" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 7. " TXR71 ,Transmission request flag 71" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " TXR70 ,Transmission request flag 70" "Not requested,Requested"
|
|
bitfld.long 0x08 5. " TXR69 ,Transmission request flag 69" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " TXR68 ,Transmission request flag 68" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 3. " TXR67 ,Transmission request flag 67" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " TXR66 ,Transmission request flag 66" "Not requested,Requested"
|
|
bitfld.long 0x08 1. " TXR65 ,Transmission request flag 65" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " TXR64 ,Transmission request flag 64" "Not requested,Requested"
|
|
line.long 0x0C "TXRQ4,Transmission Request Register 4"
|
|
bitfld.long 0x0C 31. " TXR127 ,Transmission request flag 127" "Not requested,Requested"
|
|
bitfld.long 0x0C 30. " TXR126 ,Transmission request flag 126" "Not requested,Requested"
|
|
bitfld.long 0x0C 29. " TXR125 ,Transmission request flag 125" "Not requested,Requested"
|
|
bitfld.long 0x0C 28. " TXR124 ,Transmission request flag 124" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " TXR123 ,Transmission request flag 123" "Not requested,Requested"
|
|
bitfld.long 0x0C 26. " TXR122 ,Transmission request flag 122" "Not requested,Requested"
|
|
bitfld.long 0x0C 25. " TXR121 ,Transmission request flag 121" "Not requested,Requested"
|
|
bitfld.long 0x0C 24. " TXR120 ,Transmission request flag 120" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " TXR119 ,Transmission request flag 119" "Not requested,Requested"
|
|
bitfld.long 0x0C 22. " TXR118 ,Transmission request flag 118" "Not requested,Requested"
|
|
bitfld.long 0x0C 21. " TXR117 ,Transmission request flag 117" "Not requested,Requested"
|
|
bitfld.long 0x0C 20. " TXR116 ,Transmission request flag 116" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " TXR115 ,Transmission request flag 115" "Not requested,Requested"
|
|
bitfld.long 0x0C 18. " TXR114 ,Transmission request flag 114" "Not requested,Requested"
|
|
bitfld.long 0x0C 17. " TXR113 ,Transmission request flag 113" "Not requested,Requested"
|
|
bitfld.long 0x0C 16. " TXR112 ,Transmission request flag 112" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " TXR111 ,Transmission request flag 111" "Not requested,Requested"
|
|
bitfld.long 0x0C 14. " TXR110 ,Transmission request flag 110" "Not requested,Requested"
|
|
bitfld.long 0x0C 13. " TXR109 ,Transmission request flag 109" "Not requested,Requested"
|
|
bitfld.long 0x0C 12. " TXR108 ,Transmission request flag 108" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " TXR107 ,Transmission request flag 107" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " TXR106 ,Transmission request flag 106" "Not requested,Requested"
|
|
bitfld.long 0x0C 9. " TXR105 ,Transmission request flag 105" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " TXR104 ,Transmission request flag 104" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " TXR103 ,Transmission request flag 103" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " TXR102 ,Transmission request flag 102" "Not requested,Requested"
|
|
bitfld.long 0x0C 5. " TXR101 ,Transmission request flag 101" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " TXR100 ,Transmission request flag 100" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " TXR99 ,Transmission request flag 99" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " TXR98 ,Transmission request flag 98" "Not requested,Requested"
|
|
bitfld.long 0x0C 1. " TXR97 ,Transmission request flag 97" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " TXR96 ,Transmission request flag 96" "Not requested,Requested"
|
|
line.long 0x10 "NDAT1,New Data Register 1"
|
|
bitfld.long 0x10 31. " ND31 ,New data flag 31" "Not updated,Updated"
|
|
bitfld.long 0x10 30. " ND30 ,New data flag 30" "Not updated,Updated"
|
|
bitfld.long 0x10 29. " ND29 ,New data flag 29" "Not updated,Updated"
|
|
bitfld.long 0x10 28. " ND28 ,New data flag 28" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x10 27. " ND27 ,New data flag 27" "Not updated,Updated"
|
|
bitfld.long 0x10 26. " ND26 ,New data flag 26" "Not updated,Updated"
|
|
bitfld.long 0x10 25. " ND25 ,New data flag 25" "Not updated,Updated"
|
|
bitfld.long 0x10 24. " ND24 ,New data flag 24" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x10 23. " ND23 ,New data flag 23" "Not updated,Updated"
|
|
bitfld.long 0x10 22. " ND22 ,New data flag 22" "Not updated,Updated"
|
|
bitfld.long 0x10 21. " ND21 ,New data flag 21" "Not updated,Updated"
|
|
bitfld.long 0x10 20. " ND20 ,New data flag 20" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ND19 ,New data flag 19" "Not updated,Updated"
|
|
bitfld.long 0x10 18. " ND18 ,New data flag 18" "Not updated,Updated"
|
|
bitfld.long 0x10 17. " ND17 ,New data flag 17" "Not updated,Updated"
|
|
bitfld.long 0x10 16. " ND16 ,New data flag 16" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x10 15. " ND15 ,New data flag 15" "Not updated,Updated"
|
|
bitfld.long 0x10 14. " ND14 ,New data flag 14" "Not updated,Updated"
|
|
bitfld.long 0x10 13. " ND13 ,New data flag 13" "Not updated,Updated"
|
|
bitfld.long 0x10 12. " ND12 ,New data flag 12" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x10 11. " ND11 ,New data flag 11" "Not updated,Updated"
|
|
bitfld.long 0x10 10. " ND10 ,New data flag 10" "Not updated,Updated"
|
|
bitfld.long 0x10 9. " ND9 ,New data flag 9" "Not updated,Updated"
|
|
bitfld.long 0x10 8. " ND8 ,New data flag 8" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ND7 ,New data flag 7" "Not updated,Updated"
|
|
bitfld.long 0x10 6. " ND6 ,New data flag 6" "Not updated,Updated"
|
|
bitfld.long 0x10 5. " ND5 ,New data flag 5" "Not updated,Updated"
|
|
bitfld.long 0x10 4. " ND4 ,New data flag 4" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x10 3. " ND3 ,New data flag 3" "Not updated,Updated"
|
|
bitfld.long 0x10 2. " ND2 ,New data flag 2" "Not updated,Updated"
|
|
bitfld.long 0x10 1. " ND1 ,New data flag 1" "Not updated,Updated"
|
|
bitfld.long 0x10 0. " ND0 ,New data flag 0" "Not updated,Updated"
|
|
line.long 0x14 "NDAT2,New Data Register 2"
|
|
bitfld.long 0x14 31. " ND63 ,New data flag 63" "Not updated,Updated"
|
|
bitfld.long 0x14 30. " ND62 ,New data flag 62" "Not updated,Updated"
|
|
bitfld.long 0x14 29. " ND61 ,New data flag 61" "Not updated,Updated"
|
|
bitfld.long 0x14 28. " ND60 ,New data flag 60" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x14 27. " ND59 ,New data flag 59" "Not updated,Updated"
|
|
bitfld.long 0x14 26. " ND58 ,New data flag 58" "Not updated,Updated"
|
|
bitfld.long 0x14 25. " ND57 ,New data flag 57" "Not updated,Updated"
|
|
bitfld.long 0x14 24. " ND56 ,New data flag 56" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x14 23. " ND55 ,New data flag 55" "Not updated,Updated"
|
|
bitfld.long 0x14 22. " ND54 ,New data flag 54" "Not updated,Updated"
|
|
bitfld.long 0x14 21. " ND53 ,New data flag 53" "Not updated,Updated"
|
|
bitfld.long 0x14 20. " ND52 ,New data flag 52" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ND51 ,New data flag 51" "Not updated,Updated"
|
|
bitfld.long 0x14 18. " ND50 ,New data flag 50" "Not updated,Updated"
|
|
bitfld.long 0x14 17. " ND49 ,New data flag 49" "Not updated,Updated"
|
|
bitfld.long 0x14 16. " ND48 ,New data flag 48" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x14 15. " ND47 ,New data flag 47" "Not updated,Updated"
|
|
bitfld.long 0x14 14. " ND46 ,New data flag 46" "Not updated,Updated"
|
|
bitfld.long 0x14 13. " ND45 ,New data flag 45" "Not updated,Updated"
|
|
bitfld.long 0x14 12. " ND44 ,New data flag 44" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x14 11. " ND43 ,New data flag 43" "Not updated,Updated"
|
|
bitfld.long 0x14 10. " ND42 ,New data flag 42" "Not updated,Updated"
|
|
bitfld.long 0x14 9. " ND41 ,New data flag 41" "Not updated,Updated"
|
|
bitfld.long 0x14 8. " ND40 ,New data flag 40" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ND39 ,New data flag 39" "Not updated,Updated"
|
|
bitfld.long 0x14 6. " ND38 ,New data flag 38" "Not updated,Updated"
|
|
bitfld.long 0x14 5. " ND37 ,New data flag 37" "Not updated,Updated"
|
|
bitfld.long 0x14 4. " ND36 ,New data flag 36" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x14 3. " ND35 ,New data flag 35" "Not updated,Updated"
|
|
bitfld.long 0x14 2. " ND34 ,New data flag 34" "Not updated,Updated"
|
|
bitfld.long 0x14 1. " ND33 ,New data flag 33" "Not updated,Updated"
|
|
bitfld.long 0x14 0. " ND32 ,New data flag 32" "Not updated,Updated"
|
|
line.long 0x18 "NDAT3,New Data Register 3"
|
|
bitfld.long 0x18 31. " ND95 ,New data flag 95" "Not updated,Updated"
|
|
bitfld.long 0x18 30. " ND94 ,New data flag 94" "Not updated,Updated"
|
|
bitfld.long 0x18 29. " ND93 ,New data flag 93" "Not updated,Updated"
|
|
bitfld.long 0x18 28. " ND92 ,New data flag 92" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x18 27. " ND91 ,New data flag 91" "Not updated,Updated"
|
|
bitfld.long 0x18 26. " ND90 ,New data flag 90" "Not updated,Updated"
|
|
bitfld.long 0x18 25. " ND89 ,New data flag 89" "Not updated,Updated"
|
|
bitfld.long 0x18 24. " ND88 ,New data flag 88" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x18 23. " ND87 ,New data flag 87" "Not updated,Updated"
|
|
bitfld.long 0x18 22. " ND86 ,New data flag 86" "Not updated,Updated"
|
|
bitfld.long 0x18 21. " ND85 ,New data flag 85" "Not updated,Updated"
|
|
bitfld.long 0x18 20. " ND84 ,New data flag 84" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ND83 ,New data flag 83" "Not updated,Updated"
|
|
bitfld.long 0x18 18. " ND82 ,New data flag 82" "Not updated,Updated"
|
|
bitfld.long 0x18 17. " ND81 ,New data flag 81" "Not updated,Updated"
|
|
bitfld.long 0x18 16. " ND80 ,New data flag 80" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x18 15. " ND79 ,New data flag 79" "Not updated,Updated"
|
|
bitfld.long 0x18 14. " ND78 ,New data flag 78" "Not updated,Updated"
|
|
bitfld.long 0x18 13. " ND77 ,New data flag 77" "Not updated,Updated"
|
|
bitfld.long 0x18 12. " ND76 ,New data flag 76" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x18 11. " ND75 ,New data flag 75" "Not updated,Updated"
|
|
bitfld.long 0x18 10. " ND74 ,New data flag 74" "Not updated,Updated"
|
|
bitfld.long 0x18 9. " ND73 ,New data flag 73" "Not updated,Updated"
|
|
bitfld.long 0x18 8. " ND72 ,New data flag 72" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ND71 ,New data flag 71" "Not updated,Updated"
|
|
bitfld.long 0x18 6. " ND70 ,New data flag 70" "Not updated,Updated"
|
|
bitfld.long 0x18 5. " ND69 ,New data flag 69" "Not updated,Updated"
|
|
bitfld.long 0x18 4. " ND68 ,New data flag 68" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x18 3. " ND67 ,New data flag 67" "Not updated,Updated"
|
|
bitfld.long 0x18 2. " ND66 ,New data flag 66" "Not updated,Updated"
|
|
bitfld.long 0x18 1. " ND65 ,New data flag 65" "Not updated,Updated"
|
|
bitfld.long 0x18 0. " ND64 ,New data flag 64" "Not updated,Updated"
|
|
line.long 0x1C "NDAT4,New Data Register 4"
|
|
bitfld.long 0x1C 31. " ND127 ,New data flag 127" "Not updated,Updated"
|
|
bitfld.long 0x1C 30. " ND126 ,New data flag 126" "Not updated,Updated"
|
|
bitfld.long 0x1C 29. " ND125 ,New data flag 125" "Not updated,Updated"
|
|
bitfld.long 0x1C 28. " ND124 ,New data flag 124" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " ND123 ,New data flag 123" "Not updated,Updated"
|
|
bitfld.long 0x1C 26. " ND122 ,New data flag 122" "Not updated,Updated"
|
|
bitfld.long 0x1C 25. " ND121 ,New data flag 121" "Not updated,Updated"
|
|
bitfld.long 0x1C 24. " ND120 ,New data flag 120" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " ND119 ,New data flag 119" "Not updated,Updated"
|
|
bitfld.long 0x1C 22. " ND118 ,New data flag 118" "Not updated,Updated"
|
|
bitfld.long 0x1C 21. " ND117 ,New data flag 117" "Not updated,Updated"
|
|
bitfld.long 0x1C 20. " ND116 ,New data flag 116" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " ND115 ,New data flag 115" "Not updated,Updated"
|
|
bitfld.long 0x1C 18. " ND114 ,New data flag 114" "Not updated,Updated"
|
|
bitfld.long 0x1C 17. " ND113 ,New data flag 113" "Not updated,Updated"
|
|
bitfld.long 0x1C 16. " ND112 ,New data flag 112" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " ND111 ,New data flag 111" "Not updated,Updated"
|
|
bitfld.long 0x1C 14. " ND110 ,New data flag 110" "Not updated,Updated"
|
|
bitfld.long 0x1C 13. " ND109 ,New data flag 109" "Not updated,Updated"
|
|
bitfld.long 0x1C 12. " ND108 ,New data flag 108" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " ND107 ,New data flag 107" "Not updated,Updated"
|
|
bitfld.long 0x1C 10. " ND106 ,New data flag 106" "Not updated,Updated"
|
|
bitfld.long 0x1C 9. " ND105 ,New data flag 105" "Not updated,Updated"
|
|
bitfld.long 0x1C 8. " ND104 ,New data flag 104" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " ND103 ,New data flag 103" "Not updated,Updated"
|
|
bitfld.long 0x1C 6. " ND102 ,New data flag 102" "Not updated,Updated"
|
|
bitfld.long 0x1C 5. " ND101 ,New data flag 101" "Not updated,Updated"
|
|
bitfld.long 0x1C 4. " ND100 ,New data flag 100" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " ND99 ,New data flag 99" "Not updated,Updated"
|
|
bitfld.long 0x1C 2. " ND98 ,New data flag 98" "Not updated,Updated"
|
|
bitfld.long 0x1C 1. " ND97 ,New data flag 97" "Not updated,Updated"
|
|
bitfld.long 0x1C 0. " ND96 ,New data flag 96" "Not updated,Updated"
|
|
line.long 0x20 "MBSC1,Message Buffer Status Changed Register 1"
|
|
bitfld.long 0x20 31. " MBC31 ,Message buffer 31 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 30. " MBC30 ,Message buffer 30 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 29. " MBC29 ,Message buffer 29 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 28. " MBC28 ,Message buffer 28 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x20 27. " MBC27 ,Message buffer 27 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 26. " MBC26 ,Message buffer 26 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 25. " MBC25 ,Message buffer 25 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 24. " MBC24 ,Message buffer 24 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x20 23. " MBC23 ,Message buffer 23 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 22. " MBC22 ,Message buffer 22 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 21. " MBC21 ,Message buffer 21 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 20. " MBC20 ,Message buffer 20 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x20 19. " MBC19 ,Message buffer 19 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 18. " MBC18 ,Message buffer 18 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 17. " MBC17 ,Message buffer 17 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 16. " MBC16 ,Message buffer 16 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x20 15. " MBC15 ,Message buffer 15 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 14. " MBC14 ,Message buffer 14 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 13. " MBC13 ,Message buffer 13 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 12. " MBC12 ,Message buffer 12 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x20 11. " MBC11 ,Message buffer 11 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 10. " MBC10 ,Message buffer 10 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 9. " MBC9 ,Message buffer 9 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 8. " MBC8 ,Message buffer 8 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x20 7. " MBC7 ,Message buffer 7 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 6. " MBC6 ,Message buffer 6 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 5. " MBC5 ,Message buffer 5 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 4. " MBC4 ,Message buffer 4 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x20 3. " MBC3 ,Message buffer 3 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 2. " MBC2 ,Message buffer 2 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 1. " MBC1 ,Message buffer 1 status changed" "Not changed,Changed"
|
|
bitfld.long 0x20 0. " MBC0 ,Message buffer 0 status changed" "Not changed,Changed"
|
|
line.long 0x24 "MBSC2,Message Buffer Status Changed Register 2"
|
|
bitfld.long 0x24 31. " MBC63 ,Message buffer 63 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 30. " MBC62 ,Message buffer 62 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 29. " MBC61 ,Message buffer 61 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 28. " MBC60 ,Message buffer 60 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x24 27. " MBC59 ,Message buffer 59 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 26. " MBC58 ,Message buffer 58 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 25. " MBC57 ,Message buffer 57 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 24. " MBC56 ,Message buffer 56 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x24 23. " MBC55 ,Message buffer 55 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 22. " MBC54 ,Message buffer 54 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 21. " MBC53 ,Message buffer 53 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 20. " MBC52 ,Message buffer 52 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x24 19. " MBC51 ,Message buffer 51 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 18. " MBC50 ,Message buffer 50 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 17. " MBC49 ,Message buffer 49 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 16. " MBC48 ,Message buffer 48 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x24 15. " MBC47 ,Message buffer 47 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 14. " MBC46 ,Message buffer 46 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 13. " MBC45 ,Message buffer 45 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 12. " MBC44 ,Message buffer 44 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x24 11. " MBC43 ,Message buffer 43 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 10. " MBC42 ,Message buffer 42 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 9. " MBC41 ,Message buffer 41 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 8. " MBC40 ,Message buffer 40 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x24 7. " MBC39 ,Message buffer 39 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 6. " MBC38 ,Message buffer 38 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 5. " MBC37 ,Message buffer 37 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 4. " MBC36 ,Message buffer 36 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x24 3. " MBC35 ,Message buffer 35 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 2. " MBC34 ,Message buffer 34 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 1. " MBC33 ,Message buffer 33 status changed" "Not changed,Changed"
|
|
bitfld.long 0x24 0. " MBC32 ,Message buffer 32 status changed" "Not changed,Changed"
|
|
line.long 0x28 "MBSC3,Message Buffer Status Changed Register 3"
|
|
bitfld.long 0x28 31. " MBC95 ,Message buffer 95 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 30. " MBC94 ,Message buffer 94 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 29. " MBC93 ,Message buffer 93 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 28. " MBC92 ,Message buffer 92 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x28 27. " MBC91 ,Message buffer 91 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 26. " MBC90 ,Message buffer 90 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 25. " MBC89 ,Message buffer 89 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 24. " MBC88 ,Message buffer 88 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x28 23. " MBC87 ,Message buffer 87 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 22. " MBC86 ,Message buffer 86 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 21. " MBC85 ,Message buffer 85 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 20. " MBC84 ,Message buffer 84 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x28 19. " MBC83 ,Message buffer 83 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 18. " MBC82 ,Message buffer 82 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 17. " MBC81 ,Message buffer 81 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 16. " MBC80 ,Message buffer 80 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x28 15. " MBC79 ,Message buffer 79 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 14. " MBC78 ,Message buffer 78 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 13. " MBC77 ,Message buffer 77 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 12. " MBC76 ,Message buffer 76 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x28 11. " MBC75 ,Message buffer 75 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 10. " MBC74 ,Message buffer 74 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 9. " MBC73 ,Message buffer 73 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 8. " MBC72 ,Message buffer 72 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x28 7. " MBC71 ,Message buffer 71 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 6. " MBC70 ,Message buffer 70 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 5. " MBC69 ,Message buffer 69 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 4. " MBC68 ,Message buffer 68 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x28 3. " MBC67 ,Message buffer 67 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 2. " MBC66 ,Message buffer 66 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 1. " MBC65 ,Message buffer 65 status changed" "Not changed,Changed"
|
|
bitfld.long 0x28 0. " MBC64 ,Message buffer 64 status changed" "Not changed,Changed"
|
|
line.long 0x2C "MBSC4,Message Buffer Status Changed Register 4"
|
|
bitfld.long 0x2C 31. " MBC127 ,Message buffer 127 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 30. " MBC126 ,Message buffer 126 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 29. " MBC125 ,Message buffer 125 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 28. " MBC124 ,Message buffer 124 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x2C 27. " MBC123 ,Message buffer 123 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 26. " MBC122 ,Message buffer 122 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 25. " MBC121 ,Message buffer 121 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 24. " MBC120 ,Message buffer 120 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x2C 23. " MBC119 ,Message buffer 119 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 22. " MBC118 ,Message buffer 118 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 21. " MBC117 ,Message buffer 117 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 20. " MBC116 ,Message buffer 116 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x2C 19. " MBC115 ,Message buffer 115 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 18. " MBC114 ,Message buffer 114 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 17. " MBC113 ,Message buffer 113 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 16. " MBC112 ,Message buffer 112 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x2C 15. " MBC111 ,Message buffer 111 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 14. " MBC110 ,Message buffer 110 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 13. " MBC109 ,Message buffer 109 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 12. " MBC108 ,Message buffer 108 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x2C 11. " MBC107 ,Message buffer 107 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 10. " MBC106 ,Message buffer 106 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 9. " MBC105 ,Message buffer 105 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 8. " MBC104 ,Message buffer 104 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x2C 7. " MBC103 ,Message buffer 103 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 6. " MBC102 ,Message buffer 102 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 5. " MBC101 ,Message buffer 101 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 4. " MBC100 ,Message buffer 100 status changed" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " MBC99 ,Message buffer 99 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 2. " MBC98 ,Message buffer 98 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 1. " MBC97 ,Message buffer 97 status changed" "Not changed,Changed"
|
|
bitfld.long 0x2C 0. " MBC96 ,Message buffer 96 status changed" "Not changed,Changed"
|
|
tree.end
|
|
tree "Identification Registers"
|
|
rgroup.long 0x3F0++0x07
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 20.--27. 1. " STEP ,Release step"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MON ,Month"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DAY ,Date"
|
|
line.long 0x04 "ENDN,Endian Register"
|
|
tree.end
|
|
tree "Input Buffer"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "WRDS1,Write Data Section Register 1"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "WRDS2,Write Data Section Register 2"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "WRDS3,Write Data Section Register 3"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "WRDS4,Write Data Section Register 4"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "WRDS5,Write Data Section Register 5"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "WRDS6,Write Data Section Register 6"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "WRDS7,Write Data Section Register 7"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "WRDS8,Write Data Section Register 8"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "WRDS9,Write Data Section Register 9"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "WRDS10,Write Data Section Register 10"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "WRDS11,Write Data Section Register 11"
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "WRDS12,Write Data Section Register 12"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "WRDS13,Write Data Section Register 13"
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "WRDS14,Write Data Section Register 14"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "WRDS15,Write Data Section Register 15"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "WRDS16,Write Data Section Register 16"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "WRDS17,Write Data Section Register 17"
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "WRDS18,Write Data Section Register 18"
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "WRDS19,Write Data Section Register 19"
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "WRDS20,Write Data Section Register 20"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "WRDS21,Write Data Section Register 21"
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "WRDS22,Write Data Section Register 22"
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "WRDS23,Write Data Section Register 23"
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "WRDS24,Write Data Section Register 24"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "WRDS25,Write Data Section Register 25"
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "WRDS26,Write Data Section Register 26"
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "WRDS27,Write Data Section Register 27"
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "WRDS28,Write Data Section Register 28"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "WRDS29,Write Data Section Register 29"
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "WRDS30,Write Data Section Register 30"
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "WRDS31,Write Data Section Register 31"
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "WRDS32,Write Data Section Register 32"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "WRDS33,Write Data Section Register 33"
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "WRDS34,Write Data Section Register 34"
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "WRDS35,Write Data Section Register 35"
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "WRDS36,Write Data Section Register 36"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "WRDS37,Write Data Section Register 37"
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "WRDS38,Write Data Section Register 38"
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "WRDS39,Write Data Section Register 39"
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "WRDS40,Write Data Section Register 40"
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "WRDS41,Write Data Section Register 41"
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "WRDS42,Write Data Section Register 42"
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "WRDS43,Write Data Section Register 43"
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "WRDS44,Write Data Section Register 44"
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "WRDS45,Write Data Section Register 45"
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "WRDS46,Write Data Section Register 46"
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "WRDS47,Write Data Section Register 47"
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "WRDS48,Write Data Section Register 48"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "WRDS49,Write Data Section Register 49"
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "WRDS50,Write Data Section Register 50"
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "WRDS51,Write Data Section Register 51"
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "WRDS52,Write Data Section Register 52"
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "WRDS53,Write Data Section Register 53"
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "WRDS54,Write Data Section Register 54"
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "WRDS55,Write Data Section Register 55"
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "WRDS56,Write Data Section Register 56"
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "WRDS57,Write Data Section Register 57"
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "WRDS58,Write Data Section Register 58"
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "WRDS59,Write Data Section Register 59"
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "WRDS60,Write Data Section Register 60"
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "WRDS61,Write Data Section Register 61"
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "WRDS62,Write Data Section Register 62"
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "WRDS63,Write Data Section Register 63"
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "WRDS64,Write Data Section Register 64"
|
|
group.long 0x500++0x0B
|
|
line.long 0x00 "WRHS1,Write Header Section Register 1"
|
|
bitfld.long 0x00 29. " MBI ,Message buffer interrupt" "Invalid,Valid"
|
|
bitfld.long 0x00 28. " TXM ,Transmission mode" "Continuous,Single-shot"
|
|
bitfld.long 0x00 27. " PPIT ,Payload preamble indicator transmission" "Not set,Set"
|
|
bitfld.long 0x00 26. " CFG ,Message buffer configuration" "Reception,Transmission"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " CHA_CHB ,Channel filter control bits" "No transmission,B,A,Both"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CYC ,Cycle code"
|
|
hexmask.long.word 0x00 0.--10. 1. " FID ,Frame ID"
|
|
line.long 0x04 "WRHS2,Write Header Section Register 2"
|
|
hexmask.long.byte 0x04 16.--22. 1. " PLC ,Configured payload length"
|
|
hexmask.long.word 0x04 0.--10. 1. " CRC ,Header CRC (vRF!Header!HeaderCRC)"
|
|
line.long 0x08 "WRHS3,Write Header Section Register 3"
|
|
hexmask.long.word 0x08 0.--10. 0x01 " DP ,Data pointer"
|
|
group.long 0x510++0x07
|
|
line.long 0x00 "IBCM,Input Buffer Command Mask Register"
|
|
bitfld.long 0x00 18. " STXRS ,Transmission request flag shadow setting" "Reset,Set"
|
|
bitfld.long 0x00 17. " LDSS ,Data section shadow load" "Not transferred,Transferred"
|
|
bitfld.long 0x00 16. " LHSS ,Header section shadow load" "Not transferred,Transferred"
|
|
bitfld.long 0x00 2. " STXRH ,Transmission request flag host setting" "Reset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LDSH ,Data section host load" "Not transferred,Transferred"
|
|
bitfld.long 0x00 0. " LHSH ,Header section host load" "Not transferred,Transferred"
|
|
line.long 0x04 "IBCR,Input Buffer Command Request Register"
|
|
bitfld.long 0x04 31. " IBSYS ,Input buffer shadow busy" "Not busy,Busy"
|
|
hexmask.long.byte 0x04 16.--22. 1. " IBRS ,Input buffer shadow transfer request"
|
|
bitfld.long 0x04 15. " IBSYH ,Input buffer host busy bit" "Not busy,Busy"
|
|
hexmask.long.byte 0x04 0.--6. 1. " IBRH ,Input buffer host transfer request"
|
|
tree.end
|
|
tree "Output Buffer"
|
|
rgroup.long 0x600++0x03
|
|
line.long 0x00 "RDDS1,Read Data Section Register 1"
|
|
rgroup.long 0x604++0x03
|
|
line.long 0x00 "RDDS2,Read Data Section Register 2"
|
|
rgroup.long 0x608++0x03
|
|
line.long 0x00 "RDDS3,Read Data Section Register 3"
|
|
rgroup.long 0x60C++0x03
|
|
line.long 0x00 "RDDS4,Read Data Section Register 4"
|
|
rgroup.long 0x610++0x03
|
|
line.long 0x00 "RDDS5,Read Data Section Register 5"
|
|
rgroup.long 0x614++0x03
|
|
line.long 0x00 "RDDS6,Read Data Section Register 6"
|
|
rgroup.long 0x618++0x03
|
|
line.long 0x00 "RDDS7,Read Data Section Register 7"
|
|
rgroup.long 0x61C++0x03
|
|
line.long 0x00 "RDDS8,Read Data Section Register 8"
|
|
rgroup.long 0x620++0x03
|
|
line.long 0x00 "RDDS9,Read Data Section Register 9"
|
|
rgroup.long 0x624++0x03
|
|
line.long 0x00 "RDDS10,Read Data Section Register 10"
|
|
rgroup.long 0x628++0x03
|
|
line.long 0x00 "RDDS11,Read Data Section Register 11"
|
|
rgroup.long 0x62C++0x03
|
|
line.long 0x00 "RDDS12,Read Data Section Register 12"
|
|
rgroup.long 0x630++0x03
|
|
line.long 0x00 "RDDS13,Read Data Section Register 13"
|
|
rgroup.long 0x634++0x03
|
|
line.long 0x00 "RDDS14,Read Data Section Register 14"
|
|
rgroup.long 0x638++0x03
|
|
line.long 0x00 "RDDS15,Read Data Section Register 15"
|
|
rgroup.long 0x63C++0x03
|
|
line.long 0x00 "RDDS16,Read Data Section Register 16"
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "RDDS17,Read Data Section Register 17"
|
|
rgroup.long 0x644++0x03
|
|
line.long 0x00 "RDDS18,Read Data Section Register 18"
|
|
rgroup.long 0x648++0x03
|
|
line.long 0x00 "RDDS19,Read Data Section Register 19"
|
|
rgroup.long 0x64C++0x03
|
|
line.long 0x00 "RDDS20,Read Data Section Register 20"
|
|
rgroup.long 0x650++0x03
|
|
line.long 0x00 "RDDS21,Read Data Section Register 21"
|
|
rgroup.long 0x654++0x03
|
|
line.long 0x00 "RDDS22,Read Data Section Register 22"
|
|
rgroup.long 0x658++0x03
|
|
line.long 0x00 "RDDS23,Read Data Section Register 23"
|
|
rgroup.long 0x65C++0x03
|
|
line.long 0x00 "RDDS24,Read Data Section Register 24"
|
|
rgroup.long 0x660++0x03
|
|
line.long 0x00 "RDDS25,Read Data Section Register 25"
|
|
rgroup.long 0x664++0x03
|
|
line.long 0x00 "RDDS26,Read Data Section Register 26"
|
|
rgroup.long 0x668++0x03
|
|
line.long 0x00 "RDDS27,Read Data Section Register 27"
|
|
rgroup.long 0x66C++0x03
|
|
line.long 0x00 "RDDS28,Read Data Section Register 28"
|
|
rgroup.long 0x670++0x03
|
|
line.long 0x00 "RDDS29,Read Data Section Register 29"
|
|
rgroup.long 0x674++0x03
|
|
line.long 0x00 "RDDS30,Read Data Section Register 30"
|
|
rgroup.long 0x678++0x03
|
|
line.long 0x00 "RDDS31,Read Data Section Register 31"
|
|
rgroup.long 0x67C++0x03
|
|
line.long 0x00 "RDDS32,Read Data Section Register 32"
|
|
rgroup.long 0x680++0x03
|
|
line.long 0x00 "RDDS33,Read Data Section Register 33"
|
|
rgroup.long 0x684++0x03
|
|
line.long 0x00 "RDDS34,Read Data Section Register 34"
|
|
rgroup.long 0x688++0x03
|
|
line.long 0x00 "RDDS35,Read Data Section Register 35"
|
|
rgroup.long 0x68C++0x03
|
|
line.long 0x00 "RDDS36,Read Data Section Register 36"
|
|
rgroup.long 0x690++0x03
|
|
line.long 0x00 "RDDS37,Read Data Section Register 37"
|
|
rgroup.long 0x694++0x03
|
|
line.long 0x00 "RDDS38,Read Data Section Register 38"
|
|
rgroup.long 0x698++0x03
|
|
line.long 0x00 "RDDS39,Read Data Section Register 39"
|
|
rgroup.long 0x69C++0x03
|
|
line.long 0x00 "RDDS40,Read Data Section Register 40"
|
|
rgroup.long 0x6A0++0x03
|
|
line.long 0x00 "RDDS41,Read Data Section Register 41"
|
|
rgroup.long 0x6A4++0x03
|
|
line.long 0x00 "RDDS42,Read Data Section Register 42"
|
|
rgroup.long 0x6A8++0x03
|
|
line.long 0x00 "RDDS43,Read Data Section Register 43"
|
|
rgroup.long 0x6AC++0x03
|
|
line.long 0x00 "RDDS44,Read Data Section Register 44"
|
|
rgroup.long 0x6B0++0x03
|
|
line.long 0x00 "RDDS45,Read Data Section Register 45"
|
|
rgroup.long 0x6B4++0x03
|
|
line.long 0x00 "RDDS46,Read Data Section Register 46"
|
|
rgroup.long 0x6B8++0x03
|
|
line.long 0x00 "RDDS47,Read Data Section Register 47"
|
|
rgroup.long 0x6BC++0x03
|
|
line.long 0x00 "RDDS48,Read Data Section Register 48"
|
|
rgroup.long 0x6C0++0x03
|
|
line.long 0x00 "RDDS49,Read Data Section Register 49"
|
|
rgroup.long 0x6C4++0x03
|
|
line.long 0x00 "RDDS50,Read Data Section Register 50"
|
|
rgroup.long 0x6C8++0x03
|
|
line.long 0x00 "RDDS51,Read Data Section Register 51"
|
|
rgroup.long 0x6CC++0x03
|
|
line.long 0x00 "RDDS52,Read Data Section Register 52"
|
|
rgroup.long 0x6D0++0x03
|
|
line.long 0x00 "RDDS53,Read Data Section Register 53"
|
|
rgroup.long 0x6D4++0x03
|
|
line.long 0x00 "RDDS54,Read Data Section Register 54"
|
|
rgroup.long 0x6D8++0x03
|
|
line.long 0x00 "RDDS55,Read Data Section Register 55"
|
|
rgroup.long 0x6DC++0x03
|
|
line.long 0x00 "RDDS56,Read Data Section Register 56"
|
|
rgroup.long 0x6E0++0x03
|
|
line.long 0x00 "RDDS57,Read Data Section Register 57"
|
|
rgroup.long 0x6E4++0x03
|
|
line.long 0x00 "RDDS58,Read Data Section Register 58"
|
|
rgroup.long 0x6E8++0x03
|
|
line.long 0x00 "RDDS59,Read Data Section Register 59"
|
|
rgroup.long 0x6EC++0x03
|
|
line.long 0x00 "RDDS60,Read Data Section Register 60"
|
|
rgroup.long 0x6F0++0x03
|
|
line.long 0x00 "RDDS61,Read Data Section Register 61"
|
|
rgroup.long 0x6F4++0x03
|
|
line.long 0x00 "RDDS62,Read Data Section Register 62"
|
|
rgroup.long 0x6F8++0x03
|
|
line.long 0x00 "RDDS63,Read Data Section Register 63"
|
|
rgroup.long 0x6FC++0x03
|
|
line.long 0x00 "RDDS64,Read Data Section Register 64"
|
|
rgroup.long 0x700++0x0F
|
|
line.long 0x00 "RDHS1,Read Header Section Register 1"
|
|
bitfld.long 0x00 29. " MBI ,Message buffer interrupt" "Invalid,Valid"
|
|
bitfld.long 0x00 28. " TXM ,Transmission mode" "Continuous,Single-shot"
|
|
bitfld.long 0x00 27. " PPIT ,Payload preamble indicator transmit" "Not set,Set"
|
|
bitfld.long 0x00 26. " CFG ,Message buffer configuration" "Reception,Transmission"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " CHA_CHB ,Channel filter control" "No transmission,B,A,Both"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CYC ,Cycle code"
|
|
hexmask.long.word 0x00 0.--10. 1. " FID ,Frame ID"
|
|
line.long 0x04 "RDHS2,Read Header Section Register 2"
|
|
hexmask.long.byte 0x04 24.--30. 1. " PLR ,Reception payload length (vRF!Header!Length)"
|
|
hexmask.long.byte 0x04 16.--22. 1. " PLC ,Configured payload length"
|
|
hexmask.long.word 0x04 0.--10. 1. " CRC ,Header CRC (vRF!Header!HeaderCRC)"
|
|
line.long 0x08 "RDHS3,Read Header Section Register 3"
|
|
bitfld.long 0x08 29. " RES ,Received reserved bit status (vRF!Header!Reserved)" "0,1"
|
|
bitfld.long 0x08 28. " PPI ,Payload preamble indicator (vRF!Header!PPIndicator)" "Not included,Included"
|
|
bitfld.long 0x08 27. " NFI ,Null frame indicator (vRF!Header!NFIndicator)" "Null,Not null"
|
|
bitfld.long 0x08 26. " SYN ,Sync frame indicator (vRF!Header!SyFIndicator)" "Not sync,Sync"
|
|
textline " "
|
|
bitfld.long 0x08 25. " SFI ,Startup frame indicator (vRF!Header!SuFIndicator)" "Not startup,Startup"
|
|
bitfld.long 0x08 24. " RCI ,Reception channel indicator (vSS!Channel)" "Channel B,Channel A"
|
|
hexmask.long.byte 0x08 16.--22. 1. " RCC ,Reception cycle counter (vRF!Header!CycleCount)"
|
|
hexmask.long.word 0x08 0.--10. 0x01 " DP ,Data pointer"
|
|
line.long 0x0C "MBS,Message Buffer Status Register"
|
|
bitfld.long 0x0C 29. " RESS ,Reserved bit status bit (vRF!Header!Reserved)" "0,1"
|
|
bitfld.long 0x0C 28. " PPIS ,Payload preamble indicator status (vRF!Header!PPIndicator)" "Not included,Included"
|
|
bitfld.long 0x0C 27. " NFIS ,Null frame indicator status (vRF!Header!NFIndicator)" "Null,Not null"
|
|
bitfld.long 0x0C 26. " SYNS ,Sync frame indicator status (vRF!Header!SyFIndicator)" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " SFIS ,Startup frame indicator status(vRF!Header!SuFIndicator)" "Not received,Received"
|
|
bitfld.long 0x0C 24. " RCIS ,Channel indicator status reception (vSS!Channel)" "Channel B,Channel A"
|
|
hexmask.long.byte 0x0C 16.--21. 1. " CCS ,Cycle count status"
|
|
bitfld.long 0x0C 15. " FTB ,Channel B frame transmission" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " FTB ,Channel B frame transmission" "Not transmitted,Transmitted"
|
|
bitfld.long 0x0C 12. " MLST ,Message lost" "Not lost,Lost"
|
|
bitfld.long 0x0C 11. " ESB ,Channel B empty slot " "Not idle,Idle"
|
|
bitfld.long 0x0C 10. " ESA ,Channel A empty slot " "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " TCIB ,Channel B transmission collision indicator (vSS!TxConflictB)" "Not detected,Detected"
|
|
bitfld.long 0x0C 8. " TCIA ,Channel A transmission collision indicator (vSS!TxConflictA)" "Not detected,Detected"
|
|
bitfld.long 0x0C 7. " SVOB ,Channel B boundary violation (vSS!BViolationB)" "Not detected,Detected"
|
|
bitfld.long 0x0C 6. " SVOA ,Channel A boundary violation (vSS!BViolationA)" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " CEOB ,Channel B content error (vSS!ContentErrorB)" "Not detected,Detected"
|
|
bitfld.long 0x0C 4. " CEOA ,Channel A content error (vSS!ContentErrorA)" "Not detected,Detected"
|
|
bitfld.long 0x0C 3. " SEOB ,Channel B syntax error (vSS!SyntaxErrorB)" "Not detected,Detected"
|
|
bitfld.long 0x0C 2. " SEOA ,Channel A syntax error (vSS!SyntaxErrorA)" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " VFRB ,Channel B reception valid frame (vSS!ValidFrameB)" "Not received,Received"
|
|
bitfld.long 0x0C 0. " VFRA ,Channel A reception valid frame (vSS!ValidFrameA)" "Not received,Received"
|
|
group.long 0x710++0x07
|
|
line.long 0x00 "OBCM,Output Buffer Command Mask Register"
|
|
rbitfld.long 0x00 17. " RDSH ,Read data section host bit" "Not read,Transferred"
|
|
rbitfld.long 0x00 16. " RHSH ,Read header section host bit" "Not read,Transferred"
|
|
bitfld.long 0x00 1. " RDSS ,Read data section shadow bit" "Not read,Transferred"
|
|
bitfld.long 0x00 0. " RHSS ,Read header section shadow bit" "Not read,Transferred"
|
|
line.long 0x04 "OBCR,Output Buffer Command Request Register"
|
|
hexmask.long.byte 0x04 16.--22. 1. " OBRH ,Output buffer host transfer request bits"
|
|
bitfld.long 0x04 15. " OBSYS ,Output buffer shadow busy" "Not busy,Busy"
|
|
bitfld.long 0x04 9. " REQ ,Request message RAM transfer" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " VIEW ,Shadow buffer and host buffer swap bit" "Not swapped,Swapped"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " OBRS ,Output buffer shadow transfer request bits"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "UDC (Up/Down Counter)"
|
|
tree "Channel 0"
|
|
base ad:0xB2000500
|
|
width 11.
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "UDCR,Up/Down Count Register"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "RCR,Reload Compare Register"
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UDCRL,Up/Down Count Register, Lower"
|
|
wgroup.byte 0x00++0x00
|
|
line.byte 0x00 "RCRL,Reload Compare Register, Lower"
|
|
endif
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "CSRL,Counter Status Register"
|
|
bitfld.byte 0x00 7. " CSTR ,Count start bit" "Stopped,Started"
|
|
bitfld.byte 0x00 6. " CITE ,Compare detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " UDIE ,Overflow/Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CMPF ,Compare detection interrupt flag" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " OVFF ,Overflow detection interrupt flag" "No overflow,Overflow"
|
|
bitfld.byte 0x00 2. " UDFF ,Underflow detection interrupt flag" "No underflow,Underflow"
|
|
rbitfld.byte 0x00 0.--1. " UDF ,Up/down flag" "No input,Down count,Up count,Up and down"
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "CCRH,Count Control Register, Upper"
|
|
bitfld.byte 0x00 7. " M16E ,16-bit mode enable" "8-bit,16-bit"
|
|
bitfld.byte 0x00 6. " CDCF ,Count direction change detection flag" "Not changed,Changed"
|
|
bitfld.byte 0x00 5. " CFIE ,Count direction change interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CLKS ,Internal prescaler selection" "2 clock cycles,8 clock cycles"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " CMS ,Count mode selection" "Down count,Up/down count,Multiply-by-2,Multiply-by-4"
|
|
bitfld.byte 0x00 0.--1. " CES ,Count clock edge selection" "Disabled,Falling,Rising,Both"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "CCRL,Count Control Register, Lower"
|
|
bitfld.byte 0x00 6. " CTUT ,Counter write bit" "0,1"
|
|
bitfld.byte 0x00 5. " UCRE ,Compare clear enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RLDE ,Reload enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " UDCC ,Counter clear" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " CGSC ,Counter clear/gate function selection bit" "Counter clear,Gate"
|
|
bitfld.byte 0x00 0.--1. " CGE ,CGSC operation selection (edge/level)" "Disabled,Falling/L,Rising/H,?..."
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "CMPR0,Counter Compare Register 0"
|
|
else
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "CMPRL0,Counter Compare Register 0, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "CMPR1,Counter Compare Register 1"
|
|
else
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "CMPRL1,Counter Compare Register 1, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "CMPR2,Counter Compare Register 2"
|
|
else
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "CMPRL2,Counter Compare Register 2, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "CMPR3,Counter Compare Register 3"
|
|
else
|
|
rgroup.byte 0x1C++0x00
|
|
line.byte 0x00 "CMPRL3,Counter Compare Register 3, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "CMPR4,Counter Compare Register 4"
|
|
else
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "CMPRL4,Counter Compare Register 4, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "CMPR5,Counter Compare Register 5"
|
|
else
|
|
rgroup.byte 0x24++0x00
|
|
line.byte 0x00 "CMPRL5,Counter Compare Register 5, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "CMPBRL0,Counter Compare Buffer Transfer Register 0"
|
|
else
|
|
group.byte 0x28++0x01
|
|
line.byte 0x00 "CMPBRL0,Counter Compare Buffer Transfer Register 0, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "CMPBRL1,Counter Compare Buffer Transfer Register 1"
|
|
else
|
|
group.byte 0x2C++0x01
|
|
line.byte 0x00 "CMPBRL1,Counter Compare Buffer Transfer Register 1, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "CMPBRL2,Counter Compare Buffer Transfer Register 2"
|
|
else
|
|
group.byte 0x30++0x01
|
|
line.byte 0x00 "CMPBRL2,Counter Compare Buffer Transfer Register 2, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CMPBRL3,Counter Compare Buffer Transfer Register 3"
|
|
else
|
|
group.byte 0x34++0x01
|
|
line.byte 0x00 "CMPBRL3,Counter Compare Buffer Transfer Register 3, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "CMPBRL4,Counter Compare Buffer Transfer Register 4"
|
|
else
|
|
group.byte 0x38++0x01
|
|
line.byte 0x00 "CMPBRL4,Counter Compare Buffer Transfer Register 4, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "CMPBRL5,Counter Compare Buffer Transfer Register 5"
|
|
else
|
|
group.byte 0x3C++0x01
|
|
line.byte 0x00 "CMPBRL5,Counter Compare Buffer Transfer Register 5, Lower"
|
|
endif
|
|
textline " "
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "CMPMSKR0,Counter Compare Mask Register 0"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "CMPMSKRL0,Counter Compare Mask Register 0, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "CMPMSKR1,Counter Compare Mask Register 1"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "CMPMSKRL1,Counter Compare Mask Register 1, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "CMPMSKR2,Counter Compare Mask Register 2"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "CMPMSKRL2,Counter Compare Mask Register 2, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "CMPMSKR3,Counter Compare Mask Register 3"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "CMPMSKRL3,Counter Compare Mask Register 3, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "CMPMSKR4,Counter Compare Mask Register 4"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "CMPMSKRL4,Counter Compare Mask Register 4, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB2000500+0x09))&0x80)==0x80)
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "CMPMSKR5,Counter Compare Mask Register 5"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "CMPMSKRL5,Counter Compare Mask Register 5, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
group.byte 0x58++0x01
|
|
line.byte 0x00 "CMPFR,Comparison Result Match Detection Flag Register"
|
|
bitfld.byte 0x00 5. " CMPF5 ,Comparison result match 5 detection flag 5" "Not matched,Matched"
|
|
bitfld.byte 0x00 4. " CMPF4 ,Comparison result match detection flag 4" "Not matched,Matched"
|
|
bitfld.byte 0x00 3. " CMPF3 ,Comparison result match detection flag 3" "Not matched,Matched"
|
|
bitfld.byte 0x00 2. " CMPF2 ,Comparison result match detection flag 2" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CMPF1 ,Comparison result match detection flag 1" "Not matched,Matched"
|
|
bitfld.byte 0x00 0. " CMPF0 ,Comparison result match detection flag 0" "Not matched,Matched"
|
|
line.byte 0x01 "CITER,Comparison Result Match Interrupt Enable Flag Register"
|
|
bitfld.byte 0x01 5. " CITE5 ,Comparison result match interrupt 5 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " CITE4 ,Comparison result match interrupt 4 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " CITE3 ,Comparison result match interrupt 3 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " CITE2 ,Comparison result match interrupt 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " CITE1 ,Comparison result match interrupt 1 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " CITE0 ,Comparison result match interrupt 0 enable" "Disabled,Enabled"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "CBTR,Buffer Transfer Setting Register"
|
|
bitfld.byte 0x00 0.--1. " BTC ,Buffer transfer control" "Not transferred,Transferred,Written,Written"
|
|
wgroup.byte 0x65++0x00
|
|
line.byte 0x00 "CCSRH,Counter Control Set Register, Upper"
|
|
bitfld.byte 0x00 7. " M16ES ,16-bit mode enable set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " CFIES ,Count direction change interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 4. " CLKSS ,Internal prescaler selection set" "No effect,Set"
|
|
wgroup.byte 0x64++0x00
|
|
line.byte 0x00 "CCSRL,Counter Control Set Register, Lower"
|
|
bitfld.byte 0x00 6. " CTUTS ,Counter write set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " UCRES ,Compare clear enable set" "No effect,Set"
|
|
bitfld.byte 0x00 4. " RLDES ,Reload enable set" "No effect,Set"
|
|
bitfld.byte 0x00 2. " CGSCS ,Counter clear/gate function selection set" "No effect,Set"
|
|
wgroup.byte 0x61++0x00
|
|
line.byte 0x00 "CCCRH,Counter Control Clear Register, Upper"
|
|
bitfld.byte 0x00 7. " M16EC ,16-bit mode enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " CDCFC ,Count direction change detection clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " CFIEC ,Count direction change interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " CLKSC ,Internal prescaler selection clear" "No effect,Clear"
|
|
wgroup.byte 0x60++0x00
|
|
line.byte 0x00 "CCCRL,Counter Control Clear Register, Lower"
|
|
bitfld.byte 0x00 5. " UCREC ,Compare clear enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RLDEC ,Reload enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 3. " UDCCC ,Counter clear clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " CGSCC ,Counter clear/gate function selection clear" "No effect,Clear"
|
|
wgroup.byte 0x6C++0x00
|
|
line.byte 0x00 "CSSRL,Counter Status Set Register"
|
|
bitfld.byte 0x00 7. " CSTRS ,Count start set" "No effect,Set"
|
|
bitfld.byte 0x00 6. " CITES ,Compare detection interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " UDIES ,Overflow/Underflow interrupt enable set" "No effect,Set"
|
|
wgroup.byte 0x68++0x00
|
|
line.byte 0x00 "CSCRL,Counter Status Clear Register"
|
|
bitfld.byte 0x00 7. " CSTRC ,Count start clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " CITEC ,Compare detection interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " UDIEC ,Overflow/Underflow interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " CMPFC ,Comparison result match detection flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " OVFFC ,Overflow detection flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " UDFFC ,Underflow detection flag clear" "No effect,Clear"
|
|
wgroup.byte 0x70++0x00
|
|
line.byte 0x00 "CMPFCR,Comparison Result Match Detection Flag Clear Register"
|
|
bitfld.byte 0x00 5. " CMPF5C ,Comparison result match detection 5 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " CMPF4C ,Comparison result match detection 4 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 3. " CMPF3C ,Comparison result match detection 3 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " CMPF2C ,Comparison result match detection 2 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CMPF1C ,Comparison result match detection 1 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " CMPF0C ,Comparison result match detection 0 clear" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xB2000580
|
|
width 11.
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "UDCR,Up/Down Count Register"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "RCR,Reload Compare Register"
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UDCRL,Up/Down Count Register, Lower"
|
|
wgroup.byte 0x00++0x00
|
|
line.byte 0x00 "RCRL,Reload Compare Register, Lower"
|
|
endif
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "CSRL,Counter Status Register"
|
|
bitfld.byte 0x00 7. " CSTR ,Count start bit" "Stopped,Started"
|
|
bitfld.byte 0x00 6. " CITE ,Compare detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " UDIE ,Overflow/Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CMPF ,Compare detection interrupt flag" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " OVFF ,Overflow detection interrupt flag" "No overflow,Overflow"
|
|
bitfld.byte 0x00 2. " UDFF ,Underflow detection interrupt flag" "No underflow,Underflow"
|
|
rbitfld.byte 0x00 0.--1. " UDF ,Up/down flag" "No input,Down count,Up count,Up and down"
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "CCRH,Count Control Register, Upper"
|
|
bitfld.byte 0x00 7. " M16E ,16-bit mode enable" "8-bit,16-bit"
|
|
bitfld.byte 0x00 6. " CDCF ,Count direction change detection flag" "Not changed,Changed"
|
|
bitfld.byte 0x00 5. " CFIE ,Count direction change interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CLKS ,Internal prescaler selection" "2 clock cycles,8 clock cycles"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " CMS ,Count mode selection" "Down count,Up/down count,Multiply-by-2,Multiply-by-4"
|
|
bitfld.byte 0x00 0.--1. " CES ,Count clock edge selection" "Disabled,Falling,Rising,Both"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "CCRL,Count Control Register, Lower"
|
|
bitfld.byte 0x00 6. " CTUT ,Counter write bit" "0,1"
|
|
bitfld.byte 0x00 5. " UCRE ,Compare clear enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RLDE ,Reload enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " UDCC ,Counter clear" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " CGSC ,Counter clear/gate function selection bit" "Counter clear,Gate"
|
|
bitfld.byte 0x00 0.--1. " CGE ,CGSC operation selection (edge/level)" "Disabled,Falling/L,Rising/H,?..."
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "CMPR0,Counter Compare Register 0"
|
|
else
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "CMPRL0,Counter Compare Register 0, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "CMPR1,Counter Compare Register 1"
|
|
else
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "CMPRL1,Counter Compare Register 1, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "CMPR2,Counter Compare Register 2"
|
|
else
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "CMPRL2,Counter Compare Register 2, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "CMPR3,Counter Compare Register 3"
|
|
else
|
|
rgroup.byte 0x1C++0x00
|
|
line.byte 0x00 "CMPRL3,Counter Compare Register 3, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "CMPR4,Counter Compare Register 4"
|
|
else
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "CMPRL4,Counter Compare Register 4, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "CMPR5,Counter Compare Register 5"
|
|
else
|
|
rgroup.byte 0x24++0x00
|
|
line.byte 0x00 "CMPRL5,Counter Compare Register 5, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "CMPBRL0,Counter Compare Buffer Transfer Register 0"
|
|
else
|
|
group.byte 0x28++0x01
|
|
line.byte 0x00 "CMPBRL0,Counter Compare Buffer Transfer Register 0, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "CMPBRL1,Counter Compare Buffer Transfer Register 1"
|
|
else
|
|
group.byte 0x2C++0x01
|
|
line.byte 0x00 "CMPBRL1,Counter Compare Buffer Transfer Register 1, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "CMPBRL2,Counter Compare Buffer Transfer Register 2"
|
|
else
|
|
group.byte 0x30++0x01
|
|
line.byte 0x00 "CMPBRL2,Counter Compare Buffer Transfer Register 2, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CMPBRL3,Counter Compare Buffer Transfer Register 3"
|
|
else
|
|
group.byte 0x34++0x01
|
|
line.byte 0x00 "CMPBRL3,Counter Compare Buffer Transfer Register 3, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "CMPBRL4,Counter Compare Buffer Transfer Register 4"
|
|
else
|
|
group.byte 0x38++0x01
|
|
line.byte 0x00 "CMPBRL4,Counter Compare Buffer Transfer Register 4, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "CMPBRL5,Counter Compare Buffer Transfer Register 5"
|
|
else
|
|
group.byte 0x3C++0x01
|
|
line.byte 0x00 "CMPBRL5,Counter Compare Buffer Transfer Register 5, Lower"
|
|
endif
|
|
textline " "
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "CMPMSKR0,Counter Compare Mask Register 0"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "CMPMSKRL0,Counter Compare Mask Register 0, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "CMPMSKR1,Counter Compare Mask Register 1"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "CMPMSKRL1,Counter Compare Mask Register 1, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "CMPMSKR2,Counter Compare Mask Register 2"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "CMPMSKRL2,Counter Compare Mask Register 2, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "CMPMSKR3,Counter Compare Mask Register 3"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "CMPMSKRL3,Counter Compare Mask Register 3, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "CMPMSKR4,Counter Compare Mask Register 4"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "CMPMSKRL4,Counter Compare Mask Register 4, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB2000580+0x09))&0x80)==0x80)
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "CMPMSKR5,Counter Compare Mask Register 5"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "CMPMSKRL5,Counter Compare Mask Register 5, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
group.byte 0x58++0x01
|
|
line.byte 0x00 "CMPFR,Comparison Result Match Detection Flag Register"
|
|
bitfld.byte 0x00 5. " CMPF5 ,Comparison result match 5 detection flag 5" "Not matched,Matched"
|
|
bitfld.byte 0x00 4. " CMPF4 ,Comparison result match detection flag 4" "Not matched,Matched"
|
|
bitfld.byte 0x00 3. " CMPF3 ,Comparison result match detection flag 3" "Not matched,Matched"
|
|
bitfld.byte 0x00 2. " CMPF2 ,Comparison result match detection flag 2" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CMPF1 ,Comparison result match detection flag 1" "Not matched,Matched"
|
|
bitfld.byte 0x00 0. " CMPF0 ,Comparison result match detection flag 0" "Not matched,Matched"
|
|
line.byte 0x01 "CITER,Comparison Result Match Interrupt Enable Flag Register"
|
|
bitfld.byte 0x01 5. " CITE5 ,Comparison result match interrupt 5 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " CITE4 ,Comparison result match interrupt 4 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " CITE3 ,Comparison result match interrupt 3 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " CITE2 ,Comparison result match interrupt 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " CITE1 ,Comparison result match interrupt 1 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " CITE0 ,Comparison result match interrupt 0 enable" "Disabled,Enabled"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "CBTR,Buffer Transfer Setting Register"
|
|
bitfld.byte 0x00 0.--1. " BTC ,Buffer transfer control" "Not transferred,Transferred,Written,Written"
|
|
wgroup.byte 0x65++0x00
|
|
line.byte 0x00 "CCSRH,Counter Control Set Register, Upper"
|
|
bitfld.byte 0x00 7. " M16ES ,16-bit mode enable set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " CFIES ,Count direction change interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 4. " CLKSS ,Internal prescaler selection set" "No effect,Set"
|
|
wgroup.byte 0x64++0x00
|
|
line.byte 0x00 "CCSRL,Counter Control Set Register, Lower"
|
|
bitfld.byte 0x00 6. " CTUTS ,Counter write set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " UCRES ,Compare clear enable set" "No effect,Set"
|
|
bitfld.byte 0x00 4. " RLDES ,Reload enable set" "No effect,Set"
|
|
bitfld.byte 0x00 2. " CGSCS ,Counter clear/gate function selection set" "No effect,Set"
|
|
wgroup.byte 0x61++0x00
|
|
line.byte 0x00 "CCCRH,Counter Control Clear Register, Upper"
|
|
bitfld.byte 0x00 7. " M16EC ,16-bit mode enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " CDCFC ,Count direction change detection clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " CFIEC ,Count direction change interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " CLKSC ,Internal prescaler selection clear" "No effect,Clear"
|
|
wgroup.byte 0x60++0x00
|
|
line.byte 0x00 "CCCRL,Counter Control Clear Register, Lower"
|
|
bitfld.byte 0x00 5. " UCREC ,Compare clear enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RLDEC ,Reload enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 3. " UDCCC ,Counter clear clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " CGSCC ,Counter clear/gate function selection clear" "No effect,Clear"
|
|
wgroup.byte 0x6C++0x00
|
|
line.byte 0x00 "CSSRL,Counter Status Set Register"
|
|
bitfld.byte 0x00 7. " CSTRS ,Count start set" "No effect,Set"
|
|
bitfld.byte 0x00 6. " CITES ,Compare detection interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " UDIES ,Overflow/Underflow interrupt enable set" "No effect,Set"
|
|
wgroup.byte 0x68++0x00
|
|
line.byte 0x00 "CSCRL,Counter Status Clear Register"
|
|
bitfld.byte 0x00 7. " CSTRC ,Count start clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " CITEC ,Compare detection interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " UDIEC ,Overflow/Underflow interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " CMPFC ,Comparison result match detection flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " OVFFC ,Overflow detection flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " UDFFC ,Underflow detection flag clear" "No effect,Clear"
|
|
wgroup.byte 0x70++0x00
|
|
line.byte 0x00 "CMPFCR,Comparison Result Match Detection Flag Clear Register"
|
|
bitfld.byte 0x00 5. " CMPF5C ,Comparison result match detection 5 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " CMPF4C ,Comparison result match detection 4 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 3. " CMPF3C ,Comparison result match detection 3 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " CMPF2C ,Comparison result match detection 2 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CMPF1C ,Comparison result match detection 1 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " CMPF0C ,Comparison result match detection 0 clear" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xB1000500
|
|
width 11.
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "UDCR,Up/Down Count Register"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "RCR,Reload Compare Register"
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UDCRL,Up/Down Count Register, Lower"
|
|
wgroup.byte 0x00++0x00
|
|
line.byte 0x00 "RCRL,Reload Compare Register, Lower"
|
|
endif
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "CSRL,Counter Status Register"
|
|
bitfld.byte 0x00 7. " CSTR ,Count start bit" "Stopped,Started"
|
|
bitfld.byte 0x00 6. " CITE ,Compare detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " UDIE ,Overflow/Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CMPF ,Compare detection interrupt flag" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " OVFF ,Overflow detection interrupt flag" "No overflow,Overflow"
|
|
bitfld.byte 0x00 2. " UDFF ,Underflow detection interrupt flag" "No underflow,Underflow"
|
|
rbitfld.byte 0x00 0.--1. " UDF ,Up/down flag" "No input,Down count,Up count,Up and down"
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "CCRH,Count Control Register, Upper"
|
|
bitfld.byte 0x00 7. " M16E ,16-bit mode enable" "8-bit,16-bit"
|
|
bitfld.byte 0x00 6. " CDCF ,Count direction change detection flag" "Not changed,Changed"
|
|
bitfld.byte 0x00 5. " CFIE ,Count direction change interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CLKS ,Internal prescaler selection" "2 clock cycles,8 clock cycles"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " CMS ,Count mode selection" "Down count,Up/down count,Multiply-by-2,Multiply-by-4"
|
|
bitfld.byte 0x00 0.--1. " CES ,Count clock edge selection" "Disabled,Falling,Rising,Both"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "CCRL,Count Control Register, Lower"
|
|
bitfld.byte 0x00 6. " CTUT ,Counter write bit" "0,1"
|
|
bitfld.byte 0x00 5. " UCRE ,Compare clear enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RLDE ,Reload enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " UDCC ,Counter clear" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " CGSC ,Counter clear/gate function selection bit" "Counter clear,Gate"
|
|
bitfld.byte 0x00 0.--1. " CGE ,CGSC operation selection (edge/level)" "Disabled,Falling/L,Rising/H,?..."
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "CMPR0,Counter Compare Register 0"
|
|
else
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "CMPRL0,Counter Compare Register 0, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "CMPR1,Counter Compare Register 1"
|
|
else
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "CMPRL1,Counter Compare Register 1, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "CMPR2,Counter Compare Register 2"
|
|
else
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "CMPRL2,Counter Compare Register 2, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "CMPR3,Counter Compare Register 3"
|
|
else
|
|
rgroup.byte 0x1C++0x00
|
|
line.byte 0x00 "CMPRL3,Counter Compare Register 3, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "CMPR4,Counter Compare Register 4"
|
|
else
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "CMPRL4,Counter Compare Register 4, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "CMPR5,Counter Compare Register 5"
|
|
else
|
|
rgroup.byte 0x24++0x00
|
|
line.byte 0x00 "CMPRL5,Counter Compare Register 5, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "CMPBRL0,Counter Compare Buffer Transfer Register 0"
|
|
else
|
|
group.byte 0x28++0x01
|
|
line.byte 0x00 "CMPBRL0,Counter Compare Buffer Transfer Register 0, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "CMPBRL1,Counter Compare Buffer Transfer Register 1"
|
|
else
|
|
group.byte 0x2C++0x01
|
|
line.byte 0x00 "CMPBRL1,Counter Compare Buffer Transfer Register 1, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "CMPBRL2,Counter Compare Buffer Transfer Register 2"
|
|
else
|
|
group.byte 0x30++0x01
|
|
line.byte 0x00 "CMPBRL2,Counter Compare Buffer Transfer Register 2, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CMPBRL3,Counter Compare Buffer Transfer Register 3"
|
|
else
|
|
group.byte 0x34++0x01
|
|
line.byte 0x00 "CMPBRL3,Counter Compare Buffer Transfer Register 3, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "CMPBRL4,Counter Compare Buffer Transfer Register 4"
|
|
else
|
|
group.byte 0x38++0x01
|
|
line.byte 0x00 "CMPBRL4,Counter Compare Buffer Transfer Register 4, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "CMPBRL5,Counter Compare Buffer Transfer Register 5"
|
|
else
|
|
group.byte 0x3C++0x01
|
|
line.byte 0x00 "CMPBRL5,Counter Compare Buffer Transfer Register 5, Lower"
|
|
endif
|
|
textline " "
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "CMPMSKR0,Counter Compare Mask Register 0"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "CMPMSKRL0,Counter Compare Mask Register 0, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "CMPMSKR1,Counter Compare Mask Register 1"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "CMPMSKRL1,Counter Compare Mask Register 1, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "CMPMSKR2,Counter Compare Mask Register 2"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "CMPMSKRL2,Counter Compare Mask Register 2, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "CMPMSKR3,Counter Compare Mask Register 3"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "CMPMSKRL3,Counter Compare Mask Register 3, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "CMPMSKR4,Counter Compare Mask Register 4"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "CMPMSKRL4,Counter Compare Mask Register 4, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB1000500+0x09))&0x80)==0x80)
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "CMPMSKR5,Counter Compare Mask Register 5"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "CMPMSKRL5,Counter Compare Mask Register 5, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
group.byte 0x58++0x01
|
|
line.byte 0x00 "CMPFR,Comparison Result Match Detection Flag Register"
|
|
bitfld.byte 0x00 5. " CMPF5 ,Comparison result match 5 detection flag 5" "Not matched,Matched"
|
|
bitfld.byte 0x00 4. " CMPF4 ,Comparison result match detection flag 4" "Not matched,Matched"
|
|
bitfld.byte 0x00 3. " CMPF3 ,Comparison result match detection flag 3" "Not matched,Matched"
|
|
bitfld.byte 0x00 2. " CMPF2 ,Comparison result match detection flag 2" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CMPF1 ,Comparison result match detection flag 1" "Not matched,Matched"
|
|
bitfld.byte 0x00 0. " CMPF0 ,Comparison result match detection flag 0" "Not matched,Matched"
|
|
line.byte 0x01 "CITER,Comparison Result Match Interrupt Enable Flag Register"
|
|
bitfld.byte 0x01 5. " CITE5 ,Comparison result match interrupt 5 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " CITE4 ,Comparison result match interrupt 4 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " CITE3 ,Comparison result match interrupt 3 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " CITE2 ,Comparison result match interrupt 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " CITE1 ,Comparison result match interrupt 1 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " CITE0 ,Comparison result match interrupt 0 enable" "Disabled,Enabled"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "CBTR,Buffer Transfer Setting Register"
|
|
bitfld.byte 0x00 0.--1. " BTC ,Buffer transfer control" "Not transferred,Transferred,Written,Written"
|
|
wgroup.byte 0x65++0x00
|
|
line.byte 0x00 "CCSRH,Counter Control Set Register, Upper"
|
|
bitfld.byte 0x00 7. " M16ES ,16-bit mode enable set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " CFIES ,Count direction change interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 4. " CLKSS ,Internal prescaler selection set" "No effect,Set"
|
|
wgroup.byte 0x64++0x00
|
|
line.byte 0x00 "CCSRL,Counter Control Set Register, Lower"
|
|
bitfld.byte 0x00 6. " CTUTS ,Counter write set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " UCRES ,Compare clear enable set" "No effect,Set"
|
|
bitfld.byte 0x00 4. " RLDES ,Reload enable set" "No effect,Set"
|
|
bitfld.byte 0x00 2. " CGSCS ,Counter clear/gate function selection set" "No effect,Set"
|
|
wgroup.byte 0x61++0x00
|
|
line.byte 0x00 "CCCRH,Counter Control Clear Register, Upper"
|
|
bitfld.byte 0x00 7. " M16EC ,16-bit mode enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " CDCFC ,Count direction change detection clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " CFIEC ,Count direction change interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " CLKSC ,Internal prescaler selection clear" "No effect,Clear"
|
|
wgroup.byte 0x60++0x00
|
|
line.byte 0x00 "CCCRL,Counter Control Clear Register, Lower"
|
|
bitfld.byte 0x00 5. " UCREC ,Compare clear enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RLDEC ,Reload enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 3. " UDCCC ,Counter clear clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " CGSCC ,Counter clear/gate function selection clear" "No effect,Clear"
|
|
wgroup.byte 0x6C++0x00
|
|
line.byte 0x00 "CSSRL,Counter Status Set Register"
|
|
bitfld.byte 0x00 7. " CSTRS ,Count start set" "No effect,Set"
|
|
bitfld.byte 0x00 6. " CITES ,Compare detection interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " UDIES ,Overflow/Underflow interrupt enable set" "No effect,Set"
|
|
wgroup.byte 0x68++0x00
|
|
line.byte 0x00 "CSCRL,Counter Status Clear Register"
|
|
bitfld.byte 0x00 7. " CSTRC ,Count start clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " CITEC ,Compare detection interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " UDIEC ,Overflow/Underflow interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " CMPFC ,Comparison result match detection flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " OVFFC ,Overflow detection flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " UDFFC ,Underflow detection flag clear" "No effect,Clear"
|
|
wgroup.byte 0x70++0x00
|
|
line.byte 0x00 "CMPFCR,Comparison Result Match Detection Flag Clear Register"
|
|
bitfld.byte 0x00 5. " CMPF5C ,Comparison result match detection 5 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " CMPF4C ,Comparison result match detection 4 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 3. " CMPF3C ,Comparison result match detection 3 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " CMPF2C ,Comparison result match detection 2 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CMPF1C ,Comparison result match detection 1 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " CMPF0C ,Comparison result match detection 0 clear" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0xB1000580
|
|
width 11.
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "UDCR,Up/Down Count Register"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "RCR,Reload Compare Register"
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UDCRL,Up/Down Count Register, Lower"
|
|
wgroup.byte 0x00++0x00
|
|
line.byte 0x00 "RCRL,Reload Compare Register, Lower"
|
|
endif
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "CSRL,Counter Status Register"
|
|
bitfld.byte 0x00 7. " CSTR ,Count start bit" "Stopped,Started"
|
|
bitfld.byte 0x00 6. " CITE ,Compare detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " UDIE ,Overflow/Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CMPF ,Compare detection interrupt flag" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " OVFF ,Overflow detection interrupt flag" "No overflow,Overflow"
|
|
bitfld.byte 0x00 2. " UDFF ,Underflow detection interrupt flag" "No underflow,Underflow"
|
|
rbitfld.byte 0x00 0.--1. " UDF ,Up/down flag" "No input,Down count,Up count,Up and down"
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "CCRH,Count Control Register, Upper"
|
|
bitfld.byte 0x00 7. " M16E ,16-bit mode enable" "8-bit,16-bit"
|
|
bitfld.byte 0x00 6. " CDCF ,Count direction change detection flag" "Not changed,Changed"
|
|
bitfld.byte 0x00 5. " CFIE ,Count direction change interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CLKS ,Internal prescaler selection" "2 clock cycles,8 clock cycles"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " CMS ,Count mode selection" "Down count,Up/down count,Multiply-by-2,Multiply-by-4"
|
|
bitfld.byte 0x00 0.--1. " CES ,Count clock edge selection" "Disabled,Falling,Rising,Both"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "CCRL,Count Control Register, Lower"
|
|
bitfld.byte 0x00 6. " CTUT ,Counter write bit" "0,1"
|
|
bitfld.byte 0x00 5. " UCRE ,Compare clear enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RLDE ,Reload enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " UDCC ,Counter clear" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " CGSC ,Counter clear/gate function selection bit" "Counter clear,Gate"
|
|
bitfld.byte 0x00 0.--1. " CGE ,CGSC operation selection (edge/level)" "Disabled,Falling/L,Rising/H,?..."
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "CMPR0,Counter Compare Register 0"
|
|
else
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "CMPRL0,Counter Compare Register 0, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "CMPR1,Counter Compare Register 1"
|
|
else
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "CMPRL1,Counter Compare Register 1, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "CMPR2,Counter Compare Register 2"
|
|
else
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "CMPRL2,Counter Compare Register 2, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "CMPR3,Counter Compare Register 3"
|
|
else
|
|
rgroup.byte 0x1C++0x00
|
|
line.byte 0x00 "CMPRL3,Counter Compare Register 3, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "CMPR4,Counter Compare Register 4"
|
|
else
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "CMPRL4,Counter Compare Register 4, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "CMPR5,Counter Compare Register 5"
|
|
else
|
|
rgroup.byte 0x24++0x00
|
|
line.byte 0x00 "CMPRL5,Counter Compare Register 5, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "CMPBRL0,Counter Compare Buffer Transfer Register 0"
|
|
else
|
|
group.byte 0x28++0x01
|
|
line.byte 0x00 "CMPBRL0,Counter Compare Buffer Transfer Register 0, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "CMPBRL1,Counter Compare Buffer Transfer Register 1"
|
|
else
|
|
group.byte 0x2C++0x01
|
|
line.byte 0x00 "CMPBRL1,Counter Compare Buffer Transfer Register 1, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "CMPBRL2,Counter Compare Buffer Transfer Register 2"
|
|
else
|
|
group.byte 0x30++0x01
|
|
line.byte 0x00 "CMPBRL2,Counter Compare Buffer Transfer Register 2, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CMPBRL3,Counter Compare Buffer Transfer Register 3"
|
|
else
|
|
group.byte 0x34++0x01
|
|
line.byte 0x00 "CMPBRL3,Counter Compare Buffer Transfer Register 3, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "CMPBRL4,Counter Compare Buffer Transfer Register 4"
|
|
else
|
|
group.byte 0x38++0x01
|
|
line.byte 0x00 "CMPBRL4,Counter Compare Buffer Transfer Register 4, Lower"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "CMPBRL5,Counter Compare Buffer Transfer Register 5"
|
|
else
|
|
group.byte 0x3C++0x01
|
|
line.byte 0x00 "CMPBRL5,Counter Compare Buffer Transfer Register 5, Lower"
|
|
endif
|
|
textline " "
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "CMPMSKR0,Counter Compare Mask Register 0"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "CMPMSKRL0,Counter Compare Mask Register 0, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "CMPMSKR1,Counter Compare Mask Register 1"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "CMPMSKRL1,Counter Compare Mask Register 1, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "CMPMSKR2,Counter Compare Mask Register 2"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "CMPMSKRL2,Counter Compare Mask Register 2, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "CMPMSKR3,Counter Compare Mask Register 3"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "CMPMSKRL3,Counter Compare Mask Register 3, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "CMPMSKR4,Counter Compare Mask Register 4"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "CMPMSKRL4,Counter Compare Mask Register 4, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
if (((per.l(ad:0xB1000580+0x09))&0x80)==0x80)
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "CMPMSKR5,Counter Compare Mask Register 5"
|
|
bitfld.word 0x00 15. " DM15 ,Compare comparison mask bit 15" "Masked,Not masked"
|
|
bitfld.word 0x00 14. " DM14 ,Compare comparison mask bit 14" "Masked,Not masked"
|
|
bitfld.word 0x00 13. " DM13 ,Compare comparison mask bit 13" "Masked,Not masked"
|
|
bitfld.word 0x00 12. " DM12 ,Compare comparison mask bit 12" "Masked,Not masked"
|
|
bitfld.word 0x00 11. " DM11 ,Compare comparison mask bit 11" "Masked,Not masked"
|
|
bitfld.word 0x00 10. " DM10 ,Compare comparison mask bit 10" "Masked,Not masked"
|
|
bitfld.word 0x00 9. " DM9 ,Compare comparison mask bit 9" "Masked,Not masked"
|
|
bitfld.word 0x00 8. " DM8 ,Compare comparison mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.word 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.word 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.word 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.word 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.word 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
else
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "CMPMSKRL5,Counter Compare Mask Register 5, Lower"
|
|
bitfld.byte 0x00 7. " DM7 ,Compare comparison mask bit 7" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " DM6 ,Compare comparison mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " DM5 ,Compare comparison mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " DM4 ,Compare comparison mask bit 4" "Masked,Not masked"
|
|
bitfld.byte 0x00 3. " DM3 ,Compare comparison mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " DM2 ,Compare comparison mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " DM1 ,Compare comparison mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " DM0 ,Compare comparison mask bit 0" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
group.byte 0x58++0x01
|
|
line.byte 0x00 "CMPFR,Comparison Result Match Detection Flag Register"
|
|
bitfld.byte 0x00 5. " CMPF5 ,Comparison result match 5 detection flag 5" "Not matched,Matched"
|
|
bitfld.byte 0x00 4. " CMPF4 ,Comparison result match detection flag 4" "Not matched,Matched"
|
|
bitfld.byte 0x00 3. " CMPF3 ,Comparison result match detection flag 3" "Not matched,Matched"
|
|
bitfld.byte 0x00 2. " CMPF2 ,Comparison result match detection flag 2" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CMPF1 ,Comparison result match detection flag 1" "Not matched,Matched"
|
|
bitfld.byte 0x00 0. " CMPF0 ,Comparison result match detection flag 0" "Not matched,Matched"
|
|
line.byte 0x01 "CITER,Comparison Result Match Interrupt Enable Flag Register"
|
|
bitfld.byte 0x01 5. " CITE5 ,Comparison result match interrupt 5 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " CITE4 ,Comparison result match interrupt 4 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " CITE3 ,Comparison result match interrupt 3 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " CITE2 ,Comparison result match interrupt 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " CITE1 ,Comparison result match interrupt 1 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " CITE0 ,Comparison result match interrupt 0 enable" "Disabled,Enabled"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "CBTR,Buffer Transfer Setting Register"
|
|
bitfld.byte 0x00 0.--1. " BTC ,Buffer transfer control" "Not transferred,Transferred,Written,Written"
|
|
wgroup.byte 0x65++0x00
|
|
line.byte 0x00 "CCSRH,Counter Control Set Register, Upper"
|
|
bitfld.byte 0x00 7. " M16ES ,16-bit mode enable set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " CFIES ,Count direction change interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 4. " CLKSS ,Internal prescaler selection set" "No effect,Set"
|
|
wgroup.byte 0x64++0x00
|
|
line.byte 0x00 "CCSRL,Counter Control Set Register, Lower"
|
|
bitfld.byte 0x00 6. " CTUTS ,Counter write set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " UCRES ,Compare clear enable set" "No effect,Set"
|
|
bitfld.byte 0x00 4. " RLDES ,Reload enable set" "No effect,Set"
|
|
bitfld.byte 0x00 2. " CGSCS ,Counter clear/gate function selection set" "No effect,Set"
|
|
wgroup.byte 0x61++0x00
|
|
line.byte 0x00 "CCCRH,Counter Control Clear Register, Upper"
|
|
bitfld.byte 0x00 7. " M16EC ,16-bit mode enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " CDCFC ,Count direction change detection clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " CFIEC ,Count direction change interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " CLKSC ,Internal prescaler selection clear" "No effect,Clear"
|
|
wgroup.byte 0x60++0x00
|
|
line.byte 0x00 "CCCRL,Counter Control Clear Register, Lower"
|
|
bitfld.byte 0x00 5. " UCREC ,Compare clear enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RLDEC ,Reload enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 3. " UDCCC ,Counter clear clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " CGSCC ,Counter clear/gate function selection clear" "No effect,Clear"
|
|
wgroup.byte 0x6C++0x00
|
|
line.byte 0x00 "CSSRL,Counter Status Set Register"
|
|
bitfld.byte 0x00 7. " CSTRS ,Count start set" "No effect,Set"
|
|
bitfld.byte 0x00 6. " CITES ,Compare detection interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " UDIES ,Overflow/Underflow interrupt enable set" "No effect,Set"
|
|
wgroup.byte 0x68++0x00
|
|
line.byte 0x00 "CSCRL,Counter Status Clear Register"
|
|
bitfld.byte 0x00 7. " CSTRC ,Count start clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " CITEC ,Compare detection interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " UDIEC ,Overflow/Underflow interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " CMPFC ,Comparison result match detection flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " OVFFC ,Overflow detection flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " UDFFC ,Underflow detection flag clear" "No effect,Clear"
|
|
wgroup.byte 0x70++0x00
|
|
line.byte 0x00 "CMPFCR,Comparison Result Match Detection Flag Clear Register"
|
|
bitfld.byte 0x00 5. " CMPF5C ,Comparison result match detection 5 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " CMPF4C ,Comparison result match detection 4 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 3. " CMPF3C ,Comparison result match detection 3 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " CMPF2C ,Comparison result match detection 2 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CMPF1C ,Comparison result match detection 1 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " CMPF0C ,Comparison result match detection 0 clear" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "FRT16B (16-bit Free-run Timer)"
|
|
tree "Channel 0"
|
|
base ad:0xB2000000
|
|
width 8.
|
|
if (((per.l(ad:0xB2000000+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xB2000010
|
|
width 8.
|
|
if (((per.l(ad:0xB2000010+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xB2000020
|
|
width 8.
|
|
if (((per.l(ad:0xB2000020+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0xB2000030
|
|
width 8.
|
|
if (((per.l(ad:0xB2000030+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 4"
|
|
base ad:0xB2000040
|
|
width 8.
|
|
if (((per.l(ad:0xB2000040+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 5"
|
|
base ad:0xB2000050
|
|
width 8.
|
|
if (((per.l(ad:0xB2000050+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 6"
|
|
base ad:0xB1000000
|
|
width 8.
|
|
if (((per.l(ad:0xB1000000+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 7"
|
|
base ad:0xB1000010
|
|
width 8.
|
|
if (((per.l(ad:0xB1000010+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 8"
|
|
base ad:0xB1000020
|
|
width 8.
|
|
if (((per.l(ad:0xB1000020+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 9"
|
|
base ad:0xB1000030
|
|
width 8.
|
|
if (((per.l(ad:0xB1000030+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 10"
|
|
base ad:0xB1000040
|
|
width 8.
|
|
if (((per.l(ad:0xB1000040+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 11"
|
|
base ad:0xB1000050
|
|
width 8.
|
|
if (((per.l(ad:0xB1000050+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 12"
|
|
base ad:0xB1010000
|
|
width 8.
|
|
if (((per.l(ad:0xB1010000+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 13"
|
|
base ad:0xB1010010
|
|
width 8.
|
|
if (((per.l(ad:0xB1010010+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 14"
|
|
base ad:0xB1010020
|
|
width 8.
|
|
if (((per.l(ad:0xB1010020+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 15"
|
|
base ad:0xB1010030
|
|
width 8.
|
|
if (((per.l(ad:0xB1010030+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 16"
|
|
base ad:0xB1010040
|
|
width 8.
|
|
if (((per.l(ad:0xB1010040+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 17"
|
|
base ad:0xB1010050
|
|
width 8.
|
|
if (((per.l(ad:0xB1010050+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 18"
|
|
base ad:0xB2000060
|
|
width 8.
|
|
if (((per.l(ad:0xB2000060+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 19"
|
|
base ad:0xB1000060
|
|
width 8.
|
|
if (((per.l(ad:0xB1000060+0x04))&0x800000)==0x800000)
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
else
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "CPCLR,Compare Clear Register"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
bitfld.long 0x00 31. " ECKE ,Clock selection" "Peripheral,External"
|
|
bitfld.long 0x00 30. " IRQZF ,0 detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQZE ,0 detection interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--28. " MSI[2:0] ,Interrupt mask selection bits [2:0]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICLR ,Compare clear interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ICRE ,Compare clear interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " BFE ,Compare clear buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOP ,Timer enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE ,Timer count mode" "Up,Up/down"
|
|
bitfld.long 0x00 20. " SCLR ,Timer clear" "No effect,Clear"
|
|
bitfld.long 0x00 16.--19. " CLK ,Clock frequency selection" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSI[5:3] ,Interrupt mask selection bits [5:3]" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "TCCSC,Timer State Clear Register"
|
|
bitfld.long 0x00 31. " ECKEC ,Clock selection clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " IRQZEC ,0 detection interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ICREC ,Compare clear interrupt request enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " BFEC ,Compare clear buffer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " STOPC ,Timer enable clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " MODEC ,Timer count mode clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MODE2C ,Interrupt mask mode 2 clear" "No effect,Clear"
|
|
line.long 0x04 "TCCSS,Timer State Set Register"
|
|
bitfld.long 0x04 31. " ECKES ,Clock selection set" "No effect,Set"
|
|
bitfld.long 0x04 29. " IRQZES ,0 detection interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 24. " ICRES ,Compare clear interrupt request enable set" "No effect,Set"
|
|
bitfld.long 0x04 23. " BFES ,Compare clear buffer enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " STOPS ,Timer enable set" "No effect,Set"
|
|
bitfld.long 0x04 21. " MODES ,Timer count mode set" "No effect,Set"
|
|
bitfld.long 0x04 20. " SCLRS ,Timer clear set" "No effect,Set"
|
|
bitfld.long 0x04 11. " MODE2S ,Interrupt mask mode 2 set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "FRSEL (Free-run Timer Selection and Simultaneous Activation)"
|
|
base ad:0xB1000070
|
|
width 15.
|
|
group.long 0x1000010++0x03
|
|
line.long 0x00 "FRSEL00_FRS0,Free-run Timer Selection Register 0"
|
|
bitfld.long 0x00 20.--22. " OS5 ,16-bit output compare channel 5 free-run timer selection" "Ch.0,Ch.1,Ch.2,Ch.3,Ch.4,Ch.5,?..."
|
|
bitfld.long 0x00 16.--18. " OS4 ,16-bit output compare channel 4 free-run timer selection" "Ch.0,Ch.1,Ch.2,Ch.3,Ch.4,Ch.5,?..."
|
|
bitfld.long 0x00 12.--14. " OS3 ,16-bit output compare channel 3 free-run timer selection" "Ch.0,Ch.1,Ch.2,Ch.3,Ch.4,Ch.5,?..."
|
|
bitfld.long 0x00 8.--10. " OS2 ,16-bit output compare channel 2 free-run timer selection" "Ch.0,Ch.1,Ch.2,Ch.3,Ch.4,Ch.5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OS1 ,16-bit output compare channel 1 free-run timer selection" "Ch.0,Ch.1,Ch.2,Ch.3,Ch.4,Ch.5,?..."
|
|
bitfld.long 0x00 0.--2. " OS0 ,16-bit output compare channel 0 free-run timer selection" "Ch.0,Ch.1,Ch.2,Ch.3,Ch.4,Ch.5,?..."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FRSEL01_FRS0,Free-run Timer Selection Register 0"
|
|
bitfld.long 0x00 20.--22. " OS5 ,16-bit output compare channel 11 free-run timer selection" "Ch.6,Ch.7,Ch.8,Ch.9,Ch.10,Ch.11,?..."
|
|
bitfld.long 0x00 16.--18. " OS4 ,16-bit output compare channel 10 free-run timer selection" "Ch.6,Ch.7,Ch.8,Ch.9,Ch.10,Ch.11,?..."
|
|
bitfld.long 0x00 12.--14. " OS3 ,16-bit output compare channel 9 free-run timer selection" "Ch.6,Ch.7,Ch.8,Ch.9,Ch.10,Ch.11,?..."
|
|
bitfld.long 0x00 8.--10. " OS2 ,16-bit output compare channel 8 free-run timer selection" "Ch.6,Ch.7,Ch.8,Ch.9,Ch.10,Ch.11,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OS1 ,16-bit output compare channel 7 free-run timer selection" "Ch.6,Ch.7,Ch.8,Ch.9,Ch.10,Ch.11,?..."
|
|
bitfld.long 0x00 0.--2. " OS0 ,16-bit output compare channel 6 free-run timer selection" "Ch.6,Ch.7,Ch.8,Ch.9,Ch.10,Ch.11,?..."
|
|
sif cpuis("MB9DF56?M*")
|
|
group.long 0x10010++0x03
|
|
line.long 0x00 "FRSEL02_FRS0,Free-run Timer Selection Register 0"
|
|
bitfld.long 0x00 20.--22. " OS5 ,16-bit output compare channel 17 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 16.--18. " OS4 ,16-bit output compare channel 16 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 12.--14. " OS3 ,16-bit output compare channel 15 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 8.--10. " OS2 ,16-bit output compare channel 14 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OS1 ,16-bit output compare channel 13 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 0.--2. " OS0 ,16-bit output compare channel 12 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
else
|
|
hgroup.long 0x10010++0x03
|
|
hide.long 0x00 "FRSEL02_FRS0,Free-run Timer Selection Register 0"
|
|
endif
|
|
group.long 0x10018++0x03
|
|
line.long 0x00 "FRSEL02_FRS2,Free-run Timer Selection Register 2"
|
|
bitfld.long 0x00 20.--22. " OS11 ,16-bit output compare channel 23 free-run timer selection bits" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 16.--18. " OS10 ,16-bit output compare channel 22 free-run timer selection bits" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 12.--14. " OS9 ,16-bit output compare channel 21 free-run timer selection bits" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 8.--10. " OS8 ,16-bit output compare channel 20 free-run timer selection bits" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OS7 ,16-bit output compare channel 19 free-run timer selection bits" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 0.--2. " OS6 ,16-bit output compare channel 18 free-run timer selection bits" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
group.long 0x1000014++0x03
|
|
line.long 0x00 "FRSEL00_FRS1,Free-run Timer Selection Register 1"
|
|
bitfld.long 0x00 12.--14. " IS3 ,16-bit input capture channel 3 free-run timer selection" "Ch.0,Ch.1,Ch.2,Ch.3,Ch.4,Ch.5,?..."
|
|
bitfld.long 0x00 8.--10. " IS2 ,16-bit input capture channel 2 free-run timer selection" "Ch.0,Ch.1,Ch.2,Ch.3,Ch.4,Ch.5,?..."
|
|
bitfld.long 0x00 4.--6. " IS1 ,16-bit input capture channel 1 free-run timer selection" "Ch.0,Ch.1,Ch.2,Ch.3,Ch.4,Ch.5,?..."
|
|
bitfld.long 0x00 0.--2. " IS0 ,16-bit input capture channel 0 free-run timer selection" "Ch.0,Ch.1,Ch.2,Ch.3,Ch.4,Ch.5,?..."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FRSEL01_FRS1,Free-run Timer Selection Register 1"
|
|
bitfld.long 0x00 12.--14. " IS3 ,16-bit input capture channel 7 free-run timer selection" "Ch.6,Ch.7,Ch.8,Ch.9,Ch.10,Ch.11,?..."
|
|
bitfld.long 0x00 8.--10. " IS2 ,16-bit input capture channel 6 free-run timer selection" "Ch.6,Ch.7,Ch.8,Ch.9,Ch.10,Ch.11,?..."
|
|
bitfld.long 0x00 4.--6. " IS1 ,16-bit input capture channel 5 free-run timer selection" "Ch.6,Ch.7,Ch.8,Ch.9,Ch.10,Ch.11,?..."
|
|
bitfld.long 0x00 0.--2. " IS0 ,16-bit input capture channel 4 free-run timer selection" "Ch.6,Ch.7,Ch.8,Ch.9,Ch.10,Ch.11,?..."
|
|
group.long 0x10014++0x03
|
|
line.long 0x00 "FRSEL02_FRS1,Free-run Timer Selection Register 1"
|
|
bitfld.long 0x00 12.--14. " IS3 ,16-bit input capture channel 11 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 8.--10. " IS2 ,16-bit input capture channel 10 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 4.--6. " IS1 ,16-bit input capture channel 9 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 0.--2. " IS0 ,16-bit input capture channel 8 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
group.long 0x1001C++0x03
|
|
line.long 0x00 "FRSEL02_FRS3,Free-run Timer Selection Register 3"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.long 0x00 8.--10. " IS6 ,16-bit input capture channel 14 free-run timer selection bits" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 4.--6. " IS5 ,16-bit input capture channel 13 free-run timer selection bits" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 0.--2. " IS4 ,16-bit input capture channel 12 free-run timer selection bits" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
else
|
|
bitfld.long 0x00 0.--2. " IS4 ,16-bit input capture channel 12 free-run timer selection bits" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
endif
|
|
group.long 0x1000020++0x03
|
|
line.long 0x00 "FRSEL00_FRS4,Free-run Timer Selection Register 4"
|
|
bitfld.long 0x00 4.--6. " AS1 ,4ch A/D activation compare 0 activation group 1 free-run timer selection" "Ch.0,Ch.1,Ch.2,Ch.3,Ch.4,Ch.5,?..."
|
|
bitfld.long 0x00 0.--2. " AS0 ,4ch A/D activation compare 0 activation group 0 free-run timer selection" "Ch.0,Ch.1,Ch.2,Ch.3,Ch.4,Ch.5,?..."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FRSEL01_FRS4,Free-run Timer Selection Register 4"
|
|
bitfld.long 0x00 4.--6. " AS1 ,4ch A/D activation compare1 activation group 1 free-run timer selection" "Ch.6,Ch.7,Ch.8,Ch.9,Ch.10,Ch.11,?..."
|
|
bitfld.long 0x00 0.--2. " AS0 ,4ch A/D activation compare 1 activation group 0 free-run timer selection" "Ch.6,Ch.7,Ch.8,Ch.9,Ch.10,Ch.11,?..."
|
|
group.long 0x10020++0x0F
|
|
line.long 0x00 "FRSEL02_FRS4,Free-run Timer Selection Register 4"
|
|
bitfld.long 0x00 28.--30. " AS7 ,A/D activation compare 7 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 24.--26. " AS6 ,A/D activation compare 6 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 20.--22. " AS5 ,A/D activation compare 5 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 16.--18. " AS4 ,A/D activation compare 4 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " AS3 ,A/D activation compare 3 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 8.--10. " AS2 ,A/D activation compare 2 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 4.--6. " AS1 ,A/D activation compare 1 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x00 0.--2. " AS0 ,A/D activation compare 0 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
line.long 0x04 "FRSEL02_FRS5,Free-run Timer Selection Register 5"
|
|
bitfld.long 0x04 28.--30. " AS15 ,A/D activation compare 15 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x04 24.--26. " AS14 ,A/D activation compare 14 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x04 20.--22. " AS13 ,A/D activation compare 13 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x04 16.--18. " AS12 ,A/D activation compare 12 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " AS11 ,A/D activation compare 11 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x04 8.--10. " AS10 ,A/D activation compare 10 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x04 4.--6. " AS9 ,A/D activation compare 9 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x04 0.--2. " AS8 ,A/D activation compare 8 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
line.long 0x08 "FRSEL02_FRS6,Free-run Timer Selection Register 6"
|
|
bitfld.long 0x08 28.--30. " AS23 ,A/D activation compare 23 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x08 24.--26. " AS22 ,A/D activation compare 22 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x08 20.--22. " AS21 ,A/D activation compare 21 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x08 16.--18. " AS20 ,A/D activation compare 20 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " AS19 ,A/D activation compare 19 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x08 8.--10. " AS18 ,A/D activation compare 18 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x08 4.--6. " AS17 ,A/D activation compare 17 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x08 0.--2. " AS16 ,A/D activation compare 16 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
line.long 0x0C "FRSEL02_FRS7,Free-run Timer Selection Register 7"
|
|
bitfld.long 0x0C 28.--30. " AS31 ,A/D activation compare 31 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x0C 24.--26. " AS30 ,A/D activation compare 30 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x0C 20.--22. " AS29 ,A/D activation compare 29 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x0C 16.--18. " AS28 ,A/D activation compare 28 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--14. " AS27 ,A/D activation compare 27 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x0C 8.--10. " AS26 ,A/D activation compare 26 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x0C 4.--6. " AS25 ,A/D activation compare 25 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
bitfld.long 0x0C 0.--2. " AS24 ,A/D activation compare 24 free-run timer selection" "Ch.12,Ch.13,Ch.14,Ch.15,Ch.16,Ch.17,?..."
|
|
wgroup.byte 0x1000003++0x00
|
|
line.byte 0x00 "FRSS00_TCGS,Timer Synchronous Activation Register"
|
|
bitfld.byte 0x00 1. " GSTOP ,Simultaneous timer enable" "Enable,Disable"
|
|
bitfld.byte 0x00 0. " GSCLR ,Simultaneous timer clear" "No effect,Clear"
|
|
wgroup.byte 0x03++0x00
|
|
line.byte 0x00 "FRSS01_TCGS,Timer Synchronous Activation Register"
|
|
bitfld.byte 0x00 1. " GSTOP ,Simultaneous timer enable" "Enable,Disable"
|
|
bitfld.byte 0x00 0. " GSCLR ,Simultaneous timer clear" "No effect,Clear"
|
|
wgroup.byte 0x10003++0x00
|
|
line.byte 0x00 "FRSS02_TCGS,Timer Synchronous Activation Register"
|
|
bitfld.byte 0x00 1. " GSTOP ,Simultaneous timer enable" "Enable,Disable"
|
|
bitfld.byte 0x00 0. " GSCLR ,Simultaneous timer clear" "No effect,Clear"
|
|
group.word 0x1000000++0x01
|
|
line.word 0x00 "FRSS00_TCGSE,Timer Simultaneous Activation Enable Register 0"
|
|
bitfld.word 0x00 5. " FRT5 ,Simultaneous activation/clear setting of channel 5" "Not performed,Performed"
|
|
bitfld.word 0x00 4. " FRT4 ,Simultaneous activation/clear setting of channel 4" "Not performed,Performed"
|
|
bitfld.word 0x00 3. " FRT3 ,Simultaneous activation/clear setting of channel 3" "Not performed,Performed"
|
|
bitfld.word 0x00 2. " FRT2 ,Simultaneous activation/clear setting of channel 2" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FRT1 ,Simultaneous activation/clear setting of channel 1" "Not performed,Performed"
|
|
bitfld.word 0x00 0. " FRT0 ,Simultaneous activation/clear setting of channel 0" "Not performed,Performed"
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "FRSS01_TCGSE,Timer Simultaneous Activation Enable Register 1"
|
|
bitfld.word 0x00 5. " FRT5 ,Simultaneous activation/clear setting of channel 11" "Not performed,Performed"
|
|
bitfld.word 0x00 4. " FRT4 ,Simultaneous activation/clear setting of channel 10" "Not performed,Performed"
|
|
bitfld.word 0x00 3. " FRT3 ,Simultaneous activation/clear setting of channel 9" "Not performed,Performed"
|
|
bitfld.word 0x00 2. " FRT2 ,Simultaneous activation/clear setting of channel 8" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FRT1 ,Simultaneous activation/clear setting of channel 7" "Not performed,Performed"
|
|
bitfld.word 0x00 0. " FRT0 ,Simultaneous activation/clear setting of channel 6" "Not performed,Performed"
|
|
group.word 0x10000++0x01
|
|
line.word 0x00 "FRSS02_TCGSE,Timer Simultaneous Activation Enable Register 2"
|
|
bitfld.word 0x00 11. " FRT11 ,Simultaneous activation/clear setting of channel 11" "Not performed,Performed"
|
|
bitfld.word 0x00 10. " FRT10 ,Simultaneous activation/clear setting of channel 10" "Not performed,Performed"
|
|
bitfld.word 0x00 9. " FRT9 ,Simultaneous activation/clear setting of channel 9" "Not performed,Performed"
|
|
bitfld.word 0x00 8. " FRT8 ,Simultaneous activation/clear setting of channel 8" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.word 0x00 7. " FRT7 ,Simultaneous activation/clear setting of channel 7" "Not performed,Performed"
|
|
bitfld.word 0x00 6. " FRT6 ,Simultaneous activation/clear setting of channel 6" "Not performed,Performed"
|
|
bitfld.word 0x00 5. " FRT5 ,Simultaneous activation/clear setting of channel 17" "Not performed,Performed"
|
|
bitfld.word 0x00 4. " FRT4 ,Simultaneous activation/clear setting of channel 16" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRT3 ,Simultaneous activation/clear setting of channel 15" "Not performed,Performed"
|
|
bitfld.word 0x00 2. " FRT2 ,Simultaneous activation/clear setting of channel 14" "Not performed,Performed"
|
|
bitfld.word 0x00 1. " FRT1 ,Simultaneous activation/clear setting of channel 13" "Not performed,Performed"
|
|
bitfld.word 0x00 0. " FRT0 ,Simultaneous activation/clear setting of channel 12" "Not performed,Performed"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "FRSS01_TCGSS,Timer Simultaneous Activation Source Selection Register"
|
|
bitfld.byte 0x00 0. " SEL ,Simultaneous activation source selection for free-run timer channels 6 to 11" "1,2"
|
|
rgroup.byte 0x1000030++0x00
|
|
line.byte 0x00 "FRCD00_FRTCDD,Free-run Timer Count Direction Indication Register"
|
|
bitfld.byte 0x00 5. " DOWN5 ,Channel 5 count direction indication" "Up,Down"
|
|
bitfld.byte 0x00 4. " DOWN4 ,Channel 4 count direction indication" "Up,Down"
|
|
bitfld.byte 0x00 3. " DOWN3 ,Channel 3 count direction indication" "Up,Down"
|
|
bitfld.byte 0x00 2. " DOWN2 ,Channel 2 count direction indication" "Up,Down"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DOWN1 ,Channel 1 count direction indication" "Up,Down"
|
|
bitfld.byte 0x00 0. " DOWN0 ,Channel 0 count direction indication" "Up,Down"
|
|
rgroup.byte 0x30++0x00
|
|
line.byte 0x00 "FRCD01_FRTCDD,Free-run Timer Count Direction Indication Register"
|
|
bitfld.byte 0x00 5. " DOWN5 ,Channel 11 count direction indication" "Up,Down"
|
|
bitfld.byte 0x00 4. " DOWN4 ,Channel 10 count direction indication" "Up,Down"
|
|
bitfld.byte 0x00 3. " DOWN3 ,Channel 9 count direction indication" "Up,Down"
|
|
bitfld.byte 0x00 2. " DOWN2 ,Channel 8 count direction indication" "Up,Down"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DOWN1 ,Channel 7 count direction indication" "Up,Down"
|
|
bitfld.byte 0x00 0. " DOWN0 ,Channel 6 count direction indication" "Up,Down"
|
|
rgroup.byte 0x10030++0x00
|
|
line.byte 0x00 "FRCD02_FRTCDD,Free-run Timer Count Direction Indication Register"
|
|
bitfld.byte 0x00 5. " DOWN5 ,Channel 17 count direction indication" "Up,Down"
|
|
bitfld.byte 0x00 4. " DOWN4 ,Channel 16 count direction indication" "Up,Down"
|
|
bitfld.byte 0x00 3. " DOWN3 ,Channel 15 count direction indication" "Up,Down"
|
|
bitfld.byte 0x00 2. " DOWN2 ,Channel 14 count direction indication" "Up,Down"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DOWN1 ,Channel 13 count direction indication" "Up,Down"
|
|
bitfld.byte 0x00 0. " DOWN0 ,Channel 12 count direction indication" "Up,Down"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "ICU16B (16-bit Input Capture)"
|
|
tree "Unit 0"
|
|
base ad:0xB2000200
|
|
width 7.
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "IPCP0,Input Capture Data Register 0"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "IPCP1,Input Capture Data Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "ICS,Input Capture State Control Register"
|
|
bitfld.word 0x00 9. " IEI1 ,Input capture 1 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 8. " IEI0 ,Input capture 0 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 7. " ICP1 ,Input capture 1 interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " ICP0 ,Input capture 0 interrupt request flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ICE1 ,Input capture 1 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ICE0 ,Input capture 0 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--3. " EG1 ,Input capture 1 edge selection" "None,Rising,Falling,Both"
|
|
bitfld.word 0x00 0.--1. " EG0 ,Input capture 0 edge selection" "None,Rising,Falling,Both"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "ICSC,Input Capture State Clear Register"
|
|
bitfld.word 0x00 7. " ICP1C ,Input capture 1 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " ICP0C ,Input capture 0 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " ICE1C ,Input capture 1 interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " ICE0C ,Input capture 0 interrupt request enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "ICSS,Input Capture State Set Register"
|
|
bitfld.word 0x00 5. " ICES1 ,Input capture 1 interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " ICES0 ,Input capture 0 interrupt request enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 1"
|
|
base ad:0xB2000210
|
|
width 7.
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "IPCP0,Input Capture Data Register 0"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "IPCP1,Input Capture Data Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "ICS,Input Capture State Control Register"
|
|
bitfld.word 0x00 9. " IEI1 ,Input capture 1 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 8. " IEI0 ,Input capture 0 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 7. " ICP1 ,Input capture 1 interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " ICP0 ,Input capture 0 interrupt request flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ICE1 ,Input capture 1 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ICE0 ,Input capture 0 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--3. " EG1 ,Input capture 1 edge selection" "None,Rising,Falling,Both"
|
|
bitfld.word 0x00 0.--1. " EG0 ,Input capture 0 edge selection" "None,Rising,Falling,Both"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "ICSC,Input Capture State Clear Register"
|
|
bitfld.word 0x00 7. " ICP1C ,Input capture 1 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " ICP0C ,Input capture 0 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " ICE1C ,Input capture 1 interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " ICE0C ,Input capture 0 interrupt request enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "ICSS,Input Capture State Set Register"
|
|
bitfld.word 0x00 5. " ICES1 ,Input capture 1 interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " ICES0 ,Input capture 0 interrupt request enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 2"
|
|
base ad:0xB1000200
|
|
width 7.
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "IPCP0,Input Capture Data Register 0"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "IPCP1,Input Capture Data Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "ICS,Input Capture State Control Register"
|
|
bitfld.word 0x00 9. " IEI1 ,Input capture 1 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 8. " IEI0 ,Input capture 0 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 7. " ICP1 ,Input capture 1 interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " ICP0 ,Input capture 0 interrupt request flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ICE1 ,Input capture 1 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ICE0 ,Input capture 0 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--3. " EG1 ,Input capture 1 edge selection" "None,Rising,Falling,Both"
|
|
bitfld.word 0x00 0.--1. " EG0 ,Input capture 0 edge selection" "None,Rising,Falling,Both"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "ICSC,Input Capture State Clear Register"
|
|
bitfld.word 0x00 7. " ICP1C ,Input capture 1 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " ICP0C ,Input capture 0 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " ICE1C ,Input capture 1 interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " ICE0C ,Input capture 0 interrupt request enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "ICSS,Input Capture State Set Register"
|
|
bitfld.word 0x00 5. " ICES1 ,Input capture 1 interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " ICES0 ,Input capture 0 interrupt request enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 3"
|
|
base ad:0xB1000210
|
|
width 7.
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "IPCP0,Input Capture Data Register 0"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "IPCP1,Input Capture Data Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "ICS,Input Capture State Control Register"
|
|
bitfld.word 0x00 9. " IEI1 ,Input capture 1 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 8. " IEI0 ,Input capture 0 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 7. " ICP1 ,Input capture 1 interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " ICP0 ,Input capture 0 interrupt request flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ICE1 ,Input capture 1 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ICE0 ,Input capture 0 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--3. " EG1 ,Input capture 1 edge selection" "None,Rising,Falling,Both"
|
|
bitfld.word 0x00 0.--1. " EG0 ,Input capture 0 edge selection" "None,Rising,Falling,Both"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "ICSC,Input Capture State Clear Register"
|
|
bitfld.word 0x00 7. " ICP1C ,Input capture 1 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " ICP0C ,Input capture 0 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " ICE1C ,Input capture 1 interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " ICE0C ,Input capture 0 interrupt request enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "ICSS,Input Capture State Set Register"
|
|
bitfld.word 0x00 5. " ICES1 ,Input capture 1 interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " ICES0 ,Input capture 0 interrupt request enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 4"
|
|
base ad:0xB1010200
|
|
width 7.
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "IPCP0,Input Capture Data Register 0"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "IPCP1,Input Capture Data Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "ICS,Input Capture State Control Register"
|
|
bitfld.word 0x00 9. " IEI1 ,Input capture 1 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 8. " IEI0 ,Input capture 0 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 7. " ICP1 ,Input capture 1 interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " ICP0 ,Input capture 0 interrupt request flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ICE1 ,Input capture 1 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ICE0 ,Input capture 0 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--3. " EG1 ,Input capture 1 edge selection" "None,Rising,Falling,Both"
|
|
bitfld.word 0x00 0.--1. " EG0 ,Input capture 0 edge selection" "None,Rising,Falling,Both"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "ICSC,Input Capture State Clear Register"
|
|
bitfld.word 0x00 7. " ICP1C ,Input capture 1 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " ICP0C ,Input capture 0 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " ICE1C ,Input capture 1 interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " ICE0C ,Input capture 0 interrupt request enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "ICSS,Input Capture State Set Register"
|
|
bitfld.word 0x00 5. " ICES1 ,Input capture 1 interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " ICES0 ,Input capture 0 interrupt request enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 5"
|
|
base ad:0xB1010210
|
|
width 7.
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "IPCP0,Input Capture Data Register 0"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "IPCP1,Input Capture Data Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "ICS,Input Capture State Control Register"
|
|
bitfld.word 0x00 9. " IEI1 ,Input capture 1 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 8. " IEI0 ,Input capture 0 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 7. " ICP1 ,Input capture 1 interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " ICP0 ,Input capture 0 interrupt request flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ICE1 ,Input capture 1 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ICE0 ,Input capture 0 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--3. " EG1 ,Input capture 1 edge selection" "None,Rising,Falling,Both"
|
|
bitfld.word 0x00 0.--1. " EG0 ,Input capture 0 edge selection" "None,Rising,Falling,Both"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "ICSC,Input Capture State Clear Register"
|
|
bitfld.word 0x00 7. " ICP1C ,Input capture 1 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " ICP0C ,Input capture 0 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " ICE1C ,Input capture 1 interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " ICE0C ,Input capture 0 interrupt request enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "ICSS,Input Capture State Set Register"
|
|
bitfld.word 0x00 5. " ICES1 ,Input capture 1 interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " ICES0 ,Input capture 0 interrupt request enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("MB9DF56?M*")
|
|
tree "Unit 6"
|
|
base ad:0xB1010220
|
|
width 7.
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "IPCP0,Input Capture Data Register 0"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "IPCP1,Input Capture Data Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "ICS,Input Capture State Control Register"
|
|
bitfld.word 0x00 9. " IEI1 ,Input capture 1 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 8. " IEI0 ,Input capture 0 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 7. " ICP1 ,Input capture 1 interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " ICP0 ,Input capture 0 interrupt request flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ICE1 ,Input capture 1 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ICE0 ,Input capture 0 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--3. " EG1 ,Input capture 1 edge selection" "None,Rising,Falling,Both"
|
|
bitfld.word 0x00 0.--1. " EG0 ,Input capture 0 edge selection" "None,Rising,Falling,Both"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "ICSC,Input Capture State Clear Register"
|
|
bitfld.word 0x00 7. " ICP1C ,Input capture 1 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " ICP0C ,Input capture 0 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " ICE1C ,Input capture 1 interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " ICE0C ,Input capture 0 interrupt request enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "ICSS,Input Capture State Set Register"
|
|
bitfld.word 0x00 5. " ICES1 ,Input capture 1 interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " ICES0 ,Input capture 0 interrupt request enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 7"
|
|
base ad:0xB1010230
|
|
width 7.
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "IPCP0,Input Capture Data Register 0"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "ICS,Input Capture State Control Register"
|
|
bitfld.word 0x00 8. " IEI0 ,Input capture 0 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 6. " ICP0 ,Input capture 0 interrupt request flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ICE0 ,Input capture 0 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " EG0 ,Input capture 0 edge selection" "None,Rising,Falling,Both"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "ICSC,Input Capture State Clear Register"
|
|
bitfld.word 0x00 6. " ICP0C ,Input capture 0 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " ICE0C ,Input capture 0 interrupt request enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "ICSS,Input Capture State Set Register"
|
|
bitfld.word 0x00 4. " ICES0 ,Input capture 0 interrupt request enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "Unit 6"
|
|
base ad:0xB1010220
|
|
width 7.
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "IPCP0,Input Capture Data Register 0"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "ICS,Input Capture State Control Register"
|
|
bitfld.word 0x00 8. " IEI0 ,Input capture 0 valid edge indication" "Falling,Rising"
|
|
bitfld.word 0x00 6. " ICP0 ,Input capture 0 interrupt request flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ICE0 ,Input capture 0 interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " EG0 ,Input capture 0 edge selection" "None,Rising,Falling,Both"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "ICSC,Input Capture State Clear Register"
|
|
bitfld.word 0x00 6. " ICP0C ,Input capture 0 interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " ICE0C ,Input capture 0 interrupt request enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "ICSS,Input Capture State Set Register"
|
|
bitfld.word 0x00 4. " ICES0 ,Input capture 0 interrupt request enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "OCU16B (16-bit Output Compare)"
|
|
tree "Unit 0"
|
|
base ad:0xB2000100
|
|
width 8.
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCP0,Output Compare Register 0"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCP1,Output Compare Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "OCS,Compare Control Register"
|
|
bitfld.word 0x00 14. " BTS1 ,Channel 1 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 13. " BTS0 ,Channel 0 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 12. " CMOD ,Output level inversion mode" "0,1"
|
|
bitfld.word 0x00 9. " OTD1 ,Compare output 1 output level" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTD0 ,Compare output 0 output level" "0,1"
|
|
bitfld.word 0x00 7. " IOP1 ,Channel 1 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " IOP0 ,Channel 0 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " IOE1 ,Channel 1 compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOE0 ,Channel 0 compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " BUF1 ,Channel 1 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 2. " BUF0 ,Channel 0 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 1. " CST1 ,Channel 1 compare operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CST0 ,Channel 0 compare operation enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "OCMOD,Compare Mode Control Register"
|
|
bitfld.word 0x00 1. " MOD1 ,Channel 1 compare match mode setting" "Inverted,Set"
|
|
bitfld.word 0x00 0. " MOD0 ,Channel 0 compare match mode setting" "Inverted,Set"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.word 0x00 14. " BTSC1 ,Channel 1 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " BTSC0 ,Channel 0 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 12. " CMODC ,Output level inversion mode clear" "No effect,Clear"
|
|
bitfld.word 0x00 9. " OTDC1 ,Compare output 1 output level clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDC0 ,Compare output 0 output level clear" "No effect,Clear"
|
|
bitfld.word 0x00 7. " IOPC1 ,Channel 1 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " IOPC0 ,Channel 0 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " IOEC1 ,Channel 1 compare match interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOEC0 ,Channel 0 compare match interrupt enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 3. " BUFC1 ,Channel 1 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 2. " BUFC0 ,Channel 0 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 1. " CSTC1 ,Channel 1 compare operation enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSTC0 ,Channel 0 compare operation enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "OCSS,Compare Control Set Register"
|
|
bitfld.word 0x00 14. " BTSS1 ,Channel 1 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 13. " BTSS0 ,Channel 0 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 12. " CMODS ,Output level inversion mode set" "No effect,Set"
|
|
bitfld.word 0x00 9. " OTDS1 ,Compare output 1 output level set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDS0 ,Compare output 0 output level set" "No effect,Set"
|
|
bitfld.word 0x00 5. " IOES1 ,Channel 1 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " IOES0 ,Channel 0 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 3. " BUFS1 ,Channel 1 compare buffer invalidating set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BUFS0 ,Channel 0 compare buffer invalidating set" "No effect,Set"
|
|
bitfld.word 0x00 1. " CSTS1 ,Channel 1 compare operation enable set" "No effect,Set"
|
|
bitfld.word 0x00 0. " CSTS0 ,Channel 0 compare operation enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 1"
|
|
base ad:0xB2000110
|
|
width 8.
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCP0,Output Compare Register 0"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCP1,Output Compare Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "OCS,Compare Control Register"
|
|
bitfld.word 0x00 14. " BTS1 ,Channel 1 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 13. " BTS0 ,Channel 0 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 12. " CMOD ,Output level inversion mode" "0,1"
|
|
bitfld.word 0x00 9. " OTD1 ,Compare output 1 output level" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTD0 ,Compare output 0 output level" "0,1"
|
|
bitfld.word 0x00 7. " IOP1 ,Channel 1 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " IOP0 ,Channel 0 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " IOE1 ,Channel 1 compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOE0 ,Channel 0 compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " BUF1 ,Channel 1 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 2. " BUF0 ,Channel 0 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 1. " CST1 ,Channel 1 compare operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CST0 ,Channel 0 compare operation enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "OCMOD,Compare Mode Control Register"
|
|
bitfld.word 0x00 1. " MOD1 ,Channel 1 compare match mode setting" "Inverted,Set"
|
|
bitfld.word 0x00 0. " MOD0 ,Channel 0 compare match mode setting" "Inverted,Set"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.word 0x00 14. " BTSC1 ,Channel 1 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " BTSC0 ,Channel 0 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 12. " CMODC ,Output level inversion mode clear" "No effect,Clear"
|
|
bitfld.word 0x00 9. " OTDC1 ,Compare output 1 output level clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDC0 ,Compare output 0 output level clear" "No effect,Clear"
|
|
bitfld.word 0x00 7. " IOPC1 ,Channel 1 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " IOPC0 ,Channel 0 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " IOEC1 ,Channel 1 compare match interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOEC0 ,Channel 0 compare match interrupt enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 3. " BUFC1 ,Channel 1 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 2. " BUFC0 ,Channel 0 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 1. " CSTC1 ,Channel 1 compare operation enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSTC0 ,Channel 0 compare operation enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "OCSS,Compare Control Set Register"
|
|
bitfld.word 0x00 14. " BTSS1 ,Channel 1 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 13. " BTSS0 ,Channel 0 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 12. " CMODS ,Output level inversion mode set" "No effect,Set"
|
|
bitfld.word 0x00 9. " OTDS1 ,Compare output 1 output level set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDS0 ,Compare output 0 output level set" "No effect,Set"
|
|
bitfld.word 0x00 5. " IOES1 ,Channel 1 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " IOES0 ,Channel 0 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 3. " BUFS1 ,Channel 1 compare buffer invalidating set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BUFS0 ,Channel 0 compare buffer invalidating set" "No effect,Set"
|
|
bitfld.word 0x00 1. " CSTS1 ,Channel 1 compare operation enable set" "No effect,Set"
|
|
bitfld.word 0x00 0. " CSTS0 ,Channel 0 compare operation enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 2"
|
|
base ad:0xB2000120
|
|
width 8.
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCP0,Output Compare Register 0"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCP1,Output Compare Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "OCS,Compare Control Register"
|
|
bitfld.word 0x00 14. " BTS1 ,Channel 1 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 13. " BTS0 ,Channel 0 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 12. " CMOD ,Output level inversion mode" "0,1"
|
|
bitfld.word 0x00 9. " OTD1 ,Compare output 1 output level" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTD0 ,Compare output 0 output level" "0,1"
|
|
bitfld.word 0x00 7. " IOP1 ,Channel 1 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " IOP0 ,Channel 0 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " IOE1 ,Channel 1 compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOE0 ,Channel 0 compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " BUF1 ,Channel 1 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 2. " BUF0 ,Channel 0 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 1. " CST1 ,Channel 1 compare operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CST0 ,Channel 0 compare operation enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "OCMOD,Compare Mode Control Register"
|
|
bitfld.word 0x00 1. " MOD1 ,Channel 1 compare match mode setting" "Inverted,Set"
|
|
bitfld.word 0x00 0. " MOD0 ,Channel 0 compare match mode setting" "Inverted,Set"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.word 0x00 14. " BTSC1 ,Channel 1 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " BTSC0 ,Channel 0 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 12. " CMODC ,Output level inversion mode clear" "No effect,Clear"
|
|
bitfld.word 0x00 9. " OTDC1 ,Compare output 1 output level clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDC0 ,Compare output 0 output level clear" "No effect,Clear"
|
|
bitfld.word 0x00 7. " IOPC1 ,Channel 1 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " IOPC0 ,Channel 0 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " IOEC1 ,Channel 1 compare match interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOEC0 ,Channel 0 compare match interrupt enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 3. " BUFC1 ,Channel 1 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 2. " BUFC0 ,Channel 0 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 1. " CSTC1 ,Channel 1 compare operation enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSTC0 ,Channel 0 compare operation enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "OCSS,Compare Control Set Register"
|
|
bitfld.word 0x00 14. " BTSS1 ,Channel 1 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 13. " BTSS0 ,Channel 0 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 12. " CMODS ,Output level inversion mode set" "No effect,Set"
|
|
bitfld.word 0x00 9. " OTDS1 ,Compare output 1 output level set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDS0 ,Compare output 0 output level set" "No effect,Set"
|
|
bitfld.word 0x00 5. " IOES1 ,Channel 1 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " IOES0 ,Channel 0 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 3. " BUFS1 ,Channel 1 compare buffer invalidating set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BUFS0 ,Channel 0 compare buffer invalidating set" "No effect,Set"
|
|
bitfld.word 0x00 1. " CSTS1 ,Channel 1 compare operation enable set" "No effect,Set"
|
|
bitfld.word 0x00 0. " CSTS0 ,Channel 0 compare operation enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 3"
|
|
base ad:0xB1000100
|
|
width 8.
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCP0,Output Compare Register 0"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCP1,Output Compare Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "OCS,Compare Control Register"
|
|
bitfld.word 0x00 14. " BTS1 ,Channel 1 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 13. " BTS0 ,Channel 0 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 12. " CMOD ,Output level inversion mode" "0,1"
|
|
bitfld.word 0x00 9. " OTD1 ,Compare output 1 output level" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTD0 ,Compare output 0 output level" "0,1"
|
|
bitfld.word 0x00 7. " IOP1 ,Channel 1 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " IOP0 ,Channel 0 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " IOE1 ,Channel 1 compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOE0 ,Channel 0 compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " BUF1 ,Channel 1 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 2. " BUF0 ,Channel 0 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 1. " CST1 ,Channel 1 compare operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CST0 ,Channel 0 compare operation enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "OCMOD,Compare Mode Control Register"
|
|
bitfld.word 0x00 1. " MOD1 ,Channel 1 compare match mode setting" "Inverted,Set"
|
|
bitfld.word 0x00 0. " MOD0 ,Channel 0 compare match mode setting" "Inverted,Set"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.word 0x00 14. " BTSC1 ,Channel 1 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " BTSC0 ,Channel 0 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 12. " CMODC ,Output level inversion mode clear" "No effect,Clear"
|
|
bitfld.word 0x00 9. " OTDC1 ,Compare output 1 output level clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDC0 ,Compare output 0 output level clear" "No effect,Clear"
|
|
bitfld.word 0x00 7. " IOPC1 ,Channel 1 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " IOPC0 ,Channel 0 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " IOEC1 ,Channel 1 compare match interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOEC0 ,Channel 0 compare match interrupt enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 3. " BUFC1 ,Channel 1 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 2. " BUFC0 ,Channel 0 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 1. " CSTC1 ,Channel 1 compare operation enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSTC0 ,Channel 0 compare operation enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "OCSS,Compare Control Set Register"
|
|
bitfld.word 0x00 14. " BTSS1 ,Channel 1 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 13. " BTSS0 ,Channel 0 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 12. " CMODS ,Output level inversion mode set" "No effect,Set"
|
|
bitfld.word 0x00 9. " OTDS1 ,Compare output 1 output level set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDS0 ,Compare output 0 output level set" "No effect,Set"
|
|
bitfld.word 0x00 5. " IOES1 ,Channel 1 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " IOES0 ,Channel 0 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 3. " BUFS1 ,Channel 1 compare buffer invalidating set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BUFS0 ,Channel 0 compare buffer invalidating set" "No effect,Set"
|
|
bitfld.word 0x00 1. " CSTS1 ,Channel 1 compare operation enable set" "No effect,Set"
|
|
bitfld.word 0x00 0. " CSTS0 ,Channel 0 compare operation enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 4"
|
|
base ad:0xB1000110
|
|
width 8.
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCP0,Output Compare Register 0"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCP1,Output Compare Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "OCS,Compare Control Register"
|
|
bitfld.word 0x00 14. " BTS1 ,Channel 1 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 13. " BTS0 ,Channel 0 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 12. " CMOD ,Output level inversion mode" "0,1"
|
|
bitfld.word 0x00 9. " OTD1 ,Compare output 1 output level" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTD0 ,Compare output 0 output level" "0,1"
|
|
bitfld.word 0x00 7. " IOP1 ,Channel 1 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " IOP0 ,Channel 0 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " IOE1 ,Channel 1 compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOE0 ,Channel 0 compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " BUF1 ,Channel 1 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 2. " BUF0 ,Channel 0 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 1. " CST1 ,Channel 1 compare operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CST0 ,Channel 0 compare operation enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "OCMOD,Compare Mode Control Register"
|
|
bitfld.word 0x00 1. " MOD1 ,Channel 1 compare match mode setting" "Inverted,Set"
|
|
bitfld.word 0x00 0. " MOD0 ,Channel 0 compare match mode setting" "Inverted,Set"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.word 0x00 14. " BTSC1 ,Channel 1 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " BTSC0 ,Channel 0 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 12. " CMODC ,Output level inversion mode clear" "No effect,Clear"
|
|
bitfld.word 0x00 9. " OTDC1 ,Compare output 1 output level clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDC0 ,Compare output 0 output level clear" "No effect,Clear"
|
|
bitfld.word 0x00 7. " IOPC1 ,Channel 1 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " IOPC0 ,Channel 0 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " IOEC1 ,Channel 1 compare match interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOEC0 ,Channel 0 compare match interrupt enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 3. " BUFC1 ,Channel 1 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 2. " BUFC0 ,Channel 0 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 1. " CSTC1 ,Channel 1 compare operation enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSTC0 ,Channel 0 compare operation enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "OCSS,Compare Control Set Register"
|
|
bitfld.word 0x00 14. " BTSS1 ,Channel 1 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 13. " BTSS0 ,Channel 0 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 12. " CMODS ,Output level inversion mode set" "No effect,Set"
|
|
bitfld.word 0x00 9. " OTDS1 ,Compare output 1 output level set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDS0 ,Compare output 0 output level set" "No effect,Set"
|
|
bitfld.word 0x00 5. " IOES1 ,Channel 1 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " IOES0 ,Channel 0 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 3. " BUFS1 ,Channel 1 compare buffer invalidating set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BUFS0 ,Channel 0 compare buffer invalidating set" "No effect,Set"
|
|
bitfld.word 0x00 1. " CSTS1 ,Channel 1 compare operation enable set" "No effect,Set"
|
|
bitfld.word 0x00 0. " CSTS0 ,Channel 0 compare operation enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 5"
|
|
base ad:0xB1000120
|
|
width 8.
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCP0,Output Compare Register 0"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCP1,Output Compare Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "OCS,Compare Control Register"
|
|
bitfld.word 0x00 14. " BTS1 ,Channel 1 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 13. " BTS0 ,Channel 0 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 12. " CMOD ,Output level inversion mode" "0,1"
|
|
bitfld.word 0x00 9. " OTD1 ,Compare output 1 output level" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTD0 ,Compare output 0 output level" "0,1"
|
|
bitfld.word 0x00 7. " IOP1 ,Channel 1 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " IOP0 ,Channel 0 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " IOE1 ,Channel 1 compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOE0 ,Channel 0 compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " BUF1 ,Channel 1 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 2. " BUF0 ,Channel 0 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 1. " CST1 ,Channel 1 compare operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CST0 ,Channel 0 compare operation enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "OCMOD,Compare Mode Control Register"
|
|
bitfld.word 0x00 1. " MOD1 ,Channel 1 compare match mode setting" "Inverted,Set"
|
|
bitfld.word 0x00 0. " MOD0 ,Channel 0 compare match mode setting" "Inverted,Set"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.word 0x00 14. " BTSC1 ,Channel 1 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " BTSC0 ,Channel 0 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 12. " CMODC ,Output level inversion mode clear" "No effect,Clear"
|
|
bitfld.word 0x00 9. " OTDC1 ,Compare output 1 output level clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDC0 ,Compare output 0 output level clear" "No effect,Clear"
|
|
bitfld.word 0x00 7. " IOPC1 ,Channel 1 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " IOPC0 ,Channel 0 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " IOEC1 ,Channel 1 compare match interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOEC0 ,Channel 0 compare match interrupt enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 3. " BUFC1 ,Channel 1 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 2. " BUFC0 ,Channel 0 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 1. " CSTC1 ,Channel 1 compare operation enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSTC0 ,Channel 0 compare operation enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "OCSS,Compare Control Set Register"
|
|
bitfld.word 0x00 14. " BTSS1 ,Channel 1 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 13. " BTSS0 ,Channel 0 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 12. " CMODS ,Output level inversion mode set" "No effect,Set"
|
|
bitfld.word 0x00 9. " OTDS1 ,Compare output 1 output level set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDS0 ,Compare output 0 output level set" "No effect,Set"
|
|
bitfld.word 0x00 5. " IOES1 ,Channel 1 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " IOES0 ,Channel 0 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 3. " BUFS1 ,Channel 1 compare buffer invalidating set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BUFS0 ,Channel 0 compare buffer invalidating set" "No effect,Set"
|
|
bitfld.word 0x00 1. " CSTS1 ,Channel 1 compare operation enable set" "No effect,Set"
|
|
bitfld.word 0x00 0. " CSTS0 ,Channel 0 compare operation enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("MB9DF56?M*")
|
|
tree "Unit 6"
|
|
base ad:0xB1010100
|
|
width 8.
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCP0,Output Compare Register 0"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCP1,Output Compare Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "OCS,Compare Control Register"
|
|
bitfld.word 0x00 14. " BTS1 ,Channel 1 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 13. " BTS0 ,Channel 0 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 12. " CMOD ,Output level inversion mode" "0,1"
|
|
bitfld.word 0x00 9. " OTD1 ,Compare output 1 output level" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTD0 ,Compare output 0 output level" "0,1"
|
|
bitfld.word 0x00 7. " IOP1 ,Channel 1 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " IOP0 ,Channel 0 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " IOE1 ,Channel 1 compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOE0 ,Channel 0 compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " BUF1 ,Channel 1 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 2. " BUF0 ,Channel 0 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 1. " CST1 ,Channel 1 compare operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CST0 ,Channel 0 compare operation enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "OCMOD,Compare Mode Control Register"
|
|
bitfld.word 0x00 1. " MOD1 ,Channel 1 compare match mode setting" "Inverted,Set"
|
|
bitfld.word 0x00 0. " MOD0 ,Channel 0 compare match mode setting" "Inverted,Set"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.word 0x00 14. " BTSC1 ,Channel 1 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " BTSC0 ,Channel 0 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 12. " CMODC ,Output level inversion mode clear" "No effect,Clear"
|
|
bitfld.word 0x00 9. " OTDC1 ,Compare output 1 output level clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDC0 ,Compare output 0 output level clear" "No effect,Clear"
|
|
bitfld.word 0x00 7. " IOPC1 ,Channel 1 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " IOPC0 ,Channel 0 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " IOEC1 ,Channel 1 compare match interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOEC0 ,Channel 0 compare match interrupt enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 3. " BUFC1 ,Channel 1 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 2. " BUFC0 ,Channel 0 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 1. " CSTC1 ,Channel 1 compare operation enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSTC0 ,Channel 0 compare operation enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "OCSS,Compare Control Set Register"
|
|
bitfld.word 0x00 14. " BTSS1 ,Channel 1 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 13. " BTSS0 ,Channel 0 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 12. " CMODS ,Output level inversion mode set" "No effect,Set"
|
|
bitfld.word 0x00 9. " OTDS1 ,Compare output 1 output level set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDS0 ,Compare output 0 output level set" "No effect,Set"
|
|
bitfld.word 0x00 5. " IOES1 ,Channel 1 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " IOES0 ,Channel 0 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 3. " BUFS1 ,Channel 1 compare buffer invalidating set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BUFS0 ,Channel 0 compare buffer invalidating set" "No effect,Set"
|
|
bitfld.word 0x00 1. " CSTS1 ,Channel 1 compare operation enable set" "No effect,Set"
|
|
bitfld.word 0x00 0. " CSTS0 ,Channel 0 compare operation enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 7"
|
|
base ad:0xB1010110
|
|
width 8.
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCP0,Output Compare Register 0"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCP1,Output Compare Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "OCS,Compare Control Register"
|
|
bitfld.word 0x00 14. " BTS1 ,Channel 1 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 13. " BTS0 ,Channel 0 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 12. " CMOD ,Output level inversion mode" "0,1"
|
|
bitfld.word 0x00 9. " OTD1 ,Compare output 1 output level" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTD0 ,Compare output 0 output level" "0,1"
|
|
bitfld.word 0x00 7. " IOP1 ,Channel 1 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " IOP0 ,Channel 0 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " IOE1 ,Channel 1 compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOE0 ,Channel 0 compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " BUF1 ,Channel 1 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 2. " BUF0 ,Channel 0 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 1. " CST1 ,Channel 1 compare operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CST0 ,Channel 0 compare operation enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "OCMOD,Compare Mode Control Register"
|
|
bitfld.word 0x00 1. " MOD1 ,Channel 1 compare match mode setting" "Inverted,Set"
|
|
bitfld.word 0x00 0. " MOD0 ,Channel 0 compare match mode setting" "Inverted,Set"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.word 0x00 14. " BTSC1 ,Channel 1 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " BTSC0 ,Channel 0 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 12. " CMODC ,Output level inversion mode clear" "No effect,Clear"
|
|
bitfld.word 0x00 9. " OTDC1 ,Compare output 1 output level clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDC0 ,Compare output 0 output level clear" "No effect,Clear"
|
|
bitfld.word 0x00 7. " IOPC1 ,Channel 1 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " IOPC0 ,Channel 0 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " IOEC1 ,Channel 1 compare match interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOEC0 ,Channel 0 compare match interrupt enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 3. " BUFC1 ,Channel 1 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 2. " BUFC0 ,Channel 0 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 1. " CSTC1 ,Channel 1 compare operation enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSTC0 ,Channel 0 compare operation enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "OCSS,Compare Control Set Register"
|
|
bitfld.word 0x00 14. " BTSS1 ,Channel 1 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 13. " BTSS0 ,Channel 0 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 12. " CMODS ,Output level inversion mode set" "No effect,Set"
|
|
bitfld.word 0x00 9. " OTDS1 ,Compare output 1 output level set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDS0 ,Compare output 0 output level set" "No effect,Set"
|
|
bitfld.word 0x00 5. " IOES1 ,Channel 1 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " IOES0 ,Channel 0 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 3. " BUFS1 ,Channel 1 compare buffer invalidating set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BUFS0 ,Channel 0 compare buffer invalidating set" "No effect,Set"
|
|
bitfld.word 0x00 1. " CSTS1 ,Channel 1 compare operation enable set" "No effect,Set"
|
|
bitfld.word 0x00 0. " CSTS0 ,Channel 0 compare operation enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 8"
|
|
base ad:0xB1010120
|
|
width 8.
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCP0,Output Compare Register 0"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCP1,Output Compare Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "OCS,Compare Control Register"
|
|
bitfld.word 0x00 14. " BTS1 ,Channel 1 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 13. " BTS0 ,Channel 0 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 12. " CMOD ,Output level inversion mode" "0,1"
|
|
bitfld.word 0x00 9. " OTD1 ,Compare output 1 output level" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTD0 ,Compare output 0 output level" "0,1"
|
|
bitfld.word 0x00 7. " IOP1 ,Channel 1 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " IOP0 ,Channel 0 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " IOE1 ,Channel 1 compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOE0 ,Channel 0 compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " BUF1 ,Channel 1 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 2. " BUF0 ,Channel 0 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 1. " CST1 ,Channel 1 compare operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CST0 ,Channel 0 compare operation enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "OCMOD,Compare Mode Control Register"
|
|
bitfld.word 0x00 1. " MOD1 ,Channel 1 compare match mode setting" "Inverted,Set"
|
|
bitfld.word 0x00 0. " MOD0 ,Channel 0 compare match mode setting" "Inverted,Set"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.word 0x00 14. " BTSC1 ,Channel 1 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " BTSC0 ,Channel 0 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 12. " CMODC ,Output level inversion mode clear" "No effect,Clear"
|
|
bitfld.word 0x00 9. " OTDC1 ,Compare output 1 output level clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDC0 ,Compare output 0 output level clear" "No effect,Clear"
|
|
bitfld.word 0x00 7. " IOPC1 ,Channel 1 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " IOPC0 ,Channel 0 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " IOEC1 ,Channel 1 compare match interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOEC0 ,Channel 0 compare match interrupt enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 3. " BUFC1 ,Channel 1 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 2. " BUFC0 ,Channel 0 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 1. " CSTC1 ,Channel 1 compare operation enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSTC0 ,Channel 0 compare operation enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "OCSS,Compare Control Set Register"
|
|
bitfld.word 0x00 14. " BTSS1 ,Channel 1 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 13. " BTSS0 ,Channel 0 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 12. " CMODS ,Output level inversion mode set" "No effect,Set"
|
|
bitfld.word 0x00 9. " OTDS1 ,Compare output 1 output level set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDS0 ,Compare output 0 output level set" "No effect,Set"
|
|
bitfld.word 0x00 5. " IOES1 ,Channel 1 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " IOES0 ,Channel 0 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 3. " BUFS1 ,Channel 1 compare buffer invalidating set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BUFS0 ,Channel 0 compare buffer invalidating set" "No effect,Set"
|
|
bitfld.word 0x00 1. " CSTS1 ,Channel 1 compare operation enable set" "No effect,Set"
|
|
bitfld.word 0x00 0. " CSTS0 ,Channel 0 compare operation enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "Unit 9"
|
|
base ad:0xB1010130
|
|
width 8.
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCP0,Output Compare Register 0"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCP1,Output Compare Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "OCS,Compare Control Register"
|
|
bitfld.word 0x00 14. " BTS1 ,Channel 1 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 13. " BTS0 ,Channel 0 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 12. " CMOD ,Output level inversion mode" "0,1"
|
|
bitfld.word 0x00 9. " OTD1 ,Compare output 1 output level" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTD0 ,Compare output 0 output level" "0,1"
|
|
bitfld.word 0x00 7. " IOP1 ,Channel 1 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " IOP0 ,Channel 0 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " IOE1 ,Channel 1 compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOE0 ,Channel 0 compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " BUF1 ,Channel 1 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 2. " BUF0 ,Channel 0 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 1. " CST1 ,Channel 1 compare operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CST0 ,Channel 0 compare operation enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "OCMOD,Compare Mode Control Register"
|
|
bitfld.word 0x00 1. " MOD1 ,Channel 1 compare match mode setting" "Inverted,Set"
|
|
bitfld.word 0x00 0. " MOD0 ,Channel 0 compare match mode setting" "Inverted,Set"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.word 0x00 14. " BTSC1 ,Channel 1 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " BTSC0 ,Channel 0 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 12. " CMODC ,Output level inversion mode clear" "No effect,Clear"
|
|
bitfld.word 0x00 9. " OTDC1 ,Compare output 1 output level clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDC0 ,Compare output 0 output level clear" "No effect,Clear"
|
|
bitfld.word 0x00 7. " IOPC1 ,Channel 1 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " IOPC0 ,Channel 0 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " IOEC1 ,Channel 1 compare match interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOEC0 ,Channel 0 compare match interrupt enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 3. " BUFC1 ,Channel 1 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 2. " BUFC0 ,Channel 0 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 1. " CSTC1 ,Channel 1 compare operation enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSTC0 ,Channel 0 compare operation enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "OCSS,Compare Control Set Register"
|
|
bitfld.word 0x00 14. " BTSS1 ,Channel 1 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 13. " BTSS0 ,Channel 0 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 12. " CMODS ,Output level inversion mode set" "No effect,Set"
|
|
bitfld.word 0x00 9. " OTDS1 ,Compare output 1 output level set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDS0 ,Compare output 0 output level set" "No effect,Set"
|
|
bitfld.word 0x00 5. " IOES1 ,Channel 1 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " IOES0 ,Channel 0 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 3. " BUFS1 ,Channel 1 compare buffer invalidating set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BUFS0 ,Channel 0 compare buffer invalidating set" "No effect,Set"
|
|
bitfld.word 0x00 1. " CSTS1 ,Channel 1 compare operation enable set" "No effect,Set"
|
|
bitfld.word 0x00 0. " CSTS0 ,Channel 0 compare operation enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 10"
|
|
base ad:0xB1010140
|
|
width 8.
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCP0,Output Compare Register 0"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCP1,Output Compare Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "OCS,Compare Control Register"
|
|
bitfld.word 0x00 14. " BTS1 ,Channel 1 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 13. " BTS0 ,Channel 0 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 12. " CMOD ,Output level inversion mode" "0,1"
|
|
bitfld.word 0x00 9. " OTD1 ,Compare output 1 output level" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTD0 ,Compare output 0 output level" "0,1"
|
|
bitfld.word 0x00 7. " IOP1 ,Channel 1 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " IOP0 ,Channel 0 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " IOE1 ,Channel 1 compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOE0 ,Channel 0 compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " BUF1 ,Channel 1 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 2. " BUF0 ,Channel 0 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 1. " CST1 ,Channel 1 compare operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CST0 ,Channel 0 compare operation enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "OCMOD,Compare Mode Control Register"
|
|
bitfld.word 0x00 1. " MOD1 ,Channel 1 compare match mode setting" "Inverted,Set"
|
|
bitfld.word 0x00 0. " MOD0 ,Channel 0 compare match mode setting" "Inverted,Set"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.word 0x00 14. " BTSC1 ,Channel 1 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " BTSC0 ,Channel 0 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 12. " CMODC ,Output level inversion mode clear" "No effect,Clear"
|
|
bitfld.word 0x00 9. " OTDC1 ,Compare output 1 output level clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDC0 ,Compare output 0 output level clear" "No effect,Clear"
|
|
bitfld.word 0x00 7. " IOPC1 ,Channel 1 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " IOPC0 ,Channel 0 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " IOEC1 ,Channel 1 compare match interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOEC0 ,Channel 0 compare match interrupt enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 3. " BUFC1 ,Channel 1 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 2. " BUFC0 ,Channel 0 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 1. " CSTC1 ,Channel 1 compare operation enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSTC0 ,Channel 0 compare operation enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "OCSS,Compare Control Set Register"
|
|
bitfld.word 0x00 14. " BTSS1 ,Channel 1 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 13. " BTSS0 ,Channel 0 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 12. " CMODS ,Output level inversion mode set" "No effect,Set"
|
|
bitfld.word 0x00 9. " OTDS1 ,Compare output 1 output level set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDS0 ,Compare output 0 output level set" "No effect,Set"
|
|
bitfld.word 0x00 5. " IOES1 ,Channel 1 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " IOES0 ,Channel 0 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 3. " BUFS1 ,Channel 1 compare buffer invalidating set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BUFS0 ,Channel 0 compare buffer invalidating set" "No effect,Set"
|
|
bitfld.word 0x00 1. " CSTS1 ,Channel 1 compare operation enable set" "No effect,Set"
|
|
bitfld.word 0x00 0. " CSTS0 ,Channel 0 compare operation enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 11"
|
|
base ad:0xB1010150
|
|
width 8.
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
rgroup.word 0x02++0x01
|
|
line.word 0x00 "OCCP0,Output Compare Register 0"
|
|
wgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "OCCP1,Output Compare Register 1"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "OCS,Compare Control Register"
|
|
bitfld.word 0x00 14. " BTS1 ,Channel 1 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 13. " BTS0 ,Channel 0 buffer transfer selection" "0 detected,Compare clear match occurred"
|
|
bitfld.word 0x00 12. " CMOD ,Output level inversion mode" "0,1"
|
|
bitfld.word 0x00 9. " OTD1 ,Compare output 1 output level" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTD0 ,Compare output 0 output level" "0,1"
|
|
bitfld.word 0x00 7. " IOP1 ,Channel 1 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " IOP0 ,Channel 0 compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " IOE1 ,Channel 1 compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOE0 ,Channel 0 compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " BUF1 ,Channel 1 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 2. " BUF0 ,Channel 0 compare buffer invalidating bit" "Validated,Invalidated"
|
|
bitfld.word 0x00 1. " CST1 ,Channel 1 compare operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CST0 ,Channel 0 compare operation enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "OCMOD,Compare Mode Control Register"
|
|
bitfld.word 0x00 1. " MOD1 ,Channel 1 compare match mode setting" "Inverted,Set"
|
|
bitfld.word 0x00 0. " MOD0 ,Channel 0 compare match mode setting" "Inverted,Set"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.word 0x00 14. " BTSC1 ,Channel 1 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " BTSC0 ,Channel 0 buffer transfer selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 12. " CMODC ,Output level inversion mode clear" "No effect,Clear"
|
|
bitfld.word 0x00 9. " OTDC1 ,Compare output 1 output level clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDC0 ,Compare output 0 output level clear" "No effect,Clear"
|
|
bitfld.word 0x00 7. " IOPC1 ,Channel 1 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " IOPC0 ,Channel 0 compare match interrupt flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " IOEC1 ,Channel 1 compare match interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IOEC0 ,Channel 0 compare match interrupt enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 3. " BUFC1 ,Channel 1 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 2. " BUFC0 ,Channel 0 compare buffer invalidating clear" "No effect,Clear"
|
|
bitfld.word 0x00 1. " CSTC1 ,Channel 1 compare operation enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSTC0 ,Channel 0 compare operation enable clear" "No effect,Clear"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "OCSS,Compare Control Set Register"
|
|
bitfld.word 0x00 14. " BTSS1 ,Channel 1 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 13. " BTSS0 ,Channel 0 buffer transfer selection set" "No effect,Set"
|
|
bitfld.word 0x00 12. " CMODS ,Output level inversion mode set" "No effect,Set"
|
|
bitfld.word 0x00 9. " OTDS1 ,Compare output 1 output level set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OTDS0 ,Compare output 0 output level set" "No effect,Set"
|
|
bitfld.word 0x00 5. " IOES1 ,Channel 1 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 4. " IOES0 ,Channel 0 compare match interrupt enable set" "No effect,Set"
|
|
bitfld.word 0x00 3. " BUFS1 ,Channel 1 compare buffer invalidating set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 2. " BUFS0 ,Channel 0 compare buffer invalidating set" "No effect,Set"
|
|
bitfld.word 0x00 1. " CSTS1 ,Channel 1 compare operation enable set" "No effect,Set"
|
|
bitfld.word 0x00 0. " CSTS0 ,Channel 0 compare operation enable set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "ADCI (12-bit A/D Converter Interface)"
|
|
base ad:0xB1010400
|
|
width 10.
|
|
rgroup.word 0x1B2++0x01
|
|
line.word 0x00 "ADCS,A/D Control Status Register"
|
|
bitfld.word 0x00 15. " BUSY ,A/D conversion busy" "Stopped,In operation"
|
|
rgroup.byte 0x1B1++0x00
|
|
line.byte 0x00 "ADCH,A/D Channel Status Register"
|
|
bitfld.byte 0x00 0.--4. " CH ,Analog channel" "CH.0,CH.1,CH.2,CH.3,CH.4,CH.5,CH.6,CH.7,CH.8,CH.9,CH.10,CH.11,CH.12,CH.13,CH.14,CH.15,CH.16,CH.17,CH.18,CH.19,CH.20,CH.21,CH.22,CH.23,CH.24,CH.25,CH.26,CH.27,CH.28,CH.29,CH.30,CH.31"
|
|
group.byte 0x1B0++0x00
|
|
line.byte 0x00 "ADMD,A/D Mode Setting Register"
|
|
bitfld.byte 0x00 7. " STPCEN ,Sampling time setting per channel enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " CT ,Compare time setting" "28,42,56,112"
|
|
bitfld.byte 0x00 0.--1. " ST ,Sampling time setting" "12,18,24,48"
|
|
group.byte 0x1B7++0x00
|
|
line.byte 0x00 "ADSTPCS0,A/D Sampling Time Setting Per Channel Register 0"
|
|
bitfld.byte 0x00 6.--7. " STCH3 ,Channel 3 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 4.--5. " STCH2 ,Channel 2 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 2.--3. " STCH1 ,Channel 1 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 0.--1. " STCH0 ,Channel 0 sampling time setting" "12,18,24,482"
|
|
group.byte 0x1B6++0x00
|
|
line.byte 0x00 "ADSTPCS1,A/D Sampling Time Setting Per Channel Register 1"
|
|
bitfld.byte 0x00 6.--7. " STCH7 ,Channel 7 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 4.--5. " STCH6 ,Channel 6 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 2.--3. " STCH5 ,Channel 5 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 0.--1. " STCH4 ,Channel 4 sampling time setting" "12,18,24,482"
|
|
group.byte 0x1B5++0x00
|
|
line.byte 0x00 "ADSTPCS2,A/D Sampling Time Setting Per Channel Register 2"
|
|
bitfld.byte 0x00 6.--7. " STCH11 ,Channel 11 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 4.--5. " STCH10 ,Channel 10 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 2.--3. " STCH9 ,Channel 9 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 0.--1. " STCH8 ,Channel 8 sampling time setting" "12,18,24,482"
|
|
group.byte 0x1B4++0x00
|
|
line.byte 0x00 "ADSTPCS3,A/D Sampling Time Setting Per Channel Register 3"
|
|
bitfld.byte 0x00 6.--7. " STCH15 ,Channel 15 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 4.--5. " STCH14 ,Channel 14 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 2.--3. " STCH13 ,Channel 13 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 0.--1. " STCH12 ,Channel 12 sampling time setting" "12,18,24,482"
|
|
group.byte 0x1BB++0x00
|
|
line.byte 0x00 "ADSTPCS4,A/D Sampling Time Setting Per Channel Register 4"
|
|
bitfld.byte 0x00 6.--7. " STCH19 ,Channel 19 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 4.--5. " STCH18 ,Channel 18 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 2.--3. " STCH17 ,Channel 17 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 0.--1. " STCH16 ,Channel 16 sampling time setting" "12,18,24,482"
|
|
group.byte 0x1BA++0x00
|
|
line.byte 0x00 "ADSTPCS5,A/D Sampling Time Setting Per Channel Register 5"
|
|
bitfld.byte 0x00 6.--7. " STCH23 ,Channel 23 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 4.--5. " STCH22 ,Channel 22 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 2.--3. " STCH21 ,Channel 21 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 0.--1. " STCH20 ,Channel 20 sampling time setting" "12,18,24,482"
|
|
group.byte 0x1B9++0x00
|
|
line.byte 0x00 "ADSTPCS6,A/D Sampling Time Setting Per Channel Register 6"
|
|
bitfld.byte 0x00 6.--7. " STCH27 ,Channel 27 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 4.--5. " STCH26 ,Channel 26 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 2.--3. " STCH25 ,Channel 25 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 0.--1. " STCH24 ,Channel 24 sampling time setting" "12,18,24,482"
|
|
group.byte 0x1B8++0x00
|
|
line.byte 0x00 "ADSTPCS7,A/D Sampling Time Setting Per Channel Register 7"
|
|
bitfld.byte 0x00 6.--7. " STCH31 ,Channel 31 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 4.--5. " STCH30 ,Channel 30 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 2.--3. " STCH29 ,Channel 29 sampling time setting" "12,18,24,482"
|
|
bitfld.byte 0x00 0.--1. " STCH28 ,Channel 28 sampling time setting" "12,18,24,482"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADAC (12-bit A/D converter Activation Compare)"
|
|
base ad:0xB1010400
|
|
width 11.
|
|
group.long 0x02C04++0x03
|
|
line.long 0x00 "ADER,Analog Input Control Register"
|
|
bitfld.long 0x00 31. " ADE31 ,Analog input 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ADE30 ,Analog input 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ADE29 ,Analog input 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ADE28 ,Analog input 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ADE27 ,Analog input 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ADE26 ,Analog input 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " ADE25 ,Analog input 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ADE24 ,Analog input 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ADE23 ,Analog input 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ADE22 ,Analog input 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ADE21 ,Analog input 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ADE20 ,Analog input 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ADE19 ,Analog input 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ADE18 ,Analog input 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ADE17 ,Analog input 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ADE16 ,Analog input 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ADE15 ,Analog input 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ADE14 ,Analog input 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ADE13 ,Analog input 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ADE12 ,Analog input 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADE11 ,Analog input 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ADE10 ,Analog input 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ADE9 ,Analog input 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ADE8 ,Analog input 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADE7 ,Analog input 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ADE6 ,Analog input 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ADE5 ,Analog input 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ADE4 ,Analog input 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADE3 ,Analog input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ADE2 ,Analog input 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ADE1 ,Analog input 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADE0 ,Analog input 0 enable" "Disabled,Enabled"
|
|
wgroup.byte 0x07++0x00
|
|
line.byte 0x00 "ADTSS,A/D Software Activation Register"
|
|
bitfld.byte 0x00 0. " START ,A/D conversion activation" "No effect,Activate"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADTSE,A/D Software Activation Channel Selection Register"
|
|
bitfld.long 0x00 31. " ADT31 ,Software activation channel 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ADT30 ,Software activation channel 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ADT29 ,Software activation channel 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ADT28 ,Software activation channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ADT27 ,Software activation channel 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ADT26 ,Software activation channel 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " ADT25 ,Software activation channel 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ADT24 ,Software activation channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ADT23 ,Software activation channel 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ADT22 ,Software activation channel 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ADT21 ,Software activation channel 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ADT20 ,Software activation channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ADT19 ,Software activation channel 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ADT18 ,Software activation channel 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ADT17 ,Software activation channel 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ADT16 ,Software activation channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ADT15 ,Software activation channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ADT14 ,Software activation channel 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ADT13 ,Software activation channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ADT12 ,Software activation channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADT11 ,Software activation channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ADT10 ,Software activation channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ADT9 ,Software activation channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ADT8 ,Software activation channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADT7 ,Software activation channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ADT6 ,Software activation channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ADT5 ,Software activation channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ADT4 ,Software activation channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADT3 ,Software activation channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ADT2 ,Software activation channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ADT1 ,Software activation channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADT0 ,Software activation channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.w(ad:0xB1010400+0x0E+0x40)&0x20)==0x00))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "ADCOMPB0,Compare Buffer Register 0"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "ADCOMP0,Compare Register 0"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x0C+0x40)&0x20)==0x00))
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "ADCOMPB1,Compare Buffer Register 1"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "ADCOMP1,Compare Register 1"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x12+0x40)&0x20)==0x00))
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "ADCOMPB2,Compare Buffer Register 2"
|
|
else
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "ADCOMP2,Compare Register 2"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x10+0x40)&0x20)==0x00))
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "ADCOMPB3,Compare Buffer Register 3"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "ADCOMP3,Compare Register 3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x16+0x40)&0x20)==0x00))
|
|
group.word 0x16++0x01
|
|
line.word 0x00 "ADCOMPB4,Compare Buffer Register 4"
|
|
else
|
|
group.word 0x16++0x01
|
|
line.word 0x00 "ADCOMP4,Compare Register 4"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x14+0x40)&0x20)==0x00))
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "ADCOMPB5,Compare Buffer Register 5"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "ADCOMP5,Compare Register 5"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x1A+0x40)&0x20)==0x00))
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "ADCOMPB6,Compare Buffer Register 6"
|
|
else
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "ADCOMP6,Compare Register 6"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x18+0x40)&0x20)==0x00))
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "ADCOMPB7,Compare Buffer Register 7"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "ADCOMP7,Compare Register 7"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x1E+0x40)&0x20)==0x00))
|
|
group.word 0x1E++0x01
|
|
line.word 0x00 "ADCOMPB8,Compare Buffer Register 8"
|
|
else
|
|
group.word 0x1E++0x01
|
|
line.word 0x00 "ADCOMP8,Compare Register 8"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x1C+0x40)&0x20)==0x00))
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "ADCOMPB9,Compare Buffer Register 9"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "ADCOMP9,Compare Register 9"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x22+0x40)&0x20)==0x00))
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "ADCOMPB10,Compare Buffer Register 10"
|
|
else
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "ADCOMP10,Compare Register 10"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x20+0x40)&0x20)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "ADCOMPB11,Compare Buffer Register 11"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "ADCOMP11,Compare Register 11"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x26+0x40)&0x20)==0x00))
|
|
group.word 0x26++0x01
|
|
line.word 0x00 "ADCOMPB12,Compare Buffer Register 12"
|
|
else
|
|
group.word 0x26++0x01
|
|
line.word 0x00 "ADCOMP12,Compare Register 12"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x24+0x40)&0x20)==0x00))
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "ADCOMPB13,Compare Buffer Register 13"
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "ADCOMP13,Compare Register 13"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x2A+0x40)&0x20)==0x00))
|
|
group.word 0x2A++0x01
|
|
line.word 0x00 "ADCOMPB14,Compare Buffer Register 14"
|
|
else
|
|
group.word 0x2A++0x01
|
|
line.word 0x00 "ADCOMP14,Compare Register 14"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x28+0x40)&0x20)==0x00))
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "ADCOMPB15,Compare Buffer Register 15"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "ADCOMP15,Compare Register 15"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x2E+0x40)&0x20)==0x00))
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "ADCOMPB16,Compare Buffer Register 16"
|
|
else
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "ADCOMP16,Compare Register 16"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x2C+0x40)&0x20)==0x00))
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ADCOMPB17,Compare Buffer Register 17"
|
|
else
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ADCOMP17,Compare Register 17"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x32+0x40)&0x20)==0x00))
|
|
group.word 0x32++0x01
|
|
line.word 0x00 "ADCOMPB18,Compare Buffer Register 18"
|
|
else
|
|
group.word 0x32++0x01
|
|
line.word 0x00 "ADCOMP18,Compare Register 18"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x30+0x40)&0x20)==0x00))
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "ADCOMPB19,Compare Buffer Register 19"
|
|
else
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "ADCOMP19,Compare Register 19"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x36+0x40)&0x20)==0x00))
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "ADCOMPB20,Compare Buffer Register 20"
|
|
else
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "ADCOMP20,Compare Register 20"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x34+0x40)&0x20)==0x00))
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "ADCOMPB21,Compare Buffer Register 21"
|
|
else
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "ADCOMP21,Compare Register 21"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x3A+0x40)&0x20)==0x00))
|
|
group.word 0x3A++0x01
|
|
line.word 0x00 "ADCOMPB22,Compare Buffer Register 22"
|
|
else
|
|
group.word 0x3A++0x01
|
|
line.word 0x00 "ADCOMP22,Compare Register 22"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x38+0x40)&0x20)==0x00))
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "ADCOMPB23,Compare Buffer Register 23"
|
|
else
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "ADCOMP23,Compare Register 23"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x3E+0x40)&0x20)==0x00))
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "ADCOMPB24,Compare Buffer Register 24"
|
|
else
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "ADCOMP24,Compare Register 24"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x3C+0x40)&0x20)==0x00))
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "ADCOMPB25,Compare Buffer Register 25"
|
|
else
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "ADCOMP25,Compare Register 25"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x42+0x40)&0x20)==0x00))
|
|
group.word 0x42++0x01
|
|
line.word 0x00 "ADCOMPB26,Compare Buffer Register 26"
|
|
else
|
|
group.word 0x42++0x01
|
|
line.word 0x00 "ADCOMP26,Compare Register 26"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x40+0x40)&0x20)==0x00))
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "ADCOMPB27,Compare Buffer Register 27"
|
|
else
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "ADCOMP27,Compare Register 27"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x46+0x40)&0x20)==0x00))
|
|
group.word 0x46++0x01
|
|
line.word 0x00 "ADCOMPB28,Compare Buffer Register 28"
|
|
else
|
|
group.word 0x46++0x01
|
|
line.word 0x00 "ADCOMP28,Compare Register 28"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x44+0x40)&0x20)==0x00))
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "ADCOMPB29,Compare Buffer Register 29"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "ADCOMP29,Compare Register 29"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x4A+0x40)&0x20)==0x00))
|
|
group.word 0x4A++0x01
|
|
line.word 0x00 "ADCOMPB30,Compare Buffer Register 30"
|
|
else
|
|
group.word 0x4A++0x01
|
|
line.word 0x00 "ADCOMP30,Compare Register 30"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x48+0x40)&0x20)==0x00))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "ADCOMPB31,Compare Buffer Register 31"
|
|
else
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "ADCOMP31,Compare Register 31"
|
|
endif
|
|
group.word 0x4E++0x01
|
|
line.word 0x00 "ADTCS0,A/D Activation Trigger Control Status Register 0"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "ADTCS1,A/D Activation Trigger Control Status Register 1"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x52++0x01
|
|
line.word 0x00 "ADTCS2,A/D Activation Trigger Control Status Register 2"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "ADTCS3,A/D Activation Trigger Control Status Register 3"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x56++0x01
|
|
line.word 0x00 "ADTCS4,A/D Activation Trigger Control Status Register 4"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "ADTCS5,A/D Activation Trigger Control Status Register 5"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x5A++0x01
|
|
line.word 0x00 "ADTCS6,A/D Activation Trigger Control Status Register 6"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "ADTCS7,A/D Activation Trigger Control Status Register 7"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x5E++0x01
|
|
line.word 0x00 "ADTCS8,A/D Activation Trigger Control Status Register 8"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x5C++0x01
|
|
line.word 0x00 "ADTCS9,A/D Activation Trigger Control Status Register 9"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x62++0x01
|
|
line.word 0x00 "ADTCS10,A/D Activation Trigger Control Status Register 10"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "ADTCS11,A/D Activation Trigger Control Status Register 11"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x66++0x01
|
|
line.word 0x00 "ADTCS12,A/D Activation Trigger Control Status Register 12"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "ADTCS13,A/D Activation Trigger Control Status Register 13"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x6A++0x01
|
|
line.word 0x00 "ADTCS14,A/D Activation Trigger Control Status Register 14"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "ADTCS15,A/D Activation Trigger Control Status Register 15"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x6E++0x01
|
|
line.word 0x00 "ADTCS16,A/D Activation Trigger Control Status Register 16"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "ADTCS17,A/D Activation Trigger Control Status Register 17"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x72++0x01
|
|
line.word 0x00 "ADTCS18,A/D Activation Trigger Control Status Register 18"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x70++0x01
|
|
line.word 0x00 "ADTCS19,A/D Activation Trigger Control Status Register 19"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x76++0x01
|
|
line.word 0x00 "ADTCS20,A/D Activation Trigger Control Status Register 20"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x74++0x01
|
|
line.word 0x00 "ADTCS21,A/D Activation Trigger Control Status Register 21"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x7A++0x01
|
|
line.word 0x00 "ADTCS22,A/D Activation Trigger Control Status Register 22"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x78++0x01
|
|
line.word 0x00 "ADTCS23,A/D Activation Trigger Control Status Register 23"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x7E++0x01
|
|
line.word 0x00 "ADTCS24,A/D Activation Trigger Control Status Register 24"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x7C++0x01
|
|
line.word 0x00 "ADTCS25,A/D Activation Trigger Control Status Register 25"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x82++0x01
|
|
line.word 0x00 "ADTCS26,A/D Activation Trigger Control Status Register 26"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "ADTCS27,A/D Activation Trigger Control Status Register 27"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x86++0x01
|
|
line.word 0x00 "ADTCS28,A/D Activation Trigger Control Status Register 28"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "ADTCS29,A/D Activation Trigger Control Status Register 29"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x8A++0x01
|
|
line.word 0x00 "ADTCS30,A/D Activation Trigger Control Status Register 30"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
group.word 0x88++0x01
|
|
line.word 0x00 "ADTCS31,A/D Activation Trigger Control Status Register 31"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request in progress" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection" "Software,External trigger,Base timer,Compare match"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare clear"
|
|
textline " "
|
|
if (((per.w(ad:0xB1010400+0x8E)&0x8000)==0x8000))
|
|
rgroup.word 0x8E++0x01
|
|
line.word 0x00 "ADTCD0,A/D Data Register 0"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0x8E++0x01
|
|
line.word 0x00 "ADTCD0,A/D Data Register 0"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x8C)&0x8000)==0x8000))
|
|
rgroup.word 0x8C++0x01
|
|
line.word 0x00 "ADTCD1,A/D Data Register 1"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0x8C++0x01
|
|
line.word 0x00 "ADTCD1,A/D Data Register 1"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x92)&0x8000)==0x8000))
|
|
rgroup.word 0x92++0x01
|
|
line.word 0x00 "ADTCD2,A/D Data Register 2"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0x92++0x01
|
|
line.word 0x00 "ADTCD2,A/D Data Register 2"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x90)&0x8000)==0x8000))
|
|
rgroup.word 0x90++0x01
|
|
line.word 0x00 "ADTCD3,A/D Data Register 3"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0x90++0x01
|
|
line.word 0x00 "ADTCD3,A/D Data Register 3"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x96)&0x8000)==0x8000))
|
|
rgroup.word 0x96++0x01
|
|
line.word 0x00 "ADTCD4,A/D Data Register 4"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0x96++0x01
|
|
line.word 0x00 "ADTCD4,A/D Data Register 4"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x94)&0x8000)==0x8000))
|
|
rgroup.word 0x94++0x01
|
|
line.word 0x00 "ADTCD5,A/D Data Register 5"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0x94++0x01
|
|
line.word 0x00 "ADTCD5,A/D Data Register 5"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x9A)&0x8000)==0x8000))
|
|
rgroup.word 0x9A++0x01
|
|
line.word 0x00 "ADTCD6,A/D Data Register 6"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0x9A++0x01
|
|
line.word 0x00 "ADTCD6,A/D Data Register 6"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x98)&0x8000)==0x8000))
|
|
rgroup.word 0x98++0x01
|
|
line.word 0x00 "ADTCD7,A/D Data Register 7"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0x98++0x01
|
|
line.word 0x00 "ADTCD7,A/D Data Register 7"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x9E)&0x8000)==0x8000))
|
|
rgroup.word 0x9E++0x01
|
|
line.word 0x00 "ADTCD8,A/D Data Register 8"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0x9E++0x01
|
|
line.word 0x00 "ADTCD8,A/D Data Register 8"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x9C)&0x8000)==0x8000))
|
|
rgroup.word 0x9C++0x01
|
|
line.word 0x00 "ADTCD9,A/D Data Register 9"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0x9C++0x01
|
|
line.word 0x00 "ADTCD9,A/D Data Register 9"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xA2)&0x8000)==0x8000))
|
|
rgroup.word 0xA2++0x01
|
|
line.word 0x00 "ADTCD10,A/D Data Register 10"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xA2++0x01
|
|
line.word 0x00 "ADTCD10,A/D Data Register 10"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xA0)&0x8000)==0x8000))
|
|
rgroup.word 0xA0++0x01
|
|
line.word 0x00 "ADTCD11,A/D Data Register 11"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xA0++0x01
|
|
line.word 0x00 "ADTCD11,A/D Data Register 11"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xA6)&0x8000)==0x8000))
|
|
rgroup.word 0xA6++0x01
|
|
line.word 0x00 "ADTCD12,A/D Data Register 12"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xA6++0x01
|
|
line.word 0x00 "ADTCD12,A/D Data Register 12"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xA4)&0x8000)==0x8000))
|
|
rgroup.word 0xA4++0x01
|
|
line.word 0x00 "ADTCD13,A/D Data Register 13"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xA4++0x01
|
|
line.word 0x00 "ADTCD13,A/D Data Register 13"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xAA)&0x8000)==0x8000))
|
|
rgroup.word 0xAA++0x01
|
|
line.word 0x00 "ADTCD14,A/D Data Register 14"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xAA++0x01
|
|
line.word 0x00 "ADTCD14,A/D Data Register 14"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xA8)&0x8000)==0x8000))
|
|
rgroup.word 0xA8++0x01
|
|
line.word 0x00 "ADTCD15,A/D Data Register 15"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xA8++0x01
|
|
line.word 0x00 "ADTCD15,A/D Data Register 15"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xAE)&0x8000)==0x8000))
|
|
rgroup.word 0xAE++0x01
|
|
line.word 0x00 "ADTCD16,A/D Data Register 16"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xAE++0x01
|
|
line.word 0x00 "ADTCD16,A/D Data Register 16"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xAC)&0x8000)==0x8000))
|
|
rgroup.word 0xAC++0x01
|
|
line.word 0x00 "ADTCD17,A/D Data Register 17"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xAC++0x01
|
|
line.word 0x00 "ADTCD17,A/D Data Register 17"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xB2)&0x8000)==0x8000))
|
|
rgroup.word 0xB2++0x01
|
|
line.word 0x00 "ADTCD18,A/D Data Register 18"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xB2++0x01
|
|
line.word 0x00 "ADTCD18,A/D Data Register 18"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xB0)&0x8000)==0x8000))
|
|
rgroup.word 0xB0++0x01
|
|
line.word 0x00 "ADTCD19,A/D Data Register 19"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xB0++0x01
|
|
line.word 0x00 "ADTCD19,A/D Data Register 19"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xB6)&0x8000)==0x8000))
|
|
rgroup.word 0xB6++0x01
|
|
line.word 0x00 "ADTCD20,A/D Data Register 20"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xB6++0x01
|
|
line.word 0x00 "ADTCD20,A/D Data Register 20"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xB4)&0x8000)==0x8000))
|
|
rgroup.word 0xB4++0x01
|
|
line.word 0x00 "ADTCD21,A/D Data Register 21"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xB4++0x01
|
|
line.word 0x00 "ADTCD21,A/D Data Register 21"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xBA)&0x8000)==0x8000))
|
|
rgroup.word 0xBA++0x01
|
|
line.word 0x00 "ADTCD22,A/D Data Register 22"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xBA++0x01
|
|
line.word 0x00 "ADTCD22,A/D Data Register 22"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xB8)&0x8000)==0x8000))
|
|
rgroup.word 0xB8++0x01
|
|
line.word 0x00 "ADTCD23,A/D Data Register 23"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xB8++0x01
|
|
line.word 0x00 "ADTCD23,A/D Data Register 23"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xBE)&0x8000)==0x8000))
|
|
rgroup.word 0xBE++0x01
|
|
line.word 0x00 "ADTCD24,A/D Data Register 24"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xBE++0x01
|
|
line.word 0x00 "ADTCD24,A/D Data Register 24"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xBC)&0x8000)==0x8000))
|
|
rgroup.word 0xBC++0x01
|
|
line.word 0x00 "ADTCD25,A/D Data Register 25"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xBC++0x01
|
|
line.word 0x00 "ADTCD25,A/D Data Register 25"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xC2)&0x8000)==0x8000))
|
|
rgroup.word 0xC2++0x01
|
|
line.word 0x00 "ADTCD26,A/D Data Register 26"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xC2++0x01
|
|
line.word 0x00 "ADTCD26,A/D Data Register 26"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xC0)&0x8000)==0x8000))
|
|
rgroup.word 0xC0++0x01
|
|
line.word 0x00 "ADTCD27,A/D Data Register 27"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xC0++0x01
|
|
line.word 0x00 "ADTCD27,A/D Data Register 27"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xC6)&0x8000)==0x8000))
|
|
rgroup.word 0xC6++0x01
|
|
line.word 0x00 "ADTCD28,A/D Data Register 28"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xC6++0x01
|
|
line.word 0x00 "ADTCD28,A/D Data Register 28"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xC4)&0x8000)==0x8000))
|
|
rgroup.word 0xC4++0x01
|
|
line.word 0x00 "ADTCD29,A/D Data Register 29"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xC4++0x01
|
|
line.word 0x00 "ADTCD29,A/D Data Register 29"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xCA)&0x8000)==0x8000))
|
|
rgroup.word 0xCA++0x01
|
|
line.word 0x00 "ADTCD30,A/D Data Register 30"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xCA++0x01
|
|
line.word 0x00 "ADTCD30,A/D Data Register 30"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xC8)&0x8000)==0x8000))
|
|
rgroup.word 0xC8++0x01
|
|
line.word 0x00 "ADTCD31,A/D Data Register 31"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old result,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
rgroup.word 0xC8++0x01
|
|
line.word 0x00 "ADTCD31,A/D Data Register 31"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xCE-0x80))&0x8000)==0x00)
|
|
group.word 0xCE++0x01
|
|
line.word 0x00 "ADTECS0,A/D Activation Trigger Extend Control Register 0"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xCE++0x01
|
|
line.word 0x00 "ADTECS0,A/D Activation Trigger Extend Control Register 0"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xCC-0x80))&0x8000)==0x00)
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "ADTECS1,A/D Activation Trigger Extend Control Register 1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xCC++0x01
|
|
line.word 0x00 "ADTECS1,A/D Activation Trigger Extend Control Register 1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xD2-0x80))&0x8000)==0x00)
|
|
group.word 0xD2++0x01
|
|
line.word 0x00 "ADTECS2,A/D Activation Trigger Extend Control Register 2"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xD2++0x01
|
|
line.word 0x00 "ADTECS2,A/D Activation Trigger Extend Control Register 2"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xD0-0x80))&0x8000)==0x00)
|
|
group.word 0xD0++0x01
|
|
line.word 0x00 "ADTECS3,A/D Activation Trigger Extend Control Register 3"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xD0++0x01
|
|
line.word 0x00 "ADTECS3,A/D Activation Trigger Extend Control Register 3"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xD6-0x80))&0x8000)==0x00)
|
|
group.word 0xD6++0x01
|
|
line.word 0x00 "ADTECS4,A/D Activation Trigger Extend Control Register 4"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xD6++0x01
|
|
line.word 0x00 "ADTECS4,A/D Activation Trigger Extend Control Register 4"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xD4-0x80))&0x8000)==0x00)
|
|
group.word 0xD4++0x01
|
|
line.word 0x00 "ADTECS5,A/D Activation Trigger Extend Control Register 5"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xD4++0x01
|
|
line.word 0x00 "ADTECS5,A/D Activation Trigger Extend Control Register 5"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xDA-0x80))&0x8000)==0x00)
|
|
group.word 0xDA++0x01
|
|
line.word 0x00 "ADTECS6,A/D Activation Trigger Extend Control Register 6"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xDA++0x01
|
|
line.word 0x00 "ADTECS6,A/D Activation Trigger Extend Control Register 6"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xD8-0x80))&0x8000)==0x00)
|
|
group.word 0xD8++0x01
|
|
line.word 0x00 "ADTECS7,A/D Activation Trigger Extend Control Register 7"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xD8++0x01
|
|
line.word 0x00 "ADTECS7,A/D Activation Trigger Extend Control Register 7"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xDE-0x80))&0x8000)==0x00)
|
|
group.word 0xDE++0x01
|
|
line.word 0x00 "ADTECS8,A/D Activation Trigger Extend Control Register 8"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xDE++0x01
|
|
line.word 0x00 "ADTECS8,A/D Activation Trigger Extend Control Register 8"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xDC-0x80))&0x8000)==0x00)
|
|
group.word 0xDC++0x01
|
|
line.word 0x00 "ADTECS9,A/D Activation Trigger Extend Control Register 9"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xDC++0x01
|
|
line.word 0x00 "ADTECS9,A/D Activation Trigger Extend Control Register 9"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xE2-0x80))&0x8000)==0x00)
|
|
group.word 0xE2++0x01
|
|
line.word 0x00 "ADTECS10,A/D Activation Trigger Extend Control Register 10"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xE2++0x01
|
|
line.word 0x00 "ADTECS10,A/D Activation Trigger Extend Control Register 10"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xE0-0x80))&0x8000)==0x00)
|
|
group.word 0xE0++0x01
|
|
line.word 0x00 "ADTECS11,A/D Activation Trigger Extend Control Register 11"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xE0++0x01
|
|
line.word 0x00 "ADTECS11,A/D Activation Trigger Extend Control Register 11"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xE6-0x80))&0x8000)==0x00)
|
|
group.word 0xE6++0x01
|
|
line.word 0x00 "ADTECS12,A/D Activation Trigger Extend Control Register 12"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xE6++0x01
|
|
line.word 0x00 "ADTECS12,A/D Activation Trigger Extend Control Register 12"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xE4-0x80))&0x8000)==0x00)
|
|
group.word 0xE4++0x01
|
|
line.word 0x00 "ADTECS13,A/D Activation Trigger Extend Control Register 13"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xE4++0x01
|
|
line.word 0x00 "ADTECS13,A/D Activation Trigger Extend Control Register 13"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xEA-0x80))&0x8000)==0x00)
|
|
group.word 0xEA++0x01
|
|
line.word 0x00 "ADTECS14,A/D Activation Trigger Extend Control Register 14"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xEA++0x01
|
|
line.word 0x00 "ADTECS14,A/D Activation Trigger Extend Control Register 14"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xE8-0x80))&0x8000)==0x00)
|
|
group.word 0xE8++0x01
|
|
line.word 0x00 "ADTECS15,A/D Activation Trigger Extend Control Register 15"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xE8++0x01
|
|
line.word 0x00 "ADTECS15,A/D Activation Trigger Extend Control Register 15"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xEE-0x80))&0x8000)==0x00)
|
|
group.word 0xEE++0x01
|
|
line.word 0x00 "ADTECS16,A/D Activation Trigger Extend Control Register 16"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xEE++0x01
|
|
line.word 0x00 "ADTECS16,A/D Activation Trigger Extend Control Register 16"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xEC-0x80))&0x8000)==0x00)
|
|
group.word 0xEC++0x01
|
|
line.word 0x00 "ADTECS17,A/D Activation Trigger Extend Control Register 17"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xEC++0x01
|
|
line.word 0x00 "ADTECS17,A/D Activation Trigger Extend Control Register 17"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xF2-0x80))&0x8000)==0x00)
|
|
group.word 0xF2++0x01
|
|
line.word 0x00 "ADTECS18,A/D Activation Trigger Extend Control Register 18"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xF2++0x01
|
|
line.word 0x00 "ADTECS18,A/D Activation Trigger Extend Control Register 18"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xF0-0x80))&0x8000)==0x00)
|
|
group.word 0xF0++0x01
|
|
line.word 0x00 "ADTECS19,A/D Activation Trigger Extend Control Register 19"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xF0++0x01
|
|
line.word 0x00 "ADTECS19,A/D Activation Trigger Extend Control Register 19"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xF6-0x80))&0x8000)==0x00)
|
|
group.word 0xF6++0x01
|
|
line.word 0x00 "ADTECS20,A/D Activation Trigger Extend Control Register 20"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xF6++0x01
|
|
line.word 0x00 "ADTECS20,A/D Activation Trigger Extend Control Register 20"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xF4-0x80))&0x8000)==0x00)
|
|
group.word 0xF4++0x01
|
|
line.word 0x00 "ADTECS21,A/D Activation Trigger Extend Control Register 21"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xF4++0x01
|
|
line.word 0x00 "ADTECS21,A/D Activation Trigger Extend Control Register 21"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xFA-0x80))&0x8000)==0x00)
|
|
group.word 0xFA++0x01
|
|
line.word 0x00 "ADTECS22,A/D Activation Trigger Extend Control Register 22"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xFA++0x01
|
|
line.word 0x00 "ADTECS22,A/D Activation Trigger Extend Control Register 22"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xF8-0x80))&0x8000)==0x00)
|
|
group.word 0xF8++0x01
|
|
line.word 0x00 "ADTECS23,A/D Activation Trigger Extend Control Register 23"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xF8++0x01
|
|
line.word 0x00 "ADTECS23,A/D Activation Trigger Extend Control Register 23"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xFE-0x80))&0x8000)==0x00)
|
|
group.word 0xFE++0x01
|
|
line.word 0x00 "ADTECS24,A/D Activation Trigger Extend Control Register 24"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xFE++0x01
|
|
line.word 0x00 "ADTECS24,A/D Activation Trigger Extend Control Register 24"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0xFC-0x80))&0x8000)==0x00)
|
|
group.word 0xFC++0x01
|
|
line.word 0x00 "ADTECS25,A/D Activation Trigger Extend Control Register 25"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0xFC++0x01
|
|
line.word 0x00 "ADTECS25,A/D Activation Trigger Extend Control Register 25"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x102-0x80))&0x8000)==0x00)
|
|
group.word 0x102++0x01
|
|
line.word 0x00 "ADTECS26,A/D Activation Trigger Extend Control Register 26"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0x102++0x01
|
|
line.word 0x00 "ADTECS26,A/D Activation Trigger Extend Control Register 26"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x100-0x80))&0x8000)==0x00)
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "ADTECS27,A/D Activation Trigger Extend Control Register 27"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0x100++0x01
|
|
line.word 0x00 "ADTECS27,A/D Activation Trigger Extend Control Register 27"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x106-0x80))&0x8000)==0x00)
|
|
group.word 0x106++0x01
|
|
line.word 0x00 "ADTECS28,A/D Activation Trigger Extend Control Register 28"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0x106++0x01
|
|
line.word 0x00 "ADTECS28,A/D Activation Trigger Extend Control Register 28"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x104-0x80))&0x8000)==0x00)
|
|
group.word 0x104++0x01
|
|
line.word 0x00 "ADTECS29,A/D Activation Trigger Extend Control Register 29"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0x104++0x01
|
|
line.word 0x00 "ADTECS29,A/D Activation Trigger Extend Control Register 29"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x10A-0x80))&0x8000)==0x00)
|
|
group.word 0x10A++0x01
|
|
line.word 0x00 "ADTECS30,A/D Activation Trigger Extend Control Register 30"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0x10A++0x01
|
|
line.word 0x00 "ADTECS30,A/D Activation Trigger Extend Control Register 30"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x108-0x80))&0x8000)==0x00)
|
|
group.word 0x108++0x01
|
|
line.word 0x00 "ADTECS31,A/D Activation Trigger Extend Control Register 31"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rgroup.word 0x108++0x01
|
|
line.word 0x00 "ADTECS31,A/D Activation Trigger Extend Control Register 31"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
group.word 0x10E++0x01
|
|
line.word 0x00 "ADRCUT0,Upper-limit Threshold Setting Register 0"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Upper-limit threshold"
|
|
group.word 0x112++0x01
|
|
line.word 0x00 "ADRCUT1,Upper-limit Threshold Setting Register 1"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Upper-limit threshold"
|
|
group.word 0x116++0x01
|
|
line.word 0x00 "ADRCUT2,Upper-limit Threshold Setting Register 2"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Upper-limit threshold"
|
|
group.word 0x11A++0x01
|
|
line.word 0x00 "ADRCUT3,Upper-limit Threshold Setting Register 3"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Upper-limit threshold"
|
|
group.word 0x10C++0x01
|
|
line.word 0x00 "ADRCLT0,Lower-limit Threshold Setting Register 0"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower-limit threshold"
|
|
group.word 0x110++0x01
|
|
line.word 0x00 "ADRCLT1,Lower-limit Threshold Setting Register 1"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower-limit threshold"
|
|
group.word 0x114++0x01
|
|
line.word 0x00 "ADRCLT2,Lower-limit Threshold Setting Register 2"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower-limit threshold"
|
|
group.word 0x118++0x01
|
|
line.word 0x00 "ADRCLT3,Lower-limit Threshold Setting Register 3"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower-limit threshold"
|
|
if (((per.w(ad:0xB1010400+0x4E))&0x8000)==0x8000)
|
|
group.byte 0x11F++0x00
|
|
line.byte 0x00 "ADRCCS0,Range Comparison Control Status Register 0"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x11F))&0x04)==0x04)
|
|
group.byte 0x11F++0x00
|
|
line.byte 0x00 "ADRCCS0,Range Comparison Control Status Register 0"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x11F++0x00
|
|
line.byte 0x00 "ADRCCS0,Range Comparison Control Status Register 0"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x4C))&0x8000)==0x8000)
|
|
group.byte 0x11E++0x00
|
|
line.byte 0x00 "ADRCCS1,Range Comparison Control Status Register 1"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x11E))&0x04)==0x04)
|
|
group.byte 0x11E++0x00
|
|
line.byte 0x00 "ADRCCS1,Range Comparison Control Status Register 1"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x11E++0x00
|
|
line.byte 0x00 "ADRCCS1,Range Comparison Control Status Register 1"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x52))&0x8000)==0x8000)
|
|
group.byte 0x11D++0x00
|
|
line.byte 0x00 "ADRCCS2,Range Comparison Control Status Register 2"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x11D))&0x04)==0x04)
|
|
group.byte 0x11D++0x00
|
|
line.byte 0x00 "ADRCCS2,Range Comparison Control Status Register 2"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x11D++0x00
|
|
line.byte 0x00 "ADRCCS2,Range Comparison Control Status Register 2"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x50))&0x8000)==0x8000)
|
|
group.byte 0x11C++0x00
|
|
line.byte 0x00 "ADRCCS3,Range Comparison Control Status Register 3"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x11C))&0x04)==0x04)
|
|
group.byte 0x11C++0x00
|
|
line.byte 0x00 "ADRCCS3,Range Comparison Control Status Register 3"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x11C++0x00
|
|
line.byte 0x00 "ADRCCS3,Range Comparison Control Status Register 3"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x56))&0x8000)==0x8000)
|
|
group.byte 0x123++0x00
|
|
line.byte 0x00 "ADRCCS4,Range Comparison Control Status Register 4"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x123))&0x04)==0x04)
|
|
group.byte 0x123++0x00
|
|
line.byte 0x00 "ADRCCS4,Range Comparison Control Status Register 4"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x123++0x00
|
|
line.byte 0x00 "ADRCCS4,Range Comparison Control Status Register 4"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x54))&0x8000)==0x8000)
|
|
group.byte 0x122++0x00
|
|
line.byte 0x00 "ADRCCS5,Range Comparison Control Status Register 5"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x122))&0x04)==0x04)
|
|
group.byte 0x122++0x00
|
|
line.byte 0x00 "ADRCCS5,Range Comparison Control Status Register 5"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x122++0x00
|
|
line.byte 0x00 "ADRCCS5,Range Comparison Control Status Register 5"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x5A))&0x8000)==0x8000)
|
|
group.byte 0x121++0x00
|
|
line.byte 0x00 "ADRCCS6,Range Comparison Control Status Register 6"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x121))&0x04)==0x04)
|
|
group.byte 0x121++0x00
|
|
line.byte 0x00 "ADRCCS6,Range Comparison Control Status Register 6"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x121++0x00
|
|
line.byte 0x00 "ADRCCS6,Range Comparison Control Status Register 6"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x58))&0x8000)==0x8000)
|
|
group.byte 0x120++0x00
|
|
line.byte 0x00 "ADRCCS7,Range Comparison Control Status Register 7"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x120))&0x04)==0x04)
|
|
group.byte 0x120++0x00
|
|
line.byte 0x00 "ADRCCS7,Range Comparison Control Status Register 7"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x120++0x00
|
|
line.byte 0x00 "ADRCCS7,Range Comparison Control Status Register 7"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x5E))&0x8000)==0x8000)
|
|
group.byte 0x127++0x00
|
|
line.byte 0x00 "ADRCCS8,Range Comparison Control Status Register 8"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x127))&0x04)==0x04)
|
|
group.byte 0x127++0x00
|
|
line.byte 0x00 "ADRCCS8,Range Comparison Control Status Register 8"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x127++0x00
|
|
line.byte 0x00 "ADRCCS8,Range Comparison Control Status Register 8"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x5C))&0x8000)==0x8000)
|
|
group.byte 0x126++0x00
|
|
line.byte 0x00 "ADRCCS9,Range Comparison Control Status Register 9"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x126))&0x04)==0x04)
|
|
group.byte 0x126++0x00
|
|
line.byte 0x00 "ADRCCS9,Range Comparison Control Status Register 9"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x126++0x00
|
|
line.byte 0x00 "ADRCCS9,Range Comparison Control Status Register 9"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x62))&0x8000)==0x8000)
|
|
group.byte 0x125++0x00
|
|
line.byte 0x00 "ADRCCS10,Range Comparison Control Status Register 10"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x125))&0x04)==0x04)
|
|
group.byte 0x125++0x00
|
|
line.byte 0x00 "ADRCCS10,Range Comparison Control Status Register 10"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x125++0x00
|
|
line.byte 0x00 "ADRCCS10,Range Comparison Control Status Register 10"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x60))&0x8000)==0x8000)
|
|
group.byte 0x124++0x00
|
|
line.byte 0x00 "ADRCCS11,Range Comparison Control Status Register 11"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x124))&0x04)==0x04)
|
|
group.byte 0x124++0x00
|
|
line.byte 0x00 "ADRCCS11,Range Comparison Control Status Register 11"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x124++0x00
|
|
line.byte 0x00 "ADRCCS11,Range Comparison Control Status Register 11"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x66))&0x8000)==0x8000)
|
|
group.byte 0x12B++0x00
|
|
line.byte 0x00 "ADRCCS12,Range Comparison Control Status Register 12"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x12B))&0x04)==0x04)
|
|
group.byte 0x12B++0x00
|
|
line.byte 0x00 "ADRCCS12,Range Comparison Control Status Register 12"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x12B++0x00
|
|
line.byte 0x00 "ADRCCS12,Range Comparison Control Status Register 12"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x64))&0x8000)==0x8000)
|
|
group.byte 0x12A++0x00
|
|
line.byte 0x00 "ADRCCS13,Range Comparison Control Status Register 13"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x12A))&0x04)==0x04)
|
|
group.byte 0x12A++0x00
|
|
line.byte 0x00 "ADRCCS13,Range Comparison Control Status Register 13"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x12A++0x00
|
|
line.byte 0x00 "ADRCCS13,Range Comparison Control Status Register 13"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x6A))&0x8000)==0x8000)
|
|
group.byte 0x129++0x00
|
|
line.byte 0x00 "ADRCCS14,Range Comparison Control Status Register 14"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x129))&0x04)==0x04)
|
|
group.byte 0x129++0x00
|
|
line.byte 0x00 "ADRCCS14,Range Comparison Control Status Register 14"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x129++0x00
|
|
line.byte 0x00 "ADRCCS14,Range Comparison Control Status Register 14"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x68))&0x8000)==0x8000)
|
|
group.byte 0x128++0x00
|
|
line.byte 0x00 "ADRCCS15,Range Comparison Control Status Register 15"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x128))&0x04)==0x04)
|
|
group.byte 0x128++0x00
|
|
line.byte 0x00 "ADRCCS15,Range Comparison Control Status Register 15"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x128++0x00
|
|
line.byte 0x00 "ADRCCS15,Range Comparison Control Status Register 15"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x6E))&0x8000)==0x8000)
|
|
group.byte 0x12F++0x00
|
|
line.byte 0x00 "ADRCCS16,Range Comparison Control Status Register 16"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x12F))&0x04)==0x04)
|
|
group.byte 0x12F++0x00
|
|
line.byte 0x00 "ADRCCS16,Range Comparison Control Status Register 16"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x12F++0x00
|
|
line.byte 0x00 "ADRCCS16,Range Comparison Control Status Register 16"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x6C))&0x8000)==0x8000)
|
|
group.byte 0x12E++0x00
|
|
line.byte 0x00 "ADRCCS17,Range Comparison Control Status Register 17"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x12E))&0x04)==0x04)
|
|
group.byte 0x12E++0x00
|
|
line.byte 0x00 "ADRCCS17,Range Comparison Control Status Register 17"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x12E++0x00
|
|
line.byte 0x00 "ADRCCS17,Range Comparison Control Status Register 17"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x72))&0x8000)==0x8000)
|
|
group.byte 0x12D++0x00
|
|
line.byte 0x00 "ADRCCS18,Range Comparison Control Status Register 18"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x12D))&0x04)==0x04)
|
|
group.byte 0x12D++0x00
|
|
line.byte 0x00 "ADRCCS18,Range Comparison Control Status Register 18"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x12D++0x00
|
|
line.byte 0x00 "ADRCCS18,Range Comparison Control Status Register 18"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x70))&0x8000)==0x8000)
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "ADRCCS19,Range Comparison Control Status Register 19"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x12C))&0x04)==0x04)
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "ADRCCS19,Range Comparison Control Status Register 19"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "ADRCCS19,Range Comparison Control Status Register 19"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x76))&0x8000)==0x8000)
|
|
group.byte 0x133++0x00
|
|
line.byte 0x00 "ADRCCS20,Range Comparison Control Status Register 20"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x133))&0x04)==0x04)
|
|
group.byte 0x133++0x00
|
|
line.byte 0x00 "ADRCCS20,Range Comparison Control Status Register 20"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x133++0x00
|
|
line.byte 0x00 "ADRCCS20,Range Comparison Control Status Register 20"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x74))&0x8000)==0x8000)
|
|
group.byte 0x132++0x00
|
|
line.byte 0x00 "ADRCCS21,Range Comparison Control Status Register 21"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x132))&0x04)==0x04)
|
|
group.byte 0x132++0x00
|
|
line.byte 0x00 "ADRCCS21,Range Comparison Control Status Register 21"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x132++0x00
|
|
line.byte 0x00 "ADRCCS21,Range Comparison Control Status Register 21"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x7A))&0x8000)==0x8000)
|
|
group.byte 0x131++0x00
|
|
line.byte 0x00 "ADRCCS22,Range Comparison Control Status Register 22"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x131))&0x04)==0x04)
|
|
group.byte 0x131++0x00
|
|
line.byte 0x00 "ADRCCS22,Range Comparison Control Status Register 22"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x131++0x00
|
|
line.byte 0x00 "ADRCCS22,Range Comparison Control Status Register 22"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x78))&0x8000)==0x8000)
|
|
group.byte 0x130++0x00
|
|
line.byte 0x00 "ADRCCS23,Range Comparison Control Status Register 23"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x130))&0x04)==0x04)
|
|
group.byte 0x130++0x00
|
|
line.byte 0x00 "ADRCCS23,Range Comparison Control Status Register 23"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x130++0x00
|
|
line.byte 0x00 "ADRCCS23,Range Comparison Control Status Register 23"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x7E))&0x8000)==0x8000)
|
|
group.byte 0x137++0x00
|
|
line.byte 0x00 "ADRCCS24,Range Comparison Control Status Register 24"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x137))&0x04)==0x04)
|
|
group.byte 0x137++0x00
|
|
line.byte 0x00 "ADRCCS24,Range Comparison Control Status Register 24"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x137++0x00
|
|
line.byte 0x00 "ADRCCS24,Range Comparison Control Status Register 24"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x7C))&0x8000)==0x8000)
|
|
group.byte 0x136++0x00
|
|
line.byte 0x00 "ADRCCS25,Range Comparison Control Status Register 25"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x136))&0x04)==0x04)
|
|
group.byte 0x136++0x00
|
|
line.byte 0x00 "ADRCCS25,Range Comparison Control Status Register 25"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x136++0x00
|
|
line.byte 0x00 "ADRCCS25,Range Comparison Control Status Register 25"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x82))&0x8000)==0x8000)
|
|
group.byte 0x135++0x00
|
|
line.byte 0x00 "ADRCCS26,Range Comparison Control Status Register 26"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x135))&0x04)==0x04)
|
|
group.byte 0x135++0x00
|
|
line.byte 0x00 "ADRCCS26,Range Comparison Control Status Register 26"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x135++0x00
|
|
line.byte 0x00 "ADRCCS26,Range Comparison Control Status Register 26"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x80))&0x8000)==0x8000)
|
|
group.byte 0x134++0x00
|
|
line.byte 0x00 "ADRCCS27,Range Comparison Control Status Register 27"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x134))&0x04)==0x04)
|
|
group.byte 0x134++0x00
|
|
line.byte 0x00 "ADRCCS27,Range Comparison Control Status Register 27"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x134++0x00
|
|
line.byte 0x00 "ADRCCS27,Range Comparison Control Status Register 27"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x86))&0x8000)==0x8000)
|
|
group.byte 0x13B++0x00
|
|
line.byte 0x00 "ADRCCS28,Range Comparison Control Status Register 28"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x13B))&0x04)==0x04)
|
|
group.byte 0x13B++0x00
|
|
line.byte 0x00 "ADRCCS28,Range Comparison Control Status Register 28"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x13B++0x00
|
|
line.byte 0x00 "ADRCCS28,Range Comparison Control Status Register 28"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x84))&0x8000)==0x8000)
|
|
group.byte 0x13A++0x00
|
|
line.byte 0x00 "ADRCCS29,Range Comparison Control Status Register 29"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x13A))&0x04)==0x04)
|
|
group.byte 0x13A++0x00
|
|
line.byte 0x00 "ADRCCS29,Range Comparison Control Status Register 29"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x13A++0x00
|
|
line.byte 0x00 "ADRCCS29,Range Comparison Control Status Register 29"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x8A))&0x8000)==0x8000)
|
|
group.byte 0x139++0x00
|
|
line.byte 0x00 "ADRCCS30,Range Comparison Control Status Register 30"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x139))&0x04)==0x04)
|
|
group.byte 0x139++0x00
|
|
line.byte 0x00 "ADRCCS30,Range Comparison Control Status Register 30"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x139++0x00
|
|
line.byte 0x00 "ADRCCS30,Range Comparison Control Status Register 30"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
if (((per.w(ad:0xB1010400+0x88))&0x8000)==0x8000)
|
|
group.byte 0x138++0x00
|
|
line.byte 0x00 "ADRCCS31,Range Comparison Control Status Register 31"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
elif (((per.w(ad:0xB1010400+0x138))&0x04)==0x04)
|
|
group.byte 0x138++0x00
|
|
line.byte 0x00 "ADRCCS31,Range Comparison Control Status Register 31"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
else
|
|
group.byte 0x138++0x00
|
|
line.byte 0x00 "ADRCCS31,Range Comparison Control Status Register 31"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection bits" "0,1,2,3"
|
|
endif
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "ADRCOT,Range Comparison Out-of-range Flag Register"
|
|
bitfld.long 0x00 31. " RCOOF31 ,Out-of-range flag 31" "Below,Above"
|
|
bitfld.long 0x00 30. " RCOOF30 ,Out-of-range flag 30" "Below,Above"
|
|
bitfld.long 0x00 29. " RCOOF29 ,Out-of-range flag 29" "Below,Above"
|
|
bitfld.long 0x00 28. " RCOOF28 ,Out-of-range flag 28" "Below,Above"
|
|
textline " "
|
|
bitfld.long 0x00 27. " RCOOF27 ,Out-of-range flag 27" "Below,Above"
|
|
bitfld.long 0x00 26. " RCOOF26 ,Out-of-range flag 26" "Below,Above"
|
|
bitfld.long 0x00 25. " RCOOF25 ,Out-of-range flag 25" "Below,Above"
|
|
bitfld.long 0x00 24. " RCOOF24 ,Out-of-range flag 24" "Below,Above"
|
|
textline " "
|
|
bitfld.long 0x00 23. " RCOOF23 ,Out-of-range flag 23" "Below,Above"
|
|
bitfld.long 0x00 22. " RCOOF22 ,Out-of-range flag 22" "Below,Above"
|
|
bitfld.long 0x00 21. " RCOOF21 ,Out-of-range flag 21" "Below,Above"
|
|
bitfld.long 0x00 20. " RCOOF20 ,Out-of-range flag 20" "Below,Above"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCOOF19 ,Out-of-range flag 19" "Below,Above"
|
|
bitfld.long 0x00 18. " RCOOF18 ,Out-of-range flag 18" "Below,Above"
|
|
bitfld.long 0x00 17. " RCOOF17 ,Out-of-range flag 17" "Below,Above"
|
|
bitfld.long 0x00 16. " RCOOF16 ,Out-of-range flag 16" "Below,Above"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RCOOF15 ,Out-of-range flag 15" "Below,Above"
|
|
bitfld.long 0x00 14. " RCOOF14 ,Out-of-range flag 14" "Below,Above"
|
|
bitfld.long 0x00 13. " RCOOF13 ,Out-of-range flag 13" "Below,Above"
|
|
bitfld.long 0x00 12. " RCOOF12 ,Out-of-range flag 12" "Below,Above"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCOOF11 ,Out-of-range flag 11" "Below,Above"
|
|
bitfld.long 0x00 10. " RCOOF10 ,Out-of-range flag 10" "Below,Above"
|
|
bitfld.long 0x00 9. " RCOOF9 ,Out-of-range flag 9" "Below,Above"
|
|
bitfld.long 0x00 8. " RCOOF8 ,Out-of-range flag 8" "Below,Above"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCOOF7 ,Out-of-range flag 7" "Below,Above"
|
|
bitfld.long 0x00 6. " RCOOF6 ,Out-of-range flag 6" "Below,Above"
|
|
bitfld.long 0x00 5. " RCOOF5 ,Out-of-range flag 5" "Below,Above"
|
|
bitfld.long 0x00 4. " RCOOF4 ,Out-of-range flag 4" "Below,Above"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCOOF3 ,Out-of-range flag 3" "Below,Above"
|
|
bitfld.long 0x00 2. " RCOOF2 ,Out-of-range flag 2" "Below,Above"
|
|
bitfld.long 0x00 1. " RCOOF1 ,Out-of-range flag 1" "Below,Above"
|
|
bitfld.long 0x00 0. " RCOOF0 ,Out-of-range flag 0" "Below,Above"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "ADRCIF,Range Compare Flag Register"
|
|
bitfld.long 0x00 31. " RCINT31 ,Conversion data error flag 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " RCINT30 ,Conversion data error flag 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " RCINT29 ,Conversion data error flag 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " RCINT28 ,Conversion data error flag 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " RCINT27 ,Conversion data error flag 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " RCINT26 ,Conversion data error flag 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " RCINT25 ,Conversion data error flag 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " RCINT24 ,Conversion data error flag 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " RCINT23 ,Conversion data error flag 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " RCINT22 ,Conversion data error flag 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " RCINT21 ,Conversion data error flag 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " RCINT20 ,Conversion data error flag 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCINT19 ,Conversion data error flag 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " RCINT18 ,Conversion data error flag 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " RCINT17 ,Conversion data error flag 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " RCINT16 ,Conversion data error flag 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RCINT15 ,Conversion data error flag 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " RCINT14 ,Conversion data error flag 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " RCINT13 ,Conversion data error flag 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " RCINT12 ,Conversion data error flag 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCINT11 ,Conversion data error flag 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " RCINT10 ,Conversion data error flag 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " RCINT9 ,Conversion data error flag 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RCINT8 ,Conversion data error flag 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCINT7 ,Conversion data error flag 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RCINT6 ,Conversion data error flag 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RCINT5 ,Conversion data error flag 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RCINT4 ,Conversion data error flag 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCINT3 ,Conversion data error flag 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RCINT2 ,Conversion data error flag 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RCINT1 ,Conversion data error flag 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RCINT0 ,Conversion data error flag 0" "No interrupt,Interrupt"
|
|
group.byte 0x147++0x00
|
|
line.byte 0x00 "ADSCANS0,Scan Conversion Control Status Register 0"
|
|
bitfld.byte 0x00 7. " SCINT ,Scan conversion completion interrupt factor flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 6. " SCIE ,Scan conversion completion interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SCMD ,Continuous and stop scan conversion mode select" "Continuous,Stop"
|
|
group.byte 0x14B++0x00
|
|
line.byte 0x00 "ADNCS0,Activation Channel Conversion Count Setting Register 0"
|
|
bitfld.byte 0x00 7. " CNTEN1 ,Channel 1 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT1 ,Channel 1 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN0 ,Channel 0 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT0 ,Channel 0 conversion count specification" "1,2,3,4"
|
|
group.byte 0x14A++0x00
|
|
line.byte 0x00 "ADNCS1,Activation Channel Conversion Count Setting Register 1"
|
|
bitfld.byte 0x00 7. " CNTEN3 ,Channel 3 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT3 ,Channel 3 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN2 ,Channel 2 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT2 ,Channel 2 conversion count specification" "1,2,3,4"
|
|
group.byte 0x149++0x00
|
|
line.byte 0x00 "ADNCS2,Activation Channel Conversion Count Setting Register 2"
|
|
bitfld.byte 0x00 7. " CNTEN5 ,Channel 5 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT5 ,Channel 5 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN4 ,Channel 4 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT4 ,Channel 4 conversion count specification" "1,2,3,4"
|
|
group.byte 0x148++0x00
|
|
line.byte 0x00 "ADNCS3,Activation Channel Conversion Count Setting Register 3"
|
|
bitfld.byte 0x00 7. " CNTEN7 ,Channel 7 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT7 ,Channel 7 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN6 ,Channel 6 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT6 ,Channel 6 conversion count specification" "1,2,3,4"
|
|
group.byte 0x14F++0x00
|
|
line.byte 0x00 "ADNCS4,Activation Channel Conversion Count Setting Register 4"
|
|
bitfld.byte 0x00 7. " CNTEN9 ,Channel 9 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT9 ,Channel 9 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN8 ,Channel 8 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT8 ,Channel 8 conversion count specification" "1,2,3,4"
|
|
group.byte 0x14E++0x00
|
|
line.byte 0x00 "ADNCS5,Activation Channel Conversion Count Setting Register 5"
|
|
bitfld.byte 0x00 7. " CNTEN11 ,Channel 11 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT11 ,Channel 11 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN10 ,Channel 10 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT10 ,Channel 10 conversion count specification" "1,2,3,4"
|
|
group.byte 0x14D++0x00
|
|
line.byte 0x00 "ADNCS6,Activation Channel Conversion Count Setting Register 6"
|
|
bitfld.byte 0x00 7. " CNTEN13 ,Channel 13 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT13 ,Channel 13 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN12 ,Channel 12 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT12 ,Channel 12 conversion count specification" "1,2,3,4"
|
|
group.byte 0x14C++0x00
|
|
line.byte 0x00 "ADNCS7,Activation Channel Conversion Count Setting Register 7"
|
|
bitfld.byte 0x00 7. " CNTEN15 ,Channel 15 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT15 ,Channel 15 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN14 ,Channel 14 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT14 ,Channel 14 conversion count specification" "1,2,3,4"
|
|
group.byte 0x153++0x00
|
|
line.byte 0x00 "ADNCS8,Activation Channel Conversion Count Setting Register 8"
|
|
bitfld.byte 0x00 7. " CNTEN17 ,Channel 17 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT17 ,Channel 17 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN16 ,Channel 16 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT16 ,Channel 16 conversion count specification" "1,2,3,4"
|
|
group.byte 0x152++0x00
|
|
line.byte 0x00 "ADNCS9,Activation Channel Conversion Count Setting Register 9"
|
|
bitfld.byte 0x00 7. " CNTEN19 ,Channel 19 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT19 ,Channel 19 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN18 ,Channel 18 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT18 ,Channel 18 conversion count specification" "1,2,3,4"
|
|
group.byte 0x151++0x00
|
|
line.byte 0x00 "ADNCS10,Activation Channel Conversion Count Setting Register 10"
|
|
bitfld.byte 0x00 7. " CNTEN21 ,Channel 21 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT21 ,Channel 21 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN20 ,Channel 20 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT20 ,Channel 20 conversion count specification" "1,2,3,4"
|
|
group.byte 0x150++0x00
|
|
line.byte 0x00 "ADNCS11,Activation Channel Conversion Count Setting Register 11"
|
|
bitfld.byte 0x00 7. " CNTEN23 ,Channel 23 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT23 ,Channel 23 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN22 ,Channel 22 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT22 ,Channel 22 conversion count specification" "1,2,3,4"
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "ADNCS12,Activation Channel Conversion Count Setting Register 12"
|
|
bitfld.byte 0x00 7. " CNTEN25 ,Channel 25 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT25 ,Channel 25 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN24 ,Channel 24 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT24 ,Channel 24 conversion count specification" "1,2,3,4"
|
|
group.byte 0x156++0x00
|
|
line.byte 0x00 "ADNCS13,Activation Channel Conversion Count Setting Register 13"
|
|
bitfld.byte 0x00 7. " CNTEN27 ,Channel 27 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT27 ,Channel 27 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN26 ,Channel 26 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT26 ,Channel 26 conversion count specification" "1,2,3,4"
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "ADNCS14,Activation Channel Conversion Count Setting Register 14"
|
|
bitfld.byte 0x00 7. " CNTEN29 ,Channel 29 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT29 ,Channel 29 conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN28 ,Channel 28 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT28 ,Channel 28 conversion count specification" "1,2,3,4"
|
|
group.byte 0x154++0x00
|
|
line.byte 0x00 "ADNCS15,Activation Channel Conversion Count Setting Register 15"
|
|
bitfld.byte 0x00 7. " CNTEN31 ,Channel 31 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT31 ,Conversion count specification" "1,2,3,4"
|
|
bitfld.byte 0x00 3. " CNTEN30 ,Channel 30 conversion count specification scan conversion execution enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT30 ,Channel 30 onversion count specification" "1,2,3,4"
|
|
rgroup.long 0x158++0x07
|
|
line.long 0x00 "ADPRTF,Data Protection Status Flag Register"
|
|
bitfld.long 0x00 31. " PRTF31 ,Protected data state flag 31" "Not protected,Protected"
|
|
bitfld.long 0x00 30. " PRTF30 ,Protected data state flag 30" "Not protected,Protected"
|
|
bitfld.long 0x00 29. " PRTF29 ,Protected data state flag 29" "Not protected,Protected"
|
|
bitfld.long 0x00 28. " PRTF28 ,Protected data state flag 28" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PRTF27 ,Protected data state flag 27" "Not protected,Protected"
|
|
bitfld.long 0x00 26. " PRTF26 ,Protected data state flag 26" "Not protected,Protected"
|
|
bitfld.long 0x00 25. " PRTF25 ,Protected data state flag 25" "Not protected,Protected"
|
|
bitfld.long 0x00 24. " PRTF24 ,Protected data state flag 24" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PRTF23 ,Protected data state flag 23" "Not protected,Protected"
|
|
bitfld.long 0x00 22. " PRTF22 ,Protected data state flag 22" "Not protected,Protected"
|
|
bitfld.long 0x00 21. " PRTF21 ,Protected data state flag 21" "Not protected,Protected"
|
|
bitfld.long 0x00 20. " PRTF20 ,Protected data state flag 20" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PRTF19 ,Protected data state flag 19" "Not protected,Protected"
|
|
bitfld.long 0x00 18. " PRTF18 ,Protected data state flag 18" "Not protected,Protected"
|
|
bitfld.long 0x00 17. " PRTF17 ,Protected data state flag 17" "Not protected,Protected"
|
|
bitfld.long 0x00 16. " PRTF16 ,Protected data state flag 16" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PRTF15 ,Protected data state flag 15" "Not protected,Protected"
|
|
bitfld.long 0x00 14. " PRTF14 ,Protected data state flag 14" "Not protected,Protected"
|
|
bitfld.long 0x00 13. " PRTF13 ,Protected data state flag 13" "Not protected,Protected"
|
|
bitfld.long 0x00 12. " PRTF12 ,Protected data state flag 12" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PRTF11 ,Protected data state flag 11" "Not protected,Protected"
|
|
bitfld.long 0x00 10. " PRTF10 ,Protected data state flag 10" "Not protected,Protected"
|
|
bitfld.long 0x00 9. " PRTF9 ,Protected data state flag 9" "Not protected,Protected"
|
|
bitfld.long 0x00 8. " PRTF8 ,Protected data state flag 8" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PRTF7 ,Protected data state flag 7" "Not protected,Protected"
|
|
bitfld.long 0x00 6. " PRTF6 ,Protected data state flag 6" "Not protected,Protected"
|
|
bitfld.long 0x00 5. " PRTF5 ,Protected data state flag 5" "Not protected,Protected"
|
|
bitfld.long 0x00 4. " PRTF4 ,Protected data state flag 4" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PRTF3 ,Protected data state flag 3" "Not protected,Protected"
|
|
bitfld.long 0x00 2. " PRTF2 ,Protected data state flag 2" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " PRTF1 ,Protected data state flag 1" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " PRTF0 ,Protected data state flag 0" "Not protected,Protected"
|
|
line.long 0x04 "ADEOCF,Activation Channel Conversion Completion Flag Register"
|
|
bitfld.long 0x04 31. " EOCF31 ,Conversion count completion flag 31" "Not completed,Completed"
|
|
bitfld.long 0x04 30. " EOCF30 ,Conversion count completion flag 30" "Not completed,Completed"
|
|
bitfld.long 0x04 29. " EOCF29 ,Conversion count completion flag 29" "Not completed,Completed"
|
|
bitfld.long 0x04 28. " EOCF28 ,Conversion count completion flag 28" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x04 27. " EOCF27 ,Conversion count completion flag 27" "Not completed,Completed"
|
|
bitfld.long 0x04 26. " EOCF26 ,Conversion count completion flag 26" "Not completed,Completed"
|
|
bitfld.long 0x04 25. " EOCF25 ,Conversion count completion flag 25" "Not completed,Completed"
|
|
bitfld.long 0x04 24. " EOCF24 ,Conversion count completion flag 24" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x04 23. " EOCF23 ,Conversion count completion flag 23" "Not completed,Completed"
|
|
bitfld.long 0x04 22. " EOCF22 ,Conversion count completion flag 22" "Not completed,Completed"
|
|
bitfld.long 0x04 21. " EOCF21 ,Conversion count completion flag 21" "Not completed,Completed"
|
|
bitfld.long 0x04 20. " EOCF20 ,Conversion count completion flag 20" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x04 19. " EOCF19 ,Conversion count completion flag 19" "Not completed,Completed"
|
|
bitfld.long 0x04 18. " EOCF18 ,Conversion count completion flag 18" "Not completed,Completed"
|
|
bitfld.long 0x04 17. " EOCF17 ,Conversion count completion flag 17" "Not completed,Completed"
|
|
bitfld.long 0x04 16. " EOCF16 ,Conversion count completion flag 16" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x04 15. " EOCF15 ,Conversion count completion flag 15" "Not completed,Completed"
|
|
bitfld.long 0x04 14. " EOCF14 ,Conversion count completion flag 14" "Not completed,Completed"
|
|
bitfld.long 0x04 13. " EOCF13 ,Conversion count completion flag 13" "Not completed,Completed"
|
|
bitfld.long 0x04 12. " EOCF12 ,Conversion count completion flag 12" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EOCF11 ,Conversion count completion flag 11" "Not completed,Completed"
|
|
bitfld.long 0x04 10. " EOCF10 ,Conversion count completion flag 10" "Not completed,Completed"
|
|
bitfld.long 0x04 9. " EOCF9 ,Conversion count completion flag 9" "Not completed,Completed"
|
|
bitfld.long 0x04 8. " EOCF8 ,Conversion count completion flag 8" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EOCF7 ,Conversion count completion flag 7" "Not completed,Completed"
|
|
bitfld.long 0x04 6. " EOCF6 ,Conversion count completion flag 6" "Not completed,Completed"
|
|
bitfld.long 0x04 5. " EOCF5 ,Conversion count completion flag 5" "Not completed,Completed"
|
|
bitfld.long 0x04 4. " EOCF4 ,Conversion count completion flag 4" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EOCF3 ,Conversion count completion flag 3" "Not completed,Completed"
|
|
bitfld.long 0x04 2. " EOCF2 ,Conversion count completion flag 2" "Not completed,Completed"
|
|
bitfld.long 0x04 1. " EOCF1 ,Conversion count completion flag 1" "Not completed,Completed"
|
|
bitfld.long 0x04 0. " EOCF0 ,Conversion count completion flag 0" "Not completed,Completed"
|
|
wgroup.word 0x162++0x01
|
|
line.word 0x00 "ADTCSC0,A/D Activation Trigger Control Status Clear Register 0"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x160++0x01
|
|
line.word 0x00 "ADTCSC1,A/D Activation Trigger Control Status Clear Register 1"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x166++0x01
|
|
line.word 0x00 "ADTCSC2,A/D Activation Trigger Control Status Clear Register 2"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x164++0x01
|
|
line.word 0x00 "ADTCSC3,A/D Activation Trigger Control Status Clear Register 3"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x16A++0x01
|
|
line.word 0x00 "ADTCSC4,A/D Activation Trigger Control Status Clear Register 4"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x168++0x01
|
|
line.word 0x00 "ADTCSC5,A/D Activation Trigger Control Status Clear Register 5"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x16E++0x01
|
|
line.word 0x00 "ADTCSC6,A/D Activation Trigger Control Status Clear Register 6"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x16C++0x01
|
|
line.word 0x00 "ADTCSC7,A/D Activation Trigger Control Status Clear Register 7"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x172++0x01
|
|
line.word 0x00 "ADTCSC8,A/D Activation Trigger Control Status Clear Register 8"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x170++0x01
|
|
line.word 0x00 "ADTCSC9,A/D Activation Trigger Control Status Clear Register 9"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x176++0x01
|
|
line.word 0x00 "ADTCSC10,A/D Activation Trigger Control Status Clear Register 10"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x174++0x01
|
|
line.word 0x00 "ADTCSC11,A/D Activation Trigger Control Status Clear Register 11"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x17A++0x01
|
|
line.word 0x00 "ADTCSC12,A/D Activation Trigger Control Status Clear Register 12"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x178++0x01
|
|
line.word 0x00 "ADTCSC13,A/D Activation Trigger Control Status Clear Register 13"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x17E++0x01
|
|
line.word 0x00 "ADTCSC14,A/D Activation Trigger Control Status Clear Register 14"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x17C++0x01
|
|
line.word 0x00 "ADTCSC15,A/D Activation Trigger Control Status Clear Register 15"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x182++0x01
|
|
line.word 0x00 "ADTCSC16,A/D Activation Trigger Control Status Clear Register 16"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x180++0x01
|
|
line.word 0x00 "ADTCSC17,A/D Activation Trigger Control Status Clear Register 17"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x186++0x01
|
|
line.word 0x00 "ADTCSC18,A/D Activation Trigger Control Status Clear Register 18"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x184++0x01
|
|
line.word 0x00 "ADTCSC19,A/D Activation Trigger Control Status Clear Register 19"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x18A++0x01
|
|
line.word 0x00 "ADTCSC20,A/D Activation Trigger Control Status Clear Register 20"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x188++0x01
|
|
line.word 0x00 "ADTCSC21,A/D Activation Trigger Control Status Clear Register 21"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x18E++0x01
|
|
line.word 0x00 "ADTCSC22,A/D Activation Trigger Control Status Clear Register 22"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x18C++0x01
|
|
line.word 0x00 "ADTCSC23,A/D Activation Trigger Control Status Clear Register 23"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x192++0x01
|
|
line.word 0x00 "ADTCSC24,A/D Activation Trigger Control Status Clear Register 24"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x190++0x01
|
|
line.word 0x00 "ADTCSC25,A/D Activation Trigger Control Status Clear Register 25"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x196++0x01
|
|
line.word 0x00 "ADTCSC26,A/D Activation Trigger Control Status Clear Register 26"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x194++0x01
|
|
line.word 0x00 "ADTCSC27,A/D Activation Trigger Control Status Clear Register 27"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x19A++0x01
|
|
line.word 0x00 "ADTCSC28,A/D Activation Trigger Control Status Clear Register 28"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x198++0x01
|
|
line.word 0x00 "ADTCSC29,A/D Activation Trigger Control Status Clear Register 29"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x19E++0x01
|
|
line.word 0x00 "ADTCSC30,A/D Activation Trigger Control Status Clear Register 30"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.word 0x19C++0x01
|
|
line.word 0x00 "ADTCSC31,A/D Activation Trigger Control Status Clear Register 31"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request in progress clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,Interrupt request flag clear" "No effect,Clear"
|
|
bitfld.word 0x00 13. " INTEC ,Interrupt request enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 10. " RPTC ,Repeat conversion selection clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PRTC ,A/D data register protection enable clear" "No effect,Clear"
|
|
bitfld.word 0x00 8. " PRTSC ,A/D data register protection clear selection clear" "No effect,Clear"
|
|
bitfld.word 0x00 5. " BUFXC ,Compare register buffer function control clear" "No effect,Clear"
|
|
bitfld.word 0x00 4. " BTSC ,Compare register buffer transfer control clear" "No effect,Clear"
|
|
wgroup.long 0x1A0++0x03
|
|
line.long 0x00 "ADRCIFC,Range Compare Flag Clear Register"
|
|
bitfld.long 0x00 31. " RCINTC31 ,Conversion data error flag 31 clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " RCINTC30 ,Conversion data error flag 30 clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " RCINTC29 ,Conversion data error flag 29 clear" "No effect,Clear"
|
|
bitfld.long 0x00 28. " RCINTC28 ,Conversion data error flag 28 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " RCINTC27 ,Conversion data error flag 27 clear" "No effect,Clear"
|
|
bitfld.long 0x00 26. " RCINTC26 ,Conversion data error flag 26 clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " RCINTC25 ,Conversion data error flag 25 clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " RCINTC24 ,Conversion data error flag 24 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " RCINTC23 ,Conversion data error flag 23 clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " RCINTC22 ,Conversion data error flag 22 clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " RCINTC21 ,Conversion data error flag 21 clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " RCINTC20 ,Conversion data error flag 20 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCINTC19 ,Conversion data error flag 19 clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " RCINTC18 ,Conversion data error flag 18 clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " RCINTC17 ,Conversion data error flag 17 clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " RCINTC16 ,Conversion data error flag 16 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RCINTC15 ,Conversion data error flag 15 clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " RCINTC14 ,Conversion data error flag 14 clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " RCINTC13 ,Conversion data error flag 13 clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " RCINTC12 ,Conversion data error flag 12 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCINTC11 ,Conversion data error flag 11 clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " RCINTC10 ,Conversion data error flag 10 clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " RCINTC9 ,Conversion data error flag 9 clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RCINTC8 ,Conversion data error flag 8 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCINTC7 ,Conversion data error flag 7 clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " RCINTC6 ,Conversion data error flag 6 clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " RCINTC5 ,Conversion data error flag 5 clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " RCINTC4 ,Conversion data error flag 4 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCINTC3 ,Conversion data error flag 3 clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " RCINTC2 ,Conversion data error flag 2 clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RCINTC1 ,Conversion data error flag 1 clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " RCINTC0 ,Conversion data error flag 0 clear" "No effect,Clear"
|
|
wgroup.byte 0x1A7++0x00
|
|
line.byte 0x00 "ADSCANSC0,Scan Conversion Control Status Clear Register 0"
|
|
bitfld.byte 0x00 7. " SCINTC ,Scan conversion completion interrupt factor flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " SCIEC ,Scan conversion completion interrupt request enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " SCMDC ,Continuous and stop scan conversion mode select clear" "No effect,Clear"
|
|
wgroup.word 0x1BE++0x01
|
|
line.word 0x00 "ADTCSS0,A/D Activation Trigger Control Status Set Register 0"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1BC++0x01
|
|
line.word 0x00 "ADTCSS1,A/D Activation Trigger Control Status Set Register 1"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1C2++0x01
|
|
line.word 0x00 "ADTCSS2,A/D Activation Trigger Control Status Set Register 2"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1C0++0x01
|
|
line.word 0x00 "ADTCSS3,A/D Activation Trigger Control Status Set Register 3"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1C6++0x01
|
|
line.word 0x00 "ADTCSS4,A/D Activation Trigger Control Status Set Register 4"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1C4++0x01
|
|
line.word 0x00 "ADTCSS5,A/D Activation Trigger Control Status Set Register 5"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0xCA++0x01
|
|
line.word 0x00 "ADTCSS6,A/D Activation Trigger Control Status Set Register 6"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1C8++0x01
|
|
line.word 0x00 "ADTCSS7,A/D Activation Trigger Control Status Set Register 7"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1CE++0x01
|
|
line.word 0x00 "ADTCSS8,A/D Activation Trigger Control Status Set Register 8"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1CC++0x01
|
|
line.word 0x00 "ADTCSS9,A/D Activation Trigger Control Status Set Register 9"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1D2++0x01
|
|
line.word 0x00 "ADTCSS10,A/D Activation Trigger Control Status Set Register 10"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1D0++0x01
|
|
line.word 0x00 "ADTCSS11,A/D Activation Trigger Control Status Set Register 11"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1D6++0x01
|
|
line.word 0x00 "ADTCSS12,A/D Activation Trigger Control Status Set Register 12"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1D4++0x01
|
|
line.word 0x00 "ADTCSS13,A/D Activation Trigger Control Status Set Register 13"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1DA++0x01
|
|
line.word 0x00 "ADTCSS14,A/D Activation Trigger Control Status Set Register 14"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1D8++0x01
|
|
line.word 0x00 "ADTCSS15,A/D Activation Trigger Control Status Set Register 15"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1DE++0x01
|
|
line.word 0x00 "ADTCSS16,A/D Activation Trigger Control Status Set Register 16"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1DC++0x01
|
|
line.word 0x00 "ADTCSS17,A/D Activation Trigger Control Status Set Register 17"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1E2++0x01
|
|
line.word 0x00 "ADTCSS18,A/D Activation Trigger Control Status Set Register 18"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1E0++0x01
|
|
line.word 0x00 "ADTCSS19,A/D Activation Trigger Control Status Set Register 19"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1E6++0x01
|
|
line.word 0x00 "ADTCSS20,A/D Activation Trigger Control Status Set Register 20"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1E4++0x01
|
|
line.word 0x00 "ADTCSS21,A/D Activation Trigger Control Status Set Register 21"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1EA++0x01
|
|
line.word 0x00 "ADTCSS22,A/D Activation Trigger Control Status Set Register 22"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1E8++0x01
|
|
line.word 0x00 "ADTCSS23,A/D Activation Trigger Control Status Set Register 23"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1EE++0x01
|
|
line.word 0x00 "ADTCSS24,A/D Activation Trigger Control Status Set Register 24"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1EC++0x01
|
|
line.word 0x00 "ADTCSS25,A/D Activation Trigger Control Status Set Register 25"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1F2++0x01
|
|
line.word 0x00 "ADTCSS26,A/D Activation Trigger Control Status Set Register 26"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1F0++0x01
|
|
line.word 0x00 "ADTCSS27,A/D Activation Trigger Control Status Set Register 27"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1F6++0x01
|
|
line.word 0x00 "ADTCSS28,A/D Activation Trigger Control Status Set Register 28"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1F4++0x01
|
|
line.word 0x00 "ADTCSS29,A/D Activation Trigger Control Status Set Register 29"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1FA++0x01
|
|
line.word 0x00 "ADTCSS30,A/D Activation Trigger Control Status Set Register 30"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.word 0x1F8++0x01
|
|
line.word 0x00 "ADTCSS31,A/D Activation Trigger Control Status Set Register 31"
|
|
bitfld.word 0x00 13. " INTES ,Interrupt request enable set" "No effect,Set"
|
|
bitfld.word 0x00 10. " RPTS ,A/D data register protection enable set" "No effect,Set"
|
|
bitfld.word 0x00 9. " PRTS ,Repeat conversion selection set" "No effect,Set"
|
|
bitfld.word 0x00 8. " PRTSS ,A/D data register protection clear selection set" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFXS ,Compare register buffer function control set" "No effect,Set"
|
|
bitfld.word 0x00 4. " BTSS ,Compare register buffer transfer control set" "No effect,Set"
|
|
wgroup.byte 0x1FF++0x00
|
|
line.byte 0x00 "ADSCANSS0,Scan Conversion Control Status Set Register 0"
|
|
bitfld.byte 0x00 6. " SCIES ,Scan conversion completion interrupt request enable set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " SCMDS ,Continuous and stop scan conversion mode select set" "No effect,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "WFG (Waveform Generator)"
|
|
tree "Unit 00"
|
|
base ad:0xB2000400
|
|
width 17.
|
|
group.word 0x006++0x01
|
|
line.word 0x00 "WFG00_TMRR0,16-bit Dead Timer Register 0"
|
|
group.word 0x004++0x01
|
|
line.word 0x00 "WFG00_TMRR1,16-bit Dead Timer Register 1"
|
|
group.word 0x00A++0x01
|
|
line.word 0x00 "WFG00_TMRR2,16-bit Dead Timer Register 2"
|
|
group.byte 0x00F++0x00
|
|
line.byte 0x00 "WFG00_DTCR0,16-bit Dead Timer State Control Register 0"
|
|
bitfld.byte 0x00 7. " DMOD0 ,Output polarity control" "Normal,Inverted"
|
|
bitfld.byte 0x00 6. " GTEN1 ,GATE signal control bit 1" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 5. " GTEN0 ,GATE signal control bit 0" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 4. " TMIF0 , Interrupt request flag" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIE0 ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " TMD[2:0] ,Operation mode" "Output,Output/PPG,Timer,Disabled,Dead time timer,Disabled,Disabled,Disabled"
|
|
group.byte 0x00E++0x00
|
|
line.byte 0x00 "WFG00_DTCR1,16-bit Dead Timer State Control Register 1"
|
|
bitfld.byte 0x00 7. " DMOD1 ,Output polarity control" "Normal,Inverted"
|
|
bitfld.byte 0x00 6. " GTEN3 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 5. " GTEN2 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 4. " TMIF1 , Interrupt request flag" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIE1 ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " TMD[5:3] ,Operation mode" "Output,Output/PPG,Timer,Disabled,Dead time timer,Disabled,Disabled,Disabled"
|
|
group.byte 0x00D++0x00
|
|
line.byte 0x00 "WFG00_DTCR2,16-bit Dead Timer State Control Register 2"
|
|
bitfld.byte 0x00 7. " DMOD2 ,Output polarity control" "Normal,Inverted"
|
|
bitfld.byte 0x00 6. " GTEN5 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 5. " GTEN4 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 4. " TMIF2 , Interrupt request flag" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIE2 ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " TMD[8:6] ,Operation mode" "Output,Output/PPG,Timer,Disabled,Dead time timer,Disabled,Disabled,Disabled"
|
|
group.byte 0x012++0x00
|
|
line.byte 0x00 "WFG00_DTIR,16-bit Dead Timer Reload Interrupt Register"
|
|
bitfld.byte 0x00 7. " DTRIF2 ,16-bit dead timer 2 reload interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 6. " DTRIE2 ,16-bit dead timer 2 reload interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTRIF1 ,16-bit dead timer 1 reload interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 4. " DTRIE1 ,16-bit dead timer 1 reload interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DTRIF0 ,16-bit dead timer 0 reload interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " DTRIE0 ,16-bit dead timer 1 reload interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x010++0x00
|
|
line.byte 0x00 "WFG00_DTMNS,16-bit Dead Timer Minus Control Register"
|
|
bitfld.byte 0x00 6.--7. " KEY[1:0] ,Key enable bits" "0,1,2,3"
|
|
bitfld.byte 0x00 2. " MNS2 ,Dead timer function selection for RTO4 and RTO5" "Not executed,Executed"
|
|
bitfld.byte 0x00 1. " MNS1 ,Dead timer function selection for RTO2 and RTO3" "Not executed,Executed"
|
|
bitfld.byte 0x00 0. " MNS0 ,Dead timer function selection for RTO0 and RTO1" "Not executed,Executed"
|
|
group.byte 0x016++0x00
|
|
line.byte 0x00 "WFG00_SIGCR1,Waveform Control Register 1"
|
|
bitfld.byte 0x00 7. " DTIE ,DTTI input validating" "Invalid,Valid"
|
|
bitfld.byte 0x00 6. " DTIF ,DTTI interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 5. " NRSL ,Noise cancel function validating" "Invalid,Valid"
|
|
bitfld.byte 0x00 2.--4. " DCK[2:0] ,Operating clock selection bits" "1,/2,/4,/8,/16,/32,/64,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " NWS[1:0] ,DTTI noise width selection bits" "4,8,16,32"
|
|
group.byte 0x014++0x00
|
|
line.byte 0x00 "WFG00_SIGCR2,Waveform Control Register 2"
|
|
bitfld.byte 0x00 6.--7. " PSEL2[1:0] ,PPG input channel selection for RTO4 and RTO5" "PPG0,PPG2,PPG4,?..."
|
|
bitfld.byte 0x00 4.--5. " PSEL1[1:0] ,PPG input channel selection for RTO2 and RTO3" "PPG0,PPG2,PPG4,?..."
|
|
bitfld.byte 0x00 2.--3. " PSEL0[1:0] ,PPG input channel selection for RTO0 and RTO1" "PPG0,PPG2,PPG4,?..."
|
|
bitfld.byte 0x00 0. " DTTI ,Software DTTI" "Set,Clear"
|
|
group.byte 0x01B++0x00
|
|
line.byte 0x00 "WFG00_PICS,PPG Output Control Register"
|
|
bitfld.byte 0x00 7. " PGEN5 ,Enable PPG output to the RTO5" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PGEN4 ,Enable PPG output to the RTO4" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " PGEN3 ,Enable PPG output to the RTO3" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PGEN2 ,Enable PPG output to the RTO2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PGEN1 ,Enable PPG output to the RTO1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " PGEN0 ,Enable PPG output to the RTO0" "Disabled,Enabled"
|
|
wgroup.byte 0x01F++0x00
|
|
line.byte 0x00 "WFG00_DTCRC0,16-bit Dead Timer State Control Clear Register 0"
|
|
bitfld.byte 0x00 7. " DMODC0 ,Output polarity control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " GTENC1 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " GTENC0 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TMIFC0 ,Interrupt request flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIEC0 ,Interrupt request enable clear" "No effect,Clear"
|
|
wgroup.byte 0x01E++0x00
|
|
line.byte 0x00 "WFG00_DTCRC1,16-bit Dead Timer State Control Clear Register 1"
|
|
bitfld.byte 0x00 7. " DMODC1 ,Output polarity control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " GTENC3 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " GTENC2 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TMIFC1 ,Interrupt request flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIEC1 ,Interrupt request enable clear" "No effect,Clear"
|
|
wgroup.byte 0x01D++0x00
|
|
line.byte 0x00 "WFG00_DTCRC2,16-bit Dead Timer State Control Clear Register 2"
|
|
bitfld.byte 0x00 7. " DMODC2 ,Output polarity control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " GTENC5 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " GTENC4 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TMIFC2 ,Interrupt request flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIEC2 , Interrupt request enable clear" "No effect,Clear"
|
|
wgroup.byte 0x022++0x00
|
|
line.byte 0x00 "WFG00_DTIRC,16-bit Dead Timer Reload Interrupt Clear Register"
|
|
bitfld.byte 0x00 7. " DTRIFC2 ,16-bit dead timer 2 reload interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " DTRIEC2 ,16-bit dead timer 2 reload interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " DTRIFC1 ,16-bit dead timer 1 reload interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " DTRIEC1 ,16-bit dead timer 1 reload interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DTRIFC0 ,16-bit dead timer 0 reload interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " DTRIEC0 ,16-bit dead timer 0 reload interrupt enable clear" "No effect,Clear"
|
|
wgroup.byte 0x026++0x00
|
|
line.byte 0x00 "WFG00_SIGCR1C,Waveform Control Clear Register 1"
|
|
bitfld.byte 0x00 7. " DTIEC ,DTTI input validating clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " DTIFC ,DTTI Interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " NRSLC ,Noise cancel function validating clear" "No effect,Clear"
|
|
wgroup.byte 0x02B++0x00
|
|
line.byte 0x00 "WFG00_DTCRS0,16-bit Dead Timer State Control Set Register 0"
|
|
bitfld.byte 0x00 7. " DMODS0 ,Output polarity control set" "No effect,Set"
|
|
bitfld.byte 0x00 6. " GTENS1 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " GTENS0 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 3. " TMIES0 ,Interrupt request enable set" "No effect,Set"
|
|
wgroup.byte 0x02A++0x00
|
|
line.byte 0x00 "WFG00_DTCRS1,16-bit Dead Timer State Control Set Register 1"
|
|
bitfld.byte 0x00 7. " DMODS1 ,Output polarity control set bit" "No effect,Set"
|
|
bitfld.byte 0x00 6. " GTENS3 ,GATE signal control set bit" "No effect,Set"
|
|
bitfld.byte 0x00 5. " GTENS2 ,GATE signal control set bit" "No effect,Set"
|
|
bitfld.byte 0x00 3. " TMIES1 ,Interrupt request enable set" "No effect,Set"
|
|
wgroup.byte 0x029++0x00
|
|
line.byte 0x00 "WFG00_DTCRS2,16-bit Dead Timer State Control Set Register 2"
|
|
bitfld.byte 0x00 7. " DMODS2 ,Output polarity control set" "No effect,Set"
|
|
bitfld.byte 0x00 6. " GTENS5 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " GTENS4 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 3. " TMIES2 ,Interrupt request enable set" "No effect,Set"
|
|
wgroup.byte 0x02E++0x00
|
|
line.byte 0x00 "WFG00_DTIRS,16-bit Dead Timer Reload Interrupt Set Register"
|
|
bitfld.byte 0x00 6. " DTRIES2 ,16-bit dead timer 2 reload interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 4. " DTRIES1 ,16-bit dead timer 1 reload interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 2. " DTRIES0 ,16-bit dead timer 0 reload interrupt enable set" "No effect,Set"
|
|
wgroup.byte 0x032++0x00
|
|
line.byte 0x00 "WFG00_SIGCR1S,Waveform Control Set Register 1"
|
|
bitfld.byte 0x00 7. " DTIES ,DTTI input validating set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " NRSLS ,Noise cancel function validating set" "No effect,Set"
|
|
group.byte (0x00-0xFEE400)++0x00
|
|
line.byte 0x00 "RTOSEL0, Output Level Conversion Register 0"
|
|
bitfld.byte 0x00 5. " OSEL5 ,Output polarity control bit 5" "Normal,Inverted"
|
|
bitfld.byte 0x00 4. " OSEL4 ,Output polarity control bit 4" "Normal,Inverted"
|
|
bitfld.byte 0x00 3. " OSEL3 ,Output polarity control bit 3" "Normal,Inverted"
|
|
bitfld.byte 0x00 2. " OSEL2 ,Output polarity control bit 2" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OSEL1 ,Output polarity control bit 1" "Normal,Inverted"
|
|
bitfld.byte 0x00 0. " OSEL0 ,Output polarity control bit 0" "Normal,Inverted"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 01"
|
|
base ad:0xB1000400
|
|
width 17.
|
|
group.word 0x006++0x01
|
|
line.word 0x00 "WFG01_TMRR0,16-bit Dead Timer Register 0"
|
|
group.word 0x004++0x01
|
|
line.word 0x00 "WFG01_TMRR1,16-bit Dead Timer Register 1"
|
|
group.word 0x00A++0x01
|
|
line.word 0x00 "WFG01_TMRR2,16-bit Dead Timer Register 2"
|
|
group.byte 0x00F++0x00
|
|
line.byte 0x00 "WFG01_DTCR0,16-bit Dead Timer State Control Register 0"
|
|
bitfld.byte 0x00 7. " DMOD0 ,Output polarity control" "Normal,Inverted"
|
|
bitfld.byte 0x00 6. " GTEN1 ,GATE signal control bit 1" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 5. " GTEN0 ,GATE signal control bit 0" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 4. " TMIF0 , Interrupt request flag" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIE0 ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " TMD[2:0] ,Operation mode" "Output,Output/PPG,Timer,Disabled,Dead time timer,Disabled,Disabled,Disabled"
|
|
group.byte 0x00E++0x00
|
|
line.byte 0x00 "WFG01_DTCR1,16-bit Dead Timer State Control Register 1"
|
|
bitfld.byte 0x00 7. " DMOD1 ,Output polarity control" "Normal,Inverted"
|
|
bitfld.byte 0x00 6. " GTEN3 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 5. " GTEN2 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 4. " TMIF1 , Interrupt request flag" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIE1 ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " TMD[5:3] ,Operation mode" "Output,Output/PPG,Timer,Disabled,Dead time timer,Disabled,Disabled,Disabled"
|
|
group.byte 0x00D++0x00
|
|
line.byte 0x00 "WFG01_DTCR2,16-bit Dead Timer State Control Register 2"
|
|
bitfld.byte 0x00 7. " DMOD2 ,Output polarity control" "Normal,Inverted"
|
|
bitfld.byte 0x00 6. " GTEN5 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 5. " GTEN4 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 4. " TMIF2 , Interrupt request flag" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIE2 ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " TMD[8:6] ,Operation mode" "Output,Output/PPG,Timer,Disabled,Dead time timer,Disabled,Disabled,Disabled"
|
|
group.byte 0x012++0x00
|
|
line.byte 0x00 "WFG01_DTIR,16-bit Dead Timer Reload Interrupt Register"
|
|
bitfld.byte 0x00 7. " DTRIF2 ,16-bit dead timer 2 reload interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 6. " DTRIE2 ,16-bit dead timer 2 reload interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTRIF1 ,16-bit dead timer 1 reload interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 4. " DTRIE1 ,16-bit dead timer 1 reload interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DTRIF0 ,16-bit dead timer 0 reload interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " DTRIE0 ,16-bit dead timer 1 reload interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x010++0x00
|
|
line.byte 0x00 "WFG01_DTMNS,16-bit Dead Timer Minus Control Register"
|
|
bitfld.byte 0x00 6.--7. " KEY[1:0] ,Key enable bits" "0,1,2,3"
|
|
bitfld.byte 0x00 2. " MNS2 ,Dead timer function selection for RTO4 and RTO5" "Not executed,Executed"
|
|
bitfld.byte 0x00 1. " MNS1 ,Dead timer function selection for RTO2 and RTO3" "Not executed,Executed"
|
|
bitfld.byte 0x00 0. " MNS0 ,Dead timer function selection for RTO0 and RTO1" "Not executed,Executed"
|
|
group.byte 0x016++0x00
|
|
line.byte 0x00 "WFG01_SIGCR1,Waveform Control Register 1"
|
|
bitfld.byte 0x00 7. " DTIE ,DTTI input validating" "Invalid,Valid"
|
|
bitfld.byte 0x00 6. " DTIF ,DTTI interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 5. " NRSL ,Noise cancel function validating" "Invalid,Valid"
|
|
bitfld.byte 0x00 2.--4. " DCK[2:0] ,Operating clock selection bits" "1,/2,/4,/8,/16,/32,/64,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " NWS[1:0] ,DTTI noise width selection bits" "4,8,16,32"
|
|
group.byte 0x014++0x00
|
|
line.byte 0x00 "WFG01_SIGCR2,Waveform Control Register 2"
|
|
bitfld.byte 0x00 6.--7. " PSEL2[1:0] ,PPG input channel selection for RTO4 and RTO5" "PPG0,PPG2,PPG4,?..."
|
|
bitfld.byte 0x00 4.--5. " PSEL1[1:0] ,PPG input channel selection for RTO2 and RTO3" "PPG0,PPG2,PPG4,?..."
|
|
bitfld.byte 0x00 2.--3. " PSEL0[1:0] ,PPG input channel selection for RTO0 and RTO1" "PPG0,PPG2,PPG4,?..."
|
|
bitfld.byte 0x00 0. " DTTI ,Software DTTI" "Set,Clear"
|
|
group.byte 0x01B++0x00
|
|
line.byte 0x00 "WFG01_PICS,PPG Output Control Register"
|
|
bitfld.byte 0x00 7. " PGEN5 ,Enable PPG output to the RTO5" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PGEN4 ,Enable PPG output to the RTO4" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " PGEN3 ,Enable PPG output to the RTO3" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PGEN2 ,Enable PPG output to the RTO2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PGEN1 ,Enable PPG output to the RTO1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " PGEN0 ,Enable PPG output to the RTO0" "Disabled,Enabled"
|
|
wgroup.byte 0x01F++0x00
|
|
line.byte 0x00 "WFG01_DTCRC0,16-bit Dead Timer State Control Clear Register 0"
|
|
bitfld.byte 0x00 7. " DMODC0 ,Output polarity control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " GTENC1 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " GTENC0 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TMIFC0 ,Interrupt request flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIEC0 ,Interrupt request enable clear" "No effect,Clear"
|
|
wgroup.byte 0x01E++0x00
|
|
line.byte 0x00 "WFG01_DTCRC1,16-bit Dead Timer State Control Clear Register 1"
|
|
bitfld.byte 0x00 7. " DMODC1 ,Output polarity control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " GTENC3 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " GTENC2 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TMIFC1 ,Interrupt request flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIEC1 ,Interrupt request enable clear" "No effect,Clear"
|
|
wgroup.byte 0x01D++0x00
|
|
line.byte 0x00 "WFG01_DTCRC2,16-bit Dead Timer State Control Clear Register 2"
|
|
bitfld.byte 0x00 7. " DMODC2 ,Output polarity control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " GTENC5 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " GTENC4 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TMIFC2 ,Interrupt request flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIEC2 , Interrupt request enable clear" "No effect,Clear"
|
|
wgroup.byte 0x022++0x00
|
|
line.byte 0x00 "WFG01_DTIRC,16-bit Dead Timer Reload Interrupt Clear Register"
|
|
bitfld.byte 0x00 7. " DTRIFC2 ,16-bit dead timer 2 reload interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " DTRIEC2 ,16-bit dead timer 2 reload interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " DTRIFC1 ,16-bit dead timer 1 reload interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " DTRIEC1 ,16-bit dead timer 1 reload interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DTRIFC0 ,16-bit dead timer 0 reload interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " DTRIEC0 ,16-bit dead timer 0 reload interrupt enable clear" "No effect,Clear"
|
|
wgroup.byte 0x026++0x00
|
|
line.byte 0x00 "WFG01_SIGCR1C,Waveform Control Clear Register 1"
|
|
bitfld.byte 0x00 7. " DTIEC ,DTTI input validating clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " DTIFC ,DTTI Interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " NRSLC ,Noise cancel function validating clear" "No effect,Clear"
|
|
wgroup.byte 0x02B++0x00
|
|
line.byte 0x00 "WFG01_DTCRS0,16-bit Dead Timer State Control Set Register 0"
|
|
bitfld.byte 0x00 7. " DMODS0 ,Output polarity control set" "No effect,Set"
|
|
bitfld.byte 0x00 6. " GTENS1 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " GTENS0 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 3. " TMIES0 ,Interrupt request enable set" "No effect,Set"
|
|
wgroup.byte 0x02A++0x00
|
|
line.byte 0x00 "WFG01_DTCRS1,16-bit Dead Timer State Control Set Register 1"
|
|
bitfld.byte 0x00 7. " DMODS1 ,Output polarity control set bit" "No effect,Set"
|
|
bitfld.byte 0x00 6. " GTENS3 ,GATE signal control set bit" "No effect,Set"
|
|
bitfld.byte 0x00 5. " GTENS2 ,GATE signal control set bit" "No effect,Set"
|
|
bitfld.byte 0x00 3. " TMIES1 ,Interrupt request enable set" "No effect,Set"
|
|
wgroup.byte 0x029++0x00
|
|
line.byte 0x00 "WFG01_DTCRS2,16-bit Dead Timer State Control Set Register 2"
|
|
bitfld.byte 0x00 7. " DMODS2 ,Output polarity control set" "No effect,Set"
|
|
bitfld.byte 0x00 6. " GTENS5 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " GTENS4 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 3. " TMIES2 ,Interrupt request enable set" "No effect,Set"
|
|
wgroup.byte 0x02E++0x00
|
|
line.byte 0x00 "WFG01_DTIRS,16-bit Dead Timer Reload Interrupt Set Register"
|
|
bitfld.byte 0x00 6. " DTRIES2 ,16-bit dead timer 2 reload interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 4. " DTRIES1 ,16-bit dead timer 1 reload interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 2. " DTRIES0 ,16-bit dead timer 0 reload interrupt enable set" "No effect,Set"
|
|
wgroup.byte 0x032++0x00
|
|
line.byte 0x00 "WFG01_SIGCR1S,Waveform Control Set Register 1"
|
|
bitfld.byte 0x00 7. " DTIES ,DTTI input validating set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " NRSLS ,Noise cancel function validating set" "No effect,Set"
|
|
group.byte 0x11C01++0x00
|
|
line.byte 0x00 "RTOSEL1,Output Level Conversion Register 1"
|
|
bitfld.byte 0x00 5. " OSEL5 ,Output polarity control bit 5" "Normal,Inverted"
|
|
bitfld.byte 0x00 4. " OSEL4 ,Output polarity control bit 4" "Normal,Inverted"
|
|
bitfld.byte 0x00 3. " OSEL3 ,Output polarity control bit 3" "Normal,Inverted"
|
|
bitfld.byte 0x00 2. " OSEL2 ,Output polarity control bit 2" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OSEL1 ,Output polarity control bit 1" "Normal,Inverted"
|
|
bitfld.byte 0x00 0. " OSEL0 ,Output polarity control bit 0" "Normal,Inverted"
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("MB9DF56?L*")
|
|
tree "Unit 02"
|
|
base ad:0xB1010600
|
|
width 17.
|
|
group.word 0x006++0x01
|
|
line.word 0x00 "WFG02_TMRR0,16-bit Dead Timer Register 0"
|
|
group.word 0x004++0x01
|
|
line.word 0x00 "WFG02_TMRR1,16-bit Dead Timer Register 1"
|
|
group.word 0x00A++0x01
|
|
line.word 0x00 "WFG02_TMRR2,16-bit Dead Timer Register 2"
|
|
group.byte 0x00F++0x00
|
|
line.byte 0x00 "WFG02_DTCR0,16-bit Dead Timer State Control Register 0"
|
|
bitfld.byte 0x00 7. " DMOD0 ,Output polarity control" "Normal,Inverted"
|
|
bitfld.byte 0x00 6. " GTEN1 ,GATE signal control bit 1" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 5. " GTEN0 ,GATE signal control bit 0" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 4. " TMIF0 , Interrupt request flag" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIE0 ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " TMD[2:0] ,Operation mode" "Output,Output/PPG,Timer,Disabled,Dead time timer,Disabled,Disabled,Disabled"
|
|
group.byte 0x00E++0x00
|
|
line.byte 0x00 "WFG02_DTCR1,16-bit Dead Timer State Control Register 1"
|
|
bitfld.byte 0x00 7. " DMOD1 ,Output polarity control" "Normal,Inverted"
|
|
bitfld.byte 0x00 6. " GTEN3 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 5. " GTEN2 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 4. " TMIF1 , Interrupt request flag" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIE1 ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " TMD[5:3] ,Operation mode" "Output,Output/PPG,Timer,Disabled,Dead time timer,Disabled,Disabled,Disabled"
|
|
group.byte 0x00D++0x00
|
|
line.byte 0x00 "WFG02_DTCR2,16-bit Dead Timer State Control Register 2"
|
|
bitfld.byte 0x00 7. " DMOD2 ,Output polarity control" "Normal,Inverted"
|
|
bitfld.byte 0x00 6. " GTEN5 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 5. " GTEN4 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 4. " TMIF2 , Interrupt request flag" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIE2 ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " TMD[8:6] ,Operation mode" "Output,Output/PPG,Timer,Disabled,Dead time timer,Disabled,Disabled,Disabled"
|
|
group.byte 0x012++0x00
|
|
line.byte 0x00 "WFG02_DTIR,16-bit Dead Timer Reload Interrupt Register"
|
|
bitfld.byte 0x00 7. " DTRIF2 ,16-bit dead timer 2 reload interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 6. " DTRIE2 ,16-bit dead timer 2 reload interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTRIF1 ,16-bit dead timer 1 reload interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 4. " DTRIE1 ,16-bit dead timer 1 reload interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DTRIF0 ,16-bit dead timer 0 reload interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " DTRIE0 ,16-bit dead timer 1 reload interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x010++0x00
|
|
line.byte 0x00 "WFG02_DTMNS,16-bit Dead Timer Minus Control Register"
|
|
bitfld.byte 0x00 6.--7. " KEY[1:0] ,Key enable bits" "0,1,2,3"
|
|
bitfld.byte 0x00 2. " MNS2 ,Dead timer function selection for RTO4 and RTO5" "Not executed,Executed"
|
|
bitfld.byte 0x00 1. " MNS1 ,Dead timer function selection for RTO2 and RTO3" "Not executed,Executed"
|
|
bitfld.byte 0x00 0. " MNS0 ,Dead timer function selection for RTO0 and RTO1" "Not executed,Executed"
|
|
group.byte 0x016++0x00
|
|
line.byte 0x00 "WFG02_SIGCR1,Waveform Control Register 1"
|
|
bitfld.byte 0x00 7. " DTIE ,DTTI input validating" "Invalid,Valid"
|
|
bitfld.byte 0x00 6. " DTIF ,DTTI interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 5. " NRSL ,Noise cancel function validating" "Invalid,Valid"
|
|
bitfld.byte 0x00 2.--4. " DCK[2:0] ,Operating clock selection bits" "1,/2,/4,/8,/16,/32,/64,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " NWS[1:0] ,DTTI noise width selection bits" "4,8,16,32"
|
|
group.byte 0x014++0x00
|
|
line.byte 0x00 "WFG02_SIGCR2,Waveform Control Register 2"
|
|
bitfld.byte 0x00 6.--7. " PSEL2[1:0] ,PPG input channel selection for RTO4 and RTO5" "PPG0,PPG2,PPG4,?..."
|
|
bitfld.byte 0x00 4.--5. " PSEL1[1:0] ,PPG input channel selection for RTO2 and RTO3" "PPG0,PPG2,PPG4,?..."
|
|
bitfld.byte 0x00 2.--3. " PSEL0[1:0] ,PPG input channel selection for RTO0 and RTO1" "PPG0,PPG2,PPG4,?..."
|
|
bitfld.byte 0x00 0. " DTTI ,Software DTTI" "Set,Clear"
|
|
group.byte 0x01B++0x00
|
|
line.byte 0x00 "WFG02_PICS,PPG Output Control Register"
|
|
bitfld.byte 0x00 7. " PGEN5 ,Enable PPG output to the RTO5" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PGEN4 ,Enable PPG output to the RTO4" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " PGEN3 ,Enable PPG output to the RTO3" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PGEN2 ,Enable PPG output to the RTO2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PGEN1 ,Enable PPG output to the RTO1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " PGEN0 ,Enable PPG output to the RTO0" "Disabled,Enabled"
|
|
wgroup.byte 0x01F++0x00
|
|
line.byte 0x00 "WFG02_DTCRC0,16-bit Dead Timer State Control Clear Register 0"
|
|
bitfld.byte 0x00 7. " DMODC0 ,Output polarity control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " GTENC1 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " GTENC0 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TMIFC0 ,Interrupt request flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIEC0 ,Interrupt request enable clear" "No effect,Clear"
|
|
wgroup.byte 0x01E++0x00
|
|
line.byte 0x00 "WFG02_DTCRC1,16-bit Dead Timer State Control Clear Register 1"
|
|
bitfld.byte 0x00 7. " DMODC1 ,Output polarity control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " GTENC3 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " GTENC2 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TMIFC1 ,Interrupt request flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIEC1 ,Interrupt request enable clear" "No effect,Clear"
|
|
wgroup.byte 0x01D++0x00
|
|
line.byte 0x00 "WFG02_DTCRC2,16-bit Dead Timer State Control Clear Register 2"
|
|
bitfld.byte 0x00 7. " DMODC2 ,Output polarity control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " GTENC5 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " GTENC4 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TMIFC2 ,Interrupt request flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIEC2 , Interrupt request enable clear" "No effect,Clear"
|
|
wgroup.byte 0x022++0x00
|
|
line.byte 0x00 "WFG02_DTIRC,16-bit Dead Timer Reload Interrupt Clear Register"
|
|
bitfld.byte 0x00 7. " DTRIFC2 ,16-bit dead timer 2 reload interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " DTRIEC2 ,16-bit dead timer 2 reload interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " DTRIFC1 ,16-bit dead timer 1 reload interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " DTRIEC1 ,16-bit dead timer 1 reload interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DTRIFC0 ,16-bit dead timer 0 reload interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " DTRIEC0 ,16-bit dead timer 0 reload interrupt enable clear" "No effect,Clear"
|
|
wgroup.byte 0x026++0x00
|
|
line.byte 0x00 "WFG02_SIGCR1C,Waveform Control Clear Register 1"
|
|
bitfld.byte 0x00 7. " DTIEC ,DTTI input validating clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " DTIFC ,DTTI Interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " NRSLC ,Noise cancel function validating clear" "No effect,Clear"
|
|
wgroup.byte 0x02B++0x00
|
|
line.byte 0x00 "WFG02_DTCRS0,16-bit Dead Timer State Control Set Register 0"
|
|
bitfld.byte 0x00 7. " DMODS0 ,Output polarity control set" "No effect,Set"
|
|
bitfld.byte 0x00 6. " GTENS1 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " GTENS0 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 3. " TMIES0 ,Interrupt request enable set" "No effect,Set"
|
|
wgroup.byte 0x02A++0x00
|
|
line.byte 0x00 "WFG02_DTCRS1,16-bit Dead Timer State Control Set Register 1"
|
|
bitfld.byte 0x00 7. " DMODS1 ,Output polarity control set bit" "No effect,Set"
|
|
bitfld.byte 0x00 6. " GTENS3 ,GATE signal control set bit" "No effect,Set"
|
|
bitfld.byte 0x00 5. " GTENS2 ,GATE signal control set bit" "No effect,Set"
|
|
bitfld.byte 0x00 3. " TMIES1 ,Interrupt request enable set" "No effect,Set"
|
|
wgroup.byte 0x029++0x00
|
|
line.byte 0x00 "WFG02_DTCRS2,16-bit Dead Timer State Control Set Register 2"
|
|
bitfld.byte 0x00 7. " DMODS2 ,Output polarity control set" "No effect,Set"
|
|
bitfld.byte 0x00 6. " GTENS5 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " GTENS4 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 3. " TMIES2 ,Interrupt request enable set" "No effect,Set"
|
|
wgroup.byte 0x02E++0x00
|
|
line.byte 0x00 "WFG02_DTIRS,16-bit Dead Timer Reload Interrupt Set Register"
|
|
bitfld.byte 0x00 6. " DTRIES2 ,16-bit dead timer 2 reload interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 4. " DTRIES1 ,16-bit dead timer 1 reload interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 2. " DTRIES0 ,16-bit dead timer 0 reload interrupt enable set" "No effect,Set"
|
|
wgroup.byte 0x032++0x00
|
|
line.byte 0x00 "WFG02_SIGCR1S,Waveform Control Set Register 1"
|
|
bitfld.byte 0x00 7. " DTIES ,DTTI input validating set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " NRSLS ,Noise cancel function validating set" "No effect,Set"
|
|
group.byte 0x1A02++0x00
|
|
line.byte 0x00 "RTOSEL2,Output Level Conversion Register 2"
|
|
bitfld.byte 0x00 5. " OSEL5 ,Output polarity control bit 5" "Normal,Inverted"
|
|
bitfld.byte 0x00 4. " OSEL4 ,Output polarity control bit 4" "Normal,Inverted"
|
|
bitfld.byte 0x00 3. " OSEL3 ,Output polarity control bit 3" "Normal,Inverted"
|
|
bitfld.byte 0x00 2. " OSEL2 ,Output polarity control bit 2" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OSEL1 ,Output polarity control bit 1" "Normal,Inverted"
|
|
bitfld.byte 0x00 0. " OSEL0 ,Output polarity control bit 0" "Normal,Inverted"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "Unit 03"
|
|
base ad:0xB1010640
|
|
width 17.
|
|
group.word 0x006++0x01
|
|
line.word 0x00 "WFG03_TMRR0,16-bit Dead Timer Register 0"
|
|
group.word 0x004++0x01
|
|
line.word 0x00 "WFG03_TMRR1,16-bit Dead Timer Register 1"
|
|
group.word 0x00A++0x01
|
|
line.word 0x00 "WFG03_TMRR2,16-bit Dead Timer Register 2"
|
|
group.byte 0x00F++0x00
|
|
line.byte 0x00 "WFG03_DTCR0,16-bit Dead Timer State Control Register 0"
|
|
bitfld.byte 0x00 7. " DMOD0 ,Output polarity control" "Normal,Inverted"
|
|
bitfld.byte 0x00 6. " GTEN1 ,GATE signal control bit 1" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 5. " GTEN0 ,GATE signal control bit 0" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 4. " TMIF0 , Interrupt request flag" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIE0 ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " TMD[2:0] ,Operation mode" "Output,Output/PPG,Timer,Disabled,Dead time timer,Disabled,Disabled,Disabled"
|
|
group.byte 0x00E++0x00
|
|
line.byte 0x00 "WFG03_DTCR1,16-bit Dead Timer State Control Register 1"
|
|
bitfld.byte 0x00 7. " DMOD1 ,Output polarity control" "Normal,Inverted"
|
|
bitfld.byte 0x00 6. " GTEN3 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 5. " GTEN2 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 4. " TMIF1 , Interrupt request flag" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIE1 ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " TMD[5:3] ,Operation mode" "Output,Output/PPG,Timer,Disabled,Dead time timer,Disabled,Disabled,Disabled"
|
|
group.byte 0x00D++0x00
|
|
line.byte 0x00 "WFG03_DTCR2,16-bit Dead Timer State Control Register 2"
|
|
bitfld.byte 0x00 7. " DMOD2 ,Output polarity control" "Normal,Inverted"
|
|
bitfld.byte 0x00 6. " GTEN5 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 5. " GTEN4 ,GATE signal control" "Asynchronous,Synchronous"
|
|
bitfld.byte 0x00 4. " TMIF2 , Interrupt request flag" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIE2 ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " TMD[8:6] ,Operation mode" "Output,Output/PPG,Timer,Disabled,Dead time timer,Disabled,Disabled,Disabled"
|
|
group.byte 0x012++0x00
|
|
line.byte 0x00 "WFG03_DTIR,16-bit Dead Timer Reload Interrupt Register"
|
|
bitfld.byte 0x00 7. " DTRIF2 ,16-bit dead timer 2 reload interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 6. " DTRIE2 ,16-bit dead timer 2 reload interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTRIF1 ,16-bit dead timer 1 reload interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 4. " DTRIE1 ,16-bit dead timer 1 reload interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DTRIF0 ,16-bit dead timer 0 reload interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " DTRIE0 ,16-bit dead timer 1 reload interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x010++0x00
|
|
line.byte 0x00 "WFG03_DTMNS,16-bit Dead Timer Minus Control Register"
|
|
bitfld.byte 0x00 6.--7. " KEY[1:0] ,Key enable bits" "0,1,2,3"
|
|
bitfld.byte 0x00 2. " MNS2 ,Dead timer function selection for RTO4 and RTO5" "Not executed,Executed"
|
|
bitfld.byte 0x00 1. " MNS1 ,Dead timer function selection for RTO2 and RTO3" "Not executed,Executed"
|
|
bitfld.byte 0x00 0. " MNS0 ,Dead timer function selection for RTO0 and RTO1" "Not executed,Executed"
|
|
group.byte 0x016++0x00
|
|
line.byte 0x00 "WFG03_SIGCR1,Waveform Control Register 1"
|
|
bitfld.byte 0x00 7. " DTIE ,DTTI input validating" "Invalid,Valid"
|
|
bitfld.byte 0x00 6. " DTIF ,DTTI interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 5. " NRSL ,Noise cancel function validating" "Invalid,Valid"
|
|
bitfld.byte 0x00 2.--4. " DCK[2:0] ,Operating clock selection bits" "1,/2,/4,/8,/16,/32,/64,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " NWS[1:0] ,DTTI noise width selection bits" "4,8,16,32"
|
|
group.byte 0x014++0x00
|
|
line.byte 0x00 "WFG03_SIGCR2,Waveform Control Register 2"
|
|
bitfld.byte 0x00 6.--7. " PSEL2[1:0] ,PPG input channel selection for RTO4 and RTO5" "PPG0,PPG2,PPG4,?..."
|
|
bitfld.byte 0x00 4.--5. " PSEL1[1:0] ,PPG input channel selection for RTO2 and RTO3" "PPG0,PPG2,PPG4,?..."
|
|
bitfld.byte 0x00 2.--3. " PSEL0[1:0] ,PPG input channel selection for RTO0 and RTO1" "PPG0,PPG2,PPG4,?..."
|
|
bitfld.byte 0x00 0. " DTTI ,Software DTTI" "Set,Clear"
|
|
group.byte 0x01B++0x00
|
|
line.byte 0x00 "WFG03_PICS,PPG Output Control Register"
|
|
bitfld.byte 0x00 7. " PGEN5 ,Enable PPG output to the RTO5" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PGEN4 ,Enable PPG output to the RTO4" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " PGEN3 ,Enable PPG output to the RTO3" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PGEN2 ,Enable PPG output to the RTO2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PGEN1 ,Enable PPG output to the RTO1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " PGEN0 ,Enable PPG output to the RTO0" "Disabled,Enabled"
|
|
wgroup.byte 0x01F++0x00
|
|
line.byte 0x00 "WFG03_DTCRC0,16-bit Dead Timer State Control Clear Register 0"
|
|
bitfld.byte 0x00 7. " DMODC0 ,Output polarity control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " GTENC1 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " GTENC0 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TMIFC0 ,Interrupt request flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIEC0 ,Interrupt request enable clear" "No effect,Clear"
|
|
wgroup.byte 0x01E++0x00
|
|
line.byte 0x00 "WFG03_DTCRC1,16-bit Dead Timer State Control Clear Register 1"
|
|
bitfld.byte 0x00 7. " DMODC1 ,Output polarity control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " GTENC3 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " GTENC2 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TMIFC1 ,Interrupt request flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIEC1 ,Interrupt request enable clear" "No effect,Clear"
|
|
wgroup.byte 0x01D++0x00
|
|
line.byte 0x00 "WFG03_DTCRC2,16-bit Dead Timer State Control Clear Register 2"
|
|
bitfld.byte 0x00 7. " DMODC2 ,Output polarity control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " GTENC5 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " GTENC4 ,GATE signal control clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TMIFC2 ,Interrupt request flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TMIEC2 , Interrupt request enable clear" "No effect,Clear"
|
|
wgroup.byte 0x022++0x00
|
|
line.byte 0x00 "WFG03_DTIRC,16-bit Dead Timer Reload Interrupt Clear Register"
|
|
bitfld.byte 0x00 7. " DTRIFC2 ,16-bit dead timer 2 reload interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " DTRIEC2 ,16-bit dead timer 2 reload interrupt enable clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " DTRIFC1 ,16-bit dead timer 1 reload interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " DTRIEC1 ,16-bit dead timer 1 reload interrupt enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DTRIFC0 ,16-bit dead timer 0 reload interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " DTRIEC0 ,16-bit dead timer 0 reload interrupt enable clear" "No effect,Clear"
|
|
wgroup.byte 0x026++0x00
|
|
line.byte 0x00 "WFG03_SIGCR1C,Waveform Control Clear Register 1"
|
|
bitfld.byte 0x00 7. " DTIEC ,DTTI input validating clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " DTIFC ,DTTI Interrupt flag clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " NRSLC ,Noise cancel function validating clear" "No effect,Clear"
|
|
wgroup.byte 0x02B++0x00
|
|
line.byte 0x00 "WFG03_DTCRS0,16-bit Dead Timer State Control Set Register 0"
|
|
bitfld.byte 0x00 7. " DMODS0 ,Output polarity control set" "No effect,Set"
|
|
bitfld.byte 0x00 6. " GTENS1 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " GTENS0 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 3. " TMIES0 ,Interrupt request enable set" "No effect,Set"
|
|
wgroup.byte 0x02A++0x00
|
|
line.byte 0x00 "WFG03_DTCRS1,16-bit Dead Timer State Control Set Register 1"
|
|
bitfld.byte 0x00 7. " DMODS1 ,Output polarity control set bit" "No effect,Set"
|
|
bitfld.byte 0x00 6. " GTENS3 ,GATE signal control set bit" "No effect,Set"
|
|
bitfld.byte 0x00 5. " GTENS2 ,GATE signal control set bit" "No effect,Set"
|
|
bitfld.byte 0x00 3. " TMIES1 ,Interrupt request enable set" "No effect,Set"
|
|
wgroup.byte 0x029++0x00
|
|
line.byte 0x00 "WFG03_DTCRS2,16-bit Dead Timer State Control Set Register 2"
|
|
bitfld.byte 0x00 7. " DMODS2 ,Output polarity control set" "No effect,Set"
|
|
bitfld.byte 0x00 6. " GTENS5 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " GTENS4 ,GATE signal control set" "No effect,Set"
|
|
bitfld.byte 0x00 3. " TMIES2 ,Interrupt request enable set" "No effect,Set"
|
|
wgroup.byte 0x02E++0x00
|
|
line.byte 0x00 "WFG03_DTIRS,16-bit Dead Timer Reload Interrupt Set Register"
|
|
bitfld.byte 0x00 6. " DTRIES2 ,16-bit dead timer 2 reload interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 4. " DTRIES1 ,16-bit dead timer 1 reload interrupt enable set" "No effect,Set"
|
|
bitfld.byte 0x00 2. " DTRIES0 ,16-bit dead timer 0 reload interrupt enable set" "No effect,Set"
|
|
wgroup.byte 0x032++0x00
|
|
line.byte 0x00 "WFG03_SIGCR1S,Waveform Control Set Register 1"
|
|
bitfld.byte 0x00 7. " DTIES ,DTTI input validating set" "No effect,Set"
|
|
bitfld.byte 0x00 5. " NRSLS ,Noise cancel function validating set" "No effect,Set"
|
|
group.byte 0x19C3++0x00
|
|
line.byte 0x00 "RTOSEL3,Output Level Conversion Register 3"
|
|
bitfld.byte 0x00 5. " OSEL5 ,Output polarity control bit 5" "Normal,Inverted"
|
|
bitfld.byte 0x00 4. " OSEL4 ,Output polarity control bit 4" "Normal,Inverted"
|
|
bitfld.byte 0x00 3. " OSEL3 ,Output polarity control bit 3" "Normal,Inverted"
|
|
bitfld.byte 0x00 2. " OSEL2 ,Output polarity control bit 2" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OSEL1 ,Output polarity control bit 1" "Normal,Inverted"
|
|
bitfld.byte 0x00 0. " OSEL0 ,Output polarity control bit 0" "Normal,Inverted"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Control"
|
|
base ad:0xB1010600
|
|
width 12.
|
|
group.byte 0x003++0x00
|
|
line.byte 0x00 "WFG02_DTSR,DTTI Selection Register 0"
|
|
bitfld.byte 0x00 1. " SEL1 ,DTTI input selection bit for waveform generator 1" "DTTI0,DTTI1"
|
|
bitfld.byte 0x00 0. " SEL0 ,DTTI input selection bit for waveform generator 0" "DTTI0,DTTI1"
|
|
group.byte 0x043++0x00
|
|
line.byte 0x00 "WFG03_DTSR,DTTI Selection Register 1"
|
|
bitfld.byte 0x00 1. " SEL1 ,DTTI input selection bit for waveform generator 3" "DTTI2,DTTI3"
|
|
sif cpuis("MB9DF56?M*")
|
|
bitfld.byte 0x00 0. " SEL0 ,DTTI input selection bit for waveform generator 2" "DTTI2,DTTI3"
|
|
endif
|
|
group.byte 0xA00++0x00
|
|
line.byte 0x00 "SDCTR2,Software DDTI Control Register"
|
|
bitfld.byte 0x00 3. " DTIS3 ,Set software DTTI3" "Set,Clear"
|
|
bitfld.byte 0x00 2. " DTIS2 ,Set software DTTI2" "Set,Clear"
|
|
bitfld.byte 0x00 1. " DTIS1 ,Set software DTTI1" "Set,Clear"
|
|
bitfld.byte 0x00 0. " DTIS0 ,Set software DTTI0" "Set,Clear"
|
|
group.byte 0xA04++0x01
|
|
line.byte 0x00 "EDCTR2,External DTTI Input Control Register"
|
|
bitfld.byte 0x00 3. " DTIHE3 ,External DTTI pin input control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " DTIHE2 ,External DTTI pin input control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " DTIHE1 ,External DTTI pin input control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " DTIHE0 ,External DTTI pin input control" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "DAC (D/A Converter)"
|
|
tree "Unit 00"
|
|
base ad:0xB2000D00
|
|
width 6.
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "DACR,D/A Control Register"
|
|
bitfld.byte 0x00 0. " DAE ,D/A output enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "DADR,D/A Data Register"
|
|
hexmask.word 0x00 0.--9. 1. " DA ,D/A output value"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "DAER,Analog Output Control Register"
|
|
bitfld.byte 0x00 0. " DAS ,Analog output control" "Port (digital),Analog output"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 01"
|
|
base ad:0xB1000D00
|
|
width 6.
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "DACR,D/A Control Register"
|
|
bitfld.byte 0x00 0. " DAE ,D/A output enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "DADR,D/A Data Register"
|
|
hexmask.word 0x00 0.--9. 1. " DA ,D/A output value"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "DAER,Analog Output Control Register"
|
|
bitfld.byte 0x00 0. " DAS ,Analog output control" "Port (digital),Analog output"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "ADC4SHCI (12-bit 4ch A/D Converter Interface)"
|
|
base ad:0xB1000300
|
|
width 11.
|
|
rgroup.byte 0x093++0x00
|
|
line.byte 0x00 "ADCS,A/D Control Status Register"
|
|
bitfld.byte 0x00 7. " BUSY ,A/D conversion busy" "Not busy,Busy"
|
|
bitfld.byte 0x00 6. " READY ,Operation enable" "Disabled,Enabled"
|
|
rgroup.byte 0x092++0x00
|
|
line.byte 0x00 "ADCH,A/D Channel Status Register"
|
|
bitfld.byte 0x00 0.--1. " CH ,Analog channel" "Channel 0(Ach),Channel 1(Bch),Channel 2(Cch),Channel 3(Dch)"
|
|
group.word 0x090++0x01
|
|
line.word 0x00 "ADMD,A/D Mode Setting Register"
|
|
bitfld.word 0x00 8.--11. " CT ,Compare time setting" ",28 cycles,42 cycles,56 cycles,70 cycles,84 cycles,98 cycles,112 cycles,126 cycles,140 cycles,154 cycles,168 cycles,182 cycles,196 cycles,210 cycles,224 cycles"
|
|
bitfld.word 0x00 0.--3. " ST ,Sampling time setting bits" ",24 cycles,36 cycles,48 cycles,60 cycles,72 cycles,84 cycles,96 cycles,108 cycles,120 cycles,132 cycles,144 cycles,156 cycles,168 cycles,180 cycles,192 cycles"
|
|
group.byte 0x094++0x00
|
|
line.byte 0x00 "ADCHSEL,A/D Conversion Channel Selection Register"
|
|
bitfld.byte 0x00 2.--3. " ADCSL ,A/D conversion channel selection" "All channels,1 channel(Ach),2 channels(Ach Bch),3 channels(Ach Bch Cch)"
|
|
bitfld.byte 0x00 0. " CHMD ,A/D conversion channel selection mode" "4CH conversion mode,Conversion CH selection mode"
|
|
group.byte 0x0A4++0x00
|
|
line.byte 0x00 "ADCEN,A/D Operation Enable Register"
|
|
bitfld.byte 0x00 0. " ENBL ,12-bit 4ch A/D operation enable bit" "Disabled,Enabled"
|
|
group.long 0x0A8++0x03
|
|
line.long 0x00 "ADCENTIME,A/D Converter Enable Timer Register"
|
|
group.byte 0x012D08++0x01
|
|
line.byte 0x00 "ADER4CH_0,4ch ADC Unit 0 Analog Input Enable Register"
|
|
bitfld.byte 0x00 3. " ADE4C1U3 ,4ch ADC analog input enable bit 3" "Port input/output,Analog input"
|
|
bitfld.byte 0x00 2. " ADE4C1U2 ,4ch ADC analog input enable bit 2" "Port input/output,Analog input"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ADE4C1U1 ,4ch ADC analog input enable bit 1" "Port input/output,Analog input"
|
|
bitfld.byte 0x00 0. " ADE4C1U0 ,4ch ADC analog input enable bit 0" "Port input/output,Analog input"
|
|
line.byte 0x01 "ADER4CH_1,4ch ADC Unit 1 Analog Input Enable Register"
|
|
bitfld.byte 0x01 3. " ADE4C0U3 ,4ch ADC analog input enable bit 3" "Port input/output,Analog input"
|
|
bitfld.byte 0x01 2. " ADE4C0U2 ,4ch ADC analog input enable bit 2" "Port input/output,Analog input"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " ADE4C0U1 ,4ch ADC analog input enable bit 1" "Port input/output,Analog input"
|
|
bitfld.byte 0x01 0. " ADE4C0U0 ,4ch ADC analog input enable bit 0" "Port input/output,Analog input"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "ADC4SH (12-bit 4ch A/D Converter A/D Activaton Compare)"
|
|
tree "Unit 00"
|
|
base ad:0xB2000300
|
|
width 10.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "ADTSS,A/D Software Activation Register"
|
|
bitfld.byte 0x00 0. " START ,A/D conversion activation bit" "Not activated,Activated"
|
|
group.byte 0x04++0x03
|
|
line.byte 0x00 "ADTSE,A/D Software Activation Channel Selection Register"
|
|
bitfld.byte 0x00 7. " ADT7 ,AD software activation channel selection bit 7" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADT6 ,AD software activation channel selection bit 6" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ADT5 ,AD software activation channel selection bit 5" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ADT4 ,AD software activation channel selection bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ADT3 ,AD software activation channel selection bit 3" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ADT2 ,AD software activation channel selection bit 2" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ADT1 ,AD software activation channel selection bit 1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ADT0 ,AD software activation channel selection bit 0" "Disabled,Enabled"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "ADCOMPB0,Compare Buffer Register 0"
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "ADCOMP0,Compare Register 0"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "ADCOMPB1,Compare Buffer Register 1"
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "ADCOMP1,Compare Register 1"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "ADCOMPB2,Compare Buffer Register 2"
|
|
rgroup.word 0x0E++0x01
|
|
line.word 0x00 "ADCOMP2,Compare Register 2"
|
|
wgroup.word 0x0C++0x01
|
|
line.word 0x00 "ADCOMPB3,Compare Buffer Register 3"
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "ADCOMP3,Compare Register 3"
|
|
wgroup.word 0x12++0x01
|
|
line.word 0x00 "ADCOMPB4,Compare Buffer Register 4"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "ADCOMP4,Compare Register 4"
|
|
wgroup.word 0x10++0x01
|
|
line.word 0x00 "ADCOMPB5,Compare Buffer Register 5"
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "ADCOMP5,Compare Register 5"
|
|
wgroup.word 0x16++0x01
|
|
line.word 0x00 "ADCOMPB6,Compare Buffer Register 6"
|
|
rgroup.word 0x16++0x01
|
|
line.word 0x00 "ADCOMP6,Compare Register 6"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "ADCOMPB7,Compare Buffer Register 7"
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "ADCOMP7,Compare Register 7"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "ADTC0,A/D Activation Trigger Control Register 0"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "ADTC1,A/D Activation Trigger Control Register 1"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x1E++0x01
|
|
line.word 0x00 "ADTC2,A/D Activation Trigger Control Register 2"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "ADTC3,A/D Activation Trigger Control Register 3"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "ADTC4,A/D Activation Trigger Control Register 4"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "ADTC5,A/D Activation Trigger Control Register 5"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x26++0x01
|
|
line.word 0x00 "ADTC6,A/D Activation Trigger Control Register 6"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "ADTC7,A/D Activation Trigger Control Register 7"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
rgroup.word 0x5E++0x03
|
|
line.word 0x00 "ADTS0,A/D Activation Request/Interrupt Status Register 0"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x5C++0x03
|
|
line.word 0x00 "ADTS1,A/D Activation Request/Interrupt Status Register 1"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x62++0x03
|
|
line.word 0x00 "ADTS2,A/D Activation Request/Interrupt Status Register 2"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x60++0x03
|
|
line.word 0x00 "ADTS3,A/D Activation Request/Interrupt Status Register 3"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x66++0x03
|
|
line.word 0x00 "ADTS4,A/D Activation Request/Interrupt Status Register 4"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x64++0x03
|
|
line.word 0x00 "ADTS5,A/D Activation Request/Interrupt Status Register 5"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x6A++0x03
|
|
line.word 0x00 "ADTS6,A/D Activation Request/Interrupt Status Register 6"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x68++0x03
|
|
line.word 0x00 "ADTS7,A/D Activation Request/Interrupt Status Register 7"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
wgroup.word 0x72++0x03
|
|
line.word 0x00 "ADTSC0,A/D Activation Request/Interrupt Clear Register 0"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x70++0x03
|
|
line.word 0x00 "ADTSC1,A/D Activation Request/Interrupt Clear Register 1"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x76++0x03
|
|
line.word 0x00 "ADTSC2,A/D Activation Request/Interrupt Clear Register 2"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x74++0x03
|
|
line.word 0x00 "ADTSC3,A/D Activation Request/Interrupt Clear Register 3"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x7A++0x03
|
|
line.word 0x00 "ADTSC4,A/D Activation Request/Interrupt Clear Register 4"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x78++0x03
|
|
line.word 0x00 "ADTSC5,A/D Activation Request/Interrupt Clear Register 5"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x7E++0x03
|
|
line.word 0x00 "ADTSC6,A/D Activation Request/Interrupt Clear Register 6"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x7C++0x03
|
|
line.word 0x00 "ADTSC7,A/D Activation Request/Interrupt Clear Register 7"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
if (((per.w(ad:0xB2000300+0x2A))&0x8000)==0x8000)
|
|
group.word 0x2A++0x01
|
|
line.word 0x00 "ADTCD0,A/D Data Register 0"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x2A++0x01
|
|
line.word 0x00 "ADTCD0,A/D Data Register 0"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB2000300+0x28))&0x8000)==0x8000)
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "ADTCD1,A/D Data Register 1"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "ADTCD1,A/D Data Register 1"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB2000300+0x2E))&0x8000)==0x8000)
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "ADTCD2,A/D Data Register 2"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "ADTCD2,A/D Data Register 2"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB2000300+0x2C))&0x8000)==0x8000)
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ADTCD3,A/D Data Register 3"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ADTCD3,A/D Data Register 3"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB2000300+0x32))&0x8000)==0x8000)
|
|
group.word 0x32++0x01
|
|
line.word 0x00 "ADTCD4,A/D Data Register 4"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x32++0x01
|
|
line.word 0x00 "ADTCD4,A/D Data Register 4"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB2000300+0x30))&0x8000)==0x8000)
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "ADTCD5,A/D Data Register 5"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "ADTCD5,A/D Data Register 5"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB2000300+0x36))&0x8000)==0x8000)
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "ADTCD6,A/D Data Register 6"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "ADTCD6,A/D Data Register 6"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB2000300+0x34))&0x8000)==0x8000)
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "ADTCD7,A/D Data Register 7"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "ADTCD7,A/D Data Register 7"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
group.word 0x3A++0x01
|
|
line.word 0x00 "ADRCUT0,Upper-limit Threshold Setting Register 0"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Upper-limit threshold"
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "ADRCUT1,Upper-limit Threshold Setting Register 1"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Upper-limit threshold"
|
|
group.word 0x42++0x01
|
|
line.word 0x00 "ADRCUT2,Upper-limit Threshold Setting Register 2"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Upper-limit threshold"
|
|
group.word 0x46++0x01
|
|
line.word 0x00 "ADRCUT3,Upper-limit Threshold Setting Register 3"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Upper-limit threshold"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "ADRCLT0,Lower-limit Threshold Setting Register 0"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower-limit threshold"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "ADRCLT1,Lower-limit Threshold Setting Register 1"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower-limit threshold"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "ADRCLT2,Lower-limit Threshold Setting Register 2"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower-limit threshold"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "ADRCLT3,Lower-limit Threshold Setting Register 3"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower-limit threshold"
|
|
if (((per.l(ad:0xB2000300+0x5E))&0x8000)==0x8000)
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "ADRCCS0,Range Comparison Control Status Register 0"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB2000300+0x4B))&0x04)==0x04)
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "ADRCCS0,Range Comparison Control Status Register 0"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "ADRCCS0,Range Comparison Control Status Register 0"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB2000300+0x5C))&0x8000)==0x8000)
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "ADRCCS1,Range Comparison Control Status Register 1"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB2000300+0x4A))&0x04)==0x04)
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "ADRCCS1,Range Comparison Control Status Register 1"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "ADRCCS1,Range Comparison Control Status Register 1"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB2000300+0x62))&0x8000)==0x8000)
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "ADRCCS2,Range Comparison Control Status Register 2"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB2000300+0x49))&0x04)==0x04)
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "ADRCCS2,Range Comparison Control Status Register 2"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "ADRCCS2,Range Comparison Control Status Register 2"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB2000300+0x60))&0x8000)==0x8000)
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "ADRCCS3,Range Comparison Control Status Register 3"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB2000300+0x48))&0x04)==0x04)
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "ADRCCS3,Range Comparison Control Status Register 3"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "ADRCCS3,Range Comparison Control Status Register 3"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB2000300+0x66))&0x8000)==0x8000)
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "ADRCCS4,Range Comparison Control Status Register 4"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB2000300+0x4F))&0x04)==0x04)
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "ADRCCS4,Range Comparison Control Status Register 4"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "ADRCCS4,Range Comparison Control Status Register 4"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB2000300+0x64))&0x8000)==0x8000)
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "ADRCCS5,Range Comparison Control Status Register 5"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB2000300+0x4E))&0x04)==0x04)
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "ADRCCS5,Range Comparison Control Status Register 5"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "ADRCCS5,Range Comparison Control Status Register 5"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB2000300+0x6A))&0x8000)==0x8000)
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "ADRCCS6,Range Comparison Control Status Register 6"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB2000300+0x4D))&0x04)==0x04)
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "ADRCCS6,Range Comparison Control Status Register 6"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "ADRCCS6,Range Comparison Control Status Register 6"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB2000300+0x68))&0x8000)==0x8000)
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "ADRCCS7,Range Comparison Control Status Register 7"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB2000300+0x4C))&0x04)==0x04)
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "ADRCCS7,Range Comparison Control Status Register 7"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "ADRCCS7,Range Comparison Control Status Register 7"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
rgroup.byte 0x050++0x00
|
|
line.byte 0x00 "ADRCOT,Range Comparison Out-of-range Flag Register"
|
|
bitfld.byte 0x00 7. " RCOOF7 ,Out-of-range flag 7" "Below lower-limit,Above upper-limit"
|
|
bitfld.byte 0x00 6. " RCOOF6 ,Out-of-range flag 6" "Below lower-limit,Above upper-limit"
|
|
bitfld.byte 0x00 5. " RCOOF5 ,Out-of-range flag 5" "Below lower-limit,Above upper-limit"
|
|
bitfld.byte 0x00 4. " RCOOF4 ,Out-of-range flag 4" "Below lower-limit,Above upper-limit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RCOOF3 ,Out-of-range flag 3" "Below lower-limit,Above upper-limit"
|
|
bitfld.byte 0x00 2. " RCOOF2 ,Out-of-range flag 2" "Below lower-limit,Above upper-limit"
|
|
bitfld.byte 0x00 1. " RCOOF1 ,Out-of-range flag 1" "Below lower-limit,Above upper-limit"
|
|
bitfld.byte 0x00 0. " RCOOF0 ,Out-of-range flag 0" "Below lower-limit,Above upper-limit"
|
|
rgroup.byte 0x054++0x00
|
|
line.byte 0x00 "ADRCIF,Range Comparison Flag Register"
|
|
bitfld.byte 0x00 7. " RCINT7 ,Range compare interrupt factor flag 7" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 6. " RCINT6 ,Range compare interrupt factor flag 6" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 5. " RCINT5 ,Range compare interrupt factor flag 5" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 4. " RCINT4 ,Range compare interrupt factor flag 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RCINT3 ,Range compare interrupt factor flag 3" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " RCINT2 ,Range compare interrupt factor flag 2" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " RCINT1 ,Range compare interrupt factor flag 1" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " RCINT0 ,Range compare interrupt factor flag 0" "No interrupt,Interrupt"
|
|
wgroup.byte 0x06C++0x00
|
|
line.byte 0x00 "ADRCIFC,Range Comparison Flag Clear Register"
|
|
bitfld.byte 0x00 7. " RCINT7C ,Range compare interrupt factor flag 7 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " RCINT6C ,Range compare interrupt factor flag 6 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " RCINT5C ,Range compare interrupt factor flag 5 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RCINT4C ,Range compare interrupt factor flag 4 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RCINT3C ,Range compare interrupt factor flag 3 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " RCINT2C ,Range compare interrupt factor flag 2 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " RCINT1C ,Range compare interrupt factor flag 1 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " RCINT0C ,Range compare interrupt factor flag 0 clear" "No effect,Clear"
|
|
rgroup.byte 0x058++0x00
|
|
line.byte 0x00 "ADPRTF,Protected Data State Flag Register"
|
|
bitfld.byte 0x00 7. " PRTF7 ,Protected data state flag 7" "Not protected,Protected"
|
|
bitfld.byte 0x00 6. " PRTF6 ,Protected data state flag 6" "Not protected,Protected"
|
|
bitfld.byte 0x00 5. " PRTF5 ,Protected data state flag 5" "Not protected,Protected"
|
|
bitfld.byte 0x00 4. " PRTF4 ,Protected data state flag 4" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PRTF3 ,Protected data state flag 3" "Not protected,Protected"
|
|
bitfld.byte 0x00 2. " PRTF2 ,Protected data state flag 2" "Not protected,Protected"
|
|
bitfld.byte 0x00 1. " PRTF1 ,Protected data state flag 1" "Not protected,Protected"
|
|
bitfld.byte 0x00 0. " PRTF0 ,Protected data state flag 0" "Not protected,Protected"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 01"
|
|
base ad:0xB1000300
|
|
width 10.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "ADTSS,A/D Software Activation Register"
|
|
bitfld.byte 0x00 0. " START ,A/D conversion activation bit" "Not activated,Activated"
|
|
group.byte 0x04++0x03
|
|
line.byte 0x00 "ADTSE,A/D Software Activation Channel Selection Register"
|
|
bitfld.byte 0x00 7. " ADT7 ,AD software activation channel selection bit 7" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADT6 ,AD software activation channel selection bit 6" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ADT5 ,AD software activation channel selection bit 5" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ADT4 ,AD software activation channel selection bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ADT3 ,AD software activation channel selection bit 3" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ADT2 ,AD software activation channel selection bit 2" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ADT1 ,AD software activation channel selection bit 1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ADT0 ,AD software activation channel selection bit 0" "Disabled,Enabled"
|
|
wgroup.word 0x0A++0x01
|
|
line.word 0x00 "ADCOMPB0,Compare Buffer Register 0"
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "ADCOMP0,Compare Register 0"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "ADCOMPB1,Compare Buffer Register 1"
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "ADCOMP1,Compare Register 1"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "ADCOMPB2,Compare Buffer Register 2"
|
|
rgroup.word 0x0E++0x01
|
|
line.word 0x00 "ADCOMP2,Compare Register 2"
|
|
wgroup.word 0x0C++0x01
|
|
line.word 0x00 "ADCOMPB3,Compare Buffer Register 3"
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "ADCOMP3,Compare Register 3"
|
|
wgroup.word 0x12++0x01
|
|
line.word 0x00 "ADCOMPB4,Compare Buffer Register 4"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "ADCOMP4,Compare Register 4"
|
|
wgroup.word 0x10++0x01
|
|
line.word 0x00 "ADCOMPB5,Compare Buffer Register 5"
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "ADCOMP5,Compare Register 5"
|
|
wgroup.word 0x16++0x01
|
|
line.word 0x00 "ADCOMPB6,Compare Buffer Register 6"
|
|
rgroup.word 0x16++0x01
|
|
line.word 0x00 "ADCOMP6,Compare Register 6"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "ADCOMPB7,Compare Buffer Register 7"
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "ADCOMP7,Compare Register 7"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "ADTC0,A/D Activation Trigger Control Register 0"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "ADTC1,A/D Activation Trigger Control Register 1"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x1E++0x01
|
|
line.word 0x00 "ADTC2,A/D Activation Trigger Control Register 2"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "ADTC3,A/D Activation Trigger Control Register 3"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "ADTC4,A/D Activation Trigger Control Register 4"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "ADTC5,A/D Activation Trigger Control Register 5"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x26++0x01
|
|
line.word 0x00 "ADTC6,A/D Activation Trigger Control Register 6"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "ADTC7,A/D Activation Trigger Control Register 7"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS , A/D data register protection clear selection" "Data reading and interrupt flag clearing,Data reading"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection" "Up/down,Up,Down,Disabled"
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control" "0 detection,Compare"
|
|
bitfld.word 0x00 0.--2. " STS ,A/D activation factor selection bits" "Software,External trigger,Base timer,Compare match,?..."
|
|
rgroup.word 0x5E++0x03
|
|
line.word 0x00 "ADTS0,A/D Activation Request/Interrupt Status Register 0"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x5C++0x03
|
|
line.word 0x00 "ADTS1,A/D Activation Request/Interrupt Status Register 1"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x62++0x03
|
|
line.word 0x00 "ADTS2,A/D Activation Request/Interrupt Status Register 2"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x60++0x03
|
|
line.word 0x00 "ADTS3,A/D Activation Request/Interrupt Status Register 3"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x66++0x03
|
|
line.word 0x00 "ADTS4,A/D Activation Request/Interrupt Status Register 4"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x64++0x03
|
|
line.word 0x00 "ADTS5,A/D Activation Request/Interrupt Status Register 5"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x6A++0x03
|
|
line.word 0x00 "ADTS6,A/D Activation Request/Interrupt Status Register 6"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
rgroup.word 0x68++0x03
|
|
line.word 0x00 "ADTS7,A/D Activation Request/Interrupt Status Register 7"
|
|
bitfld.word 0x00 15. " BUSY ,A/D activation request busy" "Not busy,Busy"
|
|
bitfld.word 0x00 14. " INT ,Interrupt request flag" "Not terminated,Terminated"
|
|
wgroup.word 0x72++0x03
|
|
line.word 0x00 "ADTSC0,A/D Activation Request/Interrupt Clear Register 0"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x70++0x03
|
|
line.word 0x00 "ADTSC1,A/D Activation Request/Interrupt Clear Register 1"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x76++0x03
|
|
line.word 0x00 "ADTSC2,A/D Activation Request/Interrupt Clear Register 2"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x74++0x03
|
|
line.word 0x00 "ADTSC3,A/D Activation Request/Interrupt Clear Register 3"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x7A++0x03
|
|
line.word 0x00 "ADTSC4,A/D Activation Request/Interrupt Clear Register 4"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x78++0x03
|
|
line.word 0x00 "ADTSC5,A/D Activation Request/Interrupt Clear Register 5"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x7E++0x03
|
|
line.word 0x00 "ADTSC6,A/D Activation Request/Interrupt Clear Register 6"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
wgroup.word 0x7C++0x03
|
|
line.word 0x00 "ADTSC7,A/D Activation Request/Interrupt Clear Register 7"
|
|
bitfld.word 0x00 15. " BUSYC ,A/D activation request clear" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,A/D conversion end interrupt software clear" "No effect,Clear"
|
|
if (((per.w(ad:0xB1000300+0x2A))&0x8000)==0x8000)
|
|
group.word 0x2A++0x01
|
|
line.word 0x00 "ADTCD0,A/D Data Register 0"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x2A++0x01
|
|
line.word 0x00 "ADTCD0,A/D Data Register 0"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB1000300+0x28))&0x8000)==0x8000)
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "ADTCD1,A/D Data Register 1"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "ADTCD1,A/D Data Register 1"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB1000300+0x2E))&0x8000)==0x8000)
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "ADTCD2,A/D Data Register 2"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "ADTCD2,A/D Data Register 2"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB1000300+0x2C))&0x8000)==0x8000)
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ADTCD3,A/D Data Register 3"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ADTCD3,A/D Data Register 3"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB1000300+0x32))&0x8000)==0x8000)
|
|
group.word 0x32++0x01
|
|
line.word 0x00 "ADTCD4,A/D Data Register 4"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x32++0x01
|
|
line.word 0x00 "ADTCD4,A/D Data Register 4"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB1000300+0x30))&0x8000)==0x8000)
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "ADTCD5,A/D Data Register 5"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "ADTCD5,A/D Data Register 5"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB1000300+0x36))&0x8000)==0x8000)
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "ADTCD6,A/D Data Register 6"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "ADTCD6,A/D Data Register 6"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
if (((per.w(ad:0xB1000300+0x34))&0x8000)==0x8000)
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "ADTCD7,A/D Data Register 7"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag" "Normal,Abnormal"
|
|
bitfld.word 0x00 14. " ERRST ,Conversion data error status" "Old results,Data overwritten"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data"
|
|
else
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "ADTCD7,A/D Data Register 7"
|
|
bitfld.word 0x00 15. " ERR ,Conversion data error flag bit" "Normal,Abnormal"
|
|
hexmask.word 0x00 0.--11. 1. " D ,A/D data bits"
|
|
endif
|
|
group.word 0x3A++0x01
|
|
line.word 0x00 "ADRCUT0,Upper-limit Threshold Setting Register 0"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Upper-limit threshold"
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "ADRCUT1,Upper-limit Threshold Setting Register 1"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Upper-limit threshold"
|
|
group.word 0x42++0x01
|
|
line.word 0x00 "ADRCUT2,Upper-limit Threshold Setting Register 2"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Upper-limit threshold"
|
|
group.word 0x46++0x01
|
|
line.word 0x00 "ADRCUT3,Upper-limit Threshold Setting Register 3"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Upper-limit threshold"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "ADRCLT0,Lower-limit Threshold Setting Register 0"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower-limit threshold"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "ADRCLT1,Lower-limit Threshold Setting Register 1"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower-limit threshold"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "ADRCLT2,Lower-limit Threshold Setting Register 2"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower-limit threshold"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "ADRCLT3,Lower-limit Threshold Setting Register 3"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower-limit threshold"
|
|
if (((per.l(ad:0xB1000300+0x5E))&0x8000)==0x8000)
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "ADRCCS0,Range Comparison Control Status Register 0"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB1000300+0x4B))&0x04)==0x04)
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "ADRCCS0,Range Comparison Control Status Register 0"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "ADRCCS0,Range Comparison Control Status Register 0"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB1000300+0x5C))&0x8000)==0x8000)
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "ADRCCS1,Range Comparison Control Status Register 1"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB1000300+0x4A))&0x04)==0x04)
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "ADRCCS1,Range Comparison Control Status Register 1"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "ADRCCS1,Range Comparison Control Status Register 1"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB1000300+0x62))&0x8000)==0x8000)
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "ADRCCS2,Range Comparison Control Status Register 2"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB1000300+0x49))&0x04)==0x04)
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "ADRCCS2,Range Comparison Control Status Register 2"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "ADRCCS2,Range Comparison Control Status Register 2"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB1000300+0x60))&0x8000)==0x8000)
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "ADRCCS3,Range Comparison Control Status Register 3"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB1000300+0x48))&0x04)==0x04)
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "ADRCCS3,Range Comparison Control Status Register 3"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "ADRCCS3,Range Comparison Control Status Register 3"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB1000300+0x66))&0x8000)==0x8000)
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "ADRCCS4,Range Comparison Control Status Register 4"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB1000300+0x4F))&0x04)==0x04)
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "ADRCCS4,Range Comparison Control Status Register 4"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "ADRCCS4,Range Comparison Control Status Register 4"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB1000300+0x64))&0x8000)==0x8000)
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "ADRCCS5,Range Comparison Control Status Register 5"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB1000300+0x4E))&0x04)==0x04)
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "ADRCCS5,Range Comparison Control Status Register 5"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "ADRCCS5,Range Comparison Control Status Register 5"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB1000300+0x6A))&0x8000)==0x8000)
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "ADRCCS6,Range Comparison Control Status Register 6"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB1000300+0x4D))&0x04)==0x04)
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "ADRCCS6,Range Comparison Control Status Register 6"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "ADRCCS6,Range Comparison Control Status Register 6"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB1000300+0x68))&0x8000)==0x8000)
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "ADRCCS7,Range Comparison Control Status Register 7"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
elif (((per.b(ad:0xB1000300+0x4C))&0x04)==0x04)
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "ADRCCS7,Range Comparison Control Status Register 7"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
else
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "ADRCCS7,Range Comparison Control Status Register 7"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection frequency specification and count display" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Outside/inside range confirmation selection" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range compare interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE , Range comparison execution enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper- and lower-limit threshold selection" "0,1,2,3"
|
|
endif
|
|
rgroup.byte 0x050++0x00
|
|
line.byte 0x00 "ADRCOT,Range Comparison Out-of-range Flag Register"
|
|
bitfld.byte 0x00 7. " RCOOF7 ,Out-of-range flag 7" "Below lower-limit,Above upper-limit"
|
|
bitfld.byte 0x00 6. " RCOOF6 ,Out-of-range flag 6" "Below lower-limit,Above upper-limit"
|
|
bitfld.byte 0x00 5. " RCOOF5 ,Out-of-range flag 5" "Below lower-limit,Above upper-limit"
|
|
bitfld.byte 0x00 4. " RCOOF4 ,Out-of-range flag 4" "Below lower-limit,Above upper-limit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RCOOF3 ,Out-of-range flag 3" "Below lower-limit,Above upper-limit"
|
|
bitfld.byte 0x00 2. " RCOOF2 ,Out-of-range flag 2" "Below lower-limit,Above upper-limit"
|
|
bitfld.byte 0x00 1. " RCOOF1 ,Out-of-range flag 1" "Below lower-limit,Above upper-limit"
|
|
bitfld.byte 0x00 0. " RCOOF0 ,Out-of-range flag 0" "Below lower-limit,Above upper-limit"
|
|
rgroup.byte 0x054++0x00
|
|
line.byte 0x00 "ADRCIF,Range Comparison Flag Register"
|
|
bitfld.byte 0x00 7. " RCINT7 ,Range compare interrupt factor flag 7" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 6. " RCINT6 ,Range compare interrupt factor flag 6" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 5. " RCINT5 ,Range compare interrupt factor flag 5" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 4. " RCINT4 ,Range compare interrupt factor flag 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RCINT3 ,Range compare interrupt factor flag 3" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " RCINT2 ,Range compare interrupt factor flag 2" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " RCINT1 ,Range compare interrupt factor flag 1" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " RCINT0 ,Range compare interrupt factor flag 0" "No interrupt,Interrupt"
|
|
wgroup.byte 0x06C++0x00
|
|
line.byte 0x00 "ADRCIFC,Range Comparison Flag Clear Register"
|
|
bitfld.byte 0x00 7. " RCINT7C ,Range compare interrupt factor flag 7 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " RCINT6C ,Range compare interrupt factor flag 6 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " RCINT5C ,Range compare interrupt factor flag 5 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RCINT4C ,Range compare interrupt factor flag 4 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RCINT3C ,Range compare interrupt factor flag 3 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " RCINT2C ,Range compare interrupt factor flag 2 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " RCINT1C ,Range compare interrupt factor flag 1 clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " RCINT0C ,Range compare interrupt factor flag 0 clear" "No effect,Clear"
|
|
rgroup.byte 0x058++0x00
|
|
line.byte 0x00 "ADPRTF,Protected Data State Flag Register"
|
|
bitfld.byte 0x00 7. " PRTF7 ,Protected data state flag 7" "Not protected,Protected"
|
|
bitfld.byte 0x00 6. " PRTF6 ,Protected data state flag 6" "Not protected,Protected"
|
|
bitfld.byte 0x00 5. " PRTF5 ,Protected data state flag 5" "Not protected,Protected"
|
|
bitfld.byte 0x00 4. " PRTF4 ,Protected data state flag 4" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PRTF3 ,Protected data state flag 3" "Not protected,Protected"
|
|
bitfld.byte 0x00 2. " PRTF2 ,Protected data state flag 2" "Not protected,Protected"
|
|
bitfld.byte 0x00 1. " PRTF1 ,Protected data state flag 1" "Not protected,Protected"
|
|
bitfld.byte 0x00 0. " PRTF0 ,Protected data state flag 0" "Not protected,Protected"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
textline " "
|