16113 lines
1.7 MiB
16113 lines
1.7 MiB
; --------------------------------------------------------------------------------
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; @Title: M471 On-Chip Peripherals
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; @Props: Released
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; @Author: KWI, DAB
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; @Changelog: 2020-10-07 KWI
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; 2022-01-24 DAB
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; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
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; @Doc: SVD generated based on M471.svd
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; @Core: Cortex-M4F
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; @Chip: M471KI8AE, M471QG7AE, M471QG8AE, M471QI8AE, M471R1G7AE, M471R1I8AE,
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; M471VG7AE, M471VG8AE, M471VI8AE
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perm471.per 14195 2022-01-27 17:03:00Z kwisniewski $
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config 16. 8.
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
autoindent.on center tree
|
|
tree "ACMP (ACMP Register Map)"
|
|
base ad:0x40045000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ACMP_CTL0,Analog Comparator 0 Control Register"
|
|
bitfld.long 0x00 24.--26. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,1: Hysteresis is 10mV,2: Hysteresis is 20mV,3: Hysteresis is 30mV,4: Hysteresis is 40mV,5: Hysteresis is 50mV,?..."
|
|
bitfld.long 0x00 20.--21. "FCLKDIV,Comparator Output Filter Clock Divider" "0: Comparator output filter clock = PCLK,1: Comparator output filter clock = PCLK/2,2: Comparator output filter clock = PCLK/4,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode is Selected"
|
|
bitfld.long 0x00 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
bitfld.long 0x00 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP0 output is sampled 1 consecutive PCLK,2: ACMP0 output is sampled 2 consecutive PCLKs,3: ACMP0 output is sampled 4 consecutive PCLKs,4: ACMP0 output is sampled 8 consecutive PCLKs,5: ACMP0 output is sampled 16 consecutive PCLKs,6: ACMP0 output is sampled 32 consecutive PCLKs,7: ACMP0 output is sampled 64 consecutive PCLKs"
|
|
newline
|
|
bitfld.long 0x00 12. "OUTSEL,Comparator Output Select" "0: Comparator 0 output to ACMP0_O pin is..,1: Comparator 0 output to ACMP0_O pin is from.."
|
|
bitfld.long 0x00 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected" "0: Rising edge or falling edge,1: Rising edge,2: Falling edge,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP0_P0,1: Input from ACMP0_P1,2: Input from ACMP0_P2,3: Input from ACMP0_P3"
|
|
bitfld.long 0x00 4.--5. "NEGSEL,Comparator Negative Input Selection\nNote: NEGSEL must select 2'b01 in calibration mode" "0: ACMP0_N pin,1: Internal comparator reference voltage (CRV0),2: Band-gap voltage,3: DAC0 output"
|
|
newline
|
|
bitfld.long 0x00 3. "ACMPOINV,Comparator Output Inverse" "0: Comparator 0 output inverse Disabled,1: Comparator 0 output inverse Enabled"
|
|
bitfld.long 0x00 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 0 interrupt Disabled,1: Comparator 0 interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 0 Disabled,1: Comparator 0 Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ACMP_CTL1,Analog Comparator 1 Control Register"
|
|
bitfld.long 0x00 24.--26. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,1: Hysteresis is 10mV,2: Hysteresis is 20mV,3: Hysteresis is 30mV,4: Hysteresis is 40mV,5: Hysteresis is 50mV,?..."
|
|
bitfld.long 0x00 20.--21. "FCLKDIV,Comparator Output Filter Clock Divider" "0: comparator output filter clock = PCLK,1: comparator output filter clock = PCLK/2,2: comparator output filter clock = PCLK/4,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode is Selected"
|
|
bitfld.long 0x00 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "WKEN,Power-down Wakeup Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
bitfld.long 0x00 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP1 output is sampled 1 consecutive PCLK,2: ACMP1 output is sampled 2 consecutive PCLKs,3: ACMP1 output is sampled 4 consecutive PCLKs,4: ACMP1 output is sampled 8 consecutive PCLKs,5: ACMP1 output is sampled 16 consecutive PCLKs,6: ACMP1 output is sampled 32 consecutive PCLKs,7: ACMP1 output is sampled 64 consecutive PCLKs"
|
|
newline
|
|
bitfld.long 0x00 12. "OUTSEL,Comparator Output Select" "0: Comparator 1 output to ACMP1_O pin is..,1: Comparator 1 output to ACMP1_O pin is from.."
|
|
bitfld.long 0x00 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF1 will be set to 1 when comparator output edge condition is detected" "0: Rising edge or falling edge,1: Rising edge,2: Falling edge,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP1_P0,1: Input from ACMP1_P1,2: Input from ACMP1_P2,3: Input from ACMP1_P3"
|
|
bitfld.long 0x00 4.--5. "NEGSEL,Comparator Negative Input Selection\nNote: NEGSEL must select 2'b01 in calibration mode" "0: ACMP1_N pin,1: Internal comparator reference voltage (CRV1),2: Band-gap voltage,3: DAC0 output"
|
|
newline
|
|
bitfld.long 0x00 3. "ACMPOINV,Comparator Output Inverse Control" "0: Comparator 1 output inverse Disabled,1: Comparator 1 output inverse Enabled"
|
|
bitfld.long 0x00 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 1 interrupt Disabled,1: Comparator 1 interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 1 Disabled,1: Comparator 1 Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACMP_STATUS,Analog Comparator Status Register"
|
|
bitfld.long 0x00 16. "ACMPWO,Comparator Window Output\nThis bit shows the output status of window compare mode" "0: The positive input voltage is outside the..,1: The positive input voltage is in the window"
|
|
bitfld.long 0x00 13. "ACMPS1,Comparator 1 Status\nSynchronized to the PCLK to allow reading by software" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "ACMPS0,Comparator 0 Status \nSynchronized to the PCLK to allow reading by software" "0,1"
|
|
bitfld.long 0x00 9. "WKIF1,Comparator 1 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0" "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
|
|
newline
|
|
bitfld.long 0x00 8. "WKIF0,Comparator 0 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0" "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
|
|
bitfld.long 0x00 5. "ACMPO1,Comparator 1 Output\nSynchronized to the PCLK to allow reading by software" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ACMPO0,Comparator 0 Output\nSynchronized to the PCLK to allow reading by software" "0,1"
|
|
bitfld.long 0x00 1. "ACMPIF1,Comparator 1 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ACMPIF0,Comparator 0 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ACMP_VREF,Analog Comparator Reference Voltage Control Register"
|
|
bitfld.long 0x00 24. "CRV1EN,CRV1 Enable Bit" "0: CRV1 Disabled,1: CRV1 Enabled"
|
|
bitfld.long 0x00 22. "CRV1SSEL,CRV1 Source Voltage Selection" "0: AVDD is selected as CRV1 source voltage,1: The reference voltage defined by SYS_VREFCTL.."
|
|
newline
|
|
bitfld.long 0x00 16.--21. "CRV1SEL,Comparator1 Reference Voltage Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8. "CRV0EN,CRV0 Enable Bit" "0: CRV0 Disabled,1: CRV0 Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "CRV0SSEL,CRV0 Source Voltage Selection" "0: AVDD is selected as CRV0 source voltage,1: The reference voltage defined by SYS_VREFCTL.."
|
|
bitfld.long 0x00 0.--5. "CRV0SEL,Comparator0 Reference Voltage Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ACMP_CALCTL,Analog Comparator Calibration Control Register"
|
|
bitfld.long 0x00 1. "CALTRG1,Comparator1 Calibration Trigger Bit\n" "0: Calibration is stopped,1: Calibration is triggered"
|
|
bitfld.long 0x00 0. "CALTRG0,Comparator0 Calibration Trigger Bit\n" "0: Calibration is stopped,1: Calibration is triggered"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ACMP_CALSR,Analog Comparator Calibration Status Register"
|
|
bitfld.long 0x00 6. "CALPS1,Comparator1 Calibration Result Status for PMOS" "0: Pass,1: Fail"
|
|
bitfld.long 0x00 5. "CALNS1,Comparator1 Calibration Result Status for NMOS" "0: Pass,1: Fail"
|
|
newline
|
|
bitfld.long 0x00 4. "DONE1,Comparator1 Calibration Done Status" "0: Calibrating,1: Calibration done"
|
|
bitfld.long 0x00 2. "CALPS0,Comparator0 Calibration Result Status for PMOS" "0: Pass,1: Fail"
|
|
newline
|
|
bitfld.long 0x00 1. "CALNS0,Comparator0 Calibration Result Status for NMOS" "0: Pass,1: Fail"
|
|
bitfld.long 0x00 0. "DONE0,Comparator0 Calibration Done Status" "0: Calibrating,1: Calibration done"
|
|
tree.end
|
|
tree "BPWM (BPWM Register Map)"
|
|
repeat 2. (list 0. 1.) (list ad:0x4005A000 ad:0x4005B000)
|
|
tree "BPWM$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BPWM_CTL0,BPWM Control Register 0"
|
|
bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects BPWM..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 5. "CTRLD5,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 4. "CTRLD4,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 3. "CTRLD3,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 2. "CTRLD2,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 1. "CTRLD1,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 0. "CTRLD0,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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group.long 0x04++0x03
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line.long 0x00 "BPWM_CTL1,BPWM Control Register 1"
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bitfld.long 0x00 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n" "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),2: Up-down counter type,3: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "BPWM_CLKSRC,BPWM Clock Source Register"
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bitfld.long 0x00 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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group.long 0x14++0x03
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line.long 0x00 "BPWM_CLKPSC,BPWM Clock Prescale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler"
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group.long 0x20++0x03
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line.long 0x00 "BPWM_CNTEN,BPWM Counter Enable Register"
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bitfld.long 0x00 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
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group.long 0x24++0x03
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line.long 0x00 "BPWM_CNTCLR,BPWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR0,Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
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group.long 0x30++0x03
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line.long 0x00 "BPWM_PERIOD,BPWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,BPWM Period Register\nUp-Count mode: In this mode BPWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode BPWM counter counts from PERIOD to 0 and restarts from PERIOD"
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repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
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group.long ($2+0x50)++0x03
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line.long 0x00 "BPWM_CMPDAT$1,BPWM Comparator Register $1"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger EADC0.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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repeat.end
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rgroup.long 0x90++0x03
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line.long 0x00 "BPWM_CNT,BPWM Counter Register"
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bitfld.long 0x00 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,BPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xB0++0x03
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line.long 0x00 "BPWM_WGCTL0,BPWM Generation Register 0"
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bitfld.long 0x00 26.--27. "PRDPCTL5,BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 24.--25. "PRDPCTL4,BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 22.--23. "PRDPCTL3,BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 20.--21. "PRDPCTL2,BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 18.--19. "PRDPCTL1,BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 16.--17. "PRDPCTL0,BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 10.--11. "ZPCTL5,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 8.--9. "ZPCTL4,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 6.--7. "ZPCTL3,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 4.--5. "ZPCTL2,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 2.--3. "ZPCTL1,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 0.--1. "ZPCTL0,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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group.long 0xB4++0x03
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line.long 0x00 "BPWM_WGCTL1,BPWM Generation Register 1"
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bitfld.long 0x00 26.--27. "CMPDCTL5,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 24.--25. "CMPDCTL4,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 22.--23. "CMPDCTL3,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 20.--21. "CMPDCTL2,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 18.--19. "CMPDCTL1,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 16.--17. "CMPDCTL0,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 10.--11. "CMPUCTL5,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 8.--9. "CMPUCTL4,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 4.--5. "CMPUCTL2,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 0.--1. "CMPUCTL0,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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group.long 0xB8++0x03
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line.long 0x00 "BPWM_MSKEN,BPWM Mask Enable Register"
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bitfld.long 0x00 5. "MSKEN5,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 4. "MSKEN4,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 2. "MSKEN2,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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group.long 0xBC++0x03
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line.long 0x00 "BPWM_MSK,BPWM Mask Data Register"
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bitfld.long 0x00 5. "MSKDAT5,BPWM Mask Data Bit\nThis data bit controls the state of BPWMn output pin if the corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 4. "MSKDAT4,BPWM Mask Data Bit\nThis data bit controls the state of BPWMn output pin if the corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 3. "MSKDAT3,BPWM Mask Data Bit\nThis data bit controls the state of BPWMn output pin if the corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 2. "MSKDAT2,BPWM Mask Data Bit\nThis data bit controls the state of BPWMn output pin if the corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 1. "MSKDAT1,BPWM Mask Data Bit\nThis data bit controls the state of BPWMn output pin if the corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 0. "MSKDAT0,BPWM Mask Data Bit\nThis data bit controls the state of BPWMn output pin if the corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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group.long 0xD4++0x03
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line.long 0x00 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
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bitfld.long 0x00 5. "PINV5,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
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bitfld.long 0x00 4. "PINV4,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
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bitfld.long 0x00 2. "PINV2,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "BPWM_POEN,BPWM Output Enable Register"
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bitfld.long 0x00 5. "POEN5,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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bitfld.long 0x00 4. "POEN4,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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bitfld.long 0x00 3. "POEN3,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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bitfld.long 0x00 2. "POEN2,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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newline
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bitfld.long 0x00 1. "POEN1,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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bitfld.long 0x00 0. "POEN0,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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group.long 0xE0++0x03
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line.long 0x00 "BPWM_INTEN,BPWM Interrupt Enable Register"
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bitfld.long 0x00 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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newline
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bitfld.long 0x00 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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newline
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bitfld.long 0x00 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE8++0x03
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line.long 0x00 "BPWM_INTSTS,BPWM Interrupt Flag Register"
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bitfld.long 0x00 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 8. "PIF0,BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0 software can write 1 to clear this bit to 0" "0,1"
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bitfld.long 0x00 0. "ZIF0,BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0 software can write 1 to clear this bit to 0" "0,1"
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group.long 0xF8++0x03
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line.long 0x00 "BPWM_EADCTS0,BPWM Trigger EADC0 Source Select Register 0"
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bitfld.long 0x00 31. "TRGEN3,BPWM_CH3 Trigger EADC0 Enable Bit" "0,1"
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bitfld.long 0x00 24.--27. "TRGSEL3,BPWM_CH3 Trigger EADC0 Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count CMPDAT point,4: BPWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH3 up-count CMPDAT point,9: BPWM_CH3 down-count CMPDAT point,?..."
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bitfld.long 0x00 23. "TRGEN2,BPWM_CH2 Trigger EADC0 Enable Bit" "0,1"
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bitfld.long 0x00 16.--19. "TRGSEL2,BPWM_CH2 Trigger EADC0 Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count CMPDAT point,4: BPWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH3 up-count CMPDAT point,9: BPWM_CH3 down-count CMPDAT point,?..."
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bitfld.long 0x00 15. "TRGEN1,BPWM_CH1 Trigger EADC0 Enable Bit" "0,1"
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bitfld.long 0x00 8.--11. "TRGSEL1,BPWM_CH1 Trigger EADC0 Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count CMPDAT point,4: BPWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH1 up-count CMPDAT point,9: BPWM_CH1 down-count CMPDAT point,?..."
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bitfld.long 0x00 7. "TRGEN0,BPWM_CH0 Trigger EADC0 Enable Bit" "0,1"
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bitfld.long 0x00 0.--3. "TRGSEL0,BPWM_CH0 Trigger EADC0 Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count CMPDAT point,4: BPWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH1 up-count CMPDAT point,9: BPWM_CH1 down-count CMPDAT point,?..."
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group.long 0xFC++0x03
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line.long 0x00 "BPWM_EADCTS1,BPWM Trigger EADC0 Source Select Register 1"
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bitfld.long 0x00 15. "TRGEN5,BPWM_CH5 Trigger EADC0 Enable Bit" "0,1"
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bitfld.long 0x00 8.--11. "TRGSEL5,BPWM_CH5 Trigger EADC0 Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count CMPDAT point,4: BPWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH5 up-count CMPDAT point,9: BPWM_CH5 down-count CMPDAT point,?..."
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bitfld.long 0x00 7. "TRGEN4,BPWM_CH4 Trigger EADC0 Enable Bit" "0,1"
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bitfld.long 0x00 0.--3. "TRGSEL4,BPWM_CH4 Trigger EADC0 Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count CMPDAT point,4: BPWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH5 up-count CMPDAT point,9: BPWM_CH5 down-count CMPDAT point,?..."
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group.long 0x110++0x03
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line.long 0x00 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
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bitfld.long 0x00 8.--9. "SSRC,BPWM Synchronous Start Source Select" "0: Synchronous start source come from PWM0,1: Synchronous start source come from PWM1,2: Synchronous start source come from BPWM0,3: Synchronous start source come from BPWM1"
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bitfld.long 0x00 0. "SSEN0,BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)" "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
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wgroup.long 0x114++0x03
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line.long 0x00 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
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bitfld.long 0x00 0. "CNTSEN,BPWM Counter Synchronous Start Enable Bit(Write Only)\nBPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM.." "0,1"
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group.long 0x120++0x03
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line.long 0x00 "BPWM_STATUS,BPWM Status Register"
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bitfld.long 0x00 21. "EADCTRG5,EADC0 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No EADC0 start of conversion trigger event..,1: An EADC0 start of conversion trigger event.."
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bitfld.long 0x00 20. "EADCTRG4,EADC0 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No EADC0 start of conversion trigger event..,1: An EADC0 start of conversion trigger event.."
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bitfld.long 0x00 19. "EADCTRG3,EADC0 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No EADC0 start of conversion trigger event..,1: An EADC0 start of conversion trigger event.."
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bitfld.long 0x00 18. "EADCTRG2,EADC0 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No EADC0 start of conversion trigger event..,1: An EADC0 start of conversion trigger event.."
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bitfld.long 0x00 17. "EADCTRG1,EADC0 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No EADC0 start of conversion trigger event..,1: An EADC0 start of conversion trigger event.."
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bitfld.long 0x00 16. "EADCTRG0,EADC0 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No EADC0 start of conversion trigger event..,1: An EADC0 start of conversion trigger event.."
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bitfld.long 0x00 0. "CNTMAXF0,Time-base Counter 0 Equal to 0xFFFF Latched Flag" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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group.long 0x200++0x03
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line.long 0x00 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
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bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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group.long 0x204++0x03
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line.long 0x00 "BPWM_CAPCTL,BPWM Capture Control Register"
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bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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rgroup.long 0x208++0x03
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line.long 0x00 "BPWM_CAPSTS,BPWM Capture Status Register"
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bitfld.long 0x00 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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newline
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bitfld.long 0x00 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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newline
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bitfld.long 0x00 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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rgroup.long 0x20C++0x03
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line.long 0x00 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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rgroup.long 0x210++0x03
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line.long 0x00 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x214++0x03
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line.long 0x00 "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x218++0x03
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line.long 0x00 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x21C++0x03
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line.long 0x00 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x220++0x03
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line.long 0x00 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x224++0x03
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line.long 0x00 "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x228++0x03
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line.long 0x00 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x22C++0x03
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line.long 0x00 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x230++0x03
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line.long 0x00 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x234++0x03
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line.long 0x00 "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x238++0x03
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line.long 0x00 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x250++0x03
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line.long 0x00 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
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bitfld.long 0x00 8.--13. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled,?..."
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bitfld.long 0x00 0.--5. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled,?..."
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group.long 0x254++0x03
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line.long 0x00 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
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bitfld.long 0x00 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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rgroup.long 0x304++0x03
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|
line.long 0x00 "BPWM_PBUF,BPWM PERIOD Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0x31C++0x03
|
|
line.long 0x00 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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|
group.long 0x320++0x03
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|
line.long 0x00 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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|
group.long 0x324++0x03
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line.long 0x00 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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|
group.long 0x328++0x03
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|
line.long 0x00 "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x32C++0x03
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line.long 0x00 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x330++0x03
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line.long 0x00 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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tree.end
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repeat.end
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tree.end
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tree "CIR0 (CIR0 Register Map)"
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base ad:0x4005F000
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group.long 0x00++0x03
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line.long 0x00 "CIR_CTL,CIR Control Register"
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bitfld.long 0x00 16.--18. "PSCALER,Sampling Clock Prescaler\nNote: The sampling clock should be less than PCLK1" "0: No prescaler,1: Prescaler is 2 clocks,2: Prescaler is 4 clocks,3: Prescaler is 8 clocks,4: Prescaler is 16 clocks,5: Prescaler is 32 clocks,6: Prescaler is 64 clocks,7: Prescaler is 128 clocks"
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bitfld.long 0x00 11. "FOSTRS,Filter Output Signal Stored in Register Selection" "0: Filter output signal stored in CIR_STATUS[16]..,1: Filter output signal stored in CIR_STATUS[16].."
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bitfld.long 0x00 9.--10. "DBSEL,Debounce Sampling Selection" "0: CIR noise filter Disabled,1: CIR input debounce count Enabled with two..,2: CIR input debounce count Enabled with three..,3: CIR input debounce count Enabled with four.."
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bitfld.long 0x00 5.--6. "PATTYP,CIR Pattern Format Selection" "0: Standardized positive edge mode,1: Standardized negative edge mode,2: Flexible positive edge mode,3: Reserved"
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bitfld.long 0x00 4. "ERRBYP,Error Pattern Bypass\nNote: \nIf user clears RERRF(CIR_STATUS[6]) then CIR will keep to convert data and store in CIR_DATAx.\nUser must set ERRBYP (CIR_CTL[4]) to 1 before entering Power-down mode" "0: Data will be dropped if RERRF(CIR_STATUS[6])..,1: Data will keep to save in DATAx if.."
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bitfld.long 0x00 1. "POLINV,CIR Input Polarity Inverse" "0: CIR input polarity is normal,1: CIR input polarity is inversed"
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bitfld.long 0x00 0. "CNTEN,CIR Counter Enable\nNote: When user changes CNTEN (CIR_CTL[0]) from 0 to 1 system will generate a signal to initialize all interrupt flags RBITCNT (CIR_RDBC[5:0])and ITVR (CIR_ITVR[31:0])" "0: CIR counter Disabled,1: CIR counter Enabled"
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group.long 0x04++0x03
|
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line.long 0x00 "CIR_CMPCTL,CIR Data Compare Control Register"
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bitfld.long 0x00 24.--26. "CMPVALID,Data Compared Valid Bit Selection\nNote: The sampling clock should be less than PCLK1" "0: Compare bit 0,1: Compare bit 0 to bit 1,2: Compare bit 0 to bit 2,3: Compare bit 0 to bit 3,4: Compare bit 0 to bit 4,5: Compare bit 0 to bit 5,6: Compare bit 0 to bit 6,7: Compare bit 0 to bit 7"
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bitfld.long 0x00 16. "CMPMSK,Data Compared Mask Initialization\nNote: This bit is auto cleared by hardware" "0: No effect,1: Re-initialize the data compared match.."
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bitfld.long 0x00 8. "DCMPEN,Data Compared Match Function Selection" "0: Data compared match function Disabled,1: Data compared match function Enabled"
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|
hexmask.long.byte 0x00 0.--7. 1. "CMPDAT,Compared Match Data\nThis bit field should be filled with the expected data"
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group.long 0x08++0x03
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line.long 0x00 "CIR_STATUS,CIR Status Register"
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bitfld.long 0x00 17. "RBITCBS,RBITCNT Busy Clearing Status" "0: RBITCNT has completed the clearing process..,1: RBITCNT undergoes clearing process when user.."
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bitfld.long 0x00 16. "NFOS,Noise Filter Output Signal Status" "0: Noise filter output value is 0,1: Noise filter output value is 1"
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bitfld.long 0x00 10. "PDWKF,Power Down Wake Up Flag\nNote: This bit is only cleared by writing 1 to it" "0: Power down wake up never happened,1: Power down wake up happened"
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bitfld.long 0x00 9. "RBMF,Receive Bit Match Flag\nNote: This bit is only cleared by writing 1 to it" "0: Receive bit match never happened,1: Receive bit match happened"
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bitfld.long 0x00 8. "EPMF,End Pattern Match Flag\nNote: This bit is only cleared by writing 1 to it" "0: End pattern match never happened,1: End pattern match happened"
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bitfld.long 0x00 7. "COMPMF,Compare Match Flag\nNote: This bit is only cleared by writing 1 to it" "0: Compare match never happened,1: Compare match happened"
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bitfld.long 0x00 6. "RERRF,Receive Error Flag\nNote: This bit is only cleared by writing 1 to it" "0: Receive error never happened,1: Receive error happened"
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bitfld.long 0x00 5. "DRECF,Data Receive Flag\nNote: This bit is only cleared by writing 1 to it" "0: CIR has not started to convert data,1: CIR has started to convert data"
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bitfld.long 0x00 4. "RBUFF,Receiving Buffer Full Flag\nNote: This bit is only cleared by writing 1 to it" "0: Receiving buffer full never happened,1: Receiving buffer full happened"
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bitfld.long 0x00 3. "HPMF,Header Pattern Match Flag\nNote: This bit is only cleared by writing 1 to it" "0: Header pattern never happened,1: Header pattern happened"
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bitfld.long 0x00 2. "D0PMF,Data0 Pattern Match Flag\nNote: This bit is only cleared by writing 1 to it" "0: Data0 pattern never happened,1: Data0 pattern happened"
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bitfld.long 0x00 1. "D1PMF,Data1 Pattern Match Flag\nNote: This bit is only cleared by writing 1 to it" "0: Data1 pattern never happened,1: Data1 pattern happened"
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bitfld.long 0x00 0. "SPMF,Special Pattern Match Flag\nNote: This bit is only cleared by writing 1 to it" "0: Special pattern never happened,1: Special pattern happened"
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|
group.long 0x10++0x03
|
|
line.long 0x00 "CIR_INTCTL,CIR Interrupt Control Register"
|
|
bitfld.long 0x00 10. "PDWKIEN,Power Down Wake-up interrupt Enable Bit" "0: Power down wake-up interrupt Disabled,1: Power down wake-up interrupt Enabled"
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bitfld.long 0x00 9. "RBMIEN,Receive Bit Match Interrupt Enable Bit" "0: Receive bit match interrupt Disabled,1: Receive bit match interrupt Enabled"
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bitfld.long 0x00 8. "EPMIEN,End Pattern Match Interrupt Enable Bit" "0: End pattern match interrupt Disabled,1: End pattern match interrupt Enabled"
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bitfld.long 0x00 7. "CMPMIEN,Compare Match Interrupt Enable Bit" "0: Compare match interrupt Disabled,1: Compare match interrupt Enabled"
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|
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bitfld.long 0x00 6. "PERRIEN,Pattern Error Interrupt Enable Bit" "0: Pattern error interrupt Disabled,1: Pattern error interrupt Enabled"
|
|
bitfld.long 0x00 5. "DRECIEN,Data Receive Interrupt Enable Bit" "0: Data receive interrupt Disabled,1: Data receive interrupt Enabled"
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|
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bitfld.long 0x00 4. "RBUFIEN,Receive Buffer Full Interrupt Enable Bit" "0: Receive buffer full interrupt Disabled,1: Receive buffer full interrupt Enabled"
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bitfld.long 0x00 3. "HPMIEN,Header Pattern Match Interrupt Enable Bit" "0: Header pattern match interrupt Disabled,1: Header pattern match interrupt Enabled"
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|
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bitfld.long 0x00 2. "D0PMIEN,Data0 Pattern Match Interrupt Enable Bit" "0: Data0 pattern match interrupt Disabled,1: Data0 pattern match interrupt Enabled"
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bitfld.long 0x00 1. "D1PMIEN,Data1 Pattern Match Interrupt Enable Bit" "0: Data1 pattern match interrupt Disabled,1: Data1 pattern match interrupt Enabled"
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|
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bitfld.long 0x00 0. "SPMIEN,Special Pattern Match Interrupt Enable Bit" "0: Special pattern match interrupt Disabled,1: Special pattern match interrupt Enabled"
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group.long 0x18++0x03
|
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line.long 0x00 "CIR_HDBOUND,CIR Header Pattern Boundry Register"
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hexmask.long.word 0x00 16.--26. 1. "HBOUND,High Boundary Header Pattern\nUpper limit of Header pattern input range.\nNote: If HBOUND and LBOUND are equal to 0 the CIR controller will not monitor the Header pattern boundary"
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hexmask.long.word 0x00 0.--10. 1. "LBOUND,Low Boundary Header Pattern\nLower limit of Header pattern input range.\nNote: If HBOUND and LBOUND are equal to 0 the CIR controller will not monitor the Header pattern boundary"
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group.long 0x1C++0x03
|
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line.long 0x00 "CIR_D0BOUND,CIR Data 0 Pattern Boundry Register"
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hexmask.long.word 0x00 16.--26. 1. "HBOUND,High Boundary Data0 Pattern\nUpper limit of Data 0 pattern input range.\nNote: If HBOUND and LBOUND are equal to 0 the CIR controller will not monitor the Data0 pattern boundary"
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hexmask.long.word 0x00 0.--10. 1. "LBOUND,Low Boundary Data0 Pattern\nLower limit of Data 0 pattern input range.\nNote: If HBOUND and LBOUND are equal to 0 the CIR controller will not monitor the Data0 pattern boundary"
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group.long 0x20++0x03
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line.long 0x00 "CIR_D1BOUND,CIR Data 1 Pattern Boundry Register"
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hexmask.long.word 0x00 16.--26. 1. "HBOUND,High Boundary Data 1 Pattern\nUpper limit of Data 1 pattern input range.\nNote: If HBOUND and LBOUND are equal to 0 the CIR controller will not monitor the Data1 pattern boundary"
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hexmask.long.word 0x00 0.--10. 1. "LBOUND,Low Boundary Data 1 Pattern\nUpper limit of Data 1 pattern input range.\nNote: If HBOUND and LBOUND are equal to 0 the CIR controller will not monitor the Data1 pattern boundary"
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group.long 0x24++0x03
|
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line.long 0x00 "CIR_SPBOUND,CIR Special Pattern Boundry Register"
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hexmask.long.word 0x00 16.--26. 1. "HBOUND,High Boundary Special Pattern\nUpper limit of Special pattern input range.\nNote: If HBOUND and LBOUND are equal to 0 the CIR controller will not monitor the Special pattern boundary"
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hexmask.long.word 0x00 0.--10. 1. "LBOUND,Low Boundary Special Pattern\nLower limit of Special pattern input range.\nNote: If HBOUND and LBOUND are equal to 0 the CIR controller will not monitor the Special pattern boundary"
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group.long 0x28++0x03
|
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line.long 0x00 "CIR_ENDBOUND,CIR End Pattern Boundry Register"
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hexmask.long.word 0x00 0.--10. 1. "LBOUND,Low Boundary End Pattern\nLower limit of End pattern input range"
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rgroup.long 0x38++0x03
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line.long 0x00 "CIR_LTVR,CIR Latch Timer Value Register"
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hexmask.long.word 0x00 0.--10. 1. "LTV,Latch Timer Value\nThe register is used to record CIR latch timer value.\nNote: User can only read this register when HPMF (CIR_STATUS[3]) D0PMF (CIR_STATUS[2]) D1PMF (CIR_STATUS[1]) SPMF (CIR_STATUS[0]) or RERRF (CIR_STATUS[6]) occurred"
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group.long 0x3C++0x03
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line.long 0x00 "CIR_RDBC,CIR Receive Data Bit Count Register"
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hexmask.long.byte 0x00 16.--22. 1. "RBITCMP,Receive Data Bit Compare Data\nUser can limit the converted data length by RBITCMP register"
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bitfld.long 0x00 8. "BCCMEN,Bit Count Compared Match Selection" "0: Bit count compared match function Disabled,1: Bit count compared match function Enabled"
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|
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hexmask.long.byte 0x00 0.--6. 1. "RBITCNT,Receive Data Bit Counts\nRBITCNT (CIR_RDBC[5:0]) correspond to CIR_DATA0 and CIR_DATA1 when CIR starts to convert data.\nNote: \n1"
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group.long 0x40++0x03
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line.long 0x00 "CIR_DATA0,CIR Receive Data0 Register"
|
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hexmask.long 0x00 0.--31. 1. "DATA0,CIR DATA0 Register\nCIR converts data and stores the data in Data0 when RBITCNT(CIR_RDBC[5:0]) value is between 0 to 31.\nNote: User can write 1 to CIR_DATA0[31:0] to clean DATA0 value only when the register CNTEN(CIR_CTL[0]) is set to 0"
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group.long 0x44++0x03
|
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line.long 0x00 "CIR_DATA1,CIR Receive Data1 Register"
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hexmask.long 0x00 0.--31. 1. "DATA1,CIR DATA1 Register\nCIR converts data and stores the data in Data1 when RBITCNT(CIR_RDBC[5:0]) value is between 32 to 63.\nNote: User can write 1 to CIR_DATA1[31:0] to clean DATA1 value only when the register CNTEN(CIR_CTL[0]) is set to 0"
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tree.end
|
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tree "CLK (CLK Register Map)"
|
|
base ad:0x40000200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CLK_PWRCTL,System Power-down Control Register"
|
|
bitfld.long 0x00 31. "HXTMD,HXT Bypass Mode (Write Protect)\nThis is a protected register" "0: HXT work as crystal mode,1: HXT works as external clock mode"
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bitfld.long 0x00 20.--22. "HXTGAIN,HXT Gain Control Bit (Write Protect)\nThis is a protected register" "0: HXT frequency is from 4 MHz to 8 MHz.\nHXT..,1: HXT frequency is from 8 MHz to 12 MHz.\nHXT..,2: HXT frequency is from 12 MHz to 16 MHz.\nHXT..,3: HXT frequency is from 16 MHz to 24 MHz.\nHXT..,4: HXT frequency is from 4 MHz to 8 MHz,5: HXT frequency is from 8 MHz to 12 MHz,6: HXT frequency is from 12 MHz to 16 MHz,7: HXT frequency is from 16 MHz to 24 MHz"
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bitfld.long 0x00 16.--17. "HIRCSTBS,HIRC Stable Count Select (Write Protect)\nOthers: Reserved\nNote: This bit is write protected" "0: HIRC stable count = 512 clocks,1: HIRC stable count = 1024 clocks,2: HIRC stable count = 2048 clocks,3: HIRC stable count = 256 clocks"
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bitfld.long 0x00 7. "PDEN,System Power-down Enable (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode this bit.." "0: Chip will not enter Power-down mode after CPU..,1: Chip enters Power-down mode after CPU sleep.."
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bitfld.long 0x00 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' it indicates that resume from Power-down mode' \nThe flag is set if any wake-up source is occurred" "0,1"
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bitfld.long 0x00 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\n" "0: Power-down mode wake-up interrupt Disabled,1: Power-down mode wake-up interrupt Enabled"
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newline
|
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bitfld.long 0x00 4. "PDWKDLY,Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at 4~24.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
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bitfld.long 0x00 3. "LIRCEN,LIRC Enable Bit (Write Protect)\nNote: This bit is write protected" "0: 38.4 kHz internal low speed RC oscillator..,1: 38.4 kHz internal low speed RC oscillator.."
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bitfld.long 0x00 2. "HIRCEN,HIRC Enable Bit (Write Protect)\nNote: This bit is write protected" "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.."
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bitfld.long 0x00 1. "LXTEN,LXT Enable Bit (Write Protect)\n" "0: 32.768 kHz external low speed crystal (LXT)..,1: 32.768 kHz external low speed crystal (LXT).."
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|
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bitfld.long 0x00 0. "HXTEN,HXT Enable Bit (Write Protect)\n" "0: 4~24 MHz external high speed crystal (HXT)..,1: 4~24 MHz external high speed crystal (HXT).."
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group.long 0x04++0x03
|
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line.long 0x00 "CLK_AHBCLK,AHB Devices Clock Enable Control Register"
|
|
bitfld.long 0x00 31. "GPHCKEN,GPIOH Clock Enable Bit" "0: GPIOH port clock Disabled,1: GPIOH port clock Enabled"
|
|
bitfld.long 0x00 30. "GPGCKEN,GPIOG Clock Enable Bit" "0: GPIOG port clock Disabled,1: GPIOG port clock Enabled"
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|
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bitfld.long 0x00 29. "GPFCKEN,GPIOF Clock Enable Bit" "0: GPIOF port clock Disabled,1: GPIOF port clock Enabled"
|
|
bitfld.long 0x00 28. "GPECKEN,GPIOE Clock Enable Bit" "0: GPIOE port clock Disabled,1: GPIOE port clock Enabled"
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newline
|
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bitfld.long 0x00 27. "GPDCKEN,GPIOD Clock Enable Bit" "0: GPIOD port clock Disabled,1: GPIOD port clock Enabled"
|
|
bitfld.long 0x00 26. "GPCCKEN,GPIOC Clock Enable Bit" "0: GPIOC port clock Disabled,1: GPIOC port clock Enabled"
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|
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bitfld.long 0x00 25. "GPBCKEN,GPIOB Clock Enable Bit" "0: GPIOB port clock Disabled,1: GPIOB port clock Enabled"
|
|
bitfld.long 0x00 24. "GPACKEN,GPIOA Clock Enable Bit" "0: GPIOA port clock Disabled,1: GPIOA port clock Enabled"
|
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|
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bitfld.long 0x00 23. "GPICKEN,GPIOI Clock Enable Bit" "0: GPIOI port clock Disabled,1: GPIOI port clock Enabled"
|
|
bitfld.long 0x00 19. "TRACECKEN,TRACE Clock Enable Bit" "0: TRACE clock Disabled,1: TRACE clock Enabled"
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|
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bitfld.long 0x00 15. "FMCIDLE,Flash Memory Controller Clock Enable Bit in IDLE Mode" "0: FMC clock Disabled when chip is under IDLE mode,1: FMC clock Enabled when chip is under IDLE mode"
|
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bitfld.long 0x00 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit" "0: CRC peripheral clock Disabled,1: CRC peripheral clock Enabled"
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|
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bitfld.long 0x00 4. "STCLKEN,Cortex-M4 SysTick Clock Enable Bit" "0: Cortex-M4 sys tick clock Disabled,1: Cortex-M4 sys tick clock Enabled"
|
|
bitfld.long 0x00 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
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|
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bitfld.long 0x00 1. "PDMACKEN,PDMA Controller Clock Enable Bit" "0: PDMA peripheral clock Disabled,1: PDMA peripheral clock Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0"
|
|
bitfld.long 0x00 28. "EADCCKEN,Enhanced Analog-digital-converter (EADC) Clock Enable Bit" "0: EADC clock Disabled,1: EADC clock Enabled"
|
|
bitfld.long 0x00 21. "UART5CKEN,UART5 Clock Enable Bit" "0: UART5 clock Disabled,1: UART5 clock Enabled"
|
|
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|
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bitfld.long 0x00 20. "UART4CKEN,UART4 Clock Enable Bit" "0: UART4 clock Disabled,1: UART4 clock Enabled"
|
|
bitfld.long 0x00 19. "UART3CKEN,UART3 Clock Enable Bit" "0: UART3 clock Disabled,1: UART3 clock Enabled"
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|
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|
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bitfld.long 0x00 18. "UART2CKEN,UART2 Clock Enable Bit" "0: UART2 clock Disabled,1: UART2 clock Enabled"
|
|
bitfld.long 0x00 17. "UART1CKEN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled"
|
|
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|
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bitfld.long 0x00 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled"
|
|
bitfld.long 0x00 14. "SPI1CKEN,SPI1 Clock Enable Bit" "0: SPI1 clock Disabled,1: SPI1 clock Enabled"
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|
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|
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bitfld.long 0x00 13. "SPI0CKEN,SPI0 Clock Enable Bit" "0: SPI0 clock Disabled,1: SPI0 clock Enabled"
|
|
bitfld.long 0x00 9. "I2C1CKEN,I2C1 Clock Enable Bit" "0: I2C1 clock Disabled,1: I2C1 clock Enabled"
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|
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|
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bitfld.long 0x00 8. "I2C0CKEN,I2C0 Clock Enable Bit" "0: I2C0 clock Disabled,1: I2C0 clock Enabled"
|
|
bitfld.long 0x00 7. "ACMP01CKEN,Analog Comparator 0/1 Clock Enable Bit" "0: Analog comparator 0/1 clock Disabled,1: Analog comparator 0/1 clock Enabled"
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|
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|
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bitfld.long 0x00 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO clock Disabled,1: CLKO clock Enabled"
|
|
bitfld.long 0x00 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 clock Disabled,1: Timer3 clock Enabled"
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|
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|
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bitfld.long 0x00 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 clock Disabled,1: Timer2 clock Enabled"
|
|
bitfld.long 0x00 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
|
|
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|
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bitfld.long 0x00 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
|
|
bitfld.long 0x00 1. "RTCCKEN,Real-time-clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only" "0: RTC clock Disabled,1: RTC clock Enabled"
|
|
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|
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bitfld.long 0x00 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected" "0: Watchdog timer clock Disabled,1: Watchdog timer clock Enabled"
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|
group.long 0x0C++0x03
|
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line.long 0x00 "CLK_APBCLK1,APB Devices Clock Enable Control Register 1"
|
|
bitfld.long 0x00 24. "PRNGCKEN,PRNG Clock Enable Bit" "0: PRNG clock Disabled,1: PRNG clock Enabled"
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bitfld.long 0x00 19. "BPWM1CKEN,BPWM1 Clock Enable Bit" "0: BPWM1 clock Disabled,1: BPWM1 clock Enabled"
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bitfld.long 0x00 18. "BPWM0CKEN,BPWM0 Clock Enable Bit" "0: BPWM0 clock Disabled,1: BPWM0 clock Enabled"
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bitfld.long 0x00 17. "EPWM1CKEN,EPWM1 Clock Enable Bit" "0: EPWM1 clock Disabled,1: EPWM1 clock Enabled"
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bitfld.long 0x00 16. "EPWM0CKEN,EPWM0 Clock Enable Bit" "0: EPWM0 clock Disabled,1: EPWM0 clock Enabled"
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|
bitfld.long 0x00 15. "CIR0CKEN,CIR0 Clock Enable Bit" "0: CIR0 clock Disabled,1: CIR0 clock Enabled"
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bitfld.long 0x00 12. "DACCKEN,DAC Clock Enable Bit" "0: DAC clock Disabled,1: DAC clock Enabled"
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|
group.long 0x10++0x03
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line.long 0x00 "CLK_CLKSEL0,Clock Source Select Control Register 0"
|
|
bitfld.long 0x00 3.--5. "STCLKSEL,Cortex-M4 SysTick Clock Source Selection (Write Protect)\n" "0: Clock source from HXT,1: Clock source from LXT,2: Clock source from HXT/2,3: Clock source from HCLK/2,?,?,?,7: Clock source from HIRC/2"
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bitfld.long 0x00 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on.\nThe default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration.." "0: Clock source from HXT,1: Clock source from LXT,2: Clock source from PLL,3: Clock source from LIRC,?,?,?,7: Clock source from HIRC"
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|
group.long 0x14++0x03
|
|
line.long 0x00 "CLK_CLKSEL1,Clock Source Select Control Register 1"
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bitfld.long 0x00 30.--31. "WWDTSEL,Window Watchdog Timer Clock Source Selection" "?,?,2: Clock source from HCLK/2048,3: Clock source from internal low speed RC.."
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bitfld.long 0x00 28.--29. "CLKOSEL,Clock Divider Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from HCLK,3: Clock source from internal high speed RC.."
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bitfld.long 0x00 26.--27. "UART1SEL,UART1 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC.."
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bitfld.long 0x00 24.--25. "UART0SEL,UART0 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC.."
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bitfld.long 0x00 20.--22. "TMR3SEL,TIMER3 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from PCLK1,3: Clock source from external clock TM3 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.."
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bitfld.long 0x00 16.--18. "TMR2SEL,TIMER2 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from PCLK1,3: Clock source from external clock TM2 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.."
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bitfld.long 0x00 12.--14. "TMR1SEL,TIMER1 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from PCLK0,3: Clock source from external clock TM1 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.."
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bitfld.long 0x00 8.--10. "TMR0SEL,TIMER0 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from PCLK0,3: Clock source from external clock TM0 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.."
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bitfld.long 0x00 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect)\nNote: This bit is write protected" "0: Reserved,1: Clock source from external low speed crystal..,2: Clock source from HCLK/2048,3: Clock source from internal low speed RC.."
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group.long 0x18++0x03
|
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line.long 0x00 "CLK_CLKSEL2,Clock Source Select Control Register 2"
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bitfld.long 0x00 24.--26. "CIR0SEL,CIR0 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from Timer0 clock output (TM0),3: Clock source from internal low speed RC..,4: Clock source from internal high speed RC..,?..."
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bitfld.long 0x00 9. "BPWM1SEL,BPWM1 Clock Source Selection\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL" "0: Clock source from HCLK,1: Clock source from PCLK1"
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bitfld.long 0x00 8. "BPWM0SEL,BPWM0 Clock Source Selection\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL" "0: Clock source from HCLK,1: Clock source from PCLK0"
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bitfld.long 0x00 6.--7. "SPI1SEL,SPI1 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from PCLK0,3: Clock source from internal high speed RC.."
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bitfld.long 0x00 4.--5. "SPI0SEL,SPI0 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from PCLK1,3: Clock source from internal high speed RC.."
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bitfld.long 0x00 1. "EPWM1SEL,EPWM1 Clock Source Selection\nThe peripheral clock source of EPWM1 is defined by EPWM1SEL" "0: Clock source from HCLK,1: Clock source from PCLK1"
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bitfld.long 0x00 0. "EPWM0SEL,EPWM0 Clock Source Selection\nThe peripheral clock source of EPWM0 is defined by EPWM0SEL" "0: Clock source from HCLK,1: Clock source from PCLK0"
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group.long 0x1C++0x03
|
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line.long 0x00 "CLK_CLKSEL3,Clock Source Select Control Register 3"
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bitfld.long 0x00 30.--31. "UART5SEL,UART5 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC.."
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bitfld.long 0x00 28.--29. "UART4SEL,UART4 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC.."
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bitfld.long 0x00 26.--27. "UART3SEL,UART3 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC.."
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bitfld.long 0x00 24.--25. "UART2SEL,UART2 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC.."
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group.long 0x20++0x03
|
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line.long 0x00 "CLK_CLKDIV0,Clock Divider Number Register 0"
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hexmask.long.byte 0x00 16.--23. 1. "EADCDIV,EADC Clock Divide Number From EADC Clock Source"
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bitfld.long 0x00 12.--15. "UART1DIV,UART1 Clock Divide Number From UART1 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "UART0DIV,UART0 Clock Divide Number From UART0 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
|
|
line.long 0x00 "CLK_CLKDIV4,Clock Divider Number Register 4"
|
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hexmask.long.byte 0x00 24.--31. 1. "TRACEDIV,Cortex M4 ETM Trace Clock Divide Number From ETM Trace Clock Source"
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bitfld.long 0x00 12.--15. "UART5DIV,UART5 Clock Divide Number From UART5 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 8.--11. "UART4DIV,UART4 Clock Divide Number From UART4 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "UART3DIV,UART3 Clock Divide Number From UART3 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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bitfld.long 0x00 0.--3. "UART2DIV,UART2 Clock Divide Number From UART2 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x34++0x03
|
|
line.long 0x00 "CLK_PCLKDIV,APB Clock Divider Register"
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|
bitfld.long 0x00 4.--6. "APB1DIV,APB1 Clock Divider\nAPB1 clock can be divided from HCLK\nOthers: Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "APB0DIV,APB0 Clock Divider\nAPB0 clock can be divided from HCLK\nOthers: Reserved" "0,1,2,3,4,5,6,7"
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group.long 0x40++0x03
|
|
line.long 0x00 "CLK_PLLCTL,PLL Control Register"
|
|
bitfld.long 0x00 23. "STBSEL,PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected" "0: PLL stable time is 6144 PLL source clock..,1: PLL stable time is 16128 PLL source clock.."
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bitfld.long 0x00 19. "PLLSRC,PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected" "0: PLL source clock from 4~24 MHz external..,1: PLL source clock from 48 MHz internal.."
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|
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bitfld.long 0x00 18. "OE,PLL OE (FOUT Enable) Pin Control (Write Protect)\nNote: This bit is write protected" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
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bitfld.long 0x00 17. "BP,PLL Bypass Control (Write Protect)\nNote: This bit is write protected" "0: PLL is in normal mode (default),1: PLL clock output is same as PLL input clock FIN"
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|
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|
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bitfld.long 0x00 16. "PD,Power-down Mode (Write Protect)\nIf set the PDEN bit to 1 in CLK_PWRCTL register the PLL will enter Power-down mode too.\nNote: This bit is write protected" "0: PLL is in normal mode,1: PLL is in Power-down mode (default)"
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bitfld.long 0x00 14.--15. "OUTDIV,PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected" "0,1,2,3"
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|
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bitfld.long 0x00 9.--13. "INDIV,PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--8. 1. "FBDIV,PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected"
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rgroup.long 0x50++0x03
|
|
line.long 0x00 "CLK_STATUS,Clock Status Monitor Register"
|
|
bitfld.long 0x00 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source" "0: Clock switching success,1: Clock switching failure"
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|
bitfld.long 0x00 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.."
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|
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|
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bitfld.long 0x00 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: 38.4 kHz internal low speed RC oscillator..,1: 38.4 kHz internal low speed RC oscillator.."
|
|
bitfld.long 0x00 2. "PLLSTB,Internal PLL Clock Source Stable Flag (Read Only)" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable and enabled"
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|
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|
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bitfld.long 0x00 1. "LXTSTB,LXT Clock Source Stable Flag (Read Only)" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
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bitfld.long 0x00 0. "HXTSTB,HXT Clock Source Stable Flag (Read Only)" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CLK_CLKOCTL,Clock Output Control Register"
|
|
bitfld.long 0x00 6. "CLK1HZEN,Clock Output 1Hz Enable Bit\nNote: Output for 32.768 kHz(LXT) or 38 kHz(LIRC) based on RTCCKSEL(RTC_LXTCTL[7])" "0: 1 Hz clock output for 32.768 kHz or 38 kHz..,1: 1 Hz clock output for 32.768 kHz or 38 kHz.."
|
|
bitfld.long 0x00 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.."
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|
newline
|
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bitfld.long 0x00 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled"
|
|
bitfld.long 0x00 0.--3. "FREQSEL,Clock Output Frequency Selection\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CLK_CLKDCTL,Clock Fail Detector Control Register"
|
|
bitfld.long 0x00 17. "HXTFQIEN,HXT Clock Frequency Range Detector Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
bitfld.long 0x00 16. "HXTFQDEN,HXT Clock Frequency Range Detector Enable Bit" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
newline
|
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bitfld.long 0x00 13. "LXTFIEN,LXT Clock Fail Interrupt Enable Bit" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
|
|
bitfld.long 0x00 12. "LXTFDEN,LXT Clock Fail Detector Enable Bit" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
|
|
newline
|
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bitfld.long 0x00 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
bitfld.long 0x00 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CLK_CLKDSTS,Clock Fail Detector Status Register"
|
|
bitfld.long 0x00 8. "HXTFQIF,HXT Clock Frequency Range Detector Interrupt Flag\nNote: Write 1 to clear the bit to 0" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
bitfld.long 0x00 1. "LXTFIF,LXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
|
|
newline
|
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bitfld.long 0x00 0. "HXTFIF,HXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CLK_CDUPB,Clock Frequency Range Detector Upper Boundary Register"
|
|
hexmask.long.word 0x00 0.--10. 1. "UPERBD,HXT Clock Frequency Range Detector Upper Boundary Value\nThe bits define the maximum value of frequency range detector window.\nWhen HXT frequency higher than this maximum frequency value the HXT Clock Frequency Range Detector Interrupt Flag will.."
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CLK_CDLOWB,Clock Frequency Range Detector Lower Boundary Register"
|
|
hexmask.long.word 0x00 0.--10. 1. "LOWERBD,HXT Clock Frequency Range Detector Lower Boundary Value\nThe bits define the minimum value of frequency range detector window.\nWhen HXT frequency lower than this minimum frequency value the HXT Clock Frequency Range Detector Interrupt Flag will.."
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CLK_PMUCTL,Power Manager Control Register"
|
|
bitfld.long 0x00 0.--2. "PDMSEL,Power-down Mode Selection (Write Protect)\nThis is a protected bit" "0: Power-down mode is selected,1: Reserved,2: Reserved,3: Reserved,4: Reserved,5: Reserved,6: Reserved,7: Reserved"
|
|
tree.end
|
|
tree "CRC (CRC Register Map)"
|
|
base ad:0x40031000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRC_CTL,CRC Control Register"
|
|
bitfld.long 0x00 30.--31. "CRCMODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode" "0: CRC-CCITT Polynomial mode,1: CRC-8 Polynomial mode,2: CRC-16 Polynomial mode,3: CRC-32 Polynomial mode"
|
|
bitfld.long 0x00 28.--29. "DATLEN,CPU Write Data Length\nThis field indicates the write data length.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode the valid data in CRC_DAT.." "0: Data length is 8-bit mode,1: Data length is 16-bit mode.\nData length is..,?..."
|
|
newline
|
|
bitfld.long 0x00 27. "CHKSFMT,Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register" "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled"
|
|
bitfld.long 0x00 26. "DATFMT,Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register" "0: 1's complement for CRC writes data in Disabled,1: 1's complement for CRC writes data in Enabled"
|
|
newline
|
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bitfld.long 0x00 25. "CHKSREV,Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB" "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled"
|
|
bitfld.long 0x00 24. "DATREV,Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB" "0: Bit order reversed for CRC write data in..,1: Bit order reversed for CRC write data in.."
|
|
newline
|
|
bitfld.long 0x00 1. "CHKSINIT,Checksum Initialization\nNote: This bit will be cleared automatically" "0: No effect,1: Initial checksum value by auto reload.."
|
|
bitfld.long 0x00 0. "CRCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRC_DAT,CRC Write Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,CRC Write Data Bits\nUser can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRC_SEED,CRC Seed Register"
|
|
hexmask.long 0x00 0.--31. 1. "SEED,CRC Seed Value\nThis field indicates the CRC seed value.\nNote: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1])"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CRC_CHECKSUM,CRC Checksum Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHECKSUM,CRC Checksum Results\nThis field indicates the CRC checksum result"
|
|
tree.end
|
|
tree "DAC (DAC Register Map)"
|
|
base ad:0x40047000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC0_CTL,DAC0 Control Register"
|
|
bitfld.long 0x00 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,2: Falling edge trigger,3: Rising edge trigger"
|
|
bitfld.long 0x00 5.--7. "TRGSEL,Trigger Source Selection" "0: Software trigger,1: External pin DAC0_ST trigger,2: Timer 0 trigger,3: Timer 1 trigger,4: Timer 2 trigger,5: Timer 3 trigger,6: EPWM0 trigger,7: EPWM1 trigger"
|
|
newline
|
|
bitfld.long 0x00 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled"
|
|
bitfld.long 0x00 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA under-run interrupt Disabled,1: DMA under-run interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled"
|
|
bitfld.long 0x00 1. "DACIEN,DAC Interrupt Enable Bit" "0: DAC interrupt Disabled,1: DAC interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DAC0_SWTRG,DAC0 Software Trigger Control Register"
|
|
bitfld.long 0x00 0. "SWTRG,Software Trigger\nNote: User writes this bit to generate one shot pulse and this bit is cleared to 0 by hardware automatically reading this bit will always get 0" "0: Software trigger Disabled,1: Software trigger Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DAC0_DAT,DAC0 Data Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DACDAT,DAC 8-bit Holding Data\nThese bits are written by user software which specifies 8-bit conversion data for DAC output"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "DAC0_DATOUT,DAC0 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATOUT,DAC 8-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC_DAT register and user cannot write it directly"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DAC0_STATUS,DAC0 Status Register"
|
|
rbitfld.long 0x00 8. "BUSY,DAC Busy Flag (Read Only)" "0: DAC is ready for next conversion,1: DAC is busy in conversion"
|
|
bitfld.long 0x00 1. "DMAUDR,DMA Under-run Interrupt Flag\nNote: User writes 1 to clear this bit" "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred"
|
|
newline
|
|
bitfld.long 0x00 0. "FINISH,DAC Conversion Complete Finish Flag\nNote: This bit is set to 1 when conversion time counter counts to SETTLET" "0: DAC is in conversion state,1: DAC conversion finish"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DAC0_TCTL,DAC0 Timing Control Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "SETTLET,DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example DAC controller clock speed is 80 MHz and DAC conversion settling time is 1.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DAC0_VREF,DAC0 Reference Voltage Control Register"
|
|
bitfld.long 0x00 5. "OUTFLOAT,DAC Output Floating Selection" "0: DAC_OUT output DAC_ROUT,1: DAC_OUT output Hi-z"
|
|
bitfld.long 0x00 4. "SELVREF,DAC Reference Voltage Selection" "0: DAC reference voltage is from AVDD,1: DAC reference voltage is from VREFP"
|
|
tree.end
|
|
tree "DFMC (DFMC Register Map)"
|
|
base ad:0x4000F000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DFMC_ISPCTL,ISP Control Register"
|
|
bitfld.long 0x00 24. "ISPIFEN,ISP Interrupt Enable bit (Write Protect)\nNote: This bit is write protected" "0: ISP Interrupt Disabled,1: ISP Interrupt Enabled"
|
|
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\nData Flash writes to itself if DATAEN is set to 0.\nErase or Program command.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DATAEN,Data Flash Update Enable Bit (Write Protect)\nNote: This bit is write protected" "0: Data Flash cannot be updated,1: Data Flash can be updated"
|
|
bitfld.long 0x00 0. "ISPEN,ISP Enable Bit (Write Protect)\nISP function enable bit" "0: ISP function Disabled,1: ISP function Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DFMC_ISPADDR,ISP Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPADDR,ISP Address\nThe M471 is equipped with embedded Data Flash"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DFMC_ISPDAT,ISP Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DFMC_ISPCMD,ISP Command Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CMD,ISP Command\nISP command table is shown below:\nThe other commands are invalid"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DFMC_ISPTRG,ISP Trigger Control Register"
|
|
bitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is write protected" "0: ISP operation is finished,1: ISP is progressed"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DFMC_ISPSTS,ISP Status Register"
|
|
bitfld.long 0x00 24. "ISPIF,ISP Interrupt Flag\nNote: Write 1 to clear this bit" "0: ISP command not finish or ISP fail flag is 0,1: ISP command finish or ISP fail is 1"
|
|
bitfld.long 0x00 7. "ALLONE,Data Flash All-one Verification Flag \nThis bit is set by hardware if all of Flash bits are 1 and clear if Flash bits are not all 1 after 'Run Data Flash All-One Verification' complete this bit also can be clear by writing 1" "0: Data Flash bits are not all 1 after 'Run Data..,1: All of Data Flash bits are 1 after 'Run Data.."
|
|
newline
|
|
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (DFMC_ISPCTL[6]) it needs to be cleared by writing 1 to DFMC_ISPCTL[6] or DFMC_ISPSTS[6]" "0,1"
|
|
rbitfld.long 0x00 0. "ISPBUSY,ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(DFMC_ISPTRG[0])" "0: ISP operation is finished,1: ISP is progressed"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DFMC_CYCCTL,Data Flash Access Cycle Control Register"
|
|
bitfld.long 0x00 0.--3. "CYCLE,Data Flash Access Cycle Control (Write Protect)\nThis register is updated by software.\nThe optimized HCLK working frequency range is 192 MHz\nNote: This bit is write protected" "0: CPU access with zero wait cycle Flash access..,1: CPU access with one wait cycle if cache miss..,2: CPU access with two wait cycles if cache miss..,3: CPU access with three wait cycles if cache..,4: CPU access with four wait cycles if cache..,5: CPU access with five wait cycles if cache..,6: CPU access with six wait cycles if cache miss..,7: CPU access with seven wait cycles if cache..,8: CPU access with eight wait cycles if cache..,?..."
|
|
tree.end
|
|
tree "EADC (EADC Register Map)"
|
|
base ad:0x40043000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "EADC_DAT0,EADC Data Register 0 for Sample Module 0"
|
|
bitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
bitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EADC_DAT1,EADC Data Register 1 for Sample Module 1"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EADC_DAT2,EADC Data Register 2 for Sample Module 2"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EADC_DAT3,EADC Data Register 3 for Sample Module 3"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "EADC_DAT4,EADC Data Register 4 for Sample Module 4"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EADC_DAT5,EADC Data Register 5 for Sample Module 5"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "EADC_DAT6,EADC Data Register 6 for Sample Module 6"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EADC_DAT7,EADC Data Register 7 for Sample Module 7"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADC_DAT8,EADC Data Register 8 for Sample Module 8"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "EADC_DAT9,EADC Data Register 9 for Sample Module 9"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "EADC_DAT10,EADC Data Register 10 for Sample Module 10"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "EADC_DAT11,EADC Data Register 11 for Sample Module 11"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "EADC_DAT12,EADC Data Register 12 for Sample Module 12"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "EADC_DAT13,EADC Data Register 13 for Sample Module 13"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "EADC_DAT14,EADC Data Register 14 for Sample Module 14"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "EADC_DAT15,EADC Data Register 15 for Sample Module 15"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "EADC_DAT16,EADC Data Register 16 for Sample Module 16"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "EADC_DAT17,EADC Data Register 17 for Sample Module 17"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "EADC_DAT18,EADC Data Register 18 for Sample Module 18"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode.."
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "EADC_CURDAT,EADC PDMA Current Transfer Data Register"
|
|
hexmask.long 0x00 0.--26. 1. "CURDAT,EADC PDMA Current Transfer Data (Read Only)"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "EADC_CTL,EADC Control Register"
|
|
bitfld.long 0x00 8. "DIFFEN,Differential Analog Input Mode Enable Bit\nNote: In the differential mode the input channel pair must be configured to EADC_CH15 EADC_CH14" "0: Single-end analog input mode,1: Differential analog input mode"
|
|
bitfld.long 0x00 5. "ADCIEN3,Specific Sample Module EADC ADINT3 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module EADC conversion" "0: Specific sample module EADC ADINT3 interrupt..,1: Specific sample module EADC ADINT3 interrupt.."
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bitfld.long 0x00 4. "ADCIEN2,Specific Sample Module EADC ADINT2 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module EADC conversion" "0: Specific sample module EADC ADINT2 interrupt..,1: Specific sample module EADC ADINT2 interrupt.."
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bitfld.long 0x00 3. "ADCIEN1,Specific Sample Module EADC ADINT1 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module EADC conversion" "0: Specific sample module EADC ADINT1 interrupt..,1: Specific sample module EADC ADINT1 interrupt.."
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bitfld.long 0x00 2. "ADCIEN0,Specific Sample Module EADC ADINT0 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module EADC conversion" "0: Specific sample module EADC ADINT0 interrupt..,1: Specific sample module EADC ADINT0 interrupt.."
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bitfld.long 0x00 1. "ADCRST,EADC Converter Control Circuits Reset\nNote: EADCRST bit remains 1 during EADC reset when EADC reset end the EADCRST bit is automatically cleared to 0" "0: No effect,1: Cause EADC control circuits reset to initial.."
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bitfld.long 0x00 0. "ADCEN,EADC Converter Enable Bit\nNote: Before starting EADC conversion function this bit should be set to 1" "0: EADC Disabled,1: EADC Enabled"
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wgroup.long 0x54++0x03
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line.long 0x00 "EADC_SWTRG,EADC Sample Module Software Start Register"
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hexmask.long 0x00 0.--26. 1. "SWTRG,EADC Sample Module 0~26 Software Force to Start EADC Conversion\nNote: After writing this register to start EADC conversion the EADC_PENDSTS register will show which sample module will conversion"
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group.long 0x58++0x03
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line.long 0x00 "EADC_PENDSTS,EADC Start of Conversion Pending Flag Register"
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hexmask.long 0x00 0.--26. 1. "STPF,EADC Sample Module 0~26 Start of Conversion Pending Flag\nRead Operation"
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group.long 0x5C++0x03
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line.long 0x00 "EADC_OVSTS,EADC Sample Module Start of Conversion Overrun Flag Register"
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hexmask.long 0x00 0.--26. 1. "SPOVF,EADC SAMPLE0~26 Overrun Flag\nNote: This bit is cleared by writing 1 to it"
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group.long 0x60++0x03
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line.long 0x00 "EADC_CTL1,EADC Control1 Register"
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hexmask.long.byte 0x00 24.--31. 1. "OSR,Repeat Conversion Times Select\nNote: The other steps of selection not listed above follow the same rule"
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bitfld.long 0x00 16. "DECSET,High Speed Oversampling Mode Enable Bit" "0: High speed oversampling mode Disabled,1: High speed oversampling mode Enabled"
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bitfld.long 0x00 13.--15. "ULPDIV,Ultra Low Power Mode Prescalar selection" "0: ADC_CLK divided by 1,1: ADC_CLK divided by 2,2: ADC_CLK divided by 4,3: ADC_CLK divided by 8,4: ADC_CLK divided by 16,?..."
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bitfld.long 0x00 12. "ULPEN,Ultra Low Power Mode Enable Bit" "0: Ultra low power mode Disabled,1: Ultra low power mode Enabled"
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bitfld.long 0x00 8. "FDETCHEN,Floating Detect Channel Enable Bit\nNote: if FDETCHEN is enabled internal floating detect channel is always turn on" "0: Floating Detect Channel Disabled,1: Floating Detect Channel Enabled"
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bitfld.long 0x00 1. "DISCHEN,Discharge Enable\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enabled" "0: Channel discharge Disabled,1: Channel discharge Enabled"
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bitfld.long 0x00 0. "PRECHEN,Precharge Enable\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enabled" "0: Channel precharge Disabled,1: Channel precharge Enabled"
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group.long 0x80++0x03
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line.long 0x00 "EADC_SCTL0,EADC Sample Module 0 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC convertes at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and user can extend EADC sampling time after trigger source is coming to get.."
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bitfld.long 0x00 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x84++0x03
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line.long 0x00 "EADC_SCTL1,EADC Sample Module 1 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC convertes at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and user can extend EADC sampling time after trigger source is coming to get.."
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bitfld.long 0x00 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x88++0x03
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line.long 0x00 "EADC_SCTL2,EADC Sample Module 2 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC convertes at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and user can extend EADC sampling time after trigger source is coming to get.."
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bitfld.long 0x00 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x8C++0x03
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line.long 0x00 "EADC_SCTL3,EADC Sample Module 3 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC convertes at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and user can extend EADC sampling time after trigger source is coming to get.."
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bitfld.long 0x00 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x90++0x03
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line.long 0x00 "EADC_SCTL4,EADC Sample Module 4 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x94++0x03
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line.long 0x00 "EADC_SCTL5,EADC Sample Module 5 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x98++0x03
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line.long 0x00 "EADC_SCTL6,EADC Sample Module 6 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x9C++0x03
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line.long 0x00 "EADC_SCTL7,EADC Sample Module 7 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xA0++0x03
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line.long 0x00 "EADC_SCTL8,EADC Sample Module 8 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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newline
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xA4++0x03
|
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line.long 0x00 "EADC_SCTL9,EADC Sample Module 9 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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newline
|
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xA8++0x03
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line.long 0x00 "EADC_SCTL10,EADC Sample Module 10 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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newline
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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newline
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xAC++0x03
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line.long 0x00 "EADC_SCTL11,EADC Sample Module 11 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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newline
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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newline
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xB0++0x03
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line.long 0x00 "EADC_SCTL12,EADC Sample Module 12 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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newline
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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newline
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xB4++0x03
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line.long 0x00 "EADC_SCTL13,EADC Sample Module 13 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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newline
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xB8++0x03
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line.long 0x00 "EADC_SCTL14,EADC Sample Module 14 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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newline
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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newline
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xBC++0x03
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line.long 0x00 "EADC_SCTL15,EADC Sample Module 15 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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newline
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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newline
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xC0++0x03
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line.long 0x00 "EADC_SCTL16,EADC Sample Module 16 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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newline
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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newline
|
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xC4++0x03
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line.long 0x00 "EADC_SCTL17,EADC Sample Module 17 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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newline
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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newline
|
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xC8++0x03
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line.long 0x00 "EADC_SCTL18,EADC Sample Module 18 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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newline
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
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bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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newline
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xD0++0x03
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line.long 0x00 "EADC_INTSRC0,EADC Interrupt 0 Source Enable Control Register"
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bitfld.long 0x00 26. "SPLIE26,Sample Module 26 Interrupt Enable Bit" "0: Sample Module 26 interrupt Disabled,1: Sample Module 26 interrupt Enabled"
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bitfld.long 0x00 25. "SPLIE25,Sample Module 25 Interrupt Enable Bit" "0: Sample Module 25 interrupt Disabled,1: Sample Module 25 interrupt Enabled"
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newline
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bitfld.long 0x00 24. "SPLIE24,Sample Module 24 Interrupt Enable Bit" "0: Sample Module 24 interrupt Disabled,1: Sample Module 24 interrupt Enabled"
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bitfld.long 0x00 23. "SPLIE23,Sample Module 23 Interrupt Enable Bit" "0: Sample Module 23 interrupt Disabled,1: Sample Module 23 interrupt Enabled"
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bitfld.long 0x00 22. "SPLIE22,Sample Module 22 Interrupt Enable Bit" "0: Sample Module 22 interrupt Disabled,1: Sample Module 22 interrupt Enabled"
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bitfld.long 0x00 21. "SPLIE21,Sample Module 21 Interrupt Enable Bit" "0: Sample Module 21 interrupt Disabled,1: Sample Module 21 interrupt Enabled"
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bitfld.long 0x00 20. "SPLIE20,Sample Module 20 Interrupt Enable Bit" "0: Sample Module 20 interrupt Disabled,1: Sample Module 20 interrupt Enabled"
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bitfld.long 0x00 19. "SPLIE19,Sample Module 19 Interrupt Enable Bit" "0: Sample Module 19 interrupt Disabled,1: Sample Module 19 interrupt Enabled"
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bitfld.long 0x00 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x00 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x00 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x00 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x00 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
|
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bitfld.long 0x00 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x00 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x00 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x00 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x00 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x00 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x00 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x00 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x00 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x00 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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newline
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bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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group.long 0xD4++0x03
|
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line.long 0x00 "EADC_INTSRC1,EADC Interrupt 1 Source Enable Control Register"
|
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bitfld.long 0x00 26. "SPLIE26,Sample Module 26 Interrupt Enable Bit" "0: Sample Module 26 interrupt Disabled,1: Sample Module 26 interrupt Enabled"
|
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bitfld.long 0x00 25. "SPLIE25,Sample Module 25 Interrupt Enable Bit" "0: Sample Module 25 interrupt Disabled,1: Sample Module 25 interrupt Enabled"
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bitfld.long 0x00 24. "SPLIE24,Sample Module 24 Interrupt Enable Bit" "0: Sample Module 24 interrupt Disabled,1: Sample Module 24 interrupt Enabled"
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bitfld.long 0x00 23. "SPLIE23,Sample Module 23 Interrupt Enable Bit" "0: Sample Module 23 interrupt Disabled,1: Sample Module 23 interrupt Enabled"
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newline
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bitfld.long 0x00 22. "SPLIE22,Sample Module 22 Interrupt Enable Bit" "0: Sample Module 22 interrupt Disabled,1: Sample Module 22 interrupt Enabled"
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bitfld.long 0x00 21. "SPLIE21,Sample Module 21 Interrupt Enable Bit" "0: Sample Module 21 interrupt Disabled,1: Sample Module 21 interrupt Enabled"
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newline
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bitfld.long 0x00 20. "SPLIE20,Sample Module 20 Interrupt Enable Bit" "0: Sample Module 20 interrupt Disabled,1: Sample Module 20 interrupt Enabled"
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bitfld.long 0x00 19. "SPLIE19,Sample Module 19 Interrupt Enable Bit" "0: Sample Module 19 interrupt Disabled,1: Sample Module 19 interrupt Enabled"
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newline
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bitfld.long 0x00 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x00 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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newline
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bitfld.long 0x00 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x00 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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newline
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bitfld.long 0x00 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x00 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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newline
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bitfld.long 0x00 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x00 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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newline
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bitfld.long 0x00 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x00 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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newline
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bitfld.long 0x00 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x00 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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newline
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bitfld.long 0x00 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x00 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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newline
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bitfld.long 0x00 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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newline
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bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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newline
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bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "EADC_INTSRC2,EADC Interrupt 2 Source Enable Control Register"
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bitfld.long 0x00 26. "SPLIE26,Sample Module 26 Interrupt Enable Bit" "0: Sample Module 26 interrupt Disabled,1: Sample Module 26 interrupt Enabled"
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bitfld.long 0x00 25. "SPLIE25,Sample Module 25 Interrupt Enable Bit" "0: Sample Module 25 interrupt Disabled,1: Sample Module 25 interrupt Enabled"
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newline
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bitfld.long 0x00 24. "SPLIE24,Sample Module 24 Interrupt Enable Bit" "0: Sample Module 24 interrupt Disabled,1: Sample Module 24 interrupt Enabled"
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bitfld.long 0x00 23. "SPLIE23,Sample Module 23 Interrupt Enable Bit" "0: Sample Module 23 interrupt Disabled,1: Sample Module 23 interrupt Enabled"
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newline
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bitfld.long 0x00 22. "SPLIE22,Sample Module 22 Interrupt Enable Bit" "0: Sample Module 22 interrupt Disabled,1: Sample Module 22 interrupt Enabled"
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bitfld.long 0x00 21. "SPLIE21,Sample Module 21 Interrupt Enable Bit" "0: Sample Module 21 interrupt Disabled,1: Sample Module 21 interrupt Enabled"
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newline
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bitfld.long 0x00 20. "SPLIE20,Sample Module 20 Interrupt Enable Bit" "0: Sample Module 20 interrupt Disabled,1: Sample Module 20 interrupt Enabled"
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bitfld.long 0x00 19. "SPLIE19,Sample Module 19 Interrupt Enable Bit" "0: Sample Module 19 interrupt Disabled,1: Sample Module 19 interrupt Enabled"
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newline
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bitfld.long 0x00 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x00 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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newline
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bitfld.long 0x00 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x00 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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newline
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bitfld.long 0x00 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x00 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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newline
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bitfld.long 0x00 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x00 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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newline
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bitfld.long 0x00 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x00 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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newline
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bitfld.long 0x00 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x00 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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newline
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bitfld.long 0x00 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x00 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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newline
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bitfld.long 0x00 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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newline
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bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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newline
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bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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group.long 0xDC++0x03
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line.long 0x00 "EADC_INTSRC3,EADC Interrupt 3 Source Enable Control Register"
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bitfld.long 0x00 26. "SPLIE26,Sample Module 26 Interrupt Enable Bit" "0: Sample Module 26 interrupt Disabled,1: Sample Module 26 interrupt Enabled"
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bitfld.long 0x00 25. "SPLIE25,Sample Module 25 Interrupt Enable Bit" "0: Sample Module 25 interrupt Disabled,1: Sample Module 25 interrupt Enabled"
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newline
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bitfld.long 0x00 24. "SPLIE24,Sample Module 24 Interrupt Enable Bit" "0: Sample Module 24 interrupt Disabled,1: Sample Module 24 interrupt Enabled"
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bitfld.long 0x00 23. "SPLIE23,Sample Module 23 Interrupt Enable Bit" "0: Sample Module 23 interrupt Disabled,1: Sample Module 23 interrupt Enabled"
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newline
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bitfld.long 0x00 22. "SPLIE22,Sample Module 22 Interrupt Enable Bit" "0: Sample Module 22 interrupt Disabled,1: Sample Module 22 interrupt Enabled"
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bitfld.long 0x00 21. "SPLIE21,Sample Module 21 Interrupt Enable Bit" "0: Sample Module 21 interrupt Disabled,1: Sample Module 21 interrupt Enabled"
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newline
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bitfld.long 0x00 20. "SPLIE20,Sample Module 20 Interrupt Enable Bit" "0: Sample Module 20 interrupt Disabled,1: Sample Module 20 interrupt Enabled"
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bitfld.long 0x00 19. "SPLIE19,Sample Module 19 Interrupt Enable Bit" "0: Sample Module 19 interrupt Disabled,1: Sample Module 19 interrupt Enabled"
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newline
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bitfld.long 0x00 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x00 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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newline
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bitfld.long 0x00 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x00 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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newline
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bitfld.long 0x00 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x00 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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newline
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bitfld.long 0x00 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x00 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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newline
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bitfld.long 0x00 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x00 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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newline
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bitfld.long 0x00 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x00 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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newline
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bitfld.long 0x00 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x00 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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newline
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bitfld.long 0x00 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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newline
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bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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newline
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bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
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group.long ($2+0xE0)++0x03
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line.long 0x00 "EADC_CMP$1,EADC Result Compare Register $1"
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hexmask.long.word 0x00 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module"
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bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when.."
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newline
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bitfld.long 0x00 8.--11. "CMPMCNT,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3.--7. "CMPSPL,Compare Sample Module Selection" "0: Sample Module 0 conversion result EADC_DAT0..,1: Sample Module 1 conversion result EADC_DAT1..,2: Sample Module 2 conversion result EADC_DAT2..,3: Sample Module 3 conversion result EADC_DAT3..,4: Sample Module 4 conversion result EADC_DAT4..,5: Sample Module 5 conversion result EADC_DAT5..,6: Sample Module 6 conversion result EADC_DAT6..,7: Sample Module 7 conversion result EADC_DAT7..,8: Sample Module 8 conversion result EADC_DAT8..,9: Sample Module 9 conversion result EADC_DAT9..,10: Sample Module 10 conversion result..,11: Sample Module 11 conversion result..,12: Sample Module 12 conversion result..,13: Sample Module 13 conversion result..,14: Sample Module 14 conversion result..,15: Sample Module 15 conversion result..,16: Sample Module 16 conversion result..,17: Sample Module 17 conversion result..,18: Sample Module 18 conversion result..,19: Sample Module 19 conversion result..,20: Sample Module 20 conversion result..,21: Sample Module 21 conversion result..,22: Sample Module 22 conversion result..,23: Sample Module 23 conversion result..,24: Sample Module 24 conversion result..,25: Sample Module 25 conversion result..,26: Sample Module 26 conversion result..,?..."
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newline
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bitfld.long 0x00 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
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bitfld.long 0x00 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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newline
|
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bitfld.long 0x00 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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repeat.end
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rgroup.long 0xF0++0x03
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line.long 0x00 "EADC_STATUS0,EADC Status Register 0"
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hexmask.long.word 0x00 16.--31. 1. "OV,EADC_DAT0~15 Overrun Flag"
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hexmask.long.word 0x00 0.--15. 1. "VALID,EADC_DAT0~15 Data Valid Flag"
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rgroup.long 0xF4++0x03
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line.long 0x00 "EADC_STATUS1,EADC Status Register 1"
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hexmask.long.word 0x00 16.--26. 1. "OV,EADC_DAT16~26 Overrun Flag"
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hexmask.long.word 0x00 0.--10. 1. "VALID,EADC_DAT16~26 Data Valid Flag"
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group.long 0xF8++0x03
|
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line.long 0x00 "EADC_STATUS2,EADC Status Register 2"
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rbitfld.long 0x00 27. "AOV,for All Sample Module EADC Result Data Register Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any OVn Flag is equal to 1" "0: None of sample module data register overrun..,1: Any one of sample module data register.."
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rbitfld.long 0x00 26. "AVALID,for All Sample Module EADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)\nNote: This bit will keep 1 when any VALIDn Flag is equal to 1" "0: None of sample module data register valid..,1: Any one of sample module data register valid.."
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newline
|
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rbitfld.long 0x00 25. "STOVF,for All EADC Sample Module Start of Conversion Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any SPOVFn Flag is equal to 1" "0: None of sample module event overrun flag..,1: Any one of sample module event overrun flag.."
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rbitfld.long 0x00 24. "ADOVIF,All EADC Interrupt Flag Overrun Bits Check (Read Only)\nNote: This bit will keep 1 when any ADOVIFn Flag is equal to 1" "0: None of ADINT interrupt flag ADOVIFn n=0~3 is..,1: Any one of ADINT interrupt flag ADOVIFn n=0~3.."
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newline
|
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rbitfld.long 0x00 23. "BUSY,Busy/Idle (Read Only)\nNote: this flag will be high after 4*EADC_CLK cycles when the trigger source is coming" "0: EADC is in idle state,1: EADC is busy at conversion"
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rbitfld.long 0x00 16.--20. "CHANNEL,Current Conversion Channel (Read Only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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rbitfld.long 0x00 15. "ADCMPO3,EADC Compare 3 Output Status (Read Only)\nThe 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT less than..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x00 14. "ADCMPO2,EADC Compare 2 Output Status (Read Only)\nThe 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT less than..,1: Conversion result in EADC_DAT great than or.."
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newline
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rbitfld.long 0x00 13. "ADCMPO1,EADC Compare 1 Output Status (Read Only)\nThe 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT less than..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x00 12. "ADCMPO0,EADC Compare 0 Output Status (Read Only)\nThe 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT less than..,1: Conversion result in EADC_DAT great than or.."
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newline
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bitfld.long 0x00 11. "ADOVIF3,EADC ADINT3 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT3 interrupt flag is not overwritten to 1,1: ADINT3 interrupt flag is overwritten to 1"
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bitfld.long 0x00 10. "ADOVIF2,EADC ADINT2 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT2 interrupt flag is not overwritten to 1,1: ADINT2 interrupt flag is s overwritten to 1"
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newline
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bitfld.long 0x00 9. "ADOVIF1,EADC ADINT1 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT1 interrupt flag is not overwritten to 1,1: ADINT1 interrupt flag is overwritten to 1"
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bitfld.long 0x00 8. "ADOVIF0,EADC ADINT0 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT0 interrupt flag is not overwritten to 1,1: ADINT0 interrupt flag is overwritten to 1"
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newline
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bitfld.long 0x00 7. "ADCMPF3,EADC Compare 3 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP3.."
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bitfld.long 0x00 6. "ADCMPF2,EADC Compare 2 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP2.."
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newline
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bitfld.long 0x00 5. "ADCMPF1,EADC Compare 1 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP1.."
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bitfld.long 0x00 4. "ADCMPF0,EADC Compare 0 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP0.."
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newline
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bitfld.long 0x00 3. "ADIF3,EADC ADINT3 Interrupt Flag\n" "0: No ADINT3 interrupt pulse received,1: ADINT3 interrupt pulse has been received"
|
|
bitfld.long 0x00 2. "ADIF2,EADC ADINT2 Interrupt Flag\n" "0: No ADINT2 interrupt pulse received,1: ADINT2 interrupt pulse has been received"
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newline
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bitfld.long 0x00 1. "ADIF1,EADC ADINT1 Interrupt Flag\n" "0: No ADINT1 interrupt pulse received,1: ADINT1 interrupt pulse has been received"
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|
bitfld.long 0x00 0. "ADIF0,EADC ADINT0 Interrupt Flag\n" "0: No ADINT0 interrupt pulse received,1: ADINT0 interrupt pulse has been received"
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|
rgroup.long 0xFC++0x03
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line.long 0x00 "EADC_STATUS3,EADC Status Register 3"
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|
bitfld.long 0x00 0.--4. "CURSPL,EADC Current Sample Module (Read Only)\nThis register shows the current EADC is controlled by which sample module control logic modules.\nIf the EADC is Idle the bit filed will set to 0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rgroup.long 0x100++0x03
|
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line.long 0x00 "EADC_DDAT0,EADC Double Data Register 0 for Sample Module 0"
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bitfld.long 0x00 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is..,1: Double data in RESULT (EADC_DDATn[15:0]) is.."
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bitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1" "0: Double Data in RESULT (EADC_DDATn[15:0]..,1: Double Data in RESULT (EADC_DDATn[15:0].."
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newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]"
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group.long 0x104++0x03
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line.long 0x00 "EADC_DDAT1,EADC Double Data Register 1 for Sample Module 1"
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rbitfld.long 0x00 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is..,1: Double data in RESULT (EADC_DDATn[15:0]) is.."
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1" "0: Double Data in RESULT (EADC_DDATn[15:0]..,1: Double Data in RESULT (EADC_DDATn[15:0].."
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|
newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]"
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|
group.long 0x108++0x03
|
|
line.long 0x00 "EADC_DDAT2,EADC Double Data Register 2 for Sample Module 2"
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|
rbitfld.long 0x00 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is..,1: Double data in RESULT (EADC_DDATn[15:0]) is.."
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|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1" "0: Double Data in RESULT (EADC_DDATn[15:0]..,1: Double Data in RESULT (EADC_DDATn[15:0].."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]"
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|
group.long 0x10C++0x03
|
|
line.long 0x00 "EADC_DDAT3,EADC Double Data Register 3 for Sample Module 3"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is..,1: Double data in RESULT (EADC_DDATn[15:0]) is.."
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|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1" "0: Double Data in RESULT (EADC_DDATn[15:0]..,1: Double Data in RESULT (EADC_DDATn[15:0].."
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|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]"
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|
group.long 0x114++0x03
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|
line.long 0x00 "EADC_CALCTL,EADC Calibration Control Register"
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|
hexmask.long.byte 0x00 24.--31. 1. "CALWRDATA,Calibration Write Data"
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bitfld.long 0x00 8.--12. "CALADDR,Calibration Data Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 1. "CALIE,Calibration Interrupt Enable Bit" "0: Calibration interrupt Disabled,1: Calibration interrupt Enabled"
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bitfld.long 0x00 0. "CAL,Calibration Enable Bit\nNote: This bit is hardware auto cleared when calibration is done" "0: = Calibration Disabled,1: = Calibration Enabled"
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|
group.long 0x118++0x03
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|
line.long 0x00 "EADC_CALSR,EADC Calibration Status Register"
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bitfld.long 0x00 16. "CALIF,Calibration Finish Interrupt Flag\nIf calibration is finished this flag will be set to 1" "0,1"
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|
group.long 0x130++0x03
|
|
line.long 0x00 "EADC_PDMACTL,EADC PDMA Control Register"
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|
hexmask.long 0x00 0.--26. 1. "PDMATEN,PDMA Transfer Enable Bit\nWhen EADC conversion is completed the converted data is loaded into EADC_DATn (n: 0 ~ 26) register user can enable this bit to generate a PDMA data transfer request"
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|
group.long 0x140++0x03
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|
line.long 0x00 "EADC_M0CTL1,EADC Sample Module0 Control Register 1"
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bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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|
newline
|
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bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
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|
group.long 0x144++0x03
|
|
line.long 0x00 "EADC_M1CTL1,EADC Sample Module1 Control Register 1"
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|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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|
newline
|
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bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "EADC_M2CTL1,EADC Sample Module2 Control Register 1"
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|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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|
newline
|
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bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "EADC_M3CTL1,EADC Sample Module3 Control Register 1"
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|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
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bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "EADC_M4CTL1,EADC Sample Module4 Control Register 1"
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|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
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bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "EADC_M5CTL1,EADC Sample Module5 Control Register 1"
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|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
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bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "EADC_M6CTL1,EADC Sample Module6 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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|
newline
|
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bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "EADC_M7CTL1,EADC Sample Module7 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
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bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "EADC_M8CTL1,EADC Sample Module8 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "EADC_M9CTL1,EADC Sample Module9 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "EADC_M10CTL1,EADC Sample Module10 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "EADC_M11CTL1,EADC Sample Module11 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "EADC_M12CTL1,EADC Sample Module12 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "EADC_M13CTL1,EADC Sample Module13 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "EADC_M14CTL1,EADC Sample Module14 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "EADC_M15CTL1,EADC Sample Module15 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "EADC_M16CTL1,EADC Sample Module16 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "EADC_M17CTL1,EADC Sample Module17 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "EADC_M18CTL1,EADC Sample Module18 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "EADC_M19CTL1,EADC Sample Module19 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "EADC_M20CTL1,EADC Sample Module20 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "EADC_M21CTL1,EADC Sample Module21 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "EADC_M22CTL1,EADC Sample Module22 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "EADC_M23CTL1,EADC Sample Module23 Control Register 1"
|
|
bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
|
|
bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
|
|
rgroup.long 0x200++0x03
|
|
line.long 0x00 "EADC_DAT19,EADC Data Register 19 for Sample Module 19"
|
|
bitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
bitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "EADC_DAT20,EADC Data Register 20 for Sample Module 20"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "EADC_DAT21,EADC Data Register 21 for Sample Module 21"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "EADC_DAT22,EADC Data Register 22 for Sample Module 22"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "EADC_DAT23,EADC Data Register 23 for Sample Module 23"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "EADC_DAT24,EADC Data Register 24 for Sample Module 24"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "EADC_DAT25,EADC Data Register 25 for Sample Module 25"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "EADC_DAT26,EADC Data Register 26 for Sample Module 26"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "EADC_SCTL19,EADC Sample Module 19 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
|
|
bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
|
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newline
|
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
|
|
bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
|
|
bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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|
newline
|
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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|
bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "EADC_SCTL20,EADC Sample Module 20 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
|
|
bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
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|
newline
|
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bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
|
|
bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
|
|
bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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|
newline
|
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bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
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|
bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "EADC_SCTL21,EADC Sample Module 21 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
|
|
bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
|
|
newline
|
|
bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
|
|
bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
|
|
bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
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|
newline
|
|
bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
|
|
bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "EADC_SCTL22,EADC Sample Module 22 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
|
|
bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
|
|
newline
|
|
bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
|
|
bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
|
|
bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
|
|
newline
|
|
bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
|
|
bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "EADC_SCTL23,EADC Sample Module 23 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
|
|
bitfld.long 0x00 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects..,1: Falling edge Enabled when EADC selects.."
|
|
newline
|
|
bitfld.long 0x00 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects..,1: Rising edge Enabled when EADC selects.."
|
|
bitfld.long 0x00 16.--20. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
|
|
bitfld.long 0x00 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
|
|
newline
|
|
bitfld.long 0x00 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC.."
|
|
bitfld.long 0x00 0.--4. "CHSEL,EADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "EADC_SCTL24,EADC Sample Module 24 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "EADC_SCTL25,EADC Sample Module 25 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "EADC_SCTL26,EADC Sample Module 26 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC is converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
|
|
tree.end
|
|
tree "EPWM (EPWM Register Map)"
|
|
repeat 2. (list 0. 1.) (list ad:0x40058000 ad:0x40059000)
|
|
tree "EPWM$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EPWM_CTL0,EPWM Control Register 0"
|
|
bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nEPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects EPWM..,1: ICE debug mode acknowledgement disabled"
|
|
bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled EPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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|
newline
|
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bitfld.long 0x00 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each EPWM channel are..,1: Unify the EPWM_CH2 and EPWM_CH4 to output the.."
|
|
bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
|
|
newline
|
|
bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
|
|
bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
|
|
newline
|
|
bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
|
|
bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
|
|
newline
|
|
bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
|
|
bitfld.long 0x00 13. "WINLDEN5,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
|
|
newline
|
|
bitfld.long 0x00 12. "WINLDEN4,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
|
|
bitfld.long 0x00 11. "WINLDEN3,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
|
|
newline
|
|
bitfld.long 0x00 10. "WINLDEN2,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
|
|
bitfld.long 0x00 9. "WINLDEN1,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
|
|
newline
|
|
bitfld.long 0x00 8. "WINLDEN0,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
|
|
bitfld.long 0x00 5. "CTRLD5,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CTRLD4,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
|
|
bitfld.long 0x00 3. "CTRLD3,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CTRLD2,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
|
|
bitfld.long 0x00 1. "CTRLD1,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CTRLD0,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EPWM_CTL1,EPWM Control Register 1"
|
|
bitfld.long 0x00 26. "OUTMODE4,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
|
|
bitfld.long 0x00 25. "OUTMODE2,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
|
|
newline
|
|
bitfld.long 0x00 24. "OUTMODE0,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x00 21. "CNTMODE5,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 20. "CNTMODE4,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 19. "CNTMODE3,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 18. "CNTMODE2,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 17. "CNTMODE1,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 16. "CNTMODE0,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 10.--11. "CNTTYPE5,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 8.--9. "CNTTYPE4,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 6.--7. "CNTTYPE3,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 4.--5. "CNTTYPE2,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 2.--3. "CNTTYPE1,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 0.--1. "CNTTYPE0,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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group.long 0x08++0x03
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line.long 0x00 "EPWM_SYNC,EPWM Synchronization Register"
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bitfld.long 0x00 26. "PHSDIR4,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 25. "PHSDIR2,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 24. "PHSDIR0,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of pin SYNC is passed to the..,1: The inversed state of pin SYNC is passed to.."
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bitfld.long 0x00 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 16. "SNFLTEN,EPWM0_SYNC_IN Noise Filter Enable Bits" "0: Noise filter of input pin EPWM0_SYNC_IN..,1: Noise filter of input pin EPWM0_SYNC_IN Enabled"
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bitfld.long 0x00 12.--13. "SINSRC4,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 10.--11. "SINSRC2,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 8.--9. "SINSRC0,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 2. "PHSEN4,SYNC Phase Enable Bits" "0: EPWM counter disabled to load PHS value,1: EPWM counter enabled to load PHS value"
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bitfld.long 0x00 1. "PHSEN2,SYNC Phase Enable Bits" "0: EPWM counter disabled to load PHS value,1: EPWM counter enabled to load PHS value"
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bitfld.long 0x00 0. "PHSEN0,SYNC Phase Enable Bits" "0: EPWM counter disabled to load PHS value,1: EPWM counter enabled to load PHS value"
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group.long 0x0C++0x03
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line.long 0x00 "EPWM_SWSYNC,EPWM Software Control Synchronization Register"
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bitfld.long 0x00 2. "SWSYNC4,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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bitfld.long 0x00 1. "SWSYNC2,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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bitfld.long 0x00 0. "SWSYNC0,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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group.long 0x10++0x03
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line.long 0x00 "EPWM_CLKSRC,EPWM Clock Source Register"
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bitfld.long 0x00 16.--18. "ECLKSRC4,EPWM_CH45 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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bitfld.long 0x00 8.--10. "ECLKSRC2,EPWM_CH23 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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bitfld.long 0x00 0.--2. "ECLKSRC0,EPWM_CH01 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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group.long 0x14++0x03
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line.long 0x00 "EPWM_CLKPSC0_1,EPWM Clock Prescale Register 0/1"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x18++0x03
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line.long 0x00 "EPWM_CLKPSC2_3,EPWM Clock Prescale Register 2/3"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x1C++0x03
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line.long 0x00 "EPWM_CLKPSC4_5,EPWM Clock Prescale Register 4/5"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x20++0x03
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line.long 0x00 "EPWM_CNTEN,EPWM Counter Enable Register"
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bitfld.long 0x00 5. "CNTEN5,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 4. "CNTEN4,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 3. "CNTEN3,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 2. "CNTEN2,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 1. "CNTEN1,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 0. "CNTEN0,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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group.long 0x24++0x03
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line.long 0x00 "EPWM_CNTCLR,EPWM Clear Counter Register"
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bitfld.long 0x00 5. "CNTCLR5,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 4. "CNTCLR4,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 3. "CNTCLR3,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 2. "CNTCLR2,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 1. "CNTCLR1,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 0. "CNTCLR0,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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group.long 0x28++0x03
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line.long 0x00 "EPWM_LOAD,EPWM Load Register"
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bitfld.long 0x00 5. "LOAD5,Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 4. "LOAD4,Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 3. "LOAD3,Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 2. "LOAD2,Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 1. "LOAD1,Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 0. "LOAD0,Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
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group.long ($2+0x30)++0x03
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line.long 0x00 "EPWM_PERIOD$1,EPWM Period Register $1"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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repeat.end
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repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
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group.long ($2+0x50)++0x03
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line.long 0x00 "EPWM_CMPDAT$1,EPWM Comparator Register $1"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn complementary mode EPWM_CMPDAT0 EPWM_CMPDAT2 EPWM_CMPDAT4 denote as first compared point and EPWM_CMPDAT1.."
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repeat.end
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group.long 0x70++0x03
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line.long 0x00 "EPWM_DTCTL0_1,EPWM Dead-time Control Register 0/1"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x74++0x03
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line.long 0x00 "EPWM_DTCTL2_3,EPWM Dead-time Control Register 2/3"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x78++0x03
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line.long 0x00 "EPWM_DTCTL4_5,EPWM Dead-time Control Register 4/5"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x80++0x03
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line.long 0x00 "EPWM_PHS0_1,EPWM Counter Phase Register 0/1"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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group.long 0x84++0x03
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line.long 0x00 "EPWM_PHS2_3,EPWM Counter Phase Register 2/3"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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group.long 0x88++0x03
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line.long 0x00 "EPWM_PHS4_5,EPWM Counter Phase Register 4/5"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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rgroup.long 0x90++0x03
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line.long 0x00 "EPWM_CNT0,EPWM Counter Register 0"
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bitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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repeat 5. (strings "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 )
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group.long ($2+0x94)++0x03
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line.long 0x00 "EPWM_CNT$1,EPWM Counter Register $1"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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repeat.end
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group.long 0xB0++0x03
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line.long 0x00 "EPWM_WGCTL0,EPWM Generation Register 0"
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bitfld.long 0x00 26.--27. "PRDPCTL5,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 24.--25. "PRDPCTL4,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 22.--23. "PRDPCTL3,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 20.--21. "PRDPCTL2,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 18.--19. "PRDPCTL1,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 16.--17. "PRDPCTL0,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 10.--11. "ZPCTL5,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 8.--9. "ZPCTL4,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 6.--7. "ZPCTL3,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 4.--5. "ZPCTL2,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 2.--3. "ZPCTL1,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 0.--1. "ZPCTL0,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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group.long 0xB4++0x03
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line.long 0x00 "EPWM_WGCTL1,EPWM Generation Register 1"
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bitfld.long 0x00 26.--27. "CMPDCTL5,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 24.--25. "CMPDCTL4,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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newline
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bitfld.long 0x00 22.--23. "CMPDCTL3,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 20.--21. "CMPDCTL2,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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newline
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bitfld.long 0x00 18.--19. "CMPDCTL1,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 16.--17. "CMPDCTL0,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 10.--11. "CMPUCTL5,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 8.--9. "CMPUCTL4,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 4.--5. "CMPUCTL2,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 0.--1. "CMPUCTL0,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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group.long 0xB8++0x03
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line.long 0x00 "EPWM_MSKEN,EPWM Mask Enable Register"
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bitfld.long 0x00 5. "MSKEN5,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 4. "MSKEN4,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 2. "MSKEN2,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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group.long 0xBC++0x03
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line.long 0x00 "EPWM_MSK,EPWM Mask Data Register"
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bitfld.long 0x00 5. "MSKDAT5,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 4. "MSKDAT4,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 3. "MSKDAT3,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 2. "MSKDAT2,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 1. "MSKDAT1,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 0. "MSKDAT0,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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group.long 0xC0++0x03
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line.long 0x00 "EPWM_BNF,EPWM Brake Noise Filter Register"
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bitfld.long 0x00 24. "BK1SRC,Brake 1 Pin Source Select\nFor EPWM0 setting" "0: Brake 1 pin source come from..,1: Brake 1 pin source come from.."
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bitfld.long 0x00 16. "BK0SRC,Brake 0 Pin Source Select\nFor EPWM0 setting" "0: Brake 0 pin source come from..,1: Brake 0 pin source come from.."
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bitfld.long 0x00 15. "BRK1PINV,Brake 1 Pin Inverse" "0: brake pin event will be detected if..,1: brake pin event will be detected if.."
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bitfld.long 0x00 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,2: Filter clock = PCLK/4,3: Filter clock = PCLK/8,4: Filter clock = PCLK/16,5: Filter clock = PCLK/32,6: Filter clock = PCLK/64,7: Filter clock = PCLK/128"
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bitfld.long 0x00 8. "BRK1NFEN,EPWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 1 Disabled,1: Noise filter of EPWM Brake 1 Enabled"
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bitfld.long 0x00 7. "BRK0PINV,Brake 0 Pin Inverse" "0: brake pin event will be detected if..,1: brake pin event will be detected if.."
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bitfld.long 0x00 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK0FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 0. "BRK0NFEN,EPWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 0 Disabled,1: Noise filter of EPWM Brake 0 Enabled"
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group.long 0xC4++0x03
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line.long 0x00 "EPWM_FAILBRK,EPWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
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bitfld.long 0x00 2. "RAMBRKEN,SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by CSS detection..,1: Brake Function triggered by CSS detection.."
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group.long 0xC8++0x03
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line.long 0x00 "EPWM_BRKCTL0_1,EPWM Brake Edge Detect Control Register 0/1"
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bitfld.long 0x00 28. "EADC0LBEN,Enable EADC0 Result Monitor (EADC0RM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADC0EBEN,Enable EADC0 Result Monitor (EADC0RM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xCC++0x03
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line.long 0x00 "EPWM_BRKCTL2_3,EPWM Brake Edge Detect Control Register 2/3"
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bitfld.long 0x00 28. "EADC0LBEN,Enable EADC0 Result Monitor (EADC0RM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADC0EBEN,Enable EADC0 Result Monitor (EADC0RM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xD0++0x03
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line.long 0x00 "EPWM_BRKCTL4_5,EPWM Brake Edge Detect Control Register 4/5"
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bitfld.long 0x00 28. "EADC0LBEN,Enable EADC0 Result Monitor (EADC0RM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADC0EBEN,Enable EADC0 Result Monitor (EADC0RM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xD4++0x03
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line.long 0x00 "EPWM_POLCTL,EPWM Pin Polar Inverse Register"
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bitfld.long 0x00 5. "PINV5,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin" "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 4. "PINV4,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin" "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin" "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 2. "PINV2,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin" "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin" "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin" "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "EPWM_POEN,EPWM Output Enable Register"
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bitfld.long 0x00 5. "POEN5,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 4. "POEN4,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 3. "POEN3,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 2. "POEN2,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 1. "POEN1,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 0. "POEN0,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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wgroup.long 0xDC++0x03
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line.long 0x00 "EPWM_SWBRK,EPWM Software Brake Control Register"
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bitfld.long 0x00 10. "BRKLTRG4,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 9. "BRKLTRG2,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 8. "BRKLTRG0,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 2. "BRKETRG4,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 1. "BRKETRG2,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG0,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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group.long 0xE0++0x03
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line.long 0x00 "EPWM_INTEN0,EPWM Interrupt Enable Register 0"
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bitfld.long 0x00 29. "CMPDIEN5,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 28. "CMPDIEN4,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 26. "CMPDIEN2,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 24. "CMPDIEN0,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 21. "CMPUIEN5,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 20. "CMPUIEN4,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 18. "CMPUIEN2,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 16. "CMPUIEN0,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 13. "PIEN5,EPWM Period Point Interrupt Enable Bits\n" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 12. "PIEN4,EPWM Period Point Interrupt Enable Bits\n" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 11. "PIEN3,EPWM Period Point Interrupt Enable Bits\n" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 10. "PIEN2,EPWM Period Point Interrupt Enable Bits\n" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 9. "PIEN1,EPWM Period Point Interrupt Enable Bits\n" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 8. "PIEN0,EPWM Period Point Interrupt Enable Bits\n" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 5. "ZIEN5,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 4. "ZIEN4,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 3. "ZIEN3,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 2. "ZIEN2,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 1. "ZIEN1,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN0,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE4++0x03
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line.long 0x00 "EPWM_INTEN1,EPWM Interrupt Enable Register 1"
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bitfld.long 0x00 10. "BRKLIEN4_5,EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
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bitfld.long 0x00 9. "BRKLIEN2_3,EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x00 8. "BRKLIEN0_1,EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
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bitfld.long 0x00 2. "BRKEIEN4_5,EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5.."
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bitfld.long 0x00 1. "BRKEIEN2_3,EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3.."
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bitfld.long 0x00 0. "BRKEIEN0_1,EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1.."
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group.long 0xE8++0x03
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line.long 0x00 "EPWM_INTSTS0,EPWM Interrupt Flag Register 0"
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bitfld.long 0x00 29. "CMPDIF5,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 28. "CMPDIF4,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 27. "CMPDIF3,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 26. "CMPDIF2,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 25. "CMPDIF1,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 24. "CMPDIF0,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 21. "CMPUIF5,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 20. "CMPUIF4,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 19. "CMPUIF3,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 18. "CMPUIF2,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 17. "CMPUIF1,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 16. "CMPUIF0,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 13. "PIF5,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 12. "PIF4,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 11. "PIF3,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 10. "PIF2,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 9. "PIF1,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 8. "PIF0,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 5. "ZIF5,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 4. "ZIF4,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 3. "ZIF3,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 2. "ZIF2,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 1. "ZIF1,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 0. "ZIF0,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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group.long 0xEC++0x03
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line.long 0x00 "EPWM_INTSTS1,EPWM Interrupt Flag Register 1"
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rbitfld.long 0x00 29. "BRKLSTS5,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 28. "BRKLSTS4,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 27. "BRKLSTS3,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 26. "BRKLSTS2,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 25. "BRKLSTS1,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 24. "BRKLSTS0,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 21. "BRKESTS5,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 20. "BRKESTS4,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 19. "BRKESTS3,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 18. "BRKESTS2,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 17. "BRKESTS1,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 16. "BRKESTS0,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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bitfld.long 0x00 13. "BRKLIF5,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 12. "BRKLIF4,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 11. "BRKLIF3,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 10. "BRKLIF2,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 9. "BRKLIF1,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 8. "BRKLIF0,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 5. "BRKEIF5,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 4. "BRKEIF4,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 3. "BRKEIF3,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 2. "BRKEIF2,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 1. "BRKEIF1,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 0. "BRKEIF0,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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group.long 0xF4++0x03
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line.long 0x00 "EPWM_DACTRGEN,EPWM Trigger DAC Enable Register"
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bitfld.long 0x00 29. "CDTRGE5,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\n" "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 28. "CDTRGE4,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\n" "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 27. "CDTRGE3,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\n" "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 26. "CDTRGE2,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\n" "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 25. "CDTRGE1,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\n" "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 24. "CDTRGE0,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\n" "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 21. "CUTRGE5,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\n" "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 20. "CUTRGE4,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\n" "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 19. "CUTRGE3,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\n" "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 18. "CUTRGE2,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\n" "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 17. "CUTRGE1,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\n" "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 16. "CUTRGE0,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\n" "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 13. "PTE5,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 12. "PTE4,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 11. "PTE3,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 10. "PTE2,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 9. "PTE1,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 8. "PTE0,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 5. "ZTE5,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 4. "ZTE4,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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newline
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bitfld.long 0x00 3. "ZTE3,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 2. "ZTE2,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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newline
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bitfld.long 0x00 1. "ZTE1,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 0. "ZTE0,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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group.long 0xF8++0x03
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line.long 0x00 "EPWM_EADCTS0,EPWM Trigger EADC Source Select Register 0"
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bitfld.long 0x00 31. "TRGEN3,EPWM_CH3 Trigger EADC Enable Bit" "0: EPWM_CH3 Trigger EADC function Disabled,1: EPWM_CH3 Trigger EADC function Enabled"
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bitfld.long 0x00 24.--27. "TRGSEL3,EPWM_CH3 Trigger EADC Source Select" "0: EPWM_CH2 zero point,1: EPWM_CH2 period point,2: EPWM_CH2 zero or period point,3: EPWM_CH2 up-count compared point,4: EPWM_CH2 down-count compared point,5: EPWM_CH3 zero point,6: EPWM_CH3 period point,7: EPWM_CH3 zero or period point,8: EPWM_CH3 up-count compared point,9: EPWM_CH3 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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newline
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bitfld.long 0x00 23. "TRGEN2,EPWM_CH2 Trigger EADC Enable Bit" "0: EPWM_CH2 Trigger EADC function Disabled,1: EPWM_CH2 Trigger EADC function Enabled"
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bitfld.long 0x00 16.--19. "TRGSEL2,EPWM_CH2 Trigger EADC Source Select" "0: EPWM_CH2 zero point,1: EPWM_CH2 period point,2: EPWM_CH2 zero or period point,3: EPWM_CH2 up-count compared point,4: EPWM_CH2 down-count compared point,5: EPWM_CH3 zero point,6: EPWM_CH3 period point,7: EPWM_CH3 zero or period point,8: EPWM_CH3 up-count compared point,9: EPWM_CH3 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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newline
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bitfld.long 0x00 15. "TRGEN1,EPWM_CH1 Trigger EADC Enable Bit" "0: EPWM_CH1 Trigger EADC function Disabled,1: EPWM_CH1 Trigger EADC function Enabled"
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bitfld.long 0x00 8.--11. "TRGSEL1,EPWM_CH1 Trigger EADC Source Select" "0: EPWM_CH0 zero point,1: EPWM_CH0 period point,2: EPWM_CH0 zero or period point,3: EPWM_CH0 up-count compared point,4: EPWM_CH0 down-count compared point,5: EPWM_CH1 zero point,6: EPWM_CH1 period point,7: EPWM_CH1 zero or period point,8: EPWM_CH1 up-count compared point,9: EPWM_CH1 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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newline
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bitfld.long 0x00 7. "TRGEN0,EPWM_CH0 Trigger EADC Enable Bit" "0: EPWM_CH0 Trigger EADC function Disabled,1: EPWM_CH0 Trigger EADC function Enabled"
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bitfld.long 0x00 0.--3. "TRGSEL0,EPWM_CH0 Trigger EADC Source Select" "0: EPWM_CH0 zero point,1: EPWM_CH0 period point,2: EPWM_CH0 zero or period point,3: EPWM_CH0 up-count compared point,4: EPWM_CH0 down-count compared point,5: EPWM_CH1 zero point,6: EPWM_CH1 period point,7: EPWM_CH1 zero or period point,8: EPWM_CH1 up-count compared point,9: EPWM_CH1 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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group.long 0xFC++0x03
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line.long 0x00 "EPWM_EADCTS1,EPWM Trigger EADC Source Select Register 1"
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bitfld.long 0x00 15. "TRGEN5,EPWM_CH5 Trigger EADC Enable Bit" "0: EPWM_CH5 Trigger EADC function Disabled,1: EPWM_CH5 Trigger EADC function Enabled"
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bitfld.long 0x00 8.--11. "TRGSEL5,EPWM_CH5 Trigger EADC Source Select" "0: EPWM_CH4 zero point,1: EPWM_CH4 period point,2: EPWM_CH4 zero or period point,3: EPWM_CH4 up-count compared point,4: EPWM_CH4 down-count compared point,5: EPWM_CH5 zero point,6: EPWM_CH5 period point,7: EPWM_CH5 zero or period point,8: EPWM_CH5 up-count compared point,9: EPWM_CH5 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 7. "TRGEN4,EPWM_CH4 Trigger EADC Enable Bit" "0: EPWM_CH4 Trigger EADC function Disabled,1: EPWM_CH4 Trigger EADC function Enabled"
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bitfld.long 0x00 0.--3. "TRGSEL4,EPWM_CH4 Trigger EADC Source Select" "0: EPWM_CH4 zero point,1: EPWM_CH4 period point,2: EPWM_CH4 zero or period point,3: EPWM_CH4 up-count compared point,4: EPWM_CH4 down-count compared point,5: EPWM_CH5 zero point,6: EPWM_CH5 period point,7: EPWM_CH5 zero or period point,8: EPWM_CH5 up-count compared point,9: EPWM_CH5 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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group.long 0x100++0x03
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line.long 0x00 "EPWM_FTCMPDAT0_1,EPWM Free Trigger Compare Register 0/1"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x104++0x03
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line.long 0x00 "EPWM_FTCMPDAT2_3,EPWM Free Trigger Compare Register 2/3"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x108++0x03
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line.long 0x00 "EPWM_FTCMPDAT4_5,EPWM Free Trigger Compare Register 4/5"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x110++0x03
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line.long 0x00 "EPWM_SSCTL,EPWM Synchronous Start Control Register"
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bitfld.long 0x00 8.--9. "SSRC,EPWM Synchronous Start Source Select Bits" "0: Synchronous start source come from EPWM0,1: Synchronous start source come from EPWM1,2: Synchronous start source come from BPWM0,3: Synchronous start source come from BPWM1"
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bitfld.long 0x00 5. "SSEN5,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 4. "SSEN4,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 3. "SSEN3,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 2. "SSEN2,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 1. "SSEN1,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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newline
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bitfld.long 0x00 0. "SSEN0,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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wgroup.long 0x114++0x03
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line.long 0x00 "EPWM_SSTRG,EPWM Synchronous Start Trigger Register"
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bitfld.long 0x00 0. "CNTSEN,EPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter.." "0,1"
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group.long 0x118++0x03
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line.long 0x00 "EPWM_LEBCTL,EPWM Leading Edge Blanking Control Register"
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bitfld.long 0x00 16.--17. "TRGTYPE,EPWM Leading Edge Blanking Trigger Type" "0: When detect leading edge blanking source..,1: When detect leading edge blanking source..,2: When detect leading edge blanking source..,3: Reserved"
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bitfld.long 0x00 10. "SRCEN4,EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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newline
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bitfld.long 0x00 9. "SRCEN2,EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 8. "SRCEN0,EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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newline
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bitfld.long 0x00 0. "LEBEN,EPWM Leading Edge Blanking Enable Bit" "0: EPWM Leading Edge Blanking Disabled,1: EPWM Leading Edge Blanking Enabled"
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group.long 0x11C++0x03
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line.long 0x00 "EPWM_LEBCNT,EPWM Leading Edge Blanking Counter Register"
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hexmask.long.word 0x00 0.--8. 1. "LEBCNT,EPWM Leading Edge Blanking Counter"
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group.long 0x120++0x03
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line.long 0x00 "EPWM_STATUS,EPWM Status Register"
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bitfld.long 0x00 24. "DACTRGF,DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No DAC start of conversion trigger event has..,1: A DAC start of conversion trigger event has.."
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bitfld.long 0x00 21. "EADCTRGF5,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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newline
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bitfld.long 0x00 20. "EADCTRGF4,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 19. "EADCTRGF3,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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newline
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bitfld.long 0x00 18. "EADCTRGF2,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 17. "EADCTRGF1,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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newline
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bitfld.long 0x00 16. "EADCTRGF0,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 10. "SYNCINF4,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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newline
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bitfld.long 0x00 9. "SYNCINF2,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x00 8. "SYNCINF0,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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newline
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bitfld.long 0x00 5. "CNTMAXF5,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 4. "CNTMAXF4,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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newline
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bitfld.long 0x00 3. "CNTMAXF3,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 2. "CNTMAXF2,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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newline
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bitfld.long 0x00 1. "CNTMAXF1,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 0. "CNTMAXF0,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
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group.long ($2+0x130)++0x03
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line.long 0x00 "EPWM_IFA$1,EPWM Interrupt Flag Accumulator Register $1"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bit\nNote: Disabling this bit will reset related EPWM_IFACNT" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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newline
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bitfld.long 0x00 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bit" "0: EPWM_CHn Stop Mode Disabled,1: EPWM_CHn Stop Mode Enabled"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.EPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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repeat.end
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group.long 0x150++0x03
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line.long 0x00 "EPWM_AINTSTS,EPWM Accumulator Interrupt Flag Register"
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bitfld.long 0x00 5. "IFAIF5,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 4. "IFAIF4,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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newline
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bitfld.long 0x00 3. "IFAIF3,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 2. "IFAIF2,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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newline
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bitfld.long 0x00 1. "IFAIF1,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "IFAIF0,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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group.long 0x154++0x03
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line.long 0x00 "EPWM_AINTEN,EPWM Accumulator Interrupt Enable Register"
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bitfld.long 0x00 5. "IFAIEN5,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 4. "IFAIEN4,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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newline
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bitfld.long 0x00 3. "IFAIEN3,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 2. "IFAIEN2,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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newline
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bitfld.long 0x00 1. "IFAIEN1,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 0. "IFAIEN0,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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group.long 0x158++0x03
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line.long 0x00 "EPWM_APDMACTL,EPWM Accumulator PDMA Control Register"
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bitfld.long 0x00 5. "APDMAEN5,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 4. "APDMAEN4,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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newline
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bitfld.long 0x00 3. "APDMAEN3,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 2. "APDMAEN2,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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newline
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bitfld.long 0x00 1. "APDMAEN1,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 0. "APDMAEN0,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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group.long 0x160++0x03
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line.long 0x00 "EPWM_FDEN,EPWM Fault Detect Enable Register"
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bitfld.long 0x00 21. "FDCKS5,EPWM Channel n Fault Detect Clock Source Select Bits" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x00 20. "FDCKS4,EPWM Channel n Fault Detect Clock Source Select Bits" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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newline
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bitfld.long 0x00 19. "FDCKS3,EPWM Channel n Fault Detect Clock Source Select Bits" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x00 18. "FDCKS2,EPWM Channel n Fault Detect Clock Source Select Bits" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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newline
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bitfld.long 0x00 17. "FDCKS1,EPWM Channel n Fault Detect Clock Source Select Bits" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x00 16. "FDCKS0,EPWM Channel n Fault Detect Clock Source Select Bits" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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newline
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bitfld.long 0x00 13. "FDODIS5,EPWM Channel n Output Fault Detect Disable Bits" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
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bitfld.long 0x00 12. "FDODIS4,EPWM Channel n Output Fault Detect Disable Bits" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
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newline
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bitfld.long 0x00 11. "FDODIS3,EPWM Channel n Output Fault Detect Disable Bits" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
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bitfld.long 0x00 10. "FDODIS2,EPWM Channel n Output Fault Detect Disable Bits" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
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newline
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bitfld.long 0x00 9. "FDODIS1,EPWM Channel n Output Fault Detect Disable Bits" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
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bitfld.long 0x00 8. "FDODIS0,EPWM Channel n Output Fault Detect Disable Bits" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
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newline
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bitfld.long 0x00 5. "FDEN5,EPWM Fault Detect Function Enable Bits" "0: Fault detect function Disabled,1: Fault detect function Enabled"
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bitfld.long 0x00 4. "FDEN4,EPWM Fault Detect Function Enable Bits" "0: Fault detect function Disabled,1: Fault detect function Enabled"
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|
newline
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bitfld.long 0x00 3. "FDEN3,EPWM Fault Detect Function Enable Bits" "0: Fault detect function Disabled,1: Fault detect function Enabled"
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bitfld.long 0x00 2. "FDEN2,EPWM Fault Detect Function Enable Bits" "0: Fault detect function Disabled,1: Fault detect function Enabled"
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|
newline
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bitfld.long 0x00 1. "FDEN1,EPWM Fault Detect Function Enable Bits" "0: Fault detect function Disabled,1: Fault detect function Enabled"
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bitfld.long 0x00 0. "FDEN0,EPWM Fault Detect Function Enable Bits" "0: Fault detect function Disabled,1: Fault detect function Enabled"
|
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repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
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group.long ($2+0x164)++0x03
|
|
line.long 0x00 "EPWM_FDCTL$1,EPWM Fault Detect Control Register $1"
|
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bitfld.long 0x00 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disabled,1: Fault detect deglitch function Enabled"
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bitfld.long 0x00 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,2: FLT_CLK/4,3: FLT_CLK/8"
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|
newline
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bitfld.long 0x00 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to" "0: \nSampling detect signal each EPWMx_CLK *,1: \nSampling detect signal each EPWMx_CLK *..,?..."
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bitfld.long 0x00 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disabled,1: Fault detect mask function Enabled"
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|
newline
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abitfld.long 0x00 0.--6. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to" "0x00=0: \nMask time is EPWMx_CLK * (2^FDCKSEL) *,0x01=1: \nMask time EPWMx_CLK * CLKPSC *.."
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repeat.end
|
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group.long 0x17C++0x03
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line.long 0x00 "EPWM_FDIEN,EPWM Fault Detect Interrupt Enable Register"
|
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bitfld.long 0x00 0. "FDIENn,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disabled,1: EPWM Channel n Fault Detect Interrupt Enabled"
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group.long 0x180++0x03
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line.long 0x00 "EPWM_FDSTS,EPWM Fault Detect Interrupt Flag Register"
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bitfld.long 0x00 0.--5. "FDIFn,EPWM Channel n Fault Detect Interrupt Flag Bit\nFault Detect Interrupt Flag will be set when EPWM output short" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x184++0x03
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line.long 0x00 "EPWM_EADCPSCCTL,EPWM Trigger EADC Prescale Control Register"
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bitfld.long 0x00 5. "PSCEN5,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale function Disabled,1: EPWM Trigger EADC Pre-scale function Enabled"
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bitfld.long 0x00 4. "PSCEN4,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale function Disabled,1: EPWM Trigger EADC Pre-scale function Enabled"
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newline
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bitfld.long 0x00 3. "PSCEN3,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale function Disabled,1: EPWM Trigger EADC Pre-scale function Enabled"
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bitfld.long 0x00 2. "PSCEN2,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale function Disabled,1: EPWM Trigger EADC Pre-scale function Enabled"
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newline
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bitfld.long 0x00 1. "PSCEN1,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale function Disabled,1: EPWM Trigger EADC Pre-scale function Enabled"
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bitfld.long 0x00 0. "PSCEN0,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale function Disabled,1: EPWM Trigger EADC Pre-scale function Enabled"
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group.long 0x188++0x03
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line.long 0x00 "EPWM_EADCPSC0,EPWM Trigger EADC Prescale Register 0"
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bitfld.long 0x00 24.--27. "EADCPSC3,EPWM Channel 3 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC3+1) times of EPWM_CH3 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "EADCPSC2,EPWM Channel 2 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC2+1) times of EPWM_CH2 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 8.--11. "EADCPSC1,EPWM Channel 1 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC1+1) times of EPWM_CH1 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EADCPSC0,EPWM Channel 0 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC0+1) times of EPWM_CH0 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x18C++0x03
|
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line.long 0x00 "EPWM_EADCPSC1,EPWM Trigger EADC Prescale Register 1"
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bitfld.long 0x00 8.--11. "EADCPSC5,EPWM Channel 5 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC5+1) times of EPWM_CH5 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EADCPSC4,EPWM Channel 4 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC4+1) times of EPWM_CH4 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x190++0x03
|
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line.long 0x00 "EPWM_EADCPSCNT0,EPWM Trigger EADC Prescale Counter Register 0"
|
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bitfld.long 0x00 24.--27. "PSCNT3,EPWM Trigger EADC Prescale Counter 3\nUser can monitor PSCNT3 to know the current value in 4-bit trigger EADC prescale counter.\n" "?,1: user can write only when PSCEN3 is 0.\n,2: Write data limitation,?..."
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bitfld.long 0x00 16.--19. "PSCNT2,EPWM Trigger EADC Prescale Counter 2\nUser can monitor PSCNT2 to know the current value in 4-bit trigger EADC prescale counter.\n" "?,1: user can write only when PSCEN2 is 0.\n,2: Write data limitation,?..."
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newline
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bitfld.long 0x00 8.--11. "PSCNT1,EPWM Trigger EADC Prescale Counter 1\nUser can monitor PSCNT1 to know the current value in 4-bit trigger EADC prescale counter.\n" "?,1: user can write only when PSCEN1 is 0.\n,2: Write data limitation,?..."
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bitfld.long 0x00 0.--3. "PSCNT0,EPWM Trigger EADC Prescale Counter 0\nUser can monitor PSCNT0 to know the current value in 4-bit trigger EADC prescale counter.\n" "?,1: user can write only when PSCEN0 is 0.\n,2: Write data limitation,?..."
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group.long 0x194++0x03
|
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line.long 0x00 "EPWM_EADCPSCNT1,EPWM Trigger EADC Prescale Counter Register 1"
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bitfld.long 0x00 8.--11. "PSCNT5,EPWM Trigger EADC Prescale Counter 5\nUser can monitor PSCNT5 to know the current value in 4-bit trigger EADC prescale counter.\n" "?,1: user can write only when PSCEN5 is 0.\n,2: Write data limitation,?..."
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bitfld.long 0x00 0.--3. "PSCNT4,EPWM Trigger EADC Prescale Counter 4\nUser can monitor PSCNT4 to know the current value in 4-bit trigger EADC prescale counter.\n" "?,1: user can write only when PSCEN4 is 0.\n,2: Write data limitation,?..."
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group.long 0x200++0x03
|
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line.long 0x00 "EPWM_CAPINEN,EPWM Capture Input Enable Register"
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bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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newline
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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newline
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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group.long 0x204++0x03
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line.long 0x00 "EPWM_CAPCTL,EPWM Capture Control Register"
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bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
|
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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newline
|
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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newline
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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newline
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
|
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bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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newline
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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newline
|
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
|
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bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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rgroup.long 0x208++0x03
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line.long 0x00 "EPWM_CAPSTS,EPWM Capture Status Register"
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bitfld.long 0x00 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x00 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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newline
|
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bitfld.long 0x00 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x00 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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newline
|
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bitfld.long 0x00 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x00 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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newline
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bitfld.long 0x00 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x00 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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newline
|
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bitfld.long 0x00 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x00 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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newline
|
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bitfld.long 0x00 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x00 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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rgroup.long 0x20C++0x03
|
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line.long 0x00 "EPWM_RCAPDAT0,EPWM Rising Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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rgroup.long 0x210++0x03
|
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line.long 0x00 "EPWM_FCAPDAT0,EPWM Falling Capture Data Register 0"
|
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
|
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group.long 0x214++0x03
|
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line.long 0x00 "EPWM_RCAPDAT1,EPWM Rising Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
|
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group.long 0x218++0x03
|
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line.long 0x00 "EPWM_FCAPDAT1,EPWM Falling Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
|
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group.long 0x21C++0x03
|
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line.long 0x00 "EPWM_RCAPDAT2,EPWM Rising Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x220++0x03
|
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line.long 0x00 "EPWM_FCAPDAT2,EPWM Falling Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
|
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group.long 0x224++0x03
|
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line.long 0x00 "EPWM_RCAPDAT3,EPWM Rising Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x228++0x03
|
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line.long 0x00 "EPWM_FCAPDAT3,EPWM Falling Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
|
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group.long 0x22C++0x03
|
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line.long 0x00 "EPWM_RCAPDAT4,EPWM Rising Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
|
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group.long 0x230++0x03
|
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line.long 0x00 "EPWM_FCAPDAT4,EPWM Falling Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
|
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group.long 0x234++0x03
|
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line.long 0x00 "EPWM_RCAPDAT5,EPWM Rising Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
|
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group.long 0x238++0x03
|
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line.long 0x00 "EPWM_FCAPDAT5,EPWM Falling Capture Data Register 5"
|
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "EPWM_PDMACTL,EPWM PDMA Control Register"
|
|
bitfld.long 0x00 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5"
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|
bitfld.long 0x00 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order" "0: EPWM_FCAPDAT4/5 is the first captured data to..,1: EPWM_RCAPDAT4/5 is the first captured data to.."
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newline
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bitfld.long 0x00 17.--18. "CAPMOD4_5,Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT4/5,2: EPWM_FCAPDAT4/5,3: Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5"
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bitfld.long 0x00 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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newline
|
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bitfld.long 0x00 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3"
|
|
bitfld.long 0x00 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order" "0: EPWM_FCAPDAT2/3 is the first captured data to..,1: EPWM_RCAPDAT2/3 is the first captured data to.."
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newline
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bitfld.long 0x00 9.--10. "CAPMOD2_3,Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT2/3,2: EPWM_FCAPDAT2/3,3: Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3"
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|
bitfld.long 0x00 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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newline
|
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bitfld.long 0x00 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1"
|
|
bitfld.long 0x00 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order" "0: EPWM_FCAPDAT0/1 is the first captured data to..,1: EPWM_RCAPDAT0/1 is the first captured data to.."
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newline
|
|
bitfld.long 0x00 1.--2. "CAPMOD0_1,Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT0/1,2: EPWM_FCAPDAT0/1,3: Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1"
|
|
bitfld.long 0x00 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "EPWM_PDMACAP0_1,EPWM Capture Channel 01 PDMA Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "EPWM_PDMACAP2_3,EPWM Capture Channel 23 PDMA Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "EPWM_PDMACAP4_5,EPWM Capture Channel 45 PDMA Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "EPWM_CAPIEN,EPWM Capture Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "CAPFIEN5,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
bitfld.long 0x00 12. "CAPFIEN4,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "CAPFIEN3,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
bitfld.long 0x00 10. "CAPFIEN2,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "CAPFIEN1,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
bitfld.long 0x00 8. "CAPFIEN0,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "CAPRIEN5,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
bitfld.long 0x00 4. "CAPRIEN4,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "CAPRIEN3,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
bitfld.long 0x00 2. "CAPRIEN2,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "CAPRIEN1,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
bitfld.long 0x00 0. "CAPRIEN0,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "EPWM_CAPIF,EPWM Capture Interrupt Flag Register"
|
|
bitfld.long 0x00 13. "CFLIF5,EPWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
|
|
bitfld.long 0x00 12. "CFLIF4,EPWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
|
|
newline
|
|
bitfld.long 0x00 11. "CFLIF3,EPWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
|
|
bitfld.long 0x00 10. "CFLIF2,EPWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
|
|
newline
|
|
bitfld.long 0x00 9. "CFLIF1,EPWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
|
|
bitfld.long 0x00 8. "CFLIF0,EPWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
|
|
newline
|
|
bitfld.long 0x00 5. "CRLIF5,EPWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
|
|
bitfld.long 0x00 4. "CRLIF4,EPWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
|
|
newline
|
|
bitfld.long 0x00 3. "CRLIF3,EPWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
|
|
bitfld.long 0x00 2. "CRLIF2,EPWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
|
|
newline
|
|
bitfld.long 0x00 1. "CRLIF1,EPWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
|
|
bitfld.long 0x00 0. "CRLIF0,EPWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
|
|
repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x258)++0x03
|
|
line.long 0x00 "EPWM_CAPNF$1,EPWM Capture Input Noise Filter Register $1"
|
|
bitfld.long 0x00 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,2: Filter clock = PCLK/4,3: Filter clock = PCLK/8,4: Filter clock = PCLK/16,5: Filter clock = PCLK/32,6: Filter clock = PCLK/64,7: Filter clock = PCLK/128"
|
|
newline
|
|
bitfld.long 0x00 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
|
|
repeat.end
|
|
repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x270)++0x03
|
|
line.long 0x00 "EPWM_EXTETCTL$1,EPWM External Event Trigger Control Register $1"
|
|
bitfld.long 0x00 8.--11. "EXTTRGS,External Trigger Selection" "0: INT0,1: INT1,2: INT2,3: INT3,4: INT4,5: INT5,6: INT6,7: INT7,?..."
|
|
bitfld.long 0x00 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,2: Counter reset and start,3: Reseved"
|
|
newline
|
|
bitfld.long 0x00 0. "EXETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
|
|
repeat.end
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "EPWM_SWEOFCTL,EPWM Software Event Output Force Control Register"
|
|
bitfld.long 0x00 10.--11. "OUTACTS5,Output Action Selection" "0: Do nothing,1: EPWM output Low,2: EPWM output High,3: EPWM output Toggle"
|
|
bitfld.long 0x00 8.--9. "OUTACTS4,Output Action Selection" "0: Do nothing,1: EPWM output Low,2: EPWM output High,3: EPWM output Toggle"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "OUTACTS3,Output Action Selection" "0: Do nothing,1: EPWM output Low,2: EPWM output High,3: EPWM output Toggle"
|
|
bitfld.long 0x00 4.--5. "OUTACTS2,Output Action Selection" "0: Do nothing,1: EPWM output Low,2: EPWM output High,3: EPWM output Toggle"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "OUTACTS1,Output Action Selection" "0: Do nothing,1: EPWM output Low,2: EPWM output High,3: EPWM output Toggle"
|
|
bitfld.long 0x00 0.--1. "OUTACTS0,Output Action Selection" "0: Do nothing,1: EPWM output Low,2: EPWM output High,3: EPWM output Toggle"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "EPWM_SWEOFTRG,EPWM Software Event Output Force Trigger Register"
|
|
bitfld.long 0x00 5. "SWETRG5,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware" "0,1"
|
|
bitfld.long 0x00 4. "SWETRG4,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware" "0,1"
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|
newline
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bitfld.long 0x00 3. "SWETRG3,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware" "0,1"
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|
bitfld.long 0x00 2. "SWETRG2,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware" "0,1"
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|
newline
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bitfld.long 0x00 1. "SWETRG1,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware" "0,1"
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bitfld.long 0x00 0. "SWETRG0,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware" "0,1"
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|
repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x290)++0x03
|
|
line.long 0x00 "EPWM_CLKPSC$1,EPWM Clock Prescale Register $1"
|
|
hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler"
|
|
repeat.end
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "EPWM_RDTCNT0_1,EPWM Rising Dead-time Counter Register 0/1"
|
|
hexmask.long.word 0x00 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "EPWM_RDTCNT2_3,EPWM Rising Dead-time Counter Register 2/3"
|
|
hexmask.long.word 0x00 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "EPWM_RDTCNT4_5,EPWM Rising Dead-time Counter Register 4/5"
|
|
hexmask.long.word 0x00 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "EPWM_FDTCNT0_1,EPWM Falling Dead-time Counter Register 0/1"
|
|
hexmask.long.word 0x00 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "EPWM_FDTCNT2_3,EPWM Falling Dead-time Counter Register 2/3"
|
|
hexmask.long.word 0x00 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "EPWM_FDTCNT4_5,EPWM Falling Dead-time Counter Register 4/5"
|
|
hexmask.long.word 0x00 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "EPWM_DTCTL,EPWM Dead-time Control Register"
|
|
bitfld.long 0x00 16. "DTCKSELn,Dead-time Clock Select for EPWM Pair (EPWM_CH(n/2) EPWM_CH(n/2+1)) (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
|
|
bitfld.long 0x00 10. "FDTEN4,Enable Falling Dead-time Insertion for EPWM Pair (EPWM_CH(n/2) EPWM_CH(n/2+1)) (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Falling Dead-time insertion Disabled on the..,1: Falling Dead-time insertion Enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 9. "FDTEN2,Enable Falling Dead-time Insertion for EPWM Pair (EPWM_CH(n/2) EPWM_CH(n/2+1)) (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Falling Dead-time insertion Disabled on the..,1: Falling Dead-time insertion Enabled on the.."
|
|
bitfld.long 0x00 8. "FDTEN0,Enable Falling Dead-time Insertion for EPWM Pair (EPWM_CH(n/2) EPWM_CH(n/2+1)) (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Falling Dead-time insertion Disabled on the..,1: Falling Dead-time insertion Enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 2. "RDTEN4,Enable Rising Dead-time Insertion for EPWM Pair (EPWM_CH(n/2) EPWM_CH(n/2+1)) (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Rising Dead-time insertion Disabled on the..,1: Rising Dead-time insertion Enabled on the pin.."
|
|
bitfld.long 0x00 1. "RDTEN2,Enable Rising Dead-time Insertion for EPWM Pair (EPWM_CH(n/2) EPWM_CH(n/2+1)) (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Rising Dead-time insertion Disabled on the..,1: Rising Dead-time insertion Enabled on the pin.."
|
|
newline
|
|
bitfld.long 0x00 0. "RDTEN0,Enable Rising Dead-time Insertion for EPWM Pair (EPWM_CH(n/2) EPWM_CH(n/2+1)) (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Rising Dead-time insertion Disabled on the..,1: Rising Dead-time insertion Enabled on the pin.."
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "EPWM_PBUF0,EPWM PERIOD0 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "EPWM_PBUF1,EPWM PERIOD1 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "EPWM_PBUF2,EPWM PERIOD2 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "EPWM_PBUF3,EPWM PERIOD3 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "EPWM_PBUF4,EPWM PERIOD4 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "EPWM_PBUF5,EPWM PERIOD5 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "EPWM_CMPBUF0,EPWM CMPDAT0 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "EPWM_CMPBUF1,EPWM CMPDAT1 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "EPWM_CMPBUF2,EPWM CMPDAT2 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "EPWM_CMPBUF3,EPWM CMPDAT3 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "EPWM_CMPBUF4,EPWM CMPDAT4 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "EPWM_CMPBUF5,EPWM CMPDAT5 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
rgroup.long 0x334++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF0_1,EPWM CLKPSC0_1 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF2_3,EPWM CLKPSC2_3 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF4_5,EPWM CLKPSC4_5 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "EPWM_FTCBUF0_1,EPWM FTCMPDAT0_1 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "EPWM_FTCBUF2_3,EPWM FTCMPDAT2_3 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "EPWM_FTCBUF4_5,EPWM FTCMPDAT4_5 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "EPWM_FTCI,EPWM FTCMPDAT Indicator Register"
|
|
bitfld.long 0x00 10. "FTCMD4,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
bitfld.long 0x00 9. "FTCMD2,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "FTCMD0,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
bitfld.long 0x00 2. "FTCMU4,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "FTCMU2,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
bitfld.long 0x00 0. "FTCMU0,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF0,EPWM CLKPSC0 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF1,EPWM CLKPSC1 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF2,EPWM CLKPSC2 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF3,EPWM CLKPSC3 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF4,EPWM CLKPSC4 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF5,EPWM CLKPSC5 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
rgroup.long 0x368++0x03
|
|
line.long 0x00 "EPWM_IFACNT0,EPWM Interrupt Flag Accumulator Counter 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function"
|
|
repeat 5. (strings "1" "2" "3" "4" "5" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
group.long ($2+0x36C)++0x03
|
|
line.long 0x00 "EPWM_IFACNT$1,EPWM Interrupt Flag Accumulator Counter $1"
|
|
hexmask.long.word 0x00 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "FMC (FMC Register Map)"
|
|
base ad:0x4000C000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FMC_ISPCTL,ISP Control Register"
|
|
bitfld.long 0x00 24. "INTEN,Secure ISP INT Enable Bit (Write Protect)\nNote: This bit is write protected" "0: ISP INT Disabled,1: ISP INT Enabled"
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|
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\nAPROM writes to itself if APUEN is set to 0.\nLDROM writes to itself if LDUEN.." "0,1"
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|
newline
|
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bitfld.long 0x00 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nNote: This bit is write protected" "0: LDROM cannot be updated,1: LDROM can be updated"
|
|
bitfld.long 0x00 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected" "0: CONFIG cannot be updated,1: CONFIG can be updated"
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|
newline
|
|
bitfld.long 0x00 3. "APUEN,APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected" "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in.."
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|
bitfld.long 0x00 1. "BS,Boot Select (Write Protect)\nWhen MBS in CONFIG0 is 1 set/clear this bit to select next booting from LDROM/APROM respectively" "0: Boot from APROM when MBS (CONFIG0[5]) is 1,1: Boot from LDROM when MBS (CONFIG0[5]) is 1"
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|
newline
|
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bitfld.long 0x00 0. "ISPEN,ISP Enable Bit (Write Protect)\nISP function enable bit" "0: ISP function Disabled,1: ISP function Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "FMC_ISPADDR,ISP Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPADDR,ISP Address\nThe M471 series is equipped with embedded Flash"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FMC_ISPDAT,ISP Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FMC_ISPCMD,ISP Command Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CMD,ISP Command\nISP command table is shown below:\nThe other commands are invalid"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FMC_ISPTRG,ISP Trigger Control Register"
|
|
bitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is write protected" "0: ISP operation is finished,1: ISP is progressed"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "FMC_DFBA,Data Flash Base Address"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FMC_ISPSTS,ISP Status Register"
|
|
bitfld.long 0x00 24. "INTFLAG,ISP Interuppt Flag\nNote: This function needs to be enabled by FMC_ISPCTRL[24]" "0: ISP Not Finished,1: ISP done or ISPFF set"
|
|
hexmask.long.word 0x00 9.--23. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory address {VECMAP[14:0] 9'h000} ~ {VECMAP[14:0] 9'h1FF}"
|
|
newline
|
|
bitfld.long 0x00 7. "ALLONE,Flash All-one Verification Flag \nThis bit is set by hardware if all of Flash bits are 1 and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit also can be clear by writing 1" "0: Flash bits are not all 1 after 'Run Flash..,1: All of Flash bits are 1 after 'Run Flash.."
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|
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]" "0,1"
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|
newline
|
|
rbitfld.long 0x00 5. "PGFF,Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification" "0: Flash Program is success,1: Flash Program is fail"
|
|
rbitfld.long 0x00 4. "FCYCDIS,Flash Access Cycle Auto-tuning Disable Flag (Read Only)\nThis bit is set if Flash access cycle auto-tunning function is disabled" "0: Flash access cycle auto-tuning Enabled,1: Flash access cyle auto-tuning Disabled"
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|
newline
|
|
rbitfld.long 0x00 1.--2. "CBS,Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened" "0: LDROM with IAP mode,1: LDROM without IAP mode,2: APROM with IAP mode,3: APROM without IAP mode"
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|
rbitfld.long 0x00 0. "ISPBUSY,ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0])" "0: ISP operation is finished,1: ISP is progressed"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FMC_CYCCTL,Flash Access Cycle Control Register"
|
|
bitfld.long 0x00 8. "FADIS,Flash Access Cycle Auto-tuning Disable Bit (Write Protect)\nSet this bit to disable Flash access cycle auto-tuning function\nNote: This bit is write protected" "0: Flash access cycle auto-tuning Enabled,1: Flash access cycle auto-tuning Disabled"
|
|
bitfld.long 0x00 0.--3. "CYCLE,Flash Access Cycle Control (Write Protect)\nThis register is updated by software.User needs to check the speed of HCLK and set the cycle 0 \nThe optimized HCLK working frequency range is 192 MHz\nNote: This bit is write protected" "?,1: CPU access with one wait cycle if cache miss..,2: CPU access with two wait cycles if cache miss..,3: CPU access with three wait cycles if cache..,4: CPU access with four wait cycles if cache..,5: CPU access with five wait cycles if cache..,6: CPU access with six wait cycles if cache miss..,7: CPU access with seven wait cycles if cache..,8: CPU access with eight wait cycles if cache..,?..."
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FMC_MPDAT0,ISP Data0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT0,ISP Data 0\nThis register is the first 32-bit data for 32-bit/64-bit/multi-word programming and it is also the mirror of FMC_ISPDAT both registers keep the same data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FMC_MPDAT1,ISP Data1 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT1,ISP Data 1\nThis register is the second 32-bit data for 64-bit/multi-word programming"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FMC_MPDAT2,ISP Data2 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT2,ISP Data 2\nThis register is the third 32-bit data for multi-word programming"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FMC_MPDAT3,ISP Data3 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT3,ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "FMC_MPSTS,ISP Multi-program Status Register"
|
|
bitfld.long 0x00 7. "D3,ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete" "0: FMC_MPDAT3 register is empty or program to..,1: FMC_MPDAT3 register has been written and not.."
|
|
bitfld.long 0x00 6. "D2,ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete" "0: FMC_MPDAT2 register is empty or program to..,1: FMC_MPDAT2 register has been written and not.."
|
|
newline
|
|
bitfld.long 0x00 5. "D1,ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete" "0: FMC_MPDAT1 register is empty or program to..,1: FMC_MPDAT1 register has been written and not.."
|
|
bitfld.long 0x00 4. "D0,ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete" "0: FMC_MPDAT0 register is empty or program to..,1: FMC_MPDAT0 register has been written and not.."
|
|
newline
|
|
bitfld.long 0x00 2. "ISPFF,ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]" "0,1"
|
|
bitfld.long 0x00 1. "PPGO,ISP Multi-program Status (Read Only)" "0: ISP multi-word program operation is not active,1: ISP multi-word program operation is in progress"
|
|
newline
|
|
bitfld.long 0x00 0. "MPBUSY,ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of.." "0: ISP Multi-Word program operation is finished,1: ISP Multi-Word program operation is progressed"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "FMC_MPADDR,ISP Multi-program Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "MPADDR,ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FMC_XOMR0STS,XOM Region 0 Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "BASE,XOM Region 0 Base Address (Page-aligned)\nBASE is the base address of XOM Region 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SIZE,XOM Region 0 Size (Page-aligned)\nSIZE is the page number of XOM Region 0"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "FMC_XOMR1STS,XOM Region 1 Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "BASE,XOM Region 1 Base Address (Page-aligned)\nBASE is the base address of XOM Region 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SIZE,XOM Region 1 Size (Page-aligned)\nSIZE is the page number of XOM Region 1"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "FMC_XOMR2STS,XOM Region 2 Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "BASE,XOM Region 2 Base Address (Page-aligned)\nBASE is the base address of XOM Region 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SIZE,XOM Region 2 Size (Page-aligned)\nSIZE is the page number of XOM Region 2"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "FMC_XOMR3STS,XOM Region 3 Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "BASE,XOM Region 3 Base Address (Page-aligned)\nBASE is the base address of XOM Region 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SIZE,XOM Region 3 Size (Page-aligned)\nSIZE is the page number of XOM Region 3"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "FMC_XOMSTS,XOM Status Register"
|
|
bitfld.long 0x00 4. "XOMPEF,XOM Page Erase Function Fail\nXOM page erase function status" "0: Sucess,1: Fail"
|
|
bitfld.long 0x00 3. "XOMR3ON,XOM Region 3 On\nXOM Region 3 active status" "0: No active,1: XOM region 3 is active"
|
|
newline
|
|
bitfld.long 0x00 2. "XOMR2ON,XOM Region 2 On\nXOM Region 2 active status" "0: No active,1: XOM region 2 is active"
|
|
bitfld.long 0x00 1. "XOMR1ON,XOM Region 1 On\nXOM Region 1 active status" "0: No active,1: XOM region 1 is active"
|
|
newline
|
|
bitfld.long 0x00 0. "XOMR0ON,XOM Region 0 On\nXOM Region 0 active status" "0: No active,1: XOM region 0 is active"
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
|
|
base ad:0x40004000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PA_MODE,PA I/O Mode Control"
|
|
bitfld.long 0x00 30.--31. "MODE15,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
bitfld.long 0x00 28.--29. "MODE14,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "MODE13,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
bitfld.long 0x00 24.--25. "MODE12,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "MODE11,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
bitfld.long 0x00 20.--21. "MODE10,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "MODE9,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
bitfld.long 0x00 16.--17. "MODE8,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "MODE7,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
bitfld.long 0x00 12.--13. "MODE6,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODE5,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
bitfld.long 0x00 8.--9. "MODE4,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "MODE3,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
bitfld.long 0x00 4.--5. "MODE2,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "MODE1,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
bitfld.long 0x00 0.--1. "MODE0,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PA_DINOFF,PA Digital Input Path Disable Control"
|
|
bitfld.long 0x00 31. "DINOFF15,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
|
|
bitfld.long 0x00 30. "DINOFF14,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
|
|
newline
|
|
bitfld.long 0x00 29. "DINOFF13,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
|
|
bitfld.long 0x00 28. "DINOFF12,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
|
|
newline
|
|
bitfld.long 0x00 27. "DINOFF11,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
|
|
bitfld.long 0x00 26. "DINOFF10,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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|
newline
|
|
bitfld.long 0x00 25. "DINOFF9,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
|
|
bitfld.long 0x00 24. "DINOFF8,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
|
|
newline
|
|
bitfld.long 0x00 23. "DINOFF7,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
|
|
bitfld.long 0x00 22. "DINOFF6,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
|
|
newline
|
|
bitfld.long 0x00 21. "DINOFF5,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
|
|
bitfld.long 0x00 20. "DINOFF4,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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|
newline
|
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bitfld.long 0x00 19. "DINOFF3,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
|
|
bitfld.long 0x00 18. "DINOFF2,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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|
newline
|
|
bitfld.long 0x00 17. "DINOFF1,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
|
|
bitfld.long 0x00 16. "DINOFF0,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PA_DOUT,PA Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PA_DATMSK,PA Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PA_PIN,PA Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PA_DBEN,PA De-Bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PA_INTTYPE,PA Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PA_INTEN,PA Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PA_INTSRC,PA Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 3. "INTSRC3,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 1. "INTSRC1,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PA_SMTEN,PA Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PA_SLEWCTL,PA High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PA_PUSEL,PA Pull-up Selection Register"
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bitfld.long 0x00 30. "PUSEL15,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 28. "PUSEL14,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 26. "PUSEL13,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 24. "PUSEL12,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 22. "PUSEL11,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 20. "PUSEL10,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 18. "PUSEL9,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 16. "PUSEL8,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 14. "PUSEL7,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 12. "PUSEL6,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 10. "PUSEL5,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 8. "PUSEL4,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 6. "PUSEL3,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 4. "PUSEL2,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 2. "PUSEL1,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 0. "PUSEL0,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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group.long 0x40++0x03
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line.long 0x00 "PB_MODE,PB I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x44++0x03
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line.long 0x00 "PB_DINOFF,PB Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x48++0x03
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line.long 0x00 "PB_DOUT,PB Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x4C++0x03
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line.long 0x00 "PB_DATMSK,PB Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x50++0x03
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line.long 0x00 "PB_PIN,PB Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x54++0x03
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line.long 0x00 "PB_DBEN,PB De-Bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "PB_INTTYPE,PB Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x5C++0x03
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line.long 0x00 "PB_INTEN,PB Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x60++0x03
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line.long 0x00 "PB_INTSRC,PB Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x64++0x03
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line.long 0x00 "PB_SMTEN,PB Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x68++0x03
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line.long 0x00 "PB_SLEWCTL,PB High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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group.long 0x70++0x03
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line.long 0x00 "PB_PUSEL,PB Pull-up Selection Register"
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bitfld.long 0x00 30. "PUSEL15,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 28. "PUSEL14,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 26. "PUSEL13,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 24. "PUSEL12,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 22. "PUSEL11,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 20. "PUSEL10,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 18. "PUSEL9,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 16. "PUSEL8,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 14. "PUSEL7,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 12. "PUSEL6,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 10. "PUSEL5,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 8. "PUSEL4,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 6. "PUSEL3,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 4. "PUSEL2,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 2. "PUSEL1,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 0. "PUSEL0,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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group.long 0x80++0x03
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line.long 0x00 "PC_MODE,PC I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x84++0x03
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line.long 0x00 "PC_DINOFF,PC Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x88++0x03
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line.long 0x00 "PC_DOUT,PC Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x8C++0x03
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line.long 0x00 "PC_DATMSK,PC Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x90++0x03
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line.long 0x00 "PC_PIN,PC Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x94++0x03
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line.long 0x00 "PC_DBEN,PC De-Bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x98++0x03
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line.long 0x00 "PC_INTTYPE,PC Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x9C++0x03
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line.long 0x00 "PC_INTEN,PC Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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newline
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bitfld.long 0x00 1. "FLIEN1,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0xA0++0x03
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line.long 0x00 "PC_INTSRC,PC Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 13. "INTSRC13,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 7. "INTSRC7,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 5. "INTSRC5,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 3. "INTSRC3,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 1. "INTSRC1,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0xA4++0x03
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line.long 0x00 "PC_SMTEN,PC Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 13. "SMTEN13,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 11. "SMTEN11,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 9. "SMTEN9,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 7. "SMTEN7,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 5. "SMTEN5,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 3. "SMTEN3,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 1. "SMTEN1,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0xA8++0x03
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line.long 0x00 "PC_SLEWCTL,PC High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 26.--27. "HSREN13,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 22.--23. "HSREN11,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 18.--19. "HSREN9,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 14.--15. "HSREN7,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 10.--11. "HSREN5,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 6.--7. "HSREN3,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 2.--3. "HSREN1,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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group.long 0xB0++0x03
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line.long 0x00 "PC_PUSEL,PC Pull-up Selection Register"
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bitfld.long 0x00 30. "PUSEL15,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 28. "PUSEL14,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 26. "PUSEL13,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 24. "PUSEL12,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 22. "PUSEL11,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 20. "PUSEL10,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 18. "PUSEL9,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 16. "PUSEL8,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 14. "PUSEL7,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 12. "PUSEL6,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 10. "PUSEL5,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 8. "PUSEL4,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 6. "PUSEL3,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 4. "PUSEL2,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 2. "PUSEL1,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 0. "PUSEL0,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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group.long 0xC0++0x03
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line.long 0x00 "PD_MODE,PD I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0xC4++0x03
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line.long 0x00 "PD_DINOFF,PD Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0xC8++0x03
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line.long 0x00 "PD_DOUT,PD Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0xCC++0x03
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line.long 0x00 "PD_DATMSK,PD Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0xD0++0x03
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line.long 0x00 "PD_PIN,PD Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0xD4++0x03
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line.long 0x00 "PD_DBEN,PD De-Bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "PD_INTTYPE,PD Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0xDC++0x03
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line.long 0x00 "PD_INTEN,PD Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0xE0++0x03
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line.long 0x00 "PD_INTSRC,PD Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 7. "INTSRC7,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 5. "INTSRC5,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 3. "INTSRC3,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 1. "INTSRC1,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0xE4++0x03
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line.long 0x00 "PD_SMTEN,PD Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 13. "SMTEN13,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 11. "SMTEN11,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 9. "SMTEN9,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 7. "SMTEN7,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 5. "SMTEN5,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 3. "SMTEN3,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 1. "SMTEN1,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0xE8++0x03
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line.long 0x00 "PD_SLEWCTL,PD High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 26.--27. "HSREN13,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 22.--23. "HSREN11,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 18.--19. "HSREN9,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 14.--15. "HSREN7,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 10.--11. "HSREN5,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 6.--7. "HSREN3,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 2.--3. "HSREN1,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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group.long 0xF0++0x03
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line.long 0x00 "PD_PUSEL,PD Pull-up Selection Register"
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bitfld.long 0x00 30. "PUSEL15,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 28. "PUSEL14,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 26. "PUSEL13,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 24. "PUSEL12,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 22. "PUSEL11,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 20. "PUSEL10,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 18. "PUSEL9,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 16. "PUSEL8,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 14. "PUSEL7,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 12. "PUSEL6,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 10. "PUSEL5,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 8. "PUSEL4,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 6. "PUSEL3,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 4. "PUSEL2,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 2. "PUSEL1,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 0. "PUSEL0,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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group.long 0x100++0x03
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line.long 0x00 "PE_MODE,PE I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x104++0x03
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line.long 0x00 "PE_DINOFF,PE Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x108++0x03
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line.long 0x00 "PE_DOUT,PE Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x10C++0x03
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line.long 0x00 "PE_DATMSK,PE Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x110++0x03
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line.long 0x00 "PE_PIN,PE Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x114++0x03
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line.long 0x00 "PE_DBEN,PE De-Bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x118++0x03
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line.long 0x00 "PE_INTTYPE,PE Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x11C++0x03
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line.long 0x00 "PE_INTEN,PE Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x120++0x03
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line.long 0x00 "PE_INTSRC,PE Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x124++0x03
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line.long 0x00 "PE_SMTEN,PE Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 9. "SMTEN9,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 7. "SMTEN7,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 5. "SMTEN5,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 3. "SMTEN3,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 1. "SMTEN1,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x128++0x03
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line.long 0x00 "PE_SLEWCTL,PE High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 26.--27. "HSREN13,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 22.--23. "HSREN11,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 18.--19. "HSREN9,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 14.--15. "HSREN7,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 10.--11. "HSREN5,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 6.--7. "HSREN3,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 2.--3. "HSREN1,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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group.long 0x130++0x03
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line.long 0x00 "PE_PUSEL,PE Pull-up Selection Register"
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bitfld.long 0x00 30. "PUSEL15,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 28. "PUSEL14,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 26. "PUSEL13,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 24. "PUSEL12,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 22. "PUSEL11,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 20. "PUSEL10,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 18. "PUSEL9,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 16. "PUSEL8,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 14. "PUSEL7,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 12. "PUSEL6,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 10. "PUSEL5,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 8. "PUSEL4,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 6. "PUSEL3,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 4. "PUSEL2,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 2. "PUSEL1,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 0. "PUSEL0,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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group.long 0x140++0x03
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line.long 0x00 "PF_MODE,PF I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 2.--3. "MODE1,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x144++0x03
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line.long 0x00 "PF_DINOFF,PF Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 29. "DINOFF13,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 27. "DINOFF11,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 25. "DINOFF9,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 23. "DINOFF7,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x148++0x03
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line.long 0x00 "PF_DOUT,PF Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x14C++0x03
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line.long 0x00 "PF_DATMSK,PF Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x150++0x03
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line.long 0x00 "PF_PIN,PF Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x154++0x03
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line.long 0x00 "PF_DBEN,PF De-Bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x158++0x03
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line.long 0x00 "PF_INTTYPE,PF Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x15C++0x03
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line.long 0x00 "PF_INTEN,PF Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x160++0x03
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line.long 0x00 "PF_INTSRC,PF Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x164++0x03
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line.long 0x00 "PF_SMTEN,PF Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x168++0x03
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line.long 0x00 "PF_SLEWCTL,PF High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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group.long 0x170++0x03
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line.long 0x00 "PF_PUSEL,PF Pull-up Selection Register"
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bitfld.long 0x00 30. "PUSEL15,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 28. "PUSEL14,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 26. "PUSEL13,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 24. "PUSEL12,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 22. "PUSEL11,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 20. "PUSEL10,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 18. "PUSEL9,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 16. "PUSEL8,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 14. "PUSEL7,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 12. "PUSEL6,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 10. "PUSEL5,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 8. "PUSEL4,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 6. "PUSEL3,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 4. "PUSEL2,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 2. "PUSEL1,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 0. "PUSEL0,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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group.long 0x180++0x03
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line.long 0x00 "PG_MODE,PG I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x184++0x03
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line.long 0x00 "PG_DINOFF,PG Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x188++0x03
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line.long 0x00 "PG_DOUT,PG Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x18C++0x03
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line.long 0x00 "PG_DATMSK,PG Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x190++0x03
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line.long 0x00 "PG_PIN,PG Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x194++0x03
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line.long 0x00 "PG_DBEN,PG De-Bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x198++0x03
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line.long 0x00 "PG_INTTYPE,PG Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x19C++0x03
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line.long 0x00 "PG_INTEN,PG Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x1A0++0x03
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line.long 0x00 "PG_INTSRC,PG Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x1A4++0x03
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line.long 0x00 "PG_SMTEN,PG Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x1A8++0x03
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line.long 0x00 "PG_SLEWCTL,PG High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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group.long 0x1B0++0x03
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line.long 0x00 "PG_PUSEL,PG Pull-up Selection Register"
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bitfld.long 0x00 30. "PUSEL15,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 28. "PUSEL14,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 26. "PUSEL13,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 24. "PUSEL12,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 22. "PUSEL11,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 20. "PUSEL10,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 18. "PUSEL9,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 16. "PUSEL8,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 14. "PUSEL7,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 12. "PUSEL6,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 10. "PUSEL5,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 8. "PUSEL4,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 6. "PUSEL3,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 4. "PUSEL2,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 2. "PUSEL1,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 0. "PUSEL0,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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group.long 0x1C0++0x03
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line.long 0x00 "PH_MODE,PH I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x1C4++0x03
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line.long 0x00 "PH_DINOFF,PH Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x1C8++0x03
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line.long 0x00 "PH_DOUT,PH Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x1CC++0x03
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line.long 0x00 "PH_DATMSK,PH Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x1D0++0x03
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line.long 0x00 "PH_PIN,PH Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x1D4++0x03
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line.long 0x00 "PH_DBEN,PH De-Bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x1D8++0x03
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line.long 0x00 "PH_INTTYPE,PH Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1DC++0x03
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line.long 0x00 "PH_INTEN,PH Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x1E0++0x03
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line.long 0x00 "PH_INTSRC,PH Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x1E4++0x03
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line.long 0x00 "PH_SMTEN,PH Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x1E8++0x03
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line.long 0x00 "PH_SLEWCTL,PH High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 2.--3. "HSREN1,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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group.long 0x1F0++0x03
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line.long 0x00 "PH_PUSEL,PH Pull-up Selection Register"
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bitfld.long 0x00 30. "PUSEL15,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 28. "PUSEL14,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 26. "PUSEL13,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 24. "PUSEL12,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 22. "PUSEL11,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 20. "PUSEL10,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 18. "PUSEL9,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 16. "PUSEL8,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 14. "PUSEL7,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 12. "PUSEL6,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 10. "PUSEL5,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 8. "PUSEL4,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 6. "PUSEL3,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 4. "PUSEL2,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 2. "PUSEL1,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 0. "PUSEL0,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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group.long 0x200++0x03
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line.long 0x00 "PI_MODE,PI I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-I I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x204++0x03
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line.long 0x00 "PI_DINOFF,PI Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-I Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x208++0x03
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line.long 0x00 "PI_DOUT,PI Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-I Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x20C++0x03
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line.long 0x00 "PI_DATMSK,PI Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-I Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x210++0x03
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line.long 0x00 "PI_PIN,PI Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port A-I Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x214++0x03
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line.long 0x00 "PI_DBEN,PI De-Bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-I Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x218++0x03
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line.long 0x00 "PI_INTTYPE,PI Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x21C++0x03
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line.long 0x00 "PI_INTEN,PI Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x220++0x03
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line.long 0x00 "PI_INTSRC,PI Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 9. "INTSRC9,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 7. "INTSRC7,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 5. "INTSRC5,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 3. "INTSRC3,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 1. "INTSRC1,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-I Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x224++0x03
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line.long 0x00 "PI_SMTEN,PI Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 13. "SMTEN13,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 11. "SMTEN11,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 9. "SMTEN9,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 7. "SMTEN7,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 5. "SMTEN5,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 3. "SMTEN3,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 1. "SMTEN1,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-I Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x228++0x03
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line.long 0x00 "PI_SLEWCTL,PI High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 26.--27. "HSREN13,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 22.--23. "HSREN11,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 18.--19. "HSREN9,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 14.--15. "HSREN7,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 10.--11. "HSREN5,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 6.--7. "HSREN3,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 2.--3. "HSREN1,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-I Pin[n] High Slew Rate Control\nNote: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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group.long 0x230++0x03
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line.long 0x00 "PI_PUSEL,PI Pull-up Selection Register"
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bitfld.long 0x00 30. "PUSEL15,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 28. "PUSEL14,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 26. "PUSEL13,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 24. "PUSEL12,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 22. "PUSEL11,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 20. "PUSEL10,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 18. "PUSEL9,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 16. "PUSEL8,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 14. "PUSEL7,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 12. "PUSEL6,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 10. "PUSEL5,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 8. "PUSEL4,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 6. "PUSEL3,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 4. "PUSEL2,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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newline
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bitfld.long 0x00 2. "PUSEL1,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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bitfld.long 0x00 0. "PUSEL0,Port A-I Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable"
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group.long 0x440++0x03
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line.long 0x00 "GPIO_DBCTL,Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\n" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the.."
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newline
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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group.long 0x450++0x03
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line.long 0x00 "INT0_INNF,INTn Input Noise Filter Register"
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bitfld.long 0x00 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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newline
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bitfld.long 0x00 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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group.long 0x454++0x03
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line.long 0x00 "INT1_INNF,INTn Input Noise Filter Register"
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bitfld.long 0x00 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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newline
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bitfld.long 0x00 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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group.long 0x458++0x03
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line.long 0x00 "INT2_INNF,INTn Input Noise Filter Register"
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bitfld.long 0x00 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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newline
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bitfld.long 0x00 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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group.long 0x45C++0x03
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line.long 0x00 "INT3_INNF,INTn Input Noise Filter Register"
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bitfld.long 0x00 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
|
|
newline
|
|
bitfld.long 0x00 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "INT4_INNF,INTn Input Noise Filter Register"
|
|
bitfld.long 0x00 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
|
|
newline
|
|
bitfld.long 0x00 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "INT5_INNF,INTn Input Noise Filter Register"
|
|
bitfld.long 0x00 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
|
|
newline
|
|
bitfld.long 0x00 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "INT6_INNF,INTn Input Noise Filter Register"
|
|
bitfld.long 0x00 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
|
|
newline
|
|
bitfld.long 0x00 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "INT7_INNF,INTn Input Noise Filter Register"
|
|
bitfld.long 0x00 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
|
|
newline
|
|
bitfld.long 0x00 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "INT_EDETCTL,INT Edge Detect Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "Reseved,Reseved"
|
|
bitfld.long 0x00 14.--15. "EDETCTL7,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,2: INTn high to low detection Enable,3: INTn both low to high and high to low.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "EDETCTL6,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,2: INTn high to low detection Enable,3: INTn both low to high and high to low.."
|
|
bitfld.long 0x00 10.--11. "EDETCTL5,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,2: INTn high to low detection Enable,3: INTn both low to high and high to low.."
|
|
newline
|
|
bitfld.long 0x00 8.--9. "EDETCTL4,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,2: INTn high to low detection Enable,3: INTn both low to high and high to low.."
|
|
bitfld.long 0x00 6.--7. "EDETCTL3,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,2: INTn high to low detection Enable,3: INTn both low to high and high to low.."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "EDETCTL2,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,2: INTn high to low detection Enable,3: INTn both low to high and high to low.."
|
|
bitfld.long 0x00 2.--3. "EDETCTL1,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,2: INTn high to low detection Enable,3: INTn both low to high and high to low.."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "EDETCTL0,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,2: INTn high to low detection Enable,3: INTn both low to high and high to low.."
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "INT_EDINTEN,INT Edge Detect Interrupt Enable Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "Reseved,Reseved"
|
|
bitfld.long 0x00 7. "EDIEN7,INTn Edge Detect Interrupt Enable Bit" "0: INTx Edge Detect Interrupt Disable,1: INTx Edge Detect Interrupt Enable"
|
|
newline
|
|
bitfld.long 0x00 6. "EDIEN6,INTn Edge Detect Interrupt Enable Bit" "0: INTx Edge Detect Interrupt Disable,1: INTx Edge Detect Interrupt Enable"
|
|
bitfld.long 0x00 5. "EDIEN5,INTn Edge Detect Interrupt Enable Bit" "0: INTx Edge Detect Interrupt Disable,1: INTx Edge Detect Interrupt Enable"
|
|
newline
|
|
bitfld.long 0x00 4. "EDIEN4,INTn Edge Detect Interrupt Enable Bit" "0: INTx Edge Detect Interrupt Disable,1: INTx Edge Detect Interrupt Enable"
|
|
bitfld.long 0x00 3. "EDIEN3,INTn Edge Detect Interrupt Enable Bit" "0: INTx Edge Detect Interrupt Disable,1: INTx Edge Detect Interrupt Enable"
|
|
newline
|
|
bitfld.long 0x00 2. "EDIEN2,INTn Edge Detect Interrupt Enable Bit" "0: INTx Edge Detect Interrupt Disable,1: INTx Edge Detect Interrupt Enable"
|
|
bitfld.long 0x00 1. "EDIEN1,INTn Edge Detect Interrupt Enable Bit" "0: INTx Edge Detect Interrupt Disable,1: INTx Edge Detect Interrupt Enable"
|
|
newline
|
|
bitfld.long 0x00 0. "EDIEN0,INTn Edge Detect Interrupt Enable Bit" "0: INTx Edge Detect Interrupt Disable,1: INTx Edge Detect Interrupt Enable"
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "INT_EDSTS,INT Edge Detect Interrupt Flag Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "Reseved,Reseved"
|
|
bitfld.long 0x00 7. "EDIF7,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it" "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
|
|
newline
|
|
bitfld.long 0x00 6. "EDIF6,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it" "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
|
|
bitfld.long 0x00 5. "EDIF5,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it" "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
|
|
newline
|
|
bitfld.long 0x00 4. "EDIF4,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it" "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
|
|
bitfld.long 0x00 3. "EDIF3,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it" "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
|
|
newline
|
|
bitfld.long 0x00 2. "EDIF2,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it" "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
|
|
bitfld.long 0x00 1. "EDIF1,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it" "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
|
|
newline
|
|
bitfld.long 0x00 0. "EDIF0,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it" "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x814++0x03
|
|
line.long 0x00 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "PA6_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x81C++0x03
|
|
line.long 0x00 "PA7_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "PA8_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "PA9_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "PA10_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "PA11_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "PA12_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "PA13_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "PA14_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "PA15_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x84C++0x03
|
|
line.long 0x00 "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x854++0x03
|
|
line.long 0x00 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x85C++0x03
|
|
line.long 0x00 "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "PB8_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x864++0x03
|
|
line.long 0x00 "PB9_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "PB10_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x86C++0x03
|
|
line.long 0x00 "PB11_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "PB12_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x874++0x03
|
|
line.long 0x00 "PB13_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "PB14_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x87C++0x03
|
|
line.long 0x00 "PB15_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x884++0x03
|
|
line.long 0x00 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x88C++0x03
|
|
line.long 0x00 "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x894++0x03
|
|
line.long 0x00 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "PC6_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x89C++0x03
|
|
line.long 0x00 "PC7_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "PC8_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x8A4++0x03
|
|
line.long 0x00 "PC9_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "PC10_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x8AC++0x03
|
|
line.long 0x00 "PC11_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "PC12_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x8B4++0x03
|
|
line.long 0x00 "PC13_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "PC14_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x8BC++0x03
|
|
line.long 0x00 "PC15_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "PD0_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x8C4++0x03
|
|
line.long 0x00 "PD1_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8C8++0x03
|
|
line.long 0x00 "PD2_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8CC++0x03
|
|
line.long 0x00 "PD3_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8D0++0x03
|
|
line.long 0x00 "PD4_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8D4++0x03
|
|
line.long 0x00 "PD5_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8D8++0x03
|
|
line.long 0x00 "PD6_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8DC++0x03
|
|
line.long 0x00 "PD7_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8E0++0x03
|
|
line.long 0x00 "PD8_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8E4++0x03
|
|
line.long 0x00 "PD9_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "PD10_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8EC++0x03
|
|
line.long 0x00 "PD11_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "PD12_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8F4++0x03
|
|
line.long 0x00 "PD13_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "PD14_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x8FC++0x03
|
|
line.long 0x00 "PD15_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "PE0_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x904++0x03
|
|
line.long 0x00 "PE1_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "PE2_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x90C++0x03
|
|
line.long 0x00 "PE3_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "PE4_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x914++0x03
|
|
line.long 0x00 "PE5_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "PE6_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x91C++0x03
|
|
line.long 0x00 "PE7_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "PE8_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x924++0x03
|
|
line.long 0x00 "PE9_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "PE10_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x92C++0x03
|
|
line.long 0x00 "PE11_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "PE12_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x934++0x03
|
|
line.long 0x00 "PE13_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x938++0x03
|
|
line.long 0x00 "PE14_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x93C++0x03
|
|
line.long 0x00 "PE15_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "PF0_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x944++0x03
|
|
line.long 0x00 "PF1_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "PF2_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x94C++0x03
|
|
line.long 0x00 "PF3_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "PF4_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x954++0x03
|
|
line.long 0x00 "PF5_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "PF6_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x95C++0x03
|
|
line.long 0x00 "PF7_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "PF8_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x964++0x03
|
|
line.long 0x00 "PF9_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "PF10_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x96C++0x03
|
|
line.long 0x00 "PF11_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "PF12_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x974++0x03
|
|
line.long 0x00 "PF13_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x978++0x03
|
|
line.long 0x00 "PF14_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x97C++0x03
|
|
line.long 0x00 "PF15_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "PG0_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x984++0x03
|
|
line.long 0x00 "PG1_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "PG2_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
group.long 0x98C++0x03
|
|
line.long 0x00 "PG3_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "PG4_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
group.long 0x994++0x03
|
|
line.long 0x00 "PG5_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "PG6_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
group.long 0x99C++0x03
|
|
line.long 0x00 "PG7_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "PG8_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
group.long 0x9A4++0x03
|
|
line.long 0x00 "PG9_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "PG10_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
group.long 0x9AC++0x03
|
|
line.long 0x00 "PG11_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "PG12_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "PH0_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x9C4++0x03
|
|
line.long 0x00 "PH1_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "PH2_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
group.long 0x9CC++0x03
|
|
line.long 0x00 "PH3_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "PH4_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
group.long 0x9D4++0x03
|
|
line.long 0x00 "PH5_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
group.long 0x9D8++0x03
|
|
line.long 0x00 "PH6_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
group.long 0x9DC++0x03
|
|
line.long 0x00 "PH7_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "PH8_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
group.long 0x9E4++0x03
|
|
line.long 0x00 "PH9_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "PH10_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
group.long 0x9EC++0x03
|
|
line.long 0x00 "PH11_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "PH12_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "PI0_PDIO,GPIO PI.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "PI1_PDIO,GPIO PI.n Pin Data Input/Output Register"
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "PI2_PDIO,GPIO PI.n Pin Data Input/Output Register"
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "PI3_PDIO,GPIO PI.n Pin Data Input/Output Register"
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "PI4_PDIO,GPIO PI.n Pin Data Input/Output Register"
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "PI5_PDIO,GPIO PI.n Pin Data Input/Output Register"
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "PI6_PDIO,GPIO PI.n Pin Data Input/Output Register"
|
|
group.long 0xA1C++0x03
|
|
line.long 0x00 "PI7_PDIO,GPIO PI.n Pin Data Input/Output Register"
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
repeat 2. (list 0. 1.) (list ad:0x40080000 ad:0x40081000)
|
|
tree "I2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C_CTL0,I2C Control Register 0"
|
|
bitfld.long 0x00 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
|
|
bitfld.long 0x00 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
|
|
bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware" "0,1"
|
|
bitfld.long 0x00 2. "AA,Assert Acknowledge Control" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C_ADDR0,I2C Slave Address Register0"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C_DAT,I2C Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "I2C_STATUS0,I2C Status Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STATUS,I2C Status"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C_CLKDIV,I2C Clock Divided Register"
|
|
bitfld.long 0x00 12.--15. "NFCNT,Noise Filter Counter \nThe register bits control the input filter width.\n0 : filter width 3*PCLK \n1 : filter width 4*PCLK\nN : filter width (3+N)*PCKL\nNote: Filter width Min :3*PCLK Max : 18*PCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C_TOCTL,I2C Time-out Control Register"
|
|
bitfld.long 0x00 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared" "0: Time-out counter Disabled,1: Time-out counter Enabled"
|
|
bitfld.long 0x00 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times" "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit" "0,1"
|
|
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "I2C_ADDR$1,I2C Slave Address Register $1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "I2C_ADDRMSK$1,I2C Slave Address Mask Register $1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
repeat.end
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "I2C_WKCTL,I2C Wake-up Control Register"
|
|
bitfld.long 0x00 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received" "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
|
|
bitfld.long 0x00 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "I2C_WKSTS,I2C Wake-up Status Register"
|
|
bitfld.long 0x00 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit" "0: Write command be record on the address match..,1: Read command be record on the address match.."
|
|
bitfld.long 0x00 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
|
|
newline
|
|
bitfld.long 0x00 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "I2C_CTL1,I2C Control Register 1"
|
|
bitfld.long 0x00 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
|
|
bitfld.long 0x00 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA..,1: I2C SCL bus is stretched by hardware after.."
|
|
newline
|
|
bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
|
|
bitfld.long 0x00 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "I2C_STATUS1,I2C Status Register 1"
|
|
rbitfld.long 0x00 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
|
|
bitfld.long 0x00 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used" "0,1"
|
|
bitfld.long 0x00 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "I2C_TMCTL,I2C Timing Configure Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode"
|
|
hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "I2C_BUSCTL,I2C Bus Management Control Register"
|
|
bitfld.long 0x00 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
|
|
bitfld.long 0x00 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock..,1: There is SI interrupt in the 9th clock cycle.."
|
|
bitfld.long 0x00 10. "PECCLR,PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected" "0: PEC calculation is cleared by 'Repeat Start'..,1: PEC calculation is cleared by 'Repeat Start'.."
|
|
newline
|
|
bitfld.long 0x00 9. "TIDLE,Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle" "0: BUSTOUT is used to calculate the clock low..,1: BUSTOUT is used to calculate the IDLE period.."
|
|
bitfld.long 0x00 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
|
|
newline
|
|
bitfld.long 0x00 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition" "0: The system management function Disabled,1: The system management function Enabled"
|
|
bitfld.long 0x00 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
|
|
newline
|
|
bitfld.long 0x00 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
|
|
bitfld.long 0x00 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert..,1: Drive BM_ALERT pin low and Alert Response.."
|
|
newline
|
|
bitfld.long 0x00 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
|
|
bitfld.long 0x00 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable,1: Device default address Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode the bit should be enabled after wake-up if needed PEC calculation" "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
|
|
bitfld.long 0x00 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit" "0: Slave byte control Disabled,1: Slave byte control Enabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
|
|
bitfld.long 0x00 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled"
|
|
bitfld.long 0x00 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCLK low time-out interrupt Disabled.\nBus..,1: SCLK low time-out interrupt Enabled.\nBus.."
|
|
bitfld.long 0x00 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master it calculates the period from START to ACK\nFor Slave it calculates the period from START to STOP" "0: Cumulative clock low time-out detection..,1: Cumulative clock low time-out detection Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "I2C_BUSSTS,I2C Bus Management Status Register"
|
|
bitfld.long 0x00 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: PEC transmission/ receive is not finished..,1: PEC transmission/ receive is finished when.."
|
|
bitfld.long 0x00 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit" "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "BUSTO,Bus Time-out Status \nIn bus busy the bit indicates the total clock low time-out event occurred otherwise it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit" "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
|
|
bitfld.long 0x00 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
|
|
newline
|
|
bitfld.long 0x00 3. "ALERT,SMBus Alert Status \nNote: 1" "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is.."
|
|
bitfld.long 0x00 2. "PECERR,PEC Error in Reception \nNote: Software can write 1 to clear this bit" "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
|
|
newline
|
|
bitfld.long 0x00 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: Byte count transmission/ receive is not..,1: Byte count transmission/ receive is finished.."
|
|
bitfld.long 0x00 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus" "0: Bus is IDLE (both SCLK and SDA High),1: Bus is busy"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "I2C_BUSTOUT,I2C Bus Management Timer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the.."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "NMI (NMI Register Map)"
|
|
base ad:0x40000300
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "NMIEN,NMI Source Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "UART1_INT,UART1 NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: UART1 NMI source Disabled,1: UART1 NMI source Enabled"
|
|
bitfld.long 0x00 14. "UART0_INT,UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: UART0 NMI source Disabled,1: UART0 NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "EINT5,External Interrupt From PB.7 PD.12 or PF.14 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.7 PD.12 or PF.14..,1: External interrupt from PB.7 PD.12 or PF.14.."
|
|
bitfld.long 0x00 12. "EINT4,External Interrupt From PA.8 PB.6 or PF.15 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PA.8 PB.6 or PF.15..,1: External interrupt from PA.8 PB.6 or PF.15.."
|
|
newline
|
|
bitfld.long 0x00 11. "EINT3,External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.2 or PC.7 pin NMI..,1: External interrupt from PB.2 or PC.7 pin NMI.."
|
|
bitfld.long 0x00 10. "EINT2,External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.3 or PC.6 pin NMI..,1: External interrupt from PB.3 or PC.6 pin NMI.."
|
|
newline
|
|
bitfld.long 0x00 9. "EINT1,External Interrupt From PA.7 PB.4 or PD.15 NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PA.7 PB.4 or PD.15..,1: External interrupt from PA.7 PB.4 or PD.15.."
|
|
bitfld.long 0x00 8. "EINT0,External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PA.6 or PB.5 pin NMI..,1: External interrupt from PA.6 or PB.5 pin NMI.."
|
|
newline
|
|
bitfld.long 0x00 6. "RTC_INT,RTC NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: RTC NMI source Disabled,1: RTC NMI source Enabled"
|
|
bitfld.long 0x00 4. "CLKFAIL,Clock Fail Detected NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: Clock fail detected interrupt NMI source..,1: Clock fail detected interrupt NMI source.."
|
|
newline
|
|
bitfld.long 0x00 3. "SRAM_PERR,SRAM ParityCheck Error NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: SRAM parity check error NMI source Disabled,1: SRAM parity check error NMI source Enabled"
|
|
bitfld.long 0x00 2. "PWRWU_INT,Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: Power-down mode wake-up NMI source Disabled,1: Power-down mode wake-up NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IRC_INT,IRC TRIM NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: IRC TRIM NMI source Disabled,1: IRC TRIM NMI source Enabled"
|
|
bitfld.long 0x00 0. "BODOUT,BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: BOD NMI source Disabled,1: BOD NMI source Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "NMISTS,NMI Source Interrupt Status Register"
|
|
bitfld.long 0x00 15. "UART1_INT,UART1 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
|
|
bitfld.long 0x00 14. "UART0_INT,UART0 Interrupt Flag (Read Only)" "0: UART0 interrupt is deasserted,1: UART0 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 13. "EINT5,External Interrupt From PB.7 PD.12 or PF.14 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.7 PD.12 or PF.14..,1: External Interrupt from PB.7 PD.12 or PF.14.."
|
|
bitfld.long 0x00 12. "EINT4,External Interrupt From PA.8 PB.6 or PF.15 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PA.8 PB.6 or PF.15..,1: External Interrupt from PA.8 PB.6 or PF.15.."
|
|
newline
|
|
bitfld.long 0x00 11. "EINT3,External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.2 or PC.7..,1: External Interrupt from PB.2 or PC.7.."
|
|
bitfld.long 0x00 10. "EINT2,External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.3 or PC.6..,1: External Interrupt from PB.3 or PC.6.."
|
|
newline
|
|
bitfld.long 0x00 9. "EINT1,External Interrupt From PA.7 PB.4 or PD.15 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PA.7 PB.4 or PD.15..,1: External Interrupt from PA.7 PB.4 or PD.15.."
|
|
bitfld.long 0x00 8. "EINT0,External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PA.6 or PB.5..,1: External Interrupt from PA.6 or PB.5.."
|
|
newline
|
|
bitfld.long 0x00 6. "RTC_INT,RTC Interrupt Flag (Read Only)" "0: RTC interrupt is deasserted,1: RTC interrupt is asserted"
|
|
bitfld.long 0x00 4. "CLKFAIL,Clock Fail Detected Interrupt Flag (Read Only)" "0: Clock fail detected interrupt is deasserted,1: Clock fail detected interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 3. "SRAM_PERR,SRAM ParityCheck Error Interrupt Flag (Read Only)" "0: SRAM parity check error interrupt is deasserted,1: SRAM parity check error interrupt is asserted"
|
|
bitfld.long 0x00 2. "PWRWU_INT,Power-down Mode Wake-up Interrupt Flag (Read Only)" "0: Power-down mode wake-up interrupt is deasserted,1: Power-down mode wake-up interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 1. "IRC_INT,IRC TRIM Interrupt Flag (Read Only)" "0: HIRC TRIM interrupt is deasserted,1: HIRC TRIM interrupt is asserted"
|
|
bitfld.long 0x00 0. "BODOUT,BOD Interrupt Flag (Read Only)" "0: BOD interrupt is deasserted,1: BOD interrupt is asserted"
|
|
tree.end
|
|
tree "NVIC (NVIC Register Map)"
|
|
base ad:0xE000E100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "NVIC_ISER0,IRQ0 ~ IRQ111 Set-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER0 registers enable interrupts and show which interrupts are enabled\nWrite Operation"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "NVIC_ISER1,IRQ0 ~ IRQ111 Set-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER1 registers enable interrupts and show which interrupts are enabled\nWrite Operation"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "NVIC_ISER2,IRQ0 ~ IRQ111 Set-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER2 registers enable interrupts and show which interrupts are enabled\nWrite Operation"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "NVIC_ISER3,IRQ0 ~ IRQ111 Set-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts and show which interrupts are enabled\nWrite Operation"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "NVIC_ICER0,IRQ0 ~ IRQ111 Clear-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER0 registers disable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "NVIC_ICER1,IRQ0 ~ IRQ111 Clear-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER1 registers disable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "NVIC_ICER2,IRQ0 ~ IRQ111 Clear-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER2 registers disable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "NVIC_ICER3,IRQ0 ~ IRQ111 Clear-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "NVIC_ISPR0,IRQ0 ~ IRQ111 Set-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR0 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "NVIC_ISPR1,IRQ0 ~ IRQ111 Set-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "NVIC_ISPR2,IRQ0 ~ IRQ111 Set-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR2 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "NVIC_ISPR3,IRQ0 ~ IRQ111 Set-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "NVIC_ICPR0,IRQ0 ~ IRQ111 Clear-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR0 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "NVIC_ICPR1,IRQ0 ~ IRQ111 Clear-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "NVIC_ICPR2,IRQ0 ~ IRQ111 Clear-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "NVIC_ICPR3,IRQ0 ~ IRQ111 Clear-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "NVIC_IABR0,IRQ0 ~ IRQ111 Active Bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR0 registers indicate which interrupts are active"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "NVIC_IABR1,IRQ0 ~ IRQ111 Active Bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "NVIC_IABR2,IRQ0 ~ IRQ111 Active Bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR2 registers indicate which interrupts are active"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "NVIC_IABR3,IRQ0 ~ IRQ111 Active Bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active"
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x300)++0x03
|
|
line.long 0x00 "NVIC_IPR$1,IRQ0 ~ IRQ111 Priority Control Register"
|
|
bitfld.long 0x00 28.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
repeat 13. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 )
|
|
group.long ($2+0x340)++0x03
|
|
line.long 0x00 "NVIC_IPR$1,IRQ0 ~ IRQ111 Priority Control Register"
|
|
bitfld.long 0x00 28.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "STIR,Software Trigger Interrupt Registers"
|
|
hexmask.long.word 0x00 0.--8. 1. "INTID,Interrupt ID\nWrite to the STIR To Generate An Interrupt from Software\nWhen the USERSETMPEND bit in the SCR is set to 1 unprivileged software can access the STIR\nInterrupt ID of the interrupt to trigger in the range 0-63"
|
|
tree.end
|
|
tree "PDMA (PDMA Register Map)"
|
|
base ad:0x40008000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDMA_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PDMA_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
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|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
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|
newline
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|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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|
newline
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|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
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|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
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|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PDMA_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
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|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
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|
newline
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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|
newline
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|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
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|
newline
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bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDMA_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel n"
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|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
newline
|
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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|
newline
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bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
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|
newline
|
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bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PDMA_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
newline
|
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
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|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
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|
newline
|
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bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PDMA_DSCT5_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
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|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
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|
newline
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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|
newline
|
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bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
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|
newline
|
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bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PDMA_DSCT0_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDMA_DSCT1_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PDMA_DSCT2_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PDMA_DSCT3_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PDMA_DSCT4_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PDMA_DSCT5_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PDMA_DSCT0_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PDMA_DSCT1_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PDMA_DSCT2_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PDMA_DSCT3_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PDMA_DSCT4_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PDMA_DSCT5_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PDMA_DSCT0_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PDMA_DSCT1_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PDMA_DSCT2_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PDMA_DSCT3_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PDMA_DSCT4_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PDMA_DSCT5_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "PDMA_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
repeat 5. (strings "1" "2" "3" "4" "5" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
group.long ($2+0x104)++0x03
|
|
line.long 0x00 "PDMA_CURSCAT$1,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
repeat.end
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PDMA_CHCTL,PDMA Channel Control Register"
|
|
bitfld.long 0x00 5. "CHEN5,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x00 4. "CHEN4,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "CHEN3,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x00 2. "CHEN2,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "CHEN1,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x00 0. "CHEN0,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
wgroup.long 0x404++0x03
|
|
line.long 0x00 "PDMA_PAUSE,PDMA Transfer Pause Control Register"
|
|
bitfld.long 0x00 5. "PAUSE5,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x00 4. "PAUSE4,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x00 3. "PAUSE3,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x00 2. "PAUSE2,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x00 1. "PAUSE1,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x00 0. "PAUSE0,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
wgroup.long 0x408++0x03
|
|
line.long 0x00 "PDMA_SWREQ,PDMA Software Request Register"
|
|
bitfld.long 0x00 5. "SWREQ5,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
|
|
bitfld.long 0x00 4. "SWREQ4,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
|
|
newline
|
|
bitfld.long 0x00 3. "SWREQ3,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
|
|
bitfld.long 0x00 2. "SWREQ2,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
|
|
newline
|
|
bitfld.long 0x00 1. "SWREQ1,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
|
|
bitfld.long 0x00 0. "SWREQ0,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "PDMA_TRGSTS,PDMA Channel Request Status Register"
|
|
bitfld.long 0x00 5. "REQSTS5,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x00 4. "REQSTS4,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
newline
|
|
bitfld.long 0x00 3. "REQSTS3,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x00 2. "REQSTS2,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
newline
|
|
bitfld.long 0x00 1. "REQSTS1,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x00 0. "REQSTS0,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "PDMA_PRISET,PDMA Fixed Priority Setting Register"
|
|
bitfld.long 0x00 5. "FPRISET5,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority to clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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|
bitfld.long 0x00 4. "FPRISET4,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority to clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 3. "FPRISET3,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority to clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 2. "FPRISET2,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority to clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 1. "FPRISET1,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority to clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 0. "FPRISET0,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority to clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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wgroup.long 0x414++0x03
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line.long 0x00 "PDMA_PRICLR,PDMA Fixed Priority Clear Register"
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bitfld.long 0x00 5. "FPRICLR5,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 4. "FPRICLR4,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 3. "FPRICLR3,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 2. "FPRICLR2,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 1. "FPRICLR1,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 0. "FPRICLR0,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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group.long 0x418++0x03
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line.long 0x00 "PDMA_INTEN,PDMA Interrupt Enable Register"
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bitfld.long 0x00 5. "INTEN5,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 4. "INTEN4,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 3. "INTEN3,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 2. "INTEN2,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 1. "INTEN1,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 0. "INTEN0,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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group.long 0x41C++0x03
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line.long 0x00 "PDMA_INTSTS,PDMA Interrupt Status Register"
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bitfld.long 0x00 9. "REQTOF1,Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1 user can write 1 to clear these bits.\nNote: Please disable time-out function before clearing this bit" "0: No request time-out,1: Peripheral request time-out"
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bitfld.long 0x00 8. "REQTOF0,Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0 user can write 1 to clear these bits.\nNote: Please disable time-out function before clearing this bit" "0: No request time-out,1: Peripheral request time-out"
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rbitfld.long 0x00 2. "ALIGNF,Transfer Alignment Interrupt Flag (Read Only)" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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rbitfld.long 0x00 1. "TDIF,Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer" "0: Not finished yet,1: PDMA channel has finished transmission"
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rbitfld.long 0x00 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error" "0: No AHB bus ERROR response received,1: AHB bus ERROR response received"
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group.long 0x420++0x03
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line.long 0x00 "PDMA_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register"
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bitfld.long 0x00 5. "ABTIF5,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 4. "ABTIF4,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 3. "ABTIF3,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 2. "ABTIF2,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 1. "ABTIF1,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 0. "ABTIF0,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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group.long 0x424++0x03
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line.long 0x00 "PDMA_TDSTS,PDMA Channel Transfer Done Flag Register"
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bitfld.long 0x00 5. "TDIF5,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 4. "TDIF4,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 3. "TDIF3,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 2. "TDIF2,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 1. "TDIF1,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 0. "TDIF0,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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group.long 0x428++0x03
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line.long 0x00 "PDMA_ALIGN,PDMA Transfer Alignment Status Register"
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bitfld.long 0x00 5. "ALIGN5,Transfer Alignment Flag\nNote: Source address and destination address should be alignment" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 4. "ALIGN4,Transfer Alignment Flag\nNote: Source address and destination address should be alignment" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 3. "ALIGN3,Transfer Alignment Flag\nNote: Source address and destination address should be alignment" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 2. "ALIGN2,Transfer Alignment Flag\nNote: Source address and destination address should be alignment" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 1. "ALIGN1,Transfer Alignment Flag\nNote: Source address and destination address should be alignment" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 0. "ALIGN0,Transfer Alignment Flag\nNote: Source address and destination address should be alignment" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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rgroup.long 0x42C++0x03
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line.long 0x00 "PDMA_TACTSTS,PDMA Transfer Active Flag Register"
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bitfld.long 0x00 5. "TXACTF5,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x00 4. "TXACTF4,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x00 3. "TXACTF3,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x00 2. "TXACTF2,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x00 1. "TXACTF1,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x00 0. "TXACTF0,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
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group.long 0x430++0x03
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line.long 0x00 "PDMA_TOUTPSC,PDMA Time-out Prescaler Register"
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bitfld.long 0x00 4.--6. "TOUTPSC1,PDMA Channel 1 Time-out Clock Source Prescaler Bits" "0: PDMA channel 1 time-out clock source is HCLK/28,1: PDMA channel 1 time-out clock source is HCLK/29,2: PDMA channel 1 time-out clock source is..,3: PDMA channel 1 time-out clock source is..,4: PDMA channel 1 time-out clock source is..,5: PDMA channel 1 time-out clock source is..,6: PDMA channel 1 time-out clock source is..,7: PDMA channel 1 time-out clock source is.."
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bitfld.long 0x00 0.--2. "TOUTPSC0,PDMA Channel 0 Time-out Clock Source Prescaler Bits" "0: PDMA channel 0 time-out clock source is HCLK/28,1: PDMA channel 0 time-out clock source is HCLK/29,2: PDMA channel 0 time-out clock source is..,3: PDMA channel 0 time-out clock source is..,4: PDMA channel 0 time-out clock source is..,5: PDMA channel 0 time-out clock source is..,6: PDMA channel 0 time-out clock source is..,7: PDMA channel 0 time-out clock source is.."
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group.long 0x434++0x03
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line.long 0x00 "PDMA_TOUTEN,PDMA Time-out Enable Register"
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bitfld.long 0x00 1. "TOUTEN1,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x00 0. "TOUTEN0,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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group.long 0x438++0x03
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line.long 0x00 "PDMA_TOUTIEN,PDMA Time-out Interrupt Enable Register"
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bitfld.long 0x00 1. "TOUTIEN1,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x00 0. "TOUTIEN0,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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group.long 0x43C++0x03
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line.long 0x00 "PDMA_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register"
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hexmask.long.word 0x00 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address\nIn Scatter-Gather mode this is the base address for calculating the next link - list address"
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group.long 0x440++0x03
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line.long 0x00 "PDMA_TOC0_1,PDMA Time-out Counter Ch1 and Ch0 Register"
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hexmask.long.word 0x00 16.--31. 1. "TOC1,Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1"
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hexmask.long.word 0x00 0.--15. 1. "TOC0,Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0"
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group.long 0x460++0x03
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line.long 0x00 "PDMA_CHRST,PDMA Channel Reset Register"
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bitfld.long 0x00 0.--5. "CHnRST,Channel n Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset,?..."
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group.long 0x480++0x03
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line.long 0x00 "PDMA_REQSEL0_3,PDMA Request Source Select Register 0"
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bitfld.long 0x00 24.--29. "REQSRC3,Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--21. "REQSRC2,Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "REQSRC1,Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "REQSRC0,Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0" "0: Disable PDMA peripheral request,1: Channel connects to UART0_TX,2: Channel connects to UART0_RX,3: Channel connects to UART1_TX,4: Channel connects to UART1_RX,5: Channel connects to UART2_TX,6: Channel connects to UART2_RX,7: Channel connects to UART3_TX,8: Channel connects to UART3_RX,9: Channel connects to UART4_TX,10: Channel connects to UART4_RX,11: Channel connects to UART5_TX,12: Channel connects to UART5_RX,13: Channel connects to SPI0_TX,14: Channel connects to SPI0_RX,15: Channel connects to SPI1_TX,16: Channel connects to SPI1_RX,17: Channel connects to EPWM0_P1_RX,18: Channel connects to EPWM0_P2_RX,19: Channel connects to EPWM0_P3_RX,20: Channel connects to EPWM1_P1_RX,21: Channel connects to EPWM1_P2_RX,22: Channel connects to EPWM1_P3_RX,23: Channel connects to I2C0_TX,24: Channel connects to I2C0_RX,25: Channel connects to I2C1_TX,26: Channel connects to I2C1_RX,27: Channel connects to TMR0,28: Channel connects to TMR1,29: Channel connects to TMR2,30: Channel connects to TMR3,31: Channel connects to EADC0_RX,32: Channel connects to DAC0_TX,33: Channel connects to EPWM0_CH0_TX,34: Channel connects to EPWM0_CH1_TX,35: Channel connects to EPWM0_CH2_TX,36: Channel connects to EPWM0_CH3_TX,37: Channel connects to EPWM0_CH4_TX,38: Channel connects to EPWM0_CH5_TX,39: Channel connects to EPWM1_CH0_TX,40: Channel connects to EPWM1_CH1_TX,41: Channel connects to EPWM1_CH2_TX,42: Channel connects to EPWM1_CH3_TX,43: Channel connects to EPWM1_CH4_TX,44: Channel connects to EPWM1_CH5_TX,45: Channel connects to ACMP0,46: Channel connects to ACMP1,47: Reserved,48: Reserved,49: Reserved,50: Reserved,?..."
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group.long 0x484++0x03
|
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line.long 0x00 "PDMA_REQSEL4_5,PDMA Request Source Select Register 1"
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bitfld.long 0x00 8.--13. "REQSRC5,Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "REQSRC4,Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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tree.end
|
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tree "PRNG (PRNG Register Map)"
|
|
base ad:0x400BA000
|
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group.long 0x00++0x03
|
|
line.long 0x00 "PRNG_INTEN,PRNG Interrupt Enable Control Register"
|
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bitfld.long 0x00 16. "PRNGIEN,PRNG Interrupt Enable Bit" "0: PRNG interrupt Disabled,1: PRNG interrupt Enabled"
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group.long 0x04++0x03
|
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line.long 0x00 "PRNG_INTSTS,PRNG Interrupt Flag"
|
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bitfld.long 0x00 16. "PRNGIF,PRNG Finish Interrupt Flag\nNote: This bit is cleared by writing 1 and it has no effect by writing 0" "0: No PRNG interrupt,1: PRNG key generation done interrupt"
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|
group.long 0x08++0x03
|
|
line.long 0x00 "PRNG_CTL,PRNG Control Register"
|
|
rbitfld.long 0x00 8. "BUSY,PRNG Busy (Read Only)" "0: PRNG engine is idle,1: PRNG engine is generating PRNG_KEYx"
|
|
bitfld.long 0x00 2.--3. "KEYSZ,PRNG Generate Key Size" "0: 64 bits,1: 128 bits,2: 192 bits,3: 256 bits"
|
|
newline
|
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bitfld.long 0x00 1. "SEEDRLD,Reload New Seed for PRNG Engine" "0: Generating key based on the current seed,1: Reload new seed"
|
|
bitfld.long 0x00 0. "START,Start PRNG Engine" "0: Stop PRNG engine,1: Generate a new key and store the new key to.."
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "PRNG_SEED,Seed for PRNG"
|
|
hexmask.long 0x00 0.--31. 1. "SEED,Seed for PRNG (Write Only)\nThe bits store the seed for PRNG engine"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PRNG_KEY0,PRNG Generated Key0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 )
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "PRNG_KEY$1,PRNG Generated Key $1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
repeat.end
|
|
tree.end
|
|
tree "RTC (Real-time Counter)"
|
|
base ad:0x40041000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_INIT,RTC Initiation Register"
|
|
hexmask.long 0x00 1.--31. 1. "INIT,RTC Initiation (Write Only)\nWhen RTC block is powered on RTC is at reset state"
|
|
rbitfld.long 0x00 0. "ACTIVE,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_FREQADJ,RTC Frequency Compensation Register"
|
|
rbitfld.long 0x00 31. "FCRBUSY,Frequency Compensation Register Write Operation Busy (Read Only)\nNote: This bit is only used when DYNCOMPEN(RTC_CLKFMT[16]) is enabled" "0: The new register write operation is acceptable,1: The last write operation is in progress and.."
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bitfld.long 0x00 8.--12. "INTEGER,Integer Part" "0: Integer part of detected value is 32752,1: Integer part of detected value is 32753,2: Integer part of detected value is 32754,3: Integer part of detected value is 32755,4: Integer part of detected value is 32756,5: Integer part of detected value is 32757,6: Integer part of detected value is 32758,7: Integer part of detected value is 32759,8: Integer part of detected value is 32760,9: Integer part of detected value is 32761,10: Integer part of detected value is 32762,11: Integer part of detected value is 32763,12: Integer part of detected value is 32764,13: Integer part of detected value is 32765,14: Integer part of detected value is 32766,15: Integer part of detected value is 32767,16: Integer part of detected value is 32768,17: Integer part of detected value is 32769,18: Integer part of detected value is 32770,19: Integer part of detected value is 32771,20: Integer part of detected value is 32772,21: Integer part of detected value is 32773,22: Integer part of detected value is 32774,23: Integer part of detected value is 32775,24: Integer part of detected value is 32776,25: Integer part of detected value is 32777,26: Integer part of detected value is 32778,27: Integer part of detected value is 32779,28: Integer part of detected value is 32780,29: Integer part of detected value is 32781,30: Integer part of detected value is 32782,31: Integer part of detected value is 32783"
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newline
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bitfld.long 0x00 0.--5. "FRACTION,Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x0C++0x03
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line.long 0x00 "RTC_TIME,RTC Time Loading Register"
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bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
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bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x10++0x03
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line.long 0x00 "RTC_CAL,RTC Calendar Loading Register"
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bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1"
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bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
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bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x14++0x03
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line.long 0x00 "RTC_CLKFMT,RTC Time Scale Selection Register"
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bitfld.long 0x00 16. "DYNCOMPEN,Dynamic Compensation Enable Bit" "0: Dynamic Compensation Disabled,1: Dynamic Compensation Enabled"
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bitfld.long 0x00 0. "_24HEN,24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale" "0: 12-hour time scale with AM and PM indication..,1: 24-hour time scale selected"
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group.long 0x18++0x03
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line.long 0x00 "RTC_WEEKDAY,RTC Day of the Week Register"
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bitfld.long 0x00 0.--2. "WEEKDAY,Day of the Week Register" "0: Sunday,1: Monday,2: Tuesday,3: Wednesday,4: Thursday,5: Friday,6: Saturday,7: Reserved"
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group.long 0x1C++0x03
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line.long 0x00 "RTC_TALM,RTC Time Alarm Register"
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bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
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bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x20++0x03
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line.long 0x00 "RTC_CALM,RTC Calendar Alarm Register"
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bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
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bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
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bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x24++0x03
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line.long 0x00 "RTC_LEAPYEAR,RTC Leap Year Indicator Register"
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bitfld.long 0x00 0. "LEAPYEAR,Leap Year Indication (Read Only)" "0: This year is not a leap year,1: This year is leap year"
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group.long 0x28++0x03
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line.long 0x00 "RTC_INTEN,RTC Interrupt Enable Register"
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bitfld.long 0x00 1. "TICKIEN,Time Tick Interrupt Enable Bit\nSet TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated" "0: RTC Time Tick interrupt Disabled,1: RTC Time Tick interrupt Enabled"
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bitfld.long 0x00 0. "ALMIEN,Alarm Interrupt Enable Bit\nSet ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated" "0: RTC Alarm interrupt Disabled,1: RTC Alarm interrupt Enabled"
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group.long 0x2C++0x03
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line.long 0x00 "RTC_INTSTS,RTC Interrupt Status Register"
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bitfld.long 0x00 1. "TICKIF,RTC Time Tick Interrupt Flag\nNote: Write 1 to clear this bit" "0: Tick condition did not occur,1: Tick condition occurred"
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bitfld.long 0x00 0. "ALMIF,RTC Alarm Interrupt Flag\nNote: Write 1 to clear this bit" "0: Alarm condition is not matched,1: Alarm condition is matched"
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group.long 0x30++0x03
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line.long 0x00 "RTC_TICK,RTC Time Tick Register"
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bitfld.long 0x00 0.--2. "TICK,Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request" "0: Time tick is 1 second,1: Time tick is 1/2 second,2: Time tick is 1/4 second,3: Time tick is 1/8 second,4: Time tick is 1/16 second,5: Time tick is 1/32 second,6: Time tick is 1/64 second,7: Time tick is 1/128 second"
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group.long 0x34++0x03
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line.long 0x00 "RTC_TAMSK,RTC Time Alarm Mask Register"
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bitfld.long 0x00 5. "MTENHR,Mask 10-Hour Time Digit of Alarm Setting (0~2)" "0,1"
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bitfld.long 0x00 4. "MHR,Mask 1-Hour Time Digit of Alarm Setting (0~9)" "0,1"
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newline
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bitfld.long 0x00 3. "MTENMIN,Mask 10-Min Time Digit of Alarm Setting (0~5)" "0,1"
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bitfld.long 0x00 2. "MMIN,Mask 1-Min Time Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 1. "MTENSEC,Mask 10-Sec Time Digit of Alarm Setting (0~5)" "0,1"
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bitfld.long 0x00 0. "MSEC,Mask 1-Sec Time Digit of Alarm Setting (0~9)" "0,1"
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group.long 0x38++0x03
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line.long 0x00 "RTC_CAMSK,RTC Calendar Alarm Mask Register"
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bitfld.long 0x00 5. "MTENYEAR,Mask 10-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 4. "MYEAR,Mask 1-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
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newline
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bitfld.long 0x00 3. "MTENMON,Mask 10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
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bitfld.long 0x00 2. "MMON,Mask 1-Month Calendar Digit of Alarm Setting (0~9)" "0,1"
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newline
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bitfld.long 0x00 1. "MTENDAY,Mask 10-Day Calendar Digit of Alarm Setting (0~3)" "0,1"
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bitfld.long 0x00 0. "MDAY,Mask 1-Day Calendar Digit of Alarm Setting (0~9)" "0,1"
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group.long 0x100++0x03
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line.long 0x00 "RTC_LXTCTL,RTC 32.768 kHz Oscillator Control Register"
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bitfld.long 0x00 7. "RTCCKSEL,RTC Clock Source Selection" "0: Clock source from 32 kHz crystal or external..,1: Clock source from internal low speed RC.."
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bitfld.long 0x00 1.--3. "GAIN,Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range" "0: L0 mode (ESR=35K CL =25pF),1: L1 mode (ESR=35K CL =25pF),2: L2 mode (ESR=35K CL =25pF),3: L3 mode (ESR=70K CL =25pF),4: L4 mode (ESR=70K CL =25pF),5: L5 mode (ESR=70K CL =25pF),6: L6 mode (ESR=90K CL =25pF),7: L7 mode (ESR=90K CL =25pF)"
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group.long 0x110++0x03
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line.long 0x00 "RTC_DSTCTL,RTC Daylight Saving Time Control Register"
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bitfld.long 0x00 2. "DSBAK,Daylight Saving Back" "0: Daylight Saving Change is not performed,1: Daylight Saving Change is performed"
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bitfld.long 0x00 1. "SUBHR,Subtract 1 Hour" "0: No effect,1: Indicates RTC hour digit has been subtracted.."
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newline
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bitfld.long 0x00 0. "ADDHR,Add 1 Hour" "0: No effect,1: Indicates RTC hour digit has been added one.."
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tree.end
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tree "SPI (SPI Register Map)"
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repeat 2. (list 0. 1.) (list ad:0x40061000 ad:0x40062000)
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tree "SPI$1"
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base $2
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group.long 0x00++0x03
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line.long 0x00 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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newline
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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newline
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x00 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer" "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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newline
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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newline
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bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
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group.long 0x04++0x03
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line.long 0x00 "SPIx_CLKDIV,SPI Clock Divider Register"
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abitfld.long 0x00 0.--8. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master" "0x001=1: Not supported in I2S mode.\n,0x002=2: The time interval must be larger than.."
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group.long 0x08++0x03
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line.long 0x00 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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newline
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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newline
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bitfld.long 0x00 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit \nIn Slave 3-wire mode the SPI controller can work with 3-wire interface including SPIx_CLK SPIx_MISO and SPIx_MOSI pins.\n" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit\nNote: Master Mode only" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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newline
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)" "0: The slave selection signal SPIx_SS is active..,1: The slave selection signal SPIx_SS is active.."
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bitfld.long 0x00 0. "SS,Slave Selection Control\nIf AUTOSS bit is cleared to 0 \nNote: Master Mode only.\n\n \nNote: It is Master Only.\n\nNote: It is Master Only" "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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newline
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote1: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
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line.long 0x00 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error \nNote: SPI Slave Mode only" "0: Uncompleted RX data will be dropped from RX..,1: Uncompleted RX data will be written into RX.."
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
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newline
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bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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newline
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\n" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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newline
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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newline
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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newline
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bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
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group.long 0x14++0x03
|
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line.long 0x00 "SPIx_STATUS,SPI Status Register"
|
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rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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newline
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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newline
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI controller Disabled,1: SPI controller Enabled"
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newline
|
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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newline
|
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
|
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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newline
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)\nNote: By applications this SPI bus flag should be used with other status registers in SPIx_STATUS such as TXCNT RXCNT TXTHIF TXFULL TXEMPTY RXTHIF RXFULL RXEMPTY and UNITIF" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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rgroup.long 0x18++0x03
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line.long 0x00 "SPIx_STATUS2,SPI Status2 Register"
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bitfld.long 0x00 24.--29. "SLVBENUM,Effective Bit Number of Uncompleted RX Data\nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI slave mode.\nThis status register.." "?,1: This register will be cleared to 0x0 when user,2: SPI Slave Mode only,?..."
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wgroup.long 0x20++0x03
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line.long 0x00 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers"
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rgroup.long 0x30++0x03
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line.long 0x00 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller"
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group.long 0x60++0x03
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line.long 0x00 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x00 31. "SLVERRIEN,Bit Number Error Interrupt Enable Bit for Slave Mode\nInterrupt occurs if this bit is set to 1 and bit number error event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,2: PCM mode A,3: PCM mode B"
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bitfld.long 0x00 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x00 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1" "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x00 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1" "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x00 8. "SLAVE,Slave Mode\nI2S can operate as master or slave" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x00 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x00 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,2: data size is 24-bit,3: data size is 32-bit"
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bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit\n" "0: I2S mode Disabled,1: I2S mode Enabled"
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group.long 0x64++0x03
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line.long 0x00 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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bitfld.long 0x00 25. "I2SSLAVE,I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode\nUser sets I2SSLAVE to set frequency of peripheral clock of I2S master mode and I2S slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.\nI2SSLAVE needs to be set before.." "0: The frequency of peripheral clock sets to I2S..,1: The frequency of peripheral clock sets to I2S.."
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bitfld.long 0x00 24. "I2SMODE,I2S Clock Divider Number Selection for I2S Mode and SPI Mode\nUser sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) are set.\nI2SMODE needs to be set before.." "0: The frequency of peripheral clock sets to SPI..,1: The frequency of peripheral clock sets to I2S.."
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hexmask.long.word 0x00 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
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hexmask.long.byte 0x00 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices"
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group.long 0x68++0x03
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line.long 0x00 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x00 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 22. "SLVERRIF,Bit Number Error Interrupt Flag for Slave Mode\nNote: This bit will be cleared by writing 1 to it" "0: No bit number error event occurred,1: Bit number error event occurred"
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bitfld.long 0x00 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x00 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x00 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI/I2S control logic Disabled,1: SPI/I2S control logic Enabled"
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x00 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel" "0: Left channel,1: Right channel"
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tree.end
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repeat.end
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tree.end
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tree "SYS (SYS Register Map)"
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base ad:0x40000000
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rgroup.long 0x00++0x03
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line.long 0x00 "SYS_PDID,Part Device Identification Number Register"
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hexmask.long 0x00 0.--31. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code"
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group.long 0x04++0x03
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line.long 0x00 "SYS_RSTSTS,System Reset Status Register"
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bitfld.long 0x00 8. "CPULKRF,CPU Lockup Reset Flag\n" "0: No reset from CPU lockup happened,1: The Cortex-M4 lockup happened and chip is reset"
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bitfld.long 0x00 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0" "0: No reset from CPU,1: The Cortex-M4 Core and FMC are reset by.."
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bitfld.long 0x00 6. "HRESETRF,HRESET Reset Flag\nThe HRESET reset flag is set by the 'Reset Signal' from the HRESET.\nNote: Write 1 to clear this bit to 0" "0: No reset from HRESET,1: Reset from HRESET"
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bitfld.long 0x00 5. "SYSRF,System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M4 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from Cortex-M4,1: The Cortex-M4 had issued the reset signal to.."
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bitfld.long 0x00 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from BOD,1: The BOD had issued the reset signal to reset.."
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bitfld.long 0x00 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from LVR,1: LVR controller had issued the reset signal to.."
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bitfld.long 0x00 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\n" "0: No reset from watchdog timer or window..,1: The watchdog timer or window watchdog timer.."
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bitfld.long 0x00 1. "PINRF,NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to.."
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bitfld.long 0x00 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued.."
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group.long 0x08++0x03
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line.long 0x00 "SYS_IPRST0,Peripheral Reset Control Register 0"
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bitfld.long 0x00 7. "CRCRST,CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller" "0: CRC calculation controller normal operation,1: CRC calculation controller reset"
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bitfld.long 0x00 2. "PDMARST,PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA" "0: PDMA controller normal operation,1: PDMA controller reset"
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bitfld.long 0x00 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected" "0: Processor core normal operation,1: Processor core one-shot reset"
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bitfld.long 0x00 0. "CHIPRST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the chip.." "0: Chip normal operation,1: Chip one-shot reset"
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group.long 0x0C++0x03
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line.long 0x00 "SYS_IPRST1,Peripheral Reset Control Register 1"
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bitfld.long 0x00 28. "EADCRST,EADC Controller Reset" "0: EADC controller normal operation,1: EADC controller reset"
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bitfld.long 0x00 21. "UART5RST,UART5 Controller Reset" "0: UART5 controller normal operation,1: UART5 controller reset"
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bitfld.long 0x00 20. "UART4RST,UART4 Controller Reset" "0: UART4 controller normal operation,1: UART4 controller reset"
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bitfld.long 0x00 19. "UART3RST,UART3 Controller Reset" "0: UART3 controller normal operation,1: UART3 controller reset"
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bitfld.long 0x00 18. "UART2RST,UART2 Controller Reset" "0: UART2 controller normal operation,1: UART2 controller reset"
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bitfld.long 0x00 17. "UART1RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset"
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bitfld.long 0x00 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset"
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bitfld.long 0x00 14. "SPI1RST,SPI1 Controller Reset" "0: SPI1 controller normal operation,1: SPI1 controller reset"
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bitfld.long 0x00 13. "SPI0RST,SPI0 Controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset"
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bitfld.long 0x00 9. "I2C1RST,I2C1 Controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset"
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bitfld.long 0x00 8. "I2C0RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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bitfld.long 0x00 7. "ACMP01RST,Analog Comparator 0/1 Controller Reset" "0: Analog Comparator 0/1 controller normal..,1: Analog Comparator 0/1 controller reset"
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bitfld.long 0x00 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset"
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bitfld.long 0x00 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset"
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bitfld.long 0x00 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset"
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bitfld.long 0x00 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset"
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bitfld.long 0x00 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset"
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group.long 0x10++0x03
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line.long 0x00 "SYS_IPRST2,Peripheral Reset Control Register 2"
|
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bitfld.long 0x00 24. "PRNGRST,PRNG Controller Reset" "0: PRNG controller normal operation,1: PRNG controller reset"
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bitfld.long 0x00 19. "BPWM1RST,BPWM1 Controller Reset" "0: BPWM1 controller normal operation,1: BPWM1 controller reset"
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bitfld.long 0x00 18. "BPWM0RST,BPWM0 Controller Reset" "0: BPWM0 controller normal operation,1: BPWM0 controller reset"
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bitfld.long 0x00 17. "EPWM1RST,EPWM1 Controller Reset" "0: EPWM1 controller normal operation,1: EPWM1 controller reset"
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bitfld.long 0x00 16. "EPWM0RST,EPWM0 Controller Reset" "0: EPWM0 controller normal operation,1: EPWM0 controller reset"
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bitfld.long 0x00 15. "CIR0RST,CIR0 Controller Reset" "0: CIR0 controller normal operation,1: CIR0 controller reset"
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bitfld.long 0x00 12. "DACRST,DAC Controller Reset" "0: DAC controller normal operation,1: DAC controller reset"
|
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group.long 0x18++0x03
|
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line.long 0x00 "SYS_BODCTL,Brown-out Detector Control Register"
|
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bitfld.long 0x00 16.--17. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register CBOV (CONFIG0 [22:21]).\nNote: This bit is write protected" "0: Brown-Out Detector threshold voltage is 2.4V,1: Brown-Out Detector threshold voltage is 2.7V,2: Brown-Out Detector threshold voltage is 3.7V,3: Brown-Out Detector threshold voltage is 4.4V"
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bitfld.long 0x00 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: Without de-glitch function,1: 4 system clock (HCLK),2: 8 system clock (HCLK),3: 16 system clock (HCLK),4: 32 system clock (HCLK),5: 64 system clock (HCLK),6: 128 system clock (HCLK),7: 256 system clock (HCLK)"
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bitfld.long 0x00 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: BOD output is sampled by RC10K clock,1: 4 system clock (HCLK),2: 8 system clock (HCLK),3: 16 system clock (HCLK),4: 32 system clock (HCLK),5: 64 system clock (HCLK),6: 128 system clock (HCLK),7: 256 system clock (HCLK)"
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bitfld.long 0x00 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting" "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled"
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bitfld.long 0x00 6. "BODOUT,Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting" "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
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bitfld.long 0x00 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect)\n" "0: BOD operate in normal mode (default),1: BOD Low Power mode Enabled"
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bitfld.long 0x00 4. "BODIF,Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0" "0: Brown-out Detector does not detect any..,1: When Brown-out Detector detects the VDD is.."
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bitfld.long 0x00 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit.\n" "0: Brown-out 'INTERRUPT' function Enabled,1: Brown-out 'RESET' function Enabled"
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bitfld.long 0x00 0. "BODEN,Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]).\nNote: This bit is write protected" "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
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group.long 0x1C++0x03
|
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line.long 0x00 "SYS_IVSCTL,Internal Voltage Source Control Register"
|
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bitfld.long 0x00 0. "VTEMPEN,Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function" "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
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|
group.long 0x28++0x03
|
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line.long 0x00 "SYS_VREFCTL,VREF Control Register"
|
|
bitfld.long 0x00 24. "VBGFEN,Chip Internal Voltage Band-gap Force Enable Bit(Write Only)\nNote: If user want to read the value of this bit please read bit[25]" "0: Chip internal voltage band-gap controlled by..,1: Chip internal voltage band-gap force enable"
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bitfld.long 0x00 6. "PRELOADEN,Pre-load Function Enable Bit (Write Protect)\nThis bit should be enabled and keep during Tstable when VREFCTL(SYS_VREFCTL[4:0]) change setting(except set to 00000)" "0: VREF Pre-load function Disabled,1: VREF Pre-load function Enabled"
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bitfld.long 0x00 0.--4. "VREFCTL,VREF Control Bits (Write Protect)\nNote: This bit is write protected" "0: VREF is from external pin,?,2: VREF is from internal reference voltage 2.048V,?,?,?,6: VREF is from internal reference voltage 2.56V,?,?,?,10: VREF is from internal reference voltage 3.072V,?,?,?,14: VREF is from internal reference voltage 4.096V,?..."
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group.long 0x30++0x03
|
|
line.long 0x00 "SYS_GPA_MFPL,GPIOA Low Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PA7MFP,PA.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PA6MFP,PA.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PA5MFP,PA.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PA4MFP,PA.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PA3MFP,PA.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PA2MFP,PA.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 4.--7. "PA1MFP,PA.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PA0MFP,PA.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SYS_GPA_MFPH,GPIOA High Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PA15MFP,PA.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PA14MFP,PA.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PA13MFP,PA.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PA12MFP,PA.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PA11MFP,PA.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PA10MFP,PA.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PA9MFP,PA.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PA8MFP,PA.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SYS_GPB_MFPL,GPIOB Low Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PB7MFP,PB.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PB6MFP,PB.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PB5MFP,PB.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PB4MFP,PB.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PB3MFP,PB.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PB2MFP,PB.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PB1MFP,PB.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PB0MFP,PB.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SYS_GPB_MFPH,GPIOB High Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PB15MFP,PB.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PB14MFP,PB.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PB13MFP,PB.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PB12MFP,PB.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PB11MFP,PB.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PB10MFP,PB.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PB9MFP,PB.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PB8MFP,PB.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SYS_GPC_MFPL,GPIOC Low Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PC7MFP,PC.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PC6MFP,PC.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PC5MFP,PC.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PC4MFP,PC.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PC3MFP,PC.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PC2MFP,PC.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PC1MFP,PC.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC0MFP,PC.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SYS_GPC_MFPH,GPIOC High Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 24.--27. "PC14MFP,PC.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "PC13MFP,PC.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "PC12MFP,PC.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "PC11MFP,PC.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PC10MFP,PC.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "PC9MFP,PC.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "PC8MFP,PC.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SYS_GPD_MFPL,GPIOD Low Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PD7MFP,PD.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PD6MFP,PD.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PD5MFP,PD.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PD4MFP,PD.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PD3MFP,PD.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PD2MFP,PD.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PD1MFP,PD.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PD0MFP,PD.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SYS_GPD_MFPH,GPIOD High Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PD15MFP,PD.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PD14MFP,PD.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PD13MFP,PD.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PD12MFP,PD.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PD11MFP,PD.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PD10MFP,PD.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PD9MFP,PD.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PD8MFP,PD.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SYS_GPE_MFPL,GPIOE Low Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PE7MFP,PE.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PE6MFP,PE.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PE5MFP,PE.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PE4MFP,PE.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PE3MFP,PE.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PE2MFP,PE.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PE1MFP,PE.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PE0MFP,PE.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SYS_GPE_MFPH,GPIOE High Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PE15MFP,PE.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PE14MFP,PE.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PE13MFP,PE.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PE12MFP,PE.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PE11MFP,PE.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PE10MFP,PE.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PE9MFP,PE.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PE8MFP,PE.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SYS_GPF_MFPL,GPIOF Low Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PF7MFP,PF.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PF6MFP,PF.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PF5MFP,PF.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PF4MFP,PF.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PF3MFP,PF.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PF2MFP,PF.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PF1MFP,PF.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PF0MFP,PF.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SYS_GPF_MFPH,GPIOF High Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PF15MFP,PF.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PF14MFP,PF.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PF13MFP,PF.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PF12MFP,PF.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PF11MFP,PF.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PF10MFP,PF.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PF9MFP,PF.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PF8MFP,PF.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SYS_GPG_MFPL,GPIOG Low Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 16.--19. "PG4MFP,PG.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "PG3MFP,PG.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PG2MFP,PG.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SYS_GPG_MFPH,GPIOG High Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PG15MFP,PG.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PG14MFP,PG.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PG13MFP,PG.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PG12MFP,PG.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PG11MFP,PG.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PG10MFP,PG.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PG9MFP,PG.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PG8MFP,PG.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SYS_GPH_MFPL,GPIOH Low Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PH7MFP,PH.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PH6MFP,PH.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PH5MFP,PH.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PH4MFP,PH.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "SYS_GPH_MFPH,GPIOH High Byte Multiple Function Control Register"
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bitfld.long 0x00 12.--15. "PH11MFP,PH.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PH10MFP,PH.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "PH9MFP,PH.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PH8MFP,PH.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x70++0x03
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line.long 0x00 "SYS_GPI_MFPL,GPIOI Low Byte Multiple Function Control Register"
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bitfld.long 0x00 20.--23. "PI5MFP,PI.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PI4MFP,PI.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12.--15. "PI3MFP,PI.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PI2MFP,PI.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "PI1MFP,PI.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PI0MFP,PI.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x80++0x03
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line.long 0x00 "SYS_GPA_MFOS,GPIOA Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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group.long 0x84++0x03
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line.long 0x00 "SYS_GPB_MFOS,GPIOB Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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group.long 0x88++0x03
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line.long 0x00 "SYS_GPC_MFOS,GPIOC Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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group.long 0x8C++0x03
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line.long 0x00 "SYS_GPD_MFOS,GPIOD Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
|
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
|
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
|
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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group.long 0x90++0x03
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line.long 0x00 "SYS_GPE_MFOS,GPIOE Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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group.long 0x94++0x03
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line.long 0x00 "SYS_GPF_MFOS,GPIOF Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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group.long 0x98++0x03
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line.long 0x00 "SYS_GPG_MFOS,GPIOG Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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group.long 0x9C++0x03
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line.long 0x00 "SYS_GPH_MFOS,GPIOH Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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group.long 0xA0++0x03
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line.long 0x00 "SYS_GPI_MFOS,GPIOI Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nThe PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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group.long 0xB0++0x03
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line.long 0x00 "SYS_MODCTL,Modulation Control Register"
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bitfld.long 0x00 4.--7. "MODPWMSEL,EPWM0 Channel Select for Modulation\nSelect the EPWM0 channel to modulate with the UART0_TXD.\n0000: EPWM0 Channel 0 modulate with UART0_TXD.\n0001: EPWM0 Channel 1 modulate with UART0_TXD.\n0010: EPWM0 Channel 2 modulate with.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. "MODH,Modulation at Data High\nSelect modulation pulse(EPWM0) at high or low of UART0_TXD" "0,1"
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bitfld.long 0x00 0. "MODEN,Modulation Function Enable Bit\nThis bit enables modulation funcion by modulating with EPWM0 channel output and UART0(UART0_TXD) output" "0: Modulation Function Disabled,1: Modulation Function Enabled"
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group.long 0xC0++0x03
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line.long 0x00 "SYS_SRAM_INTCTL,System SRAM Interrupt Enable Control Register"
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bitfld.long 0x00 0. "PERRIEN,SRAM Parity Check Error Interrupt Enable Bit" "0: SRAM parity check error interrupt Disabled,1: SRAM parity check error interrupt Enabled"
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group.long 0xC4++0x03
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line.long 0x00 "SYS_SRAM_STATUS,System SRAM Parity Error Status Register"
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bitfld.long 0x00 0. "PERRIF,SRAM Parity Check Error Flag\nThis bit indicates the System SRAM parity error occurred" "0: No System SRAM parity error,1: System SRAM parity error occur"
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rgroup.long 0xC8++0x03
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line.long 0x00 "SYS_SRAM_ERRADDR,System SRAM Parity Check Error Address Register"
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hexmask.long 0x00 0.--31. 1. "ERRADDR,System SRAM Parity Error Address\nThis register shows system SRAM parity error byte address"
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group.long 0xD0++0x03
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line.long 0x00 "SYS_SRAM_BISTCTL,System SRAM BIST Test Control Register"
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bitfld.long 0x00 7. "PDMABIST,PDMA BIST Enable Bit (Write Protect)\nThis bit enables BIST test for PDMA RAM\nNote: This bit is write protected" "0: system PDMA BIST Disabled,1: system PDMA BIST Enabled"
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bitfld.long 0x00 2. "CRBIST,CACHE BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CACHE RAM\nNote: This bit is write protected" "0: system CACHE BIST Disabled,1: system CACHE BIST Enabled"
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bitfld.long 0x00 1. "SRBIST1,SRAM Bank1 BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SRAM bank1.\nNote: This bit is write protected" "0: system SRAM bank1 BIST Disabled,1: system SRAM bank1 BIST Enabled"
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bitfld.long 0x00 0. "SRBIST0,SRAM Bank0 BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SRAM bank0.\nNote: This bit is write protected" "0: system SRAM bank0 BIST Disabled,1: system SRAM bank0 BIST Enabled"
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rgroup.long 0xD4++0x03
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line.long 0x00 "SYS_SRAM_BISTSTS,System SRAM BIST Test Status Register"
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bitfld.long 0x00 23. "PDMABEND,PDMA SRAM BIST Test Finish" "0: PDMA SRAM BIST is active,1: PDMA SRAM BIST test finish"
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bitfld.long 0x00 18. "CRBEND,CACHE SRAM BIST Test Finish" "0: System CACHE RAM BIST is active,1: System CACHE RAM BIST test finish"
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bitfld.long 0x00 17. "SRBEND1,2nd SRAM BIST Test Finish" "0: 2nd system SRAM BIST is active,1: 2nd system SRAM BIST finish"
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bitfld.long 0x00 16. "SRBEND0,1st SRAM BIST Test Finish" "0: 1st system SRAM BIST active,1: 1st system SRAM BIST finish"
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bitfld.long 0x00 7. "PDMABEF,PDMA SRAM BIST Fail Flag" "0: PDMA SRAM BIST test pass,1: PDMA SRAM BIST test fail"
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bitfld.long 0x00 2. "CRBISTEF,CACHE SRAM BIST Fail Flag" "0: System CACHE RAM BIST test pass,1: System CACHE RAM BIST test fail"
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bitfld.long 0x00 1. "SRBISTEF1,2nd System SRAM BIST Fail Flag" "0: 2nd system SRAM BIST test pass,1: 2nd system SRAM BIST test fail"
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bitfld.long 0x00 0. "SRBISTEF0,1st System SRAM BIST Fail Flag" "0: 1st system SRAM BIST test pass,1: 1st system SRAM BIST test fail"
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group.long 0xF0++0x03
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line.long 0x00 "SYS_IRCTCTL,HIRC Trim Control Register"
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bitfld.long 0x00 16.--20. "BOUNDARY,Boundary Selection\nFill the boundary range from 0x1 to 0x31 0x0 is reserved.\nThis field shows the update value range" "?,1: When the RC clock shift over 0.25 percent due..,2: Only when the difference of the current,?..."
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bitfld.long 0x00 10. "REFCKSEL,Reference Clock Selection\nNote: The HIRC trim reference clock is 20 kHz in test mode" "0: HIRC trim reference clock is from LXT (32.768..,1: Reserved"
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bitfld.long 0x00 9. "BOUNDEN,Boundary Enable Bit" "0: Boundary function Disabled,1: Boundary function Enabled"
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bitfld.long 0x00 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation keeps going if clock is..,1: The trim operation is stopped if clock is.."
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bitfld.long 0x00 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC is locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,2: Trim retry count limitation is 256 loops,3: Trim retry count limitation is 512 loops"
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bitfld.long 0x00 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,2: Trim value calculation is based on average..,3: Trim value calculation is based on average.."
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bitfld.long 0x00 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC..,2: Reserved,3: Reserved"
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group.long 0xF4++0x03
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line.long 0x00 "SYS_IRCTIEN,HIRC Trim Interrupt Enable Register"
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bitfld.long 0x00 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccurate during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation an interrupt will be.." "0: Disable CLKERRIF(SYS_IRCTISTS[2]) status to..,1: Enable CLKERRIF(SYS_IRCTISTS[2]) status to.."
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bitfld.long 0x00 1. "TFAILIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).\nIf this bit.." "0: Disable TFAILIF(SYS_IRCTISTS[1]) status to..,1: Enable TFAILIF(SYS_IRCTISTS[1]) status to.."
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group.long 0xF8++0x03
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line.long 0x00 "SYS_IRCTISTS,HIRC Trim Interrupt Status Register"
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bitfld.long 0x00 3. "OVBDIF,Over Boundary Status\nWhen the over boundary function is set if there occurs the over boundary condition this flag will be set.\n" "0: Over boundary coundition did not occur,1: Over boundary coundition occurred"
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bitfld.long 0x00 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that.." "0: Clock frequency is accurate,1: Clock frequency is inaccurate"
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bitfld.long 0x00 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count is reached and the HIRC clock frequency is still not locked" "0: Trim value update limitation count is not..,1: Trim value update limitation count is reached.."
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bitfld.long 0x00 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and does not trigger any interrupt\nWrite 1 to clear this to 0" "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
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group.long 0x100++0x03
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line.long 0x00 "SYS_REGLCTL,Register Lock Control Register"
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hexmask.long.byte 0x00 0.--7. 1. "REGLCTL,Register Lock Control Code (Write Only)\nSome registers have write-protection function"
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group.long 0x1EC++0x03
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line.long 0x00 "SYS_PORDISAN,Analog POR Disable Control Register"
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hexmask.long.word 0x00 0.--15. 1. "POROFFAN,Power-on Reset Enable Bit (Write Protect)\nAfter powered on user can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field.\nThe analog POR circuit will be active again when this field is set to another value or.."
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group.long 0x1F8++0x03
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line.long 0x00 "SYS_PLCTL,Power Level Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "LVSPRD,LDO Voltage Scaling Period(Write Protect)\nThe LVSPRD value is the period of each LDO voltage rising step"
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bitfld.long 0x00 16.--20. "LVSSTEP,LDO Voltage Scaling Step(Write Protect)\nThe LVSSTEP value is LDO voltage rising step" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--1. "PLSEL,Power Level Select(Write Protect)\nThese bits indicate the status of power level.\nNote: Refer to section 6.2.5 for Power Modes and Power Level Transition" "0: Power level is PL0,1: Power level is PL1,2: Power level is PL2,?..."
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rgroup.long 0x1FC++0x03
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line.long 0x00 "SYS_PLSTS,Power Level Status Register"
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bitfld.long 0x00 8.--9. "PLSTATUS,Power Level Status (Read Only)\nThis bit indicates the status of power level" "0: Power level is PL0,1: Power level is PL1,?..."
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bitfld.long 0x00 0. "PLCBUSY,Power Level Change Busy Bit (Read Only)\nThis bit is set by hardware when power level is changing" "0: Core voltage change is completed,1: Core voltage change is ongoing"
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group.long 0x400++0x03
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line.long 0x00 "SYS_AHBMCTL,AHB Bus Matrix Priority Control Register"
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bitfld.long 0x00 0. "INTACTEN,Highest AHB Bus Priority of Cortex-M4 Core Enable Bit (Write Protect)\nEnable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix\nNote: This bit is write protected" "0: Round-robin mode,1: Cortex-M4 CPU with highest bus priority when.."
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tree.end
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tree "SYST_SCR (SYST_SCR Register Map)"
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base ad:0xE000E000
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group.long 0x10++0x03
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line.long 0x00 "SYST_CTRL,SysTick Control and Status Register"
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bitfld.long 0x00 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register" "0,1"
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bitfld.long 0x00 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is the (optional) external..,1: Core clock used for SysTick"
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bitfld.long 0x00 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
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bitfld.long 0x00 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
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group.long 0x14++0x03
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line.long 0x00 "SYST_LOAD,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0"
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group.long 0x18++0x03
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line.long 0x00 "SYST_VAL,SysTick Current Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value"
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group.long 0xD04++0x03
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x00 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit" "0: No effect.\nNMI exception is not pending,1: Change NMI exception state to pending.\nNMI.."
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bitfld.long 0x00 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Change PendSV exception state to.."
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bitfld.long 0x00 27. "PENDSVRTC_CAL,PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Remove the pending state from the PendSV.."
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bitfld.long 0x00 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation" "0: No effect.\nSysTick exception is not pending,1: Change SysTick exception state to.."
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bitfld.long 0x00 25. "PENDSTRTC_CAL,SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Remove the pending state from the SysTick.."
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rbitfld.long 0x00 23. "ISRPREEMPT,Interrupt Preempt Bit (Read Only)\nIf set a pending exception will be serviced on exit from the debug halt state" "0,1"
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rbitfld.long 0x00 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)" "0: Interrupt not pending,1: Interrupt pending"
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bitfld.long 0x00 12.--17. "VECTPENDING,Number of the Highest Pended Exception\nIndicates the Exception Number of the Highest Priority Pending Enabled Exception\nThe value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers but not any effect of the.." "0: No pending exceptions,?..."
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bitfld.long 0x00 11. "RETTOBASE,Preempted Active Exceptions Indicator\nIndicates whether there are Preempted Active Exceptions" "0: There are preempted active exceptions to..,1: There are no active exceptions or the.."
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hexmask.long.byte 0x00 0.--6. 1. "VECTACTIVE,Number of the Current Active Exception"
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group.long 0xD0C++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. "VECTORKEY,Register Access Key\nWhen writing this register this field should be 0x05FA otherwise the write action will be unpredictable.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of.."
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bitfld.long 0x00 15. "ENDIANNESS,Data Endianness" "0: Little-endian,1: Big-endian"
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bitfld.long 0x00 8.--10. "PRIGROUP,Interrupt Priority Grouping\nThis field determines the Split Of Group priority from subpriority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence" "0,1"
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bitfld.long 0x00 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's.." "0,1"
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bitfld.long 0x00 0. "VECTRESET,Reserved" "0,1"
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group.long 0xD10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.."
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bitfld.long 0x00 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControl whether the Processor uses Sleep Or Deep Sleep as its Low Power Mode" "0: Sleep,1: Deep sleep"
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bitfld.long 0x00 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application" "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an.."
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group.long 0xD18++0x03
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line.long 0x00 "SHPR1,System Handler Priority Register 1"
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bitfld.long 0x00 20.--23. "PRI_6,Priority of system handler 6 UsageFault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PRI_5,Priority of system handler 5 BusFault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PRI_4,Priority of system handler 4 MemManage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD1C++0x03
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 28.--31. "PRI_11,Priority of System Handler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD20++0x03
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line.long 0x00 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x00 28.--31. "PRI_15,Priority of System Handler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PRI_14,Priority of System Handler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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tree.end
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tree "TIMER (Timer/Counter)"
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tree "TMR01"
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base ad:0x40050000
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group.long 0x00++0x03
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line.long 0x00 "TIMER0_CTL,Timer0 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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bitfld.long 0x00 15. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x04++0x03
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line.long 0x00 "TIMER0_CMP,Timer0 Comparator Register"
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abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.."
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group.long 0x08++0x03
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line.long 0x00 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x0C++0x03
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line.long 0x00 "TIMER0_CNT,Timer0 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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rgroup.long 0x10++0x03
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line.long 0x00 "TIMER0_CAP,Timer0 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT.."
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group.long 0x14++0x03
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line.long 0x00 "TIMER0_EXTCTL,Timer0 External Control Register"
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bitfld.long 0x00 28.--31. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source/1,1: Capture source/2,2: Capture source/4,3: Capture source/8,4: Capture source/16,5: Capture source/32,6: Capture source/64,7: Capture source/128,8: Capture source/256,?..."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,2: Capture Function source is from HXT,3: Capture Function source is from LXT,4: Capture Function source is from HIRC,5: Capture Function source is from LIRC,6: Reserved,7: Reserved"
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x18++0x03
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line.long 0x00 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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group.long 0x1C++0x03
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line.long 0x00 "TIMER0_TRGCTL,Timer0 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger EPWM/BPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as EPWM/BPWM counter clock source" "0: Timer interrupt trigger EPWM/BPWM Disabled,1: Timer interrupt trigger EPWM/BPWM Enabled"
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x40++0x03
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line.long 0x00 "TIMER0_PWMCTL,Timer0 PWM Control Register"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 12. "PWMINTWKEN,PWM Interrupt Wake-up Enable Bit\nIf PWM interrupt occurs when chip is in Power-down mode PWMINTWKEN can determine whether chip wake-up occurs or not" "0: PWM interrupt wake-up Disabled,1: PWM interrupt wake-up Enabled"
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bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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group.long 0x44++0x03
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line.long 0x00 "TIMER0_PWMCLKPSC,Timer0 PWM Counter Clock Pre-scale Register"
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hexmask.long.byte 0x00 0.--7. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
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group.long 0x48++0x03
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line.long 0x00 "TIMER0_PWMCNTCLR,Timer0 PWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware.\nNote: Timer peripheral clock source should be set as PCLK to ensure that this bit can be automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x0000 in up.."
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group.long 0x4C++0x03
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line.long 0x00 "TIMER0_PWMPERIOD,Timer0 PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn up count type"
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group.long 0x50++0x03
|
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line.long 0x00 "TIMER0_PWMCMPDAT,Timer0 PWM Comparator Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger EADC PDMA and DAC start convert"
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rgroup.long 0x54++0x03
|
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line.long 0x00 "TIMER0_PWMCNT,Timer0 PWM Counter Register"
|
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
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group.long 0x58++0x03
|
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line.long 0x00 "TIMER0_PWMPOLCTL,Timer0 PWM Pin Output Polar Control Register"
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bitfld.long 0x00 0. "PINV,PWMx Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_OUT pin.\nNote: Sets POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin" "0: PWMx_OUT pin polar inverse Disabled,1: PWMx_OUT polar inverse Enabled"
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group.long 0x5C++0x03
|
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line.long 0x00 "TIMER0_PWMPOCTL,Timer0 PWM Pin Output Control Register"
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bitfld.long 0x00 8. "POSEL,PWM Output Pin Select" "0: PWMx_OUT pin is TMx,1: PWMx_OUT pin is TMx_EXT"
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bitfld.long 0x00 0. "POEN,PWMx Output Pin Enable Bit\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin" "0: PWMx_OUT pin at tri-state mode,1: PWMx_OUT pin in output mode"
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group.long 0x60++0x03
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line.long 0x00 "TIMER0_PWMINTEN0,Timer0 PWM Interrupt Enable Register 0"
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bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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group.long 0x64++0x03
|
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line.long 0x00 "TIMER0_PWMINTSTS0,Timer0 PWM Interrupt Status Register 0"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\n" "0,1"
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x68++0x03
|
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line.long 0x00 "TIMER0_PWMTRGCTL,Timer0 PWM Trigger Control Register"
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bitfld.long 0x00 9. "PWMTRGPDMA,PWM Counter Event Trigger PDMA Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger PDMA conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source" "0: PWM trigger PDMA Disabled,1: PWM trigger PDMA Enabled"
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bitfld.long 0x00 8. "PWMTRGDAC,PWM Counter Event Trigger DAC Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger DAC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source" "0: PWM trigger DAC Disabled,1: PWM trigger DAC Enabled"
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newline
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bitfld.long 0x00 7. "PWMTRGEADC,PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source" "0: PWM counter event trigger EADC conversion..,1: PWM counter event trigger EADC conversion.."
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bitfld.long 0x00 0.--1. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at period point (PIF),1: Trigger conversion at compare up count point..,2: Trigger conversion at period or compare up..,3: Reserved"
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group.long 0x6C++0x03
|
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line.long 0x00 "TIMER0_PWMSTATUS,Timer0 PWM Status Register"
|
|
bitfld.long 0x00 18. "PDMATRGF,Trigger PDMA Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger PDMA start..,1: PWM counter event trigger PDMA start.."
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bitfld.long 0x00 17. "DACTRGF,Trigger DAC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger DAC start..,1: PWM counter event trigger DAC start.."
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bitfld.long 0x00 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger EADC start..,1: PWM counter event trigger EADC start.."
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bitfld.long 0x00 8. "PWMINTWKF,PWM Interrupt Wake-up Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM interrupt wake-up has not occurred,1: PWM interrupt wake-up has occurred"
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bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: The PWM counter value never reached its..,1: The PWM counter value has reached its maximum.."
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rgroup.long 0x70++0x03
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line.long 0x00 "TIMER0_PWMPBUF,Timer0 PWM Period Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0x74++0x03
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line.long 0x00 "TIMER0_PWMCMPBUF,Timer0 PWM Comparator Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
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group.long 0x100++0x03
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line.long 0x00 "TIMER1_CTL,Timer1 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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bitfld.long 0x00 15. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x104++0x03
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line.long 0x00 "TIMER1_CMP,Timer1 Comparator Register"
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abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.."
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group.long 0x108++0x03
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line.long 0x00 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x10C++0x03
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line.long 0x00 "TIMER1_CNT,Timer1 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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group.long 0x110++0x03
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line.long 0x00 "TIMER1_CAP,Timer1 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT.."
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group.long 0x114++0x03
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line.long 0x00 "TIMER1_EXTCTL,Timer1 External Control Register"
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bitfld.long 0x00 28.--31. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source/1,1: Capture source/2,2: Capture source/4,3: Capture source/8,4: Capture source/16,5: Capture source/32,6: Capture source/64,7: Capture source/128,8: Capture source/256,?..."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,2: Capture Function source is from HXT,3: Capture Function source is from LXT,4: Capture Function source is from HIRC,5: Capture Function source is from LIRC,6: Reserved,7: Reserved"
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x118++0x03
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line.long 0x00 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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group.long 0x11C++0x03
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line.long 0x00 "TIMER1_TRGCTL,Timer1 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger EPWM/BPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as EPWM/BPWM counter clock source" "0: Timer interrupt trigger EPWM/BPWM Disabled,1: Timer interrupt trigger EPWM/BPWM Enabled"
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x140++0x03
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line.long 0x00 "TIMER1_PWMCTL,Timer1 PWM Control Register"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 12. "PWMINTWKEN,PWM Interrupt Wake-up Enable Bit\nIf PWM interrupt occurs when chip is in Power-down mode PWMINTWKEN can determine whether chip wake-up occurs or not" "0: PWM interrupt wake-up Disabled,1: PWM interrupt wake-up Enabled"
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bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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group.long 0x144++0x03
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line.long 0x00 "TIMER1_PWMCLKPSC,Timer1 PWM Counter Clock Pre-scale Register"
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hexmask.long.byte 0x00 0.--7. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
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group.long 0x148++0x03
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line.long 0x00 "TIMER1_PWMCNTCLR,Timer1 PWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware.\nNote: Timer peripheral clock source should be set as PCLK to ensure that this bit can be automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x0000 in up.."
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group.long 0x14C++0x03
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line.long 0x00 "TIMER1_PWMPERIOD,Timer1 PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn up count type"
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group.long 0x150++0x03
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line.long 0x00 "TIMER1_PWMCMPDAT,Timer1 PWM Comparator Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger EADC PDMA and DAC start convert"
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group.long 0x154++0x03
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line.long 0x00 "TIMER1_PWMCNT,Timer1 PWM Counter Register"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
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group.long 0x158++0x03
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line.long 0x00 "TIMER1_PWMPOLCTL,Timer1 PWM Pin Output Polar Control Register"
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bitfld.long 0x00 0. "PINV,PWMx Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_OUT pin.\nNote: Sets POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin" "0: PWMx_OUT pin polar inverse Disabled,1: PWMx_OUT polar inverse Enabled"
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group.long 0x15C++0x03
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line.long 0x00 "TIMER1_PWMPOCTL,Timer1 PWM Pin Output Control Register"
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bitfld.long 0x00 8. "POSEL,PWM Output Pin Select" "0: PWMx_OUT pin is TMx,1: PWMx_OUT pin is TMx_EXT"
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bitfld.long 0x00 0. "POEN,PWMx Output Pin Enable Bit\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin" "0: PWMx_OUT pin at tri-state mode,1: PWMx_OUT pin in output mode"
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group.long 0x160++0x03
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line.long 0x00 "TIMER1_PWMINTEN0,Timer1 PWM Interrupt Enable Register 0"
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bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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group.long 0x164++0x03
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line.long 0x00 "TIMER1_PWMINTSTS0,Timer1 PWM Interrupt Status Register 0"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\n" "0,1"
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x168++0x03
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line.long 0x00 "TIMER1_PWMTRGCTL,Timer1 PWM Trigger Control Register"
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bitfld.long 0x00 9. "PWMTRGPDMA,PWM Counter Event Trigger PDMA Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger PDMA conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source" "0: PWM trigger PDMA Disabled,1: PWM trigger PDMA Enabled"
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bitfld.long 0x00 8. "PWMTRGDAC,PWM Counter Event Trigger DAC Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger DAC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source" "0: PWM trigger DAC Disabled,1: PWM trigger DAC Enabled"
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bitfld.long 0x00 7. "PWMTRGEADC,PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source" "0: PWM counter event trigger EADC conversion..,1: PWM counter event trigger EADC conversion.."
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bitfld.long 0x00 0.--1. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at period point (PIF),1: Trigger conversion at compare up count point..,2: Trigger conversion at period or compare up..,3: Reserved"
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group.long 0x16C++0x03
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line.long 0x00 "TIMER1_PWMSTATUS,Timer1 PWM Status Register"
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bitfld.long 0x00 18. "PDMATRGF,Trigger PDMA Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger PDMA start..,1: PWM counter event trigger PDMA start.."
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bitfld.long 0x00 17. "DACTRGF,Trigger DAC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger DAC start..,1: PWM counter event trigger DAC start.."
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newline
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bitfld.long 0x00 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger EADC start..,1: PWM counter event trigger EADC start.."
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bitfld.long 0x00 8. "PWMINTWKF,PWM Interrupt Wake-up Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM interrupt wake-up has not occurred,1: PWM interrupt wake-up has occurred"
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newline
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bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: The PWM counter value never reached its..,1: The PWM counter value has reached its maximum.."
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group.long 0x170++0x03
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line.long 0x00 "TIMER1_PWMPBUF,Timer1 PWM Period Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
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group.long 0x174++0x03
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line.long 0x00 "TIMER1_PWMCMPBUF,Timer1 PWM Comparator Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
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tree.end
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tree "TMR23"
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base ad:0x40051000
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group.long 0x00++0x03
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line.long 0x00 "TIMER2_CTL,Timer2 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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newline
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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newline
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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bitfld.long 0x00 15. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x04++0x03
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line.long 0x00 "TIMER2_CMP,Timer2 Comparator Register"
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abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.."
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group.long 0x08++0x03
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line.long 0x00 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x0C++0x03
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line.long 0x00 "TIMER2_CNT,Timer2 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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rgroup.long 0x10++0x03
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line.long 0x00 "TIMER2_CAP,Timer2 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT.."
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group.long 0x14++0x03
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line.long 0x00 "TIMER2_EXTCTL,Timer2 External Control Register"
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bitfld.long 0x00 28.--31. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source/1,1: Capture source/2,2: Capture source/4,3: Capture source/8,4: Capture source/16,5: Capture source/32,6: Capture source/64,7: Capture source/128,8: Capture source/256,?..."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,2: Capture Function source is from HXT,3: Capture Function source is from LXT,4: Capture Function source is from HIRC,5: Capture Function source is from LIRC,6: Reserved,7: Reserved"
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x18++0x03
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line.long 0x00 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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group.long 0x1C++0x03
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line.long 0x00 "TIMER2_TRGCTL,Timer2 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger EPWM/BPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as EPWM/BPWM counter clock source" "0: Timer interrupt trigger EPWM/BPWM Disabled,1: Timer interrupt trigger EPWM/BPWM Enabled"
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x40++0x03
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line.long 0x00 "TIMER2_PWMCTL,Timer2 PWM Control Register"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 12. "PWMINTWKEN,PWM Interrupt Wake-up Enable Bit\nIf PWM interrupt occurs when chip is in Power-down mode PWMINTWKEN can determine whether chip wake-up occurs or not" "0: PWM interrupt wake-up Disabled,1: PWM interrupt wake-up Enabled"
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bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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group.long 0x44++0x03
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line.long 0x00 "TIMER2_PWMCLKPSC,Timer2 PWM Counter Clock Pre-scale Register"
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hexmask.long.byte 0x00 0.--7. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
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group.long 0x48++0x03
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line.long 0x00 "TIMER2_PWMCNTCLR,Timer2 PWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware.\nNote: Timer peripheral clock source should be set as PCLK to ensure that this bit can be automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x0000 in up.."
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group.long 0x4C++0x03
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line.long 0x00 "TIMER2_PWMPERIOD,Timer2 PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn up count type"
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group.long 0x50++0x03
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line.long 0x00 "TIMER2_PWMCMPDAT,Timer2 PWM Comparator Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger EADC PDMA and DAC start convert"
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rgroup.long 0x54++0x03
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line.long 0x00 "TIMER2_PWMCNT,Timer2 PWM Counter Register"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
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group.long 0x58++0x03
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line.long 0x00 "TIMER2_PWMPOLCTL,Timer2 PWM Pin Output Polar Control Register"
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bitfld.long 0x00 0. "PINV,PWMx Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_OUT pin.\nNote: Sets POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin" "0: PWMx_OUT pin polar inverse Disabled,1: PWMx_OUT polar inverse Enabled"
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group.long 0x5C++0x03
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line.long 0x00 "TIMER2_PWMPOCTL,Timer2 PWM Pin Output Control Register"
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bitfld.long 0x00 8. "POSEL,PWM Output Pin Select" "0: PWMx_OUT pin is TMx,1: PWMx_OUT pin is TMx_EXT"
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bitfld.long 0x00 0. "POEN,PWMx Output Pin Enable Bit\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin" "0: PWMx_OUT pin at tri-state mode,1: PWMx_OUT pin in output mode"
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group.long 0x60++0x03
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line.long 0x00 "TIMER2_PWMINTEN0,Timer2 PWM Interrupt Enable Register 0"
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bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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group.long 0x64++0x03
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line.long 0x00 "TIMER2_PWMINTSTS0,Timer2 PWM Interrupt Status Register 0"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\n" "0,1"
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x68++0x03
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line.long 0x00 "TIMER2_PWMTRGCTL,Timer2 PWM Trigger Control Register"
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bitfld.long 0x00 9. "PWMTRGPDMA,PWM Counter Event Trigger PDMA Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger PDMA conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source" "0: PWM trigger PDMA Disabled,1: PWM trigger PDMA Enabled"
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bitfld.long 0x00 8. "PWMTRGDAC,PWM Counter Event Trigger DAC Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger DAC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source" "0: PWM trigger DAC Disabled,1: PWM trigger DAC Enabled"
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bitfld.long 0x00 7. "PWMTRGEADC,PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source" "0: PWM counter event trigger EADC conversion..,1: PWM counter event trigger EADC conversion.."
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bitfld.long 0x00 0.--1. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at period point (PIF),1: Trigger conversion at compare up count point..,2: Trigger conversion at period or compare up..,3: Reserved"
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group.long 0x6C++0x03
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line.long 0x00 "TIMER2_PWMSTATUS,Timer2 PWM Status Register"
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bitfld.long 0x00 18. "PDMATRGF,Trigger PDMA Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger PDMA start..,1: PWM counter event trigger PDMA start.."
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bitfld.long 0x00 17. "DACTRGF,Trigger DAC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger DAC start..,1: PWM counter event trigger DAC start.."
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bitfld.long 0x00 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger EADC start..,1: PWM counter event trigger EADC start.."
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bitfld.long 0x00 8. "PWMINTWKF,PWM Interrupt Wake-up Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM interrupt wake-up has not occurred,1: PWM interrupt wake-up has occurred"
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bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: The PWM counter value never reached its..,1: The PWM counter value has reached its maximum.."
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rgroup.long 0x70++0x03
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line.long 0x00 "TIMER2_PWMPBUF,Timer2 PWM Period Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0x74++0x03
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line.long 0x00 "TIMER2_PWMCMPBUF,Timer2 PWM Comparator Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
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group.long 0x100++0x03
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line.long 0x00 "TIMER3_CTL,Timer3 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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bitfld.long 0x00 15. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x104++0x03
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line.long 0x00 "TIMER3_CMP,Timer3 Comparator Register"
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abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.."
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group.long 0x108++0x03
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line.long 0x00 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x10C++0x03
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line.long 0x00 "TIMER3_CNT,Timer3 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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group.long 0x110++0x03
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line.long 0x00 "TIMER3_CAP,Timer3 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT.."
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group.long 0x114++0x03
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line.long 0x00 "TIMER3_EXTCTL,Timer3 External Control Register"
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bitfld.long 0x00 28.--31. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source/1,1: Capture source/2,2: Capture source/4,3: Capture source/8,4: Capture source/16,5: Capture source/32,6: Capture source/64,7: Capture source/128,8: Capture source/256,?..."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,2: Capture Function source is from HXT,3: Capture Function source is from LXT,4: Capture Function source is from HIRC,5: Capture Function source is from LIRC,6: Reserved,7: Reserved"
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x118++0x03
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line.long 0x00 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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group.long 0x11C++0x03
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line.long 0x00 "TIMER3_TRGCTL,Timer3 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger EPWM/BPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as EPWM/BPWM counter clock source" "0: Timer interrupt trigger EPWM/BPWM Disabled,1: Timer interrupt trigger EPWM/BPWM Enabled"
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x140++0x03
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line.long 0x00 "TIMER3_PWMCTL,Timer3 PWM Control Register"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 12. "PWMINTWKEN,PWM Interrupt Wake-up Enable Bit\nIf PWM interrupt occurs when chip is in Power-down mode PWMINTWKEN can determine whether chip wake-up occurs or not" "0: PWM interrupt wake-up Disabled,1: PWM interrupt wake-up Enabled"
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bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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group.long 0x144++0x03
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line.long 0x00 "TIMER3_PWMCLKPSC,Timer3 PWM Counter Clock Pre-scale Register"
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hexmask.long.byte 0x00 0.--7. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
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group.long 0x148++0x03
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line.long 0x00 "TIMER3_PWMCNTCLR,Timer3 PWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware.\nNote: Timer peripheral clock source should be set as PCLK to ensure that this bit can be automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x0000 in up.."
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group.long 0x14C++0x03
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line.long 0x00 "TIMER3_PWMPERIOD,Timer3 PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn up count type"
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group.long 0x150++0x03
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line.long 0x00 "TIMER3_PWMCMPDAT,Timer3 PWM Comparator Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger EADC PDMA and DAC start convert"
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group.long 0x154++0x03
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line.long 0x00 "TIMER3_PWMCNT,Timer3 PWM Counter Register"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
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group.long 0x158++0x03
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line.long 0x00 "TIMER3_PWMPOLCTL,Timer3 PWM Pin Output Polar Control Register"
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bitfld.long 0x00 0. "PINV,PWMx Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_OUT pin.\nNote: Sets POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin" "0: PWMx_OUT pin polar inverse Disabled,1: PWMx_OUT polar inverse Enabled"
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group.long 0x15C++0x03
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line.long 0x00 "TIMER3_PWMPOCTL,Timer3 PWM Pin Output Control Register"
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bitfld.long 0x00 8. "POSEL,PWM Output Pin Select" "0: PWMx_OUT pin is TMx,1: PWMx_OUT pin is TMx_EXT"
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bitfld.long 0x00 0. "POEN,PWMx Output Pin Enable Bit\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin" "0: PWMx_OUT pin at tri-state mode,1: PWMx_OUT pin in output mode"
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group.long 0x160++0x03
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line.long 0x00 "TIMER3_PWMINTEN0,Timer3 PWM Interrupt Enable Register 0"
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bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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group.long 0x164++0x03
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line.long 0x00 "TIMER3_PWMINTSTS0,Timer3 PWM Interrupt Status Register 0"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\n" "0,1"
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x168++0x03
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line.long 0x00 "TIMER3_PWMTRGCTL,Timer3 PWM Trigger Control Register"
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bitfld.long 0x00 9. "PWMTRGPDMA,PWM Counter Event Trigger PDMA Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger PDMA conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source" "0: PWM trigger PDMA Disabled,1: PWM trigger PDMA Enabled"
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bitfld.long 0x00 8. "PWMTRGDAC,PWM Counter Event Trigger DAC Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger DAC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source" "0: PWM trigger DAC Disabled,1: PWM trigger DAC Enabled"
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bitfld.long 0x00 7. "PWMTRGEADC,PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source" "0: PWM counter event trigger EADC conversion..,1: PWM counter event trigger EADC conversion.."
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bitfld.long 0x00 0.--1. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at period point (PIF),1: Trigger conversion at compare up count point..,2: Trigger conversion at period or compare up..,3: Reserved"
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group.long 0x16C++0x03
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line.long 0x00 "TIMER3_PWMSTATUS,Timer3 PWM Status Register"
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bitfld.long 0x00 18. "PDMATRGF,Trigger PDMA Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger PDMA start..,1: PWM counter event trigger PDMA start.."
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bitfld.long 0x00 17. "DACTRGF,Trigger DAC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger DAC start..,1: PWM counter event trigger DAC start.."
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bitfld.long 0x00 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger EADC start..,1: PWM counter event trigger EADC start.."
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bitfld.long 0x00 8. "PWMINTWKF,PWM Interrupt Wake-up Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM interrupt wake-up has not occurred,1: PWM interrupt wake-up has occurred"
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bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: The PWM counter value never reached its..,1: The PWM counter value has reached its maximum.."
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group.long 0x170++0x03
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line.long 0x00 "TIMER3_PWMPBUF,Timer3 PWM Period Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
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group.long 0x174++0x03
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line.long 0x00 "TIMER3_PWMCMPBUF,Timer3 PWM Comparator Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
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tree.end
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tree.end
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tree "UART (Universal Asynchronous Receiver/Transmitter)"
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tree "UART0"
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base ad:0x40070000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Inerrupt Disabled,1: Single-wire Bit Error Detect Inerrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\n" "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\n" "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\n" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\n" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\n" "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: PARITY bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data" "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\n" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\n" "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\n" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\n" "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.."
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF (UART_LINSTS[0]) BRKDETF (UART_LINSTS[8]) BITEF (UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF (UART_LINSTS[1]) all are cleared and software writing '1' to LINIF (UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,2: 4-bit time from START bit to the 1st rising..,3: 8-bit time from START bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 6. "DGE,Deglitch Enable Bit\nNote: When this bit is set to logic 1 any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX)" "0: Deglitch Disabled,1: Deglitch Enabled"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..."
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group.long 0x34++0x03
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line.long 0x00 "UART_LINCTL,UART LIN Control Register"
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abitfld.long 0x00 24.--31. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID[29:24]) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\n" "0x01=1: User can fill any 8-bit value to this..,0x02=2: This field can be used for LIN master.."
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bitfld.long 0x00 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved"
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bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1-bit..,1: The LIN break/sync delimiter length is 2-bit..,2: The LIN break/sync delimiter length is 3-bit..,3: The LIN break/sync delimiter length is 4-bit.."
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bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\n" "?,1: These registers are shadow registers of BRKFL,2: This break field length is BRKFL + 1,?..."
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bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
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bitfld.long 0x00 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\n" "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.14.5.10 (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\n" "0: UART_BAUD updated is written by software (if..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\n" "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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group.long 0x38++0x03
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line.long 0x00 "UART_LINSTS,UART LIN Status Register"
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bitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set" "0: Bit error not detected,1: Bit error detected"
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bitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
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bitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n" "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\n" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\n" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART1"
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base ad:0x40071000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Inerrupt Disabled,1: Single-wire Bit Error Detect Inerrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\n" "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\n" "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\n" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\n" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\n" "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: PARITY bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data" "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\n" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\n" "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\n" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\n" "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.."
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF (UART_LINSTS[0]) BRKDETF (UART_LINSTS[8]) BITEF (UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF (UART_LINSTS[1]) all are cleared and software writing '1' to LINIF (UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,2: 4-bit time from START bit to the 1st rising..,3: 8-bit time from START bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 6. "DGE,Deglitch Enable Bit\nNote: When this bit is set to logic 1 any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX)" "0: Deglitch Disabled,1: Deglitch Enabled"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..."
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group.long 0x34++0x03
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line.long 0x00 "UART_LINCTL,UART LIN Control Register"
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abitfld.long 0x00 24.--31. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID[29:24]) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\n" "0x01=1: User can fill any 8-bit value to this..,0x02=2: This field can be used for LIN master.."
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bitfld.long 0x00 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved"
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bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1-bit..,1: The LIN break/sync delimiter length is 2-bit..,2: The LIN break/sync delimiter length is 3-bit..,3: The LIN break/sync delimiter length is 4-bit.."
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bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\n" "?,1: These registers are shadow registers of BRKFL,2: This break field length is BRKFL + 1,?..."
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bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
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bitfld.long 0x00 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\n" "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.14.5.10 (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\n" "0: UART_BAUD updated is written by software (if..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\n" "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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group.long 0x38++0x03
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line.long 0x00 "UART_LINSTS,UART LIN Status Register"
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bitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set" "0: Bit error not detected,1: Bit error detected"
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bitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
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bitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n" "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\n" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\n" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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repeat 4. (list 2. 3. 4. 5.) (list ad:0x40072000 ad:0x40073000 ad:0x40074000 ad:0x40075000)
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tree "UART$1"
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base $2
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Inerrupt Disabled,1: Single-wire Bit Error Detect Inerrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\n" "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\n" "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\n" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\n" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\n" "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: PARITY bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data" "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\n" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\n" "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\n" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\n" "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.."
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF (UART_LINSTS[0]) BRKDETF (UART_LINSTS[8]) BITEF (UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF (UART_LINSTS[1]) all are cleared and software writing '1' to LINIF (UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,2: 4-bit time from START bit to the 1st rising..,3: 8-bit time from START bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 6. "DGE,Deglitch Enable Bit\nNote: When this bit is set to logic 1 any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX)" "0: Deglitch Disabled,1: Deglitch Enabled"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..."
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\n" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\n" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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repeat.end
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tree.end
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tree "WDT (Watchdog Timer Unit)"
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base ad:0x40040000
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group.long 0x00++0x03
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line.long 0x00 "WDT_CTL,WDT Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled"
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rbitfld.long 0x00 30. "SYNC,WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable WDTEN (WDT_CTL[7]) this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Performing enable or disable WDTEN bit needs 2 * WDT_CLK.." "0: Set WDTEN bit is completed,1: Set WDTEN bit is synchronizing and not become.."
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bitfld.long 0x00 8.--10. "TOUTSEL,WDT Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\nNote: This bit is write protected" "0: 24 * WDT_CLK,1: 26 * WDT_CLK,?..."
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bitfld.long 0x00 7. "WDTEN,WDT Enable Bit (Write Protect)\n" "0: WDT Disabled (This action will reset the..,1: WDT Enabled"
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bitfld.long 0x00 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU" "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
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bitfld.long 0x00 5. "WKF,WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\n" "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will.." "0: Wake-up trigger event Disabled if WDT..,1: Wake-up trigger event Enabled if WDT time-out.."
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bitfld.long 0x00 3. "IF,WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
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bitfld.long 0x00 2. "RSTF,WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
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bitfld.long 0x00 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected" "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
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bitfld.long 0x00 0. "RSTCNT,Reset WDT Up Counter (Write Protect)\n" "0: No effect,1: Reset the internal 20-bit WDT up counter value"
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group.long 0x04++0x03
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line.long 0x00 "WDT_ALTCTL,WDT Alternative Control Register"
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bitfld.long 0x00 0.--1. "RSTDSEL,WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened" "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: WDT Reset Delay Period is 130 * WDT_CLK,2: WDT Reset Delay Period is 18 * WDT_CLK,3: WDT Reset Delay Period is 3 * WDT_CLK"
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wgroup.long 0x08++0x03
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line.long 0x00 "WDT_RSTCNT,WDT Reset Counter Register"
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abitfld.long 0x00 0.--31. "RSTCNT,WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0.\n" "0x00000001=1: Performing RSTCNT to reset counter..,0x00000002=2: RSTCNT (WDT_CTL[0]) bit is a write.."
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tree.end
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tree "WWDT (WWDT Register Map)"
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base ad:0x40040100
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wgroup.long 0x00++0x03
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line.long 0x00 "WWDT_RLDCNT,WWDT Reload Counter Register"
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hexmask.long 0x00 0.--31. 1. "RLDCNT,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.."
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group.long 0x04++0x03
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line.long 0x00 "WWDT_CTL,WWDT Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nNote: WWDT down counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 16.--21. "CMPDAT,WWDT Window Compare\nSet this register to adjust the valid reload window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 8.--11. "PSCSEL,WWDT Counter Prescale Period Selection" "0: Pre-scale is 1 Max time-out period is 1 * 64..,1: Pre-scale is 2 Max time-out period is 2 * 64..,2: Pre-scale is 4 Max time-out period is 4 * 64..,3: Pre-scale is 8 Max time-out period is 8 * 64..,4: Pre-scale is 16 Max time-out period is 16 *..,5: Pre-scale is 32 Max time-out period is 32 *..,6: Pre-scale is 64 Max time-out period is 64 *..,7: Pre-scale is 128 Max time-out period is 128 *..,8: Pre-scale is 192 Max time-out period is 192 *..,9: Pre-scale is 256 Max time-out period is 256 *..,10: Pre-scale is 384 Max time-out period is 384..,11: Pre-scale is 512 Max time-out period is 512..,12: Pre-scale is 768 Max time-out period is 768..,13: Pre-scale is 1024 Max time-out period is..,14: Pre-scale is 1536 Max time-out period is..,15: Pre-scale is 2048 Max time-out period is.."
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bitfld.long 0x00 1. "INTEN,WWDT Interrupt Enable Bit\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU" "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
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newline
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bitfld.long 0x00 0. "WWDTEN,WWDT Enable Bit" "0: WWDT counter is stopped,1: WWDT counter starts counting"
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group.long 0x08++0x03
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line.long 0x00 "WWDT_STATUS,WWDT Status Register"
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bitfld.long 0x00 1. "WWDTRF,WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
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bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: WWDT counter value matches CMPDAT"
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rgroup.long 0x0C++0x03
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line.long 0x00 "WWDT_CNT,WWDT Counter Value Register"
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bitfld.long 0x00 0.--5. "CNTDAT,WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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tree.end
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autoindent.off
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newline
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